drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@foss.st.com>
   7  *           Erwan Le Ray <erwan.leray@foss.st.com>
   8  *
   9  * Inspired by st-asc.c from STMicroelectronics (c)
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-direction.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/pm_wakeirq.h>
  28 #include <linux/serial_core.h>
  29 #include <linux/serial.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/sysrq.h>
  32 #include <linux/tty_flip.h>
  33 #include <linux/tty.h>
  34
  35 #include "serial_mctrl_gpio.h"
  36 #include "stm32-usart.h"
  37
  38 static void stm32_usart_stop_tx(struct uart_port *port);
  39 static void stm32_usart_transmit_chars(struct uart_port *port);
  40
  41 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  42 {
  43         return container_of(port, struct stm32_port, port);
  44 }
  45
  46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
  47 {
  48         u32 val;
  49
  50         val = readl_relaxed(port->membase + reg);
  51         val |= bits;
  52         writel_relaxed(val, port->membase + reg);
  53 }
  54
  55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  56 {
  57         u32 val;
  58
  59         val = readl_relaxed(port->membase + reg);
  60         val &= ~bits;
  61         writel_relaxed(val, port->membase + reg);
  62 }
  63
  64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
  65                                          u32 delay_DDE, u32 baud)
  66 {
  67         u32 rs485_deat_dedt;
  68         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
  69         bool over8;
  70
  71         *cr3 |= USART_CR3_DEM;
  72         over8 = *cr1 & USART_CR1_OVER8;
  73
  74         if (over8)
  75                 rs485_deat_dedt = delay_ADE * baud * 8;
  76         else
  77                 rs485_deat_dedt = delay_ADE * baud * 16;
  78
  79         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  80         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  81                           rs485_deat_dedt_max : rs485_deat_dedt;
  82         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
  83                            USART_CR1_DEAT_MASK;
  84         *cr1 |= rs485_deat_dedt;
  85
  86         if (over8)
  87                 rs485_deat_dedt = delay_DDE * baud * 8;
  88         else
  89                 rs485_deat_dedt = delay_DDE * baud * 16;
  90
  91         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  92         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  93                           rs485_deat_dedt_max : rs485_deat_dedt;
  94         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
  95                            USART_CR1_DEDT_MASK;
  96         *cr1 |= rs485_deat_dedt;
  97 }
  98
  99 static int stm32_usart_config_rs485(struct uart_port *port,
 100                                     struct serial_rs485 *rs485conf)
 101 {
 102         struct stm32_port *stm32_port = to_stm32_port(port);
 103         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 104         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 105         u32 usartdiv, baud, cr1, cr3;
 106         bool over8;
 107
 108         stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 109
 110         port->rs485 = *rs485conf;
 111
 112         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 113
 114         if (rs485conf->flags & SER_RS485_ENABLED) {
 115                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 116                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 117                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 118                 usartdiv = usartdiv & GENMASK(15, 0);
 119                 over8 = cr1 & USART_CR1_OVER8;
 120
 121                 if (over8)
 122                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 123                                    << USART_BRR_04_R_SHIFT;
 124
 125                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 126                 stm32_usart_config_reg_rs485(&cr1, &cr3,
 127                                              rs485conf->delay_rts_before_send,
 128                                              rs485conf->delay_rts_after_send,
 129                                              baud);
 130
 131                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 132                         cr3 &= ~USART_CR3_DEP;
 133                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 134                 } else {
 135                         cr3 |= USART_CR3_DEP;
 136                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 137                 }
 138
 139                 writel_relaxed(cr3, port->membase + ofs->cr3);
 140                 writel_relaxed(cr1, port->membase + ofs->cr1);
 141         } else {
 142                 stm32_usart_clr_bits(port, ofs->cr3,
 143                                      USART_CR3_DEM | USART_CR3_DEP);
 144                 stm32_usart_clr_bits(port, ofs->cr1,
 145                                      USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 146         }
 147
 148         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 149
 150         return 0;
 151 }
 152
 153 static int stm32_usart_init_rs485(struct uart_port *port,
 154                                   struct platform_device *pdev)
 155 {
 156         struct serial_rs485 *rs485conf = &port->rs485;
 157
 158         rs485conf->flags = 0;
 159         rs485conf->delay_rts_before_send = 0;
 160         rs485conf->delay_rts_after_send = 0;
 161
 162         if (!pdev->dev.of_node)
 163                 return -ENODEV;
 164
 165         return uart_get_rs485_mode(port);
 166 }
 167
 168 static bool stm32_usart_rx_dma_enabled(struct uart_port *port)
 169 {
 170         struct stm32_port *stm32_port = to_stm32_port(port);
 171         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 172
 173         if (!stm32_port->rx_ch)
 174                 return false;
 175
 176         return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR);
 177 }
 178
 179 /* Return true when data is pending (in pio mode), and false when no data is pending. */
 180 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr)
 181 {
 182         struct stm32_port *stm32_port = to_stm32_port(port);
 183         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 184
 185         *sr = readl_relaxed(port->membase + ofs->isr);
 186         /* Get pending characters in RDR or FIFO */
 187         if (*sr & USART_SR_RXNE) {
 188                 /* Get all pending characters from the RDR or the FIFO when using interrupts */
 189                 if (!stm32_usart_rx_dma_enabled(port))
 190                         return true;
 191
 192                 /* Handle only RX data errors when using DMA */
 193                 if (*sr & USART_SR_ERR_MASK)
 194                         return true;
 195         }
 196
 197         return false;
 198 }
 199
 200 static unsigned long stm32_usart_get_char_pio(struct uart_port *port)
 201 {
 202         struct stm32_port *stm32_port = to_stm32_port(port);
 203         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 204         unsigned long c;
 205
 206         c = readl_relaxed(port->membase + ofs->rdr);
 207         /* Apply RDR data mask */
 208         c &= stm32_port->rdr_mask;
 209
 210         return c;
 211 }
 212
 213 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
 214 {
 215         struct stm32_port *stm32_port = to_stm32_port(port);
 216         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 217         unsigned long c;
 218         unsigned int size = 0;
 219         u32 sr;
 220         char flag;
 221
 222         while (stm32_usart_pending_rx_pio(port, &sr)) {
 223                 sr |= USART_SR_DUMMY_RX;
 224                 flag = TTY_NORMAL;
 225
 226                 /*
 227                  * Status bits has to be cleared before reading the RDR:
 228                  * In FIFO mode, reading the RDR will pop the next data
 229                  * (if any) along with its status bits into the SR.
 230                  * Not doing so leads to misalignement between RDR and SR,
 231                  * and clear status bits of the next rx data.
 232                  *
 233                  * Clear errors flags for stm32f7 and stm32h7 compatible
 234                  * devices. On stm32f4 compatible devices, the error bit is
 235                  * cleared by the sequence [read SR - read DR].
 236                  */
 237                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 238                         writel_relaxed(sr & USART_SR_ERR_MASK,
 239                                        port->membase + ofs->icr);
 240
 241                 c = stm32_usart_get_char_pio(port);
 242                 port->icount.rx++;
 243                 size++;
 244                 if (sr & USART_SR_ERR_MASK) {
 245                         if (sr & USART_SR_ORE) {
 246                                 port->icount.overrun++;
 247                         } else if (sr & USART_SR_PE) {
 248                                 port->icount.parity++;
 249                         } else if (sr & USART_SR_FE) {
 250                                 /* Break detection if character is null */
 251                                 if (!c) {
 252                                         port->icount.brk++;
 253                                         if (uart_handle_break(port))
 254                                                 continue;
 255                                 } else {
 256                                         port->icount.frame++;
 257                                 }
 258                         }
 259
 260                         sr &= port->read_status_mask;
 261
 262                         if (sr & USART_SR_PE) {
 263                                 flag = TTY_PARITY;
 264                         } else if (sr & USART_SR_FE) {
 265                                 if (!c)
 266                                         flag = TTY_BREAK;
 267                                 else
 268                                         flag = TTY_FRAME;
 269                         }
 270                 }
 271
 272                 if (uart_prepare_sysrq_char(port, c))
 273                         continue;
 274                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 275         }
 276
 277         return size;
 278 }
 279
 280 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size)
 281 {
 282         struct stm32_port *stm32_port = to_stm32_port(port);
 283         struct tty_port *ttyport = &stm32_port->port.state->port;
 284         unsigned char *dma_start;
 285         int dma_count, i;
 286
 287         dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res);
 288
 289         /*
 290          * Apply rdr_mask on buffer in order to mask parity bit.
 291          * This loop is useless in cs8 mode because DMA copies only
 292          * 8 bits and already ignores parity bit.
 293          */
 294         if (!(stm32_port->rdr_mask == (BIT(8) - 1)))
 295                 for (i = 0; i < dma_size; i++)
 296                         *(dma_start + i) &= stm32_port->rdr_mask;
 297
 298         dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size);
 299         port->icount.rx += dma_count;
 300         if (dma_count != dma_size)
 301                 port->icount.buf_overrun++;
 302         stm32_port->last_res -= dma_count;
 303         if (stm32_port->last_res == 0)
 304                 stm32_port->last_res = RX_BUF_L;
 305 }
 306
 307 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port)
 308 {
 309         struct stm32_port *stm32_port = to_stm32_port(port);
 310         unsigned int dma_size, size = 0;
 311
 312         /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */
 313         if (stm32_port->rx_dma_state.residue > stm32_port->last_res) {
 314                 /* Conditional first part: from last_res to end of DMA buffer */
 315                 dma_size = stm32_port->last_res;
 316                 stm32_usart_push_buffer_dma(port, dma_size);
 317                 size = dma_size;
 318         }
 319
 320         dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue;
 321         stm32_usart_push_buffer_dma(port, dma_size);
 322         size += dma_size;
 323
 324         return size;
 325 }
 326
 327 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush)
 328 {
 329         struct stm32_port *stm32_port = to_stm32_port(port);
 330         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 331         enum dma_status rx_dma_status;
 332         u32 sr;
 333         unsigned int size = 0;
 334
 335         if (stm32_usart_rx_dma_enabled(port) || force_dma_flush) {
 336                 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
 337                                                     stm32_port->rx_ch->cookie,
 338                                                     &stm32_port->rx_dma_state);
 339                 if (rx_dma_status == DMA_IN_PROGRESS) {
 340                         /* Empty DMA buffer */
 341                         size = stm32_usart_receive_chars_dma(port);
 342                         sr = readl_relaxed(port->membase + ofs->isr);
 343                         if (sr & USART_SR_ERR_MASK) {
 344                                 /* Disable DMA request line */
 345                                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 346
 347                                 /* Switch to PIO mode to handle the errors */
 348                                 size += stm32_usart_receive_chars_pio(port);
 349
 350                                 /* Switch back to DMA mode */
 351                                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
 352                         }
 353                 } else {
 354                         /* Disable RX DMA */
 355                         dmaengine_terminate_async(stm32_port->rx_ch);
 356                         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 357                         /* Fall back to interrupt mode */
 358                         dev_dbg(port->dev, "DMA error, fallback to irq mode\n");
 359                         size = stm32_usart_receive_chars_pio(port);
 360                 }
 361         } else {
 362                 size = stm32_usart_receive_chars_pio(port);
 363         }
 364
 365         return size;
 366 }
 367
 368 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
 369 {
 370         dmaengine_terminate_async(stm32_port->tx_ch);
 371         stm32_port->tx_dma_busy = false;
 372 }
 373
 374 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
 375 {
 376         /*
 377          * We cannot use the function "dmaengine_tx_status" to know the
 378          * status of DMA. This function does not show if the "dma complete"
 379          * callback of the DMA transaction has been called. So we prefer
 380          * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
 381          * same time.
 382          */
 383         return stm32_port->tx_dma_busy;
 384 }
 385
 386 static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port)
 387 {
 388         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 389
 390         return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT);
 391 }
 392
 393 static void stm32_usart_tx_dma_complete(void *arg)
 394 {
 395         struct uart_port *port = arg;
 396         struct stm32_port *stm32port = to_stm32_port(port);
 397         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 398         unsigned long flags;
 399
 400         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 401         stm32_usart_tx_dma_terminate(stm32port);
 402
 403         /* Let's see if we have pending data to send */
 404         spin_lock_irqsave(&port->lock, flags);
 405         stm32_usart_transmit_chars(port);
 406         spin_unlock_irqrestore(&port->lock, flags);
 407 }
 408
 409 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
 410 {
 411         struct stm32_port *stm32_port = to_stm32_port(port);
 412         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 413
 414         /*
 415          * Enables TX FIFO threashold irq when FIFO is enabled,
 416          * or TX empty irq when FIFO is disabled
 417          */
 418         if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
 419                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 420         else
 421                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 422 }
 423
 424 static void stm32_usart_rx_dma_complete(void *arg)
 425 {
 426         struct uart_port *port = arg;
 427         struct tty_port *tport = &port->state->port;
 428         unsigned int size;
 429         unsigned long flags;
 430
 431         spin_lock_irqsave(&port->lock, flags);
 432         size = stm32_usart_receive_chars(port, false);
 433         uart_unlock_and_check_sysrq_irqrestore(port, flags);
 434         if (size)
 435                 tty_flip_buffer_push(tport);
 436 }
 437
 438 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
 439 {
 440         struct stm32_port *stm32_port = to_stm32_port(port);
 441         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 442
 443         if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
 444                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 445         else
 446                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 447 }
 448
 449 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
 450 {
 451         struct stm32_port *stm32_port = to_stm32_port(port);
 452         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 453         struct circ_buf *xmit = &port->state->xmit;
 454
 455         if (stm32_usart_tx_dma_enabled(stm32_port))
 456                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 457
 458         while (!uart_circ_empty(xmit)) {
 459                 /* Check that TDR is empty before filling FIFO */
 460                 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 461                         break;
 462                 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 463                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 464                 port->icount.tx++;
 465         }
 466
 467         /* rely on TXE irq (mask or unmask) for sending remaining data */
 468         if (uart_circ_empty(xmit))
 469                 stm32_usart_tx_interrupt_disable(port);
 470         else
 471                 stm32_usart_tx_interrupt_enable(port);
 472 }
 473
 474 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
 475 {
 476         struct stm32_port *stm32port = to_stm32_port(port);
 477         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 478         struct circ_buf *xmit = &port->state->xmit;
 479         struct dma_async_tx_descriptor *desc = NULL;
 480         unsigned int count;
 481
 482         if (stm32_usart_tx_dma_started(stm32port)) {
 483                 if (!stm32_usart_tx_dma_enabled(stm32port))
 484                         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 485                 return;
 486         }
 487
 488         count = uart_circ_chars_pending(xmit);
 489
 490         if (count > TX_BUF_L)
 491                 count = TX_BUF_L;
 492
 493         if (xmit->tail < xmit->head) {
 494                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 495         } else {
 496                 size_t one = UART_XMIT_SIZE - xmit->tail;
 497                 size_t two;
 498
 499                 if (one > count)
 500                         one = count;
 501                 two = count - one;
 502
 503                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 504                 if (two)
 505                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 506         }
 507
 508         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 509                                            stm32port->tx_dma_buf,
 510                                            count,
 511                                            DMA_MEM_TO_DEV,
 512                                            DMA_PREP_INTERRUPT);
 513
 514         if (!desc)
 515                 goto fallback_err;
 516
 517         /*
 518          * Set "tx_dma_busy" flag. This flag will be released when
 519          * dmaengine_terminate_async will be called. This flag helps
 520          * transmit_chars_dma not to start another DMA transaction
 521          * if the callback of the previous is not yet called.
 522          */
 523         stm32port->tx_dma_busy = true;
 524
 525         desc->callback = stm32_usart_tx_dma_complete;
 526         desc->callback_param = port;
 527
 528         /* Push current DMA TX transaction in the pending queue */
 529         if (dma_submit_error(dmaengine_submit(desc))) {
 530                 /* dma no yet started, safe to free resources */
 531                 stm32_usart_tx_dma_terminate(stm32port);
 532                 goto fallback_err;
 533         }
 534
 535         /* Issue pending DMA TX requests */
 536         dma_async_issue_pending(stm32port->tx_ch);
 537
 538         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 539
 540         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 541         port->icount.tx += count;
 542         return;
 543
 544 fallback_err:
 545         stm32_usart_transmit_chars_pio(port);
 546 }
 547
 548 static void stm32_usart_transmit_chars(struct uart_port *port)
 549 {
 550         struct stm32_port *stm32_port = to_stm32_port(port);
 551         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 552         struct circ_buf *xmit = &port->state->xmit;
 553         u32 isr;
 554         int ret;
 555
 556         if (port->x_char) {
 557                 if (stm32_usart_tx_dma_started(stm32_port) &&
 558                     stm32_usart_tx_dma_enabled(stm32_port))
 559                         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 560
 561                 /* Check that TDR is empty before filling FIFO */
 562                 ret =
 563                 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 564                                                   isr,
 565                                                   (isr & USART_SR_TXE),
 566                                                   10, 1000);
 567                 if (ret)
 568                         dev_warn(port->dev, "1 character may be erased\n");
 569
 570                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 571                 port->x_char = 0;
 572                 port->icount.tx++;
 573                 if (stm32_usart_tx_dma_started(stm32_port))
 574                         stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 575                 return;
 576         }
 577
 578         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 579                 stm32_usart_tx_interrupt_disable(port);
 580                 return;
 581         }
 582
 583         if (ofs->icr == UNDEF_REG)
 584                 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
 585         else
 586                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 587
 588         if (stm32_port->tx_ch)
 589                 stm32_usart_transmit_chars_dma(port);
 590         else
 591                 stm32_usart_transmit_chars_pio(port);
 592
 593         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 594                 uart_write_wakeup(port);
 595
 596         if (uart_circ_empty(xmit))
 597                 stm32_usart_tx_interrupt_disable(port);
 598 }
 599
 600 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
 601 {
 602         struct uart_port *port = ptr;
 603         struct tty_port *tport = &port->state->port;
 604         struct stm32_port *stm32_port = to_stm32_port(port);
 605         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 606         u32 sr;
 607         unsigned int size;
 608
 609         sr = readl_relaxed(port->membase + ofs->isr);
 610
 611         if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
 612                 writel_relaxed(USART_ICR_RTOCF,
 613                                port->membase + ofs->icr);
 614
 615         if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
 616                 /* Clear wake up flag and disable wake up interrupt */
 617                 writel_relaxed(USART_ICR_WUCF,
 618                                port->membase + ofs->icr);
 619                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
 620                 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 621                         pm_wakeup_event(tport->tty->dev, 0);
 622         }
 623
 624         /*
 625          * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
 626          * line has been masked by HW and rx data are stacking in FIFO.
 627          */
 628         if (!stm32_port->throttled) {
 629                 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_enabled(port)) ||
 630                     ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_enabled(port))) {
 631                         spin_lock(&port->lock);
 632                         size = stm32_usart_receive_chars(port, false);
 633                         uart_unlock_and_check_sysrq(port);
 634                         if (size)
 635                                 tty_flip_buffer_push(tport);
 636                 }
 637         }
 638
 639         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
 640                 spin_lock(&port->lock);
 641                 stm32_usart_transmit_chars(port);
 642                 spin_unlock(&port->lock);
 643         }
 644
 645         if (stm32_usart_rx_dma_enabled(port))
 646                 return IRQ_WAKE_THREAD;
 647         else
 648                 return IRQ_HANDLED;
 649 }
 650
 651 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
 652 {
 653         struct uart_port *port = ptr;
 654         struct tty_port *tport = &port->state->port;
 655         struct stm32_port *stm32_port = to_stm32_port(port);
 656         unsigned int size;
 657         unsigned long flags;
 658
 659         /* Receiver timeout irq for DMA RX */
 660         if (!stm32_port->throttled) {
 661                 spin_lock_irqsave(&port->lock, flags);
 662                 size = stm32_usart_receive_chars(port, false);
 663                 uart_unlock_and_check_sysrq_irqrestore(port, flags);
 664                 if (size)
 665                         tty_flip_buffer_push(tport);
 666         }
 667
 668         return IRQ_HANDLED;
 669 }
 670
 671 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
 672 {
 673         struct stm32_port *stm32_port = to_stm32_port(port);
 674         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 675
 676         if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
 677                 return TIOCSER_TEMT;
 678
 679         return 0;
 680 }
 681
 682 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 683 {
 684         struct stm32_port *stm32_port = to_stm32_port(port);
 685         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 686
 687         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 688                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 689         else
 690                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 691
 692         mctrl_gpio_set(stm32_port->gpios, mctrl);
 693 }
 694
 695 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
 696 {
 697         struct stm32_port *stm32_port = to_stm32_port(port);
 698         unsigned int ret;
 699
 700         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 701         ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 702
 703         return mctrl_gpio_get(stm32_port->gpios, &ret);
 704 }
 705
 706 static void stm32_usart_enable_ms(struct uart_port *port)
 707 {
 708         mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
 709 }
 710
 711 static void stm32_usart_disable_ms(struct uart_port *port)
 712 {
 713         mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
 714 }
 715
 716 /* Transmit stop */
 717 static void stm32_usart_stop_tx(struct uart_port *port)
 718 {
 719         struct stm32_port *stm32_port = to_stm32_port(port);
 720         struct serial_rs485 *rs485conf = &port->rs485;
 721         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 722
 723         stm32_usart_tx_interrupt_disable(port);
 724         if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))
 725                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 726
 727         if (rs485conf->flags & SER_RS485_ENABLED) {
 728                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 729                         mctrl_gpio_set(stm32_port->gpios,
 730                                         stm32_port->port.mctrl & ~TIOCM_RTS);
 731                 } else {
 732                         mctrl_gpio_set(stm32_port->gpios,
 733                                         stm32_port->port.mctrl | TIOCM_RTS);
 734                 }
 735         }
 736 }
 737
 738 /* There are probably characters waiting to be transmitted. */
 739 static void stm32_usart_start_tx(struct uart_port *port)
 740 {
 741         struct stm32_port *stm32_port = to_stm32_port(port);
 742         struct serial_rs485 *rs485conf = &port->rs485;
 743         struct circ_buf *xmit = &port->state->xmit;
 744
 745         if (uart_circ_empty(xmit) && !port->x_char)
 746                 return;
 747
 748         if (rs485conf->flags & SER_RS485_ENABLED) {
 749                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 750                         mctrl_gpio_set(stm32_port->gpios,
 751                                         stm32_port->port.mctrl | TIOCM_RTS);
 752                 } else {
 753                         mctrl_gpio_set(stm32_port->gpios,
 754                                         stm32_port->port.mctrl & ~TIOCM_RTS);
 755                 }
 756         }
 757
 758         stm32_usart_transmit_chars(port);
 759 }
 760
 761 /* Flush the transmit buffer. */
 762 static void stm32_usart_flush_buffer(struct uart_port *port)
 763 {
 764         struct stm32_port *stm32_port = to_stm32_port(port);
 765         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 766
 767         if (stm32_port->tx_ch) {
 768                 stm32_usart_tx_dma_terminate(stm32_port);
 769                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 770         }
 771 }
 772
 773 /* Throttle the remote when input buffer is about to overflow. */
 774 static void stm32_usart_throttle(struct uart_port *port)
 775 {
 776         struct stm32_port *stm32_port = to_stm32_port(port);
 777         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 778         unsigned long flags;
 779
 780         spin_lock_irqsave(&port->lock, flags);
 781
 782         /*
 783          * Disable DMA request line if enabled, so the RX data gets queued into the FIFO.
 784          * Hardware flow control is triggered when RX FIFO is full.
 785          */
 786         if (stm32_usart_rx_dma_enabled(port))
 787                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 788
 789         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
 790         if (stm32_port->cr3_irq)
 791                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
 792
 793         stm32_port->throttled = true;
 794         spin_unlock_irqrestore(&port->lock, flags);
 795 }
 796
 797 /* Unthrottle the remote, the input buffer can now accept data. */
 798 static void stm32_usart_unthrottle(struct uart_port *port)
 799 {
 800         struct stm32_port *stm32_port = to_stm32_port(port);
 801         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 802         unsigned long flags;
 803
 804         spin_lock_irqsave(&port->lock, flags);
 805         stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
 806         if (stm32_port->cr3_irq)
 807                 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
 808
 809         /*
 810          * Switch back to DMA mode (re-enable DMA request line).
 811          * Hardware flow control is stopped when FIFO is not full any more.
 812          */
 813         if (stm32_port->rx_ch)
 814                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
 815
 816         stm32_port->throttled = false;
 817         spin_unlock_irqrestore(&port->lock, flags);
 818 }
 819
 820 /* Receive stop */
 821 static void stm32_usart_stop_rx(struct uart_port *port)
 822 {
 823         struct stm32_port *stm32_port = to_stm32_port(port);
 824         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 825
 826         /* Disable DMA request line. */
 827         if (stm32_port->rx_ch)
 828                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 829
 830         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
 831         if (stm32_port->cr3_irq)
 832                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
 833 }
 834
 835 /* Handle breaks - ignored by us */
 836 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
 837 {
 838 }
 839
 840 static int stm32_usart_start_rx_dma_cyclic(struct uart_port *port)
 841 {
 842         struct stm32_port *stm32_port = to_stm32_port(port);
 843         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 844         struct dma_async_tx_descriptor *desc;
 845         int ret;
 846
 847         stm32_port->last_res = RX_BUF_L;
 848         /* Prepare a DMA cyclic transaction */
 849         desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
 850                                          stm32_port->rx_dma_buf,
 851                                          RX_BUF_L, RX_BUF_P,
 852                                          DMA_DEV_TO_MEM,
 853                                          DMA_PREP_INTERRUPT);
 854         if (!desc) {
 855                 dev_err(port->dev, "rx dma prep cyclic failed\n");
 856                 return -ENODEV;
 857         }
 858
 859         desc->callback = stm32_usart_rx_dma_complete;
 860         desc->callback_param = port;
 861
 862         /* Push current DMA transaction in the pending queue */
 863         ret = dma_submit_error(dmaengine_submit(desc));
 864         if (ret) {
 865                 dmaengine_terminate_sync(stm32_port->rx_ch);
 866                 return ret;
 867         }
 868
 869         /* Issue pending DMA requests */
 870         dma_async_issue_pending(stm32_port->rx_ch);
 871
 872         /*
 873          * DMA request line not re-enabled at resume when port is throttled.
 874          * It will be re-enabled by unthrottle ops.
 875          */
 876         if (!stm32_port->throttled)
 877                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
 878
 879         return 0;
 880 }
 881
 882 static int stm32_usart_startup(struct uart_port *port)
 883 {
 884         struct stm32_port *stm32_port = to_stm32_port(port);
 885         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 886         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 887         const char *name = to_platform_device(port->dev)->name;
 888         u32 val;
 889         int ret;
 890
 891         ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
 892                                    stm32_usart_threaded_interrupt,
 893                                    IRQF_ONESHOT | IRQF_NO_SUSPEND,
 894                                    name, port);
 895         if (ret)
 896                 return ret;
 897
 898         if (stm32_port->swap) {
 899                 val = readl_relaxed(port->membase + ofs->cr2);
 900                 val |= USART_CR2_SWAP;
 901                 writel_relaxed(val, port->membase + ofs->cr2);
 902         }
 903
 904         /* RX FIFO Flush */
 905         if (ofs->rqr != UNDEF_REG)
 906                 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
 907
 908         if (stm32_port->rx_ch) {
 909                 ret = stm32_usart_start_rx_dma_cyclic(port);
 910                 if (ret) {
 911                         free_irq(port->irq, port);
 912                         return ret;
 913                 }
 914         }
 915
 916         /* RX enabling */
 917         val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
 918         stm32_usart_set_bits(port, ofs->cr1, val);
 919
 920         return 0;
 921 }
 922
 923 static void stm32_usart_shutdown(struct uart_port *port)
 924 {
 925         struct stm32_port *stm32_port = to_stm32_port(port);
 926         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 927         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 928         u32 val, isr;
 929         int ret;
 930
 931         if (stm32_usart_tx_dma_enabled(stm32_port))
 932                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 933
 934         if (stm32_usart_tx_dma_started(stm32_port))
 935                 stm32_usart_tx_dma_terminate(stm32_port);
 936
 937         /* Disable modem control interrupts */
 938         stm32_usart_disable_ms(port);
 939
 940         val = USART_CR1_TXEIE | USART_CR1_TE;
 941         val |= stm32_port->cr1_irq | USART_CR1_RE;
 942         val |= BIT(cfg->uart_enable_bit);
 943         if (stm32_port->fifoen)
 944                 val |= USART_CR1_FIFOEN;
 945
 946         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
 947                                          isr, (isr & USART_SR_TC),
 948                                          10, 100000);
 949
 950         /* Send the TC error message only when ISR_TC is not set */
 951         if (ret)
 952                 dev_err(port->dev, "Transmission is not complete\n");
 953
 954         /* Disable RX DMA. */
 955         if (stm32_port->rx_ch)
 956                 dmaengine_terminate_async(stm32_port->rx_ch);
 957
 958         /* flush RX & TX FIFO */
 959         if (ofs->rqr != UNDEF_REG)
 960                 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
 961                                port->membase + ofs->rqr);
 962
 963         stm32_usart_clr_bits(port, ofs->cr1, val);
 964
 965         free_irq(port->irq, port);
 966 }
 967
 968 static void stm32_usart_set_termios(struct uart_port *port,
 969                                     struct ktermios *termios,
 970                                     struct ktermios *old)
 971 {
 972         struct stm32_port *stm32_port = to_stm32_port(port);
 973         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 974         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 975         struct serial_rs485 *rs485conf = &port->rs485;
 976         unsigned int baud, bits;
 977         u32 usartdiv, mantissa, fraction, oversampling;
 978         tcflag_t cflag = termios->c_cflag;
 979         u32 cr1, cr2, cr3, isr;
 980         unsigned long flags;
 981         int ret;
 982
 983         if (!stm32_port->hw_flow_control)
 984                 cflag &= ~CRTSCTS;
 985
 986         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 987
 988         spin_lock_irqsave(&port->lock, flags);
 989
 990         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 991                                                 isr,
 992                                                 (isr & USART_SR_TC),
 993                                                 10, 100000);
 994
 995         /* Send the TC error message only when ISR_TC is not set. */
 996         if (ret)
 997                 dev_err(port->dev, "Transmission is not complete\n");
 998
 999         /* Stop serial port and reset value */
1000         writel_relaxed(0, port->membase + ofs->cr1);
1001
1002         /* flush RX & TX FIFO */
1003         if (ofs->rqr != UNDEF_REG)
1004                 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1005                                port->membase + ofs->rqr);
1006
1007         cr1 = USART_CR1_TE | USART_CR1_RE;
1008         if (stm32_port->fifoen)
1009                 cr1 |= USART_CR1_FIFOEN;
1010         cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
1011
1012         /* Tx and RX FIFO configuration */
1013         cr3 = readl_relaxed(port->membase + ofs->cr3);
1014         cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
1015         if (stm32_port->fifoen) {
1016                 if (stm32_port->txftcfg >= 0)
1017                         cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
1018                 if (stm32_port->rxftcfg >= 0)
1019                         cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
1020         }
1021
1022         if (cflag & CSTOPB)
1023                 cr2 |= USART_CR2_STOP_2B;
1024
1025         bits = tty_get_char_size(cflag);
1026         stm32_port->rdr_mask = (BIT(bits) - 1);
1027
1028         if (cflag & PARENB) {
1029                 bits++;
1030                 cr1 |= USART_CR1_PCE;
1031         }
1032
1033         /*
1034          * Word length configuration:
1035          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
1036          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
1037          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
1038          * M0 and M1 already cleared by cr1 initialization.
1039          */
1040         if (bits == 9)
1041                 cr1 |= USART_CR1_M0;
1042         else if ((bits == 7) && cfg->has_7bits_data)
1043                 cr1 |= USART_CR1_M1;
1044         else if (bits != 8)
1045                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
1046                         , bits);
1047
1048         if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
1049                                        (stm32_port->fifoen &&
1050                                         stm32_port->rxftcfg >= 0))) {
1051                 if (cflag & CSTOPB)
1052                         bits = bits + 3; /* 1 start bit + 2 stop bits */
1053                 else
1054                         bits = bits + 2; /* 1 start bit + 1 stop bit */
1055
1056                 /* RX timeout irq to occur after last stop bit + bits */
1057                 stm32_port->cr1_irq = USART_CR1_RTOIE;
1058                 writel_relaxed(bits, port->membase + ofs->rtor);
1059                 cr2 |= USART_CR2_RTOEN;
1060                 /*
1061                  * Enable fifo threshold irq in two cases, either when there is no DMA, or when
1062                  * wake up over usart, from low power until the DMA gets re-enabled by resume.
1063                  */
1064                 stm32_port->cr3_irq =  USART_CR3_RXFTIE;
1065         }
1066
1067         cr1 |= stm32_port->cr1_irq;
1068         cr3 |= stm32_port->cr3_irq;
1069
1070         if (cflag & PARODD)
1071                 cr1 |= USART_CR1_PS;
1072
1073         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1074         if (cflag & CRTSCTS) {
1075                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1076                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
1077         }
1078
1079         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
1080
1081         /*
1082          * The USART supports 16 or 8 times oversampling.
1083          * By default we prefer 16 times oversampling, so that the receiver
1084          * has a better tolerance to clock deviations.
1085          * 8 times oversampling is only used to achieve higher speeds.
1086          */
1087         if (usartdiv < 16) {
1088                 oversampling = 8;
1089                 cr1 |= USART_CR1_OVER8;
1090                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
1091         } else {
1092                 oversampling = 16;
1093                 cr1 &= ~USART_CR1_OVER8;
1094                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
1095         }
1096
1097         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
1098         fraction = usartdiv % oversampling;
1099         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
1100
1101         uart_update_timeout(port, cflag, baud);
1102
1103         port->read_status_mask = USART_SR_ORE;
1104         if (termios->c_iflag & INPCK)
1105                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
1106         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1107                 port->read_status_mask |= USART_SR_FE;
1108
1109         /* Characters to ignore */
1110         port->ignore_status_mask = 0;
1111         if (termios->c_iflag & IGNPAR)
1112                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
1113         if (termios->c_iflag & IGNBRK) {
1114                 port->ignore_status_mask |= USART_SR_FE;
1115                 /*
1116                  * If we're ignoring parity and break indicators,
1117                  * ignore overruns too (for real raw support).
1118                  */
1119                 if (termios->c_iflag & IGNPAR)
1120                         port->ignore_status_mask |= USART_SR_ORE;
1121         }
1122
1123         /* Ignore all characters if CREAD is not set */
1124         if ((termios->c_cflag & CREAD) == 0)
1125                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
1126
1127         if (stm32_port->rx_ch) {
1128                 /*
1129                  * Setup DMA to collect only valid data and enable error irqs.
1130                  * This also enables break reception when using DMA.
1131                  */
1132                 cr1 |= USART_CR1_PEIE;
1133                 cr3 |= USART_CR3_EIE;
1134                 cr3 |= USART_CR3_DMAR;
1135                 cr3 |= USART_CR3_DDRE;
1136         }
1137
1138         if (rs485conf->flags & SER_RS485_ENABLED) {
1139                 stm32_usart_config_reg_rs485(&cr1, &cr3,
1140                                              rs485conf->delay_rts_before_send,
1141                                              rs485conf->delay_rts_after_send,
1142                                              baud);
1143                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1144                         cr3 &= ~USART_CR3_DEP;
1145                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1146                 } else {
1147                         cr3 |= USART_CR3_DEP;
1148                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1149                 }
1150
1151         } else {
1152                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
1153                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
1154         }
1155
1156         /* Configure wake up from low power on start bit detection */
1157         if (stm32_port->wakeup_src) {
1158                 cr3 &= ~USART_CR3_WUS_MASK;
1159                 cr3 |= USART_CR3_WUS_START_BIT;
1160         }
1161
1162         writel_relaxed(cr3, port->membase + ofs->cr3);
1163         writel_relaxed(cr2, port->membase + ofs->cr2);
1164         writel_relaxed(cr1, port->membase + ofs->cr1);
1165
1166         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1167         spin_unlock_irqrestore(&port->lock, flags);
1168
1169         /* Handle modem control interrupts */
1170         if (UART_ENABLE_MS(port, termios->c_cflag))
1171                 stm32_usart_enable_ms(port);
1172         else
1173                 stm32_usart_disable_ms(port);
1174 }
1175
1176 static const char *stm32_usart_type(struct uart_port *port)
1177 {
1178         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
1179 }
1180
1181 static void stm32_usart_release_port(struct uart_port *port)
1182 {
1183 }
1184
1185 static int stm32_usart_request_port(struct uart_port *port)
1186 {
1187         return 0;
1188 }
1189
1190 static void stm32_usart_config_port(struct uart_port *port, int flags)
1191 {
1192         if (flags & UART_CONFIG_TYPE)
1193                 port->type = PORT_STM32;
1194 }
1195
1196 static int
1197 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
1198 {
1199         /* No user changeable parameters */
1200         return -EINVAL;
1201 }
1202
1203 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
1204                            unsigned int oldstate)
1205 {
1206         struct stm32_port *stm32port = container_of(port,
1207                         struct stm32_port, port);
1208         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1209         const struct stm32_usart_config *cfg = &stm32port->info->cfg;
1210         unsigned long flags;
1211
1212         switch (state) {
1213         case UART_PM_STATE_ON:
1214                 pm_runtime_get_sync(port->dev);
1215                 break;
1216         case UART_PM_STATE_OFF:
1217                 spin_lock_irqsave(&port->lock, flags);
1218                 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1219                 spin_unlock_irqrestore(&port->lock, flags);
1220                 pm_runtime_put_sync(port->dev);
1221                 break;
1222         }
1223 }
1224
1225 static const struct uart_ops stm32_uart_ops = {
1226         .tx_empty       = stm32_usart_tx_empty,
1227         .set_mctrl      = stm32_usart_set_mctrl,
1228         .get_mctrl      = stm32_usart_get_mctrl,
1229         .stop_tx        = stm32_usart_stop_tx,
1230         .start_tx       = stm32_usart_start_tx,
1231         .throttle       = stm32_usart_throttle,
1232         .unthrottle     = stm32_usart_unthrottle,
1233         .stop_rx        = stm32_usart_stop_rx,
1234         .enable_ms      = stm32_usart_enable_ms,
1235         .break_ctl      = stm32_usart_break_ctl,
1236         .startup        = stm32_usart_startup,
1237         .shutdown       = stm32_usart_shutdown,
1238         .flush_buffer   = stm32_usart_flush_buffer,
1239         .set_termios    = stm32_usart_set_termios,
1240         .pm             = stm32_usart_pm,
1241         .type           = stm32_usart_type,
1242         .release_port   = stm32_usart_release_port,
1243         .request_port   = stm32_usart_request_port,
1244         .config_port    = stm32_usart_config_port,
1245         .verify_port    = stm32_usart_verify_port,
1246 };
1247
1248 /*
1249  * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1250  * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case,
1251  * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE.
1252  * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1.
1253  */
1254 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 };
1255
1256 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p,
1257                                   int *ftcfg)
1258 {
1259         u32 bytes, i;
1260
1261         /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */
1262         if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1263                 bytes = 8;
1264
1265         for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++)
1266                 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes)
1267                         break;
1268         if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1269                 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1270
1271         dev_dbg(&pdev->dev, "%s set to %d bytes\n", p,
1272                 stm32h7_usart_fifo_thresh_cfg[i]);
1273
1274         /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */
1275         if (i)
1276                 *ftcfg = i - 1;
1277         else
1278                 *ftcfg = -EINVAL;
1279 }
1280
1281 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1282 {
1283         clk_disable_unprepare(stm32port->clk);
1284 }
1285
1286 static int stm32_usart_init_port(struct stm32_port *stm32port,
1287                                  struct platform_device *pdev)
1288 {
1289         struct uart_port *port = &stm32port->port;
1290         struct resource *res;
1291         int ret, irq;
1292
1293         irq = platform_get_irq(pdev, 0);
1294         if (irq < 0)
1295                 return irq;
1296
1297         port->iotype    = UPIO_MEM;
1298         port->flags     = UPF_BOOT_AUTOCONF;
1299         port->ops       = &stm32_uart_ops;
1300         port->dev       = &pdev->dev;
1301         port->fifosize  = stm32port->info->cfg.fifosize;
1302         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1303         port->irq = irq;
1304         port->rs485_config = stm32_usart_config_rs485;
1305
1306         ret = stm32_usart_init_rs485(port, pdev);
1307         if (ret)
1308                 return ret;
1309
1310         stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1311                 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1312
1313         stm32port->swap = stm32port->info->cfg.has_swap &&
1314                 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1315
1316         stm32port->fifoen = stm32port->info->cfg.has_fifo;
1317         if (stm32port->fifoen) {
1318                 stm32_usart_get_ftcfg(pdev, "rx-threshold",
1319                                       &stm32port->rxftcfg);
1320                 stm32_usart_get_ftcfg(pdev, "tx-threshold",
1321                                       &stm32port->txftcfg);
1322         }
1323
1324         port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1325         if (IS_ERR(port->membase))
1326                 return PTR_ERR(port->membase);
1327         port->mapbase = res->start;
1328
1329         spin_lock_init(&port->lock);
1330
1331         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1332         if (IS_ERR(stm32port->clk))
1333                 return PTR_ERR(stm32port->clk);
1334
1335         /* Ensure that clk rate is correct by enabling the clk */
1336         ret = clk_prepare_enable(stm32port->clk);
1337         if (ret)
1338                 return ret;
1339
1340         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1341         if (!stm32port->port.uartclk) {
1342                 ret = -EINVAL;
1343                 goto err_clk;
1344         }
1345
1346         stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1347         if (IS_ERR(stm32port->gpios)) {
1348                 ret = PTR_ERR(stm32port->gpios);
1349                 goto err_clk;
1350         }
1351
1352         /*
1353          * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1354          * properties should not be specified.
1355          */
1356         if (stm32port->hw_flow_control) {
1357                 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1358                     mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1359                         dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1360                         ret = -EINVAL;
1361                         goto err_clk;
1362                 }
1363         }
1364
1365         return ret;
1366
1367 err_clk:
1368         clk_disable_unprepare(stm32port->clk);
1369
1370         return ret;
1371 }
1372
1373 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1374 {
1375         struct device_node *np = pdev->dev.of_node;
1376         int id;
1377
1378         if (!np)
1379                 return NULL;
1380
1381         id = of_alias_get_id(np, "serial");
1382         if (id < 0) {
1383                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1384                 return NULL;
1385         }
1386
1387         if (WARN_ON(id >= STM32_MAX_PORTS))
1388                 return NULL;
1389
1390         stm32_ports[id].hw_flow_control =
1391                 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1392                 of_property_read_bool (np, "uart-has-rtscts");
1393         stm32_ports[id].port.line = id;
1394         stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1395         stm32_ports[id].cr3_irq = 0;
1396         stm32_ports[id].last_res = RX_BUF_L;
1397         return &stm32_ports[id];
1398 }
1399
1400 #ifdef CONFIG_OF
1401 static const struct of_device_id stm32_match[] = {
1402         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1403         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1404         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1405         {},
1406 };
1407
1408 MODULE_DEVICE_TABLE(of, stm32_match);
1409 #endif
1410
1411 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1412                                          struct platform_device *pdev)
1413 {
1414         if (stm32port->rx_buf)
1415                 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1416                                   stm32port->rx_dma_buf);
1417 }
1418
1419 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1420                                        struct platform_device *pdev)
1421 {
1422         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1423         struct uart_port *port = &stm32port->port;
1424         struct device *dev = &pdev->dev;
1425         struct dma_slave_config config;
1426         int ret;
1427
1428         /*
1429          * Using DMA and threaded handler for the console could lead to
1430          * deadlocks.
1431          */
1432         if (uart_console(port))
1433                 return -ENODEV;
1434
1435         stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L,
1436                                                &stm32port->rx_dma_buf,
1437                                                GFP_KERNEL);
1438         if (!stm32port->rx_buf)
1439                 return -ENOMEM;
1440
1441         /* Configure DMA channel */
1442         memset(&config, 0, sizeof(config));
1443         config.src_addr = port->mapbase + ofs->rdr;
1444         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1445
1446         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1447         if (ret < 0) {
1448                 dev_err(dev, "rx dma channel config failed\n");
1449                 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1450                 return ret;
1451         }
1452
1453         return 0;
1454 }
1455
1456 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1457                                          struct platform_device *pdev)
1458 {
1459         if (stm32port->tx_buf)
1460                 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1461                                   stm32port->tx_dma_buf);
1462 }
1463
1464 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1465                                        struct platform_device *pdev)
1466 {
1467         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1468         struct uart_port *port = &stm32port->port;
1469         struct device *dev = &pdev->dev;
1470         struct dma_slave_config config;
1471         int ret;
1472
1473         stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1474                                                &stm32port->tx_dma_buf,
1475                                                GFP_KERNEL);
1476         if (!stm32port->tx_buf)
1477                 return -ENOMEM;
1478
1479         /* Configure DMA channel */
1480         memset(&config, 0, sizeof(config));
1481         config.dst_addr = port->mapbase + ofs->tdr;
1482         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1483
1484         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1485         if (ret < 0) {
1486                 dev_err(dev, "tx dma channel config failed\n");
1487                 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1488                 return ret;
1489         }
1490
1491         return 0;
1492 }
1493
1494 static int stm32_usart_serial_probe(struct platform_device *pdev)
1495 {
1496         struct stm32_port *stm32port;
1497         int ret;
1498
1499         stm32port = stm32_usart_of_get_port(pdev);
1500         if (!stm32port)
1501                 return -ENODEV;
1502
1503         stm32port->info = of_device_get_match_data(&pdev->dev);
1504         if (!stm32port->info)
1505                 return -EINVAL;
1506
1507         ret = stm32_usart_init_port(stm32port, pdev);
1508         if (ret)
1509                 return ret;
1510
1511         if (stm32port->wakeup_src) {
1512                 device_set_wakeup_capable(&pdev->dev, true);
1513                 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1514                 if (ret)
1515                         goto err_deinit_port;
1516         }
1517
1518         stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1519         if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) {
1520                 ret = -EPROBE_DEFER;
1521                 goto err_wakeirq;
1522         }
1523         /* Fall back in interrupt mode for any non-deferral error */
1524         if (IS_ERR(stm32port->rx_ch))
1525                 stm32port->rx_ch = NULL;
1526
1527         stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1528         if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1529                 ret = -EPROBE_DEFER;
1530                 goto err_dma_rx;
1531         }
1532         /* Fall back in interrupt mode for any non-deferral error */
1533         if (IS_ERR(stm32port->tx_ch))
1534                 stm32port->tx_ch = NULL;
1535
1536         if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1537                 /* Fall back in interrupt mode */
1538                 dma_release_channel(stm32port->rx_ch);
1539                 stm32port->rx_ch = NULL;
1540         }
1541
1542         if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1543                 /* Fall back in interrupt mode */
1544                 dma_release_channel(stm32port->tx_ch);
1545                 stm32port->tx_ch = NULL;
1546         }
1547
1548         if (!stm32port->rx_ch)
1549                 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1550         if (!stm32port->tx_ch)
1551                 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1552
1553         platform_set_drvdata(pdev, &stm32port->port);
1554
1555         pm_runtime_get_noresume(&pdev->dev);
1556         pm_runtime_set_active(&pdev->dev);
1557         pm_runtime_enable(&pdev->dev);
1558
1559         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1560         if (ret)
1561                 goto err_port;
1562
1563         pm_runtime_put_sync(&pdev->dev);
1564
1565         return 0;
1566
1567 err_port:
1568         pm_runtime_disable(&pdev->dev);
1569         pm_runtime_set_suspended(&pdev->dev);
1570         pm_runtime_put_noidle(&pdev->dev);
1571
1572         if (stm32port->tx_ch) {
1573                 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1574                 dma_release_channel(stm32port->tx_ch);
1575         }
1576
1577         if (stm32port->rx_ch)
1578                 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1579
1580 err_dma_rx:
1581         if (stm32port->rx_ch)
1582                 dma_release_channel(stm32port->rx_ch);
1583
1584 err_wakeirq:
1585         if (stm32port->wakeup_src)
1586                 dev_pm_clear_wake_irq(&pdev->dev);
1587
1588 err_deinit_port:
1589         if (stm32port->wakeup_src)
1590                 device_set_wakeup_capable(&pdev->dev, false);
1591
1592         stm32_usart_deinit_port(stm32port);
1593
1594         return ret;
1595 }
1596
1597 static int stm32_usart_serial_remove(struct platform_device *pdev)
1598 {
1599         struct uart_port *port = platform_get_drvdata(pdev);
1600         struct stm32_port *stm32_port = to_stm32_port(port);
1601         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1602         int err;
1603         u32 cr3;
1604
1605         pm_runtime_get_sync(&pdev->dev);
1606         err = uart_remove_one_port(&stm32_usart_driver, port);
1607         if (err)
1608                 return(err);
1609
1610         pm_runtime_disable(&pdev->dev);
1611         pm_runtime_set_suspended(&pdev->dev);
1612         pm_runtime_put_noidle(&pdev->dev);
1613
1614         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
1615         cr3 = readl_relaxed(port->membase + ofs->cr3);
1616         cr3 &= ~USART_CR3_EIE;
1617         cr3 &= ~USART_CR3_DMAR;
1618         cr3 &= ~USART_CR3_DDRE;
1619         writel_relaxed(cr3, port->membase + ofs->cr3);
1620
1621         if (stm32_port->tx_ch) {
1622                 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1623                 dma_release_channel(stm32_port->tx_ch);
1624         }
1625
1626         if (stm32_port->rx_ch) {
1627                 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1628                 dma_release_channel(stm32_port->rx_ch);
1629         }
1630
1631         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1632
1633         if (stm32_port->wakeup_src) {
1634                 dev_pm_clear_wake_irq(&pdev->dev);
1635                 device_init_wakeup(&pdev->dev, false);
1636         }
1637
1638         stm32_usart_deinit_port(stm32_port);
1639
1640         return 0;
1641 }
1642
1643 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1644 static void stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1645 {
1646         struct stm32_port *stm32_port = to_stm32_port(port);
1647         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1648
1649         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1650                 cpu_relax();
1651
1652         writel_relaxed(ch, port->membase + ofs->tdr);
1653 }
1654
1655 static void stm32_usart_console_write(struct console *co, const char *s,
1656                                       unsigned int cnt)
1657 {
1658         struct uart_port *port = &stm32_ports[co->index].port;
1659         struct stm32_port *stm32_port = to_stm32_port(port);
1660         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1661         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1662         unsigned long flags;
1663         u32 old_cr1, new_cr1;
1664         int locked = 1;
1665
1666         if (oops_in_progress)
1667                 locked = spin_trylock_irqsave(&port->lock, flags);
1668         else
1669                 spin_lock_irqsave(&port->lock, flags);
1670
1671         /* Save and disable interrupts, enable the transmitter */
1672         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1673         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1674         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1675         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1676
1677         uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1678
1679         /* Restore interrupt state */
1680         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1681
1682         if (locked)
1683                 spin_unlock_irqrestore(&port->lock, flags);
1684 }
1685
1686 static int stm32_usart_console_setup(struct console *co, char *options)
1687 {
1688         struct stm32_port *stm32port;
1689         int baud = 9600;
1690         int bits = 8;
1691         int parity = 'n';
1692         int flow = 'n';
1693
1694         if (co->index >= STM32_MAX_PORTS)
1695                 return -ENODEV;
1696
1697         stm32port = &stm32_ports[co->index];
1698
1699         /*
1700          * This driver does not support early console initialization
1701          * (use ARM early printk support instead), so we only expect
1702          * this to be called during the uart port registration when the
1703          * driver gets probed and the port should be mapped at that point.
1704          */
1705         if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1706                 return -ENXIO;
1707
1708         if (options)
1709                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1710
1711         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1712 }
1713
1714 static struct console stm32_console = {
1715         .name           = STM32_SERIAL_NAME,
1716         .device         = uart_console_device,
1717         .write          = stm32_usart_console_write,
1718         .setup          = stm32_usart_console_setup,
1719         .flags          = CON_PRINTBUFFER,
1720         .index          = -1,
1721         .data           = &stm32_usart_driver,
1722 };
1723
1724 #define STM32_SERIAL_CONSOLE (&stm32_console)
1725
1726 #else
1727 #define STM32_SERIAL_CONSOLE NULL
1728 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1729
1730 static struct uart_driver stm32_usart_driver = {
1731         .driver_name    = DRIVER_NAME,
1732         .dev_name       = STM32_SERIAL_NAME,
1733         .major          = 0,
1734         .minor          = 0,
1735         .nr             = STM32_MAX_PORTS,
1736         .cons           = STM32_SERIAL_CONSOLE,
1737 };
1738
1739 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1740                                                        bool enable)
1741 {
1742         struct stm32_port *stm32_port = to_stm32_port(port);
1743         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1744         struct tty_port *tport = &port->state->port;
1745         int ret;
1746         unsigned int size;
1747         unsigned long flags;
1748
1749         if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
1750                 return 0;
1751
1752         /*
1753          * Enable low-power wake-up and wake-up irq if argument is set to
1754          * "enable", disable low-power wake-up and wake-up irq otherwise
1755          */
1756         if (enable) {
1757                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1758                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1759                 mctrl_gpio_enable_irq_wake(stm32_port->gpios);
1760
1761                 /*
1762                  * When DMA is used for reception, it must be disabled before
1763                  * entering low-power mode and re-enabled when exiting from
1764                  * low-power mode.
1765                  */
1766                 if (stm32_port->rx_ch) {
1767                         spin_lock_irqsave(&port->lock, flags);
1768                         /* Avoid race with RX IRQ when DMAR is cleared */
1769                         stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1770                         /* Poll data from DMA RX buffer if any */
1771                         size = stm32_usart_receive_chars(port, true);
1772                         dmaengine_terminate_async(stm32_port->rx_ch);
1773                         uart_unlock_and_check_sysrq_irqrestore(port, flags);
1774                         if (size)
1775                                 tty_flip_buffer_push(tport);
1776                 }
1777
1778                 /* Poll data from RX FIFO if any */
1779                 stm32_usart_receive_chars(port, false);
1780         } else {
1781                 if (stm32_port->rx_ch) {
1782                         ret = stm32_usart_start_rx_dma_cyclic(port);
1783                         if (ret)
1784                                 return ret;
1785                 }
1786                 mctrl_gpio_disable_irq_wake(stm32_port->gpios);
1787                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1788                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1795 {
1796         struct uart_port *port = dev_get_drvdata(dev);
1797         int ret;
1798
1799         uart_suspend_port(&stm32_usart_driver, port);
1800
1801         if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
1802                 ret = stm32_usart_serial_en_wakeup(port, true);
1803                 if (ret)
1804                         return ret;
1805         }
1806
1807         /*
1808          * When "no_console_suspend" is enabled, keep the pinctrl default state
1809          * and rely on bootloader stage to restore this state upon resume.
1810          * Otherwise, apply the idle or sleep states depending on wakeup
1811          * capabilities.
1812          */
1813         if (console_suspend_enabled || !uart_console(port)) {
1814                 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1815                         pinctrl_pm_select_idle_state(dev);
1816                 else
1817                         pinctrl_pm_select_sleep_state(dev);
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1824 {
1825         struct uart_port *port = dev_get_drvdata(dev);
1826         int ret;
1827
1828         pinctrl_pm_select_default_state(dev);
1829
1830         if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
1831                 ret = stm32_usart_serial_en_wakeup(port, false);
1832                 if (ret)
1833                         return ret;
1834         }
1835
1836         return uart_resume_port(&stm32_usart_driver, port);
1837 }
1838
1839 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1840 {
1841         struct uart_port *port = dev_get_drvdata(dev);
1842         struct stm32_port *stm32port = container_of(port,
1843                         struct stm32_port, port);
1844
1845         clk_disable_unprepare(stm32port->clk);
1846
1847         return 0;
1848 }
1849
1850 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1851 {
1852         struct uart_port *port = dev_get_drvdata(dev);
1853         struct stm32_port *stm32port = container_of(port,
1854                         struct stm32_port, port);
1855
1856         return clk_prepare_enable(stm32port->clk);
1857 }
1858
1859 static const struct dev_pm_ops stm32_serial_pm_ops = {
1860         SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1861                            stm32_usart_runtime_resume, NULL)
1862         SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1863                                 stm32_usart_serial_resume)
1864 };
1865
1866 static struct platform_driver stm32_serial_driver = {
1867         .probe          = stm32_usart_serial_probe,
1868         .remove         = stm32_usart_serial_remove,
1869         .driver = {
1870                 .name   = DRIVER_NAME,
1871                 .pm     = &stm32_serial_pm_ops,
1872                 .of_match_table = of_match_ptr(stm32_match),
1873         },
1874 };
1875
1876 static int __init stm32_usart_init(void)
1877 {
1878         static char banner[] __initdata = "STM32 USART driver initialized";
1879         int ret;
1880
1881         pr_info("%s\n", banner);
1882
1883         ret = uart_register_driver(&stm32_usart_driver);
1884         if (ret)
1885                 return ret;
1886
1887         ret = platform_driver_register(&stm32_serial_driver);
1888         if (ret)
1889                 uart_unregister_driver(&stm32_usart_driver);
1890
1891         return ret;
1892 }
1893
1894 static void __exit stm32_usart_exit(void)
1895 {
1896         platform_driver_unregister(&stm32_serial_driver);
1897         uart_unregister_driver(&stm32_usart_driver);
1898 }
1899
1900 module_init(stm32_usart_init);
1901 module_exit(stm32_usart_exit);
1902
1903 MODULE_ALIAS("platform:" DRIVER_NAME);
1904 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1905 MODULE_LICENSE("GPL v2");