2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/regmap.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/spi/spi.h>
29 #include <linux/uaccess.h>
31 #define SC16IS7XX_NAME "sc16is7xx"
33 /* SC16IS7XX register definitions */
34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
68 /* Enhanced Register set: Only if (LCR == 0xBF) */
69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
75 /* IER register bits */
76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
84 /* IER register bits - write only if (EFR[4] == 1) */
85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
90 /* FCR register bits */
91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
97 /* FCR register bits - write only if (EFR[4] == 1) */
98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
101 /* IIR register bits */
102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
119 /* LCR register bits */
120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
123 * Word length bits table:
129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
131 * STOP length bit table:
133 * 1 -> 1-1.5 stop bits if
135 * 2 stop bits otherwise
137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
151 /* MCR register bits */
152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
171 /* LSR register bits */
172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
182 /* MSR register bits */
183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
196 #define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197 #define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
200 #define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
203 #define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
238 /* IOControl register bits (Only 750/760) */
239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240 #define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
243 /* EFCR register bits */
244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
253 * 1 = rate upto 1.152 Mbit/s
257 /* EFR register bits */
258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
271 * 01 -> transmitter generates
273 * 10 -> transmitter generates
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
285 * 01 -> receiver compares
287 * 10 -> receiver compares
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
294 /* Misc definitions */
295 #define SC16IS7XX_FIFO_SIZE (64)
296 #define SC16IS7XX_REG_SHIFT 2
298 struct sc16is7xx_devtype {
304 struct sc16is7xx_one {
305 struct uart_port port;
306 struct work_struct tx_work;
307 struct work_struct md_work;
310 struct sc16is7xx_port {
311 struct uart_driver uart;
312 struct sc16is7xx_devtype *devtype;
313 struct regmap *regmap;
316 #ifdef CONFIG_GPIOLIB
317 struct gpio_chip gpio;
319 unsigned char buf[SC16IS7XX_FIFO_SIZE];
320 struct sc16is7xx_one p[0];
323 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
325 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
327 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
328 unsigned int val = 0;
330 regmap_read(s->regmap,
331 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
336 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
338 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
340 regmap_write(s->regmap,
341 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
344 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
347 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
349 regmap_update_bits(s->regmap,
350 (reg << SC16IS7XX_REG_SHIFT) | port->line,
355 static void sc16is7xx_power(struct uart_port *port, int on)
357 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
358 SC16IS7XX_IER_SLEEP_BIT,
359 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
362 static const struct sc16is7xx_devtype sc16is74x_devtype = {
368 static const struct sc16is7xx_devtype sc16is750_devtype = {
374 static const struct sc16is7xx_devtype sc16is752_devtype = {
380 static const struct sc16is7xx_devtype sc16is760_devtype = {
386 static const struct sc16is7xx_devtype sc16is762_devtype = {
392 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
394 switch (reg >> SC16IS7XX_REG_SHIFT) {
395 case SC16IS7XX_RHR_REG:
396 case SC16IS7XX_IIR_REG:
397 case SC16IS7XX_LSR_REG:
398 case SC16IS7XX_MSR_REG:
399 case SC16IS7XX_TXLVL_REG:
400 case SC16IS7XX_RXLVL_REG:
401 case SC16IS7XX_IOSTATE_REG:
410 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
412 switch (reg >> SC16IS7XX_REG_SHIFT) {
413 case SC16IS7XX_RHR_REG:
422 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
424 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
427 unsigned long clk = port->uartclk, div = clk / 16 / baud;
430 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
434 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
436 /* Open the LCR divisors for configuration */
437 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
438 SC16IS7XX_LCR_CONF_MODE_B);
440 /* Enable enhanced features */
441 regcache_cache_bypass(s->regmap, true);
442 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
443 SC16IS7XX_EFR_ENABLE_BIT);
444 regcache_cache_bypass(s->regmap, false);
446 /* Put LCR back to the normal mode */
447 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
449 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
450 SC16IS7XX_MCR_CLKSEL_BIT,
453 /* Open the LCR divisors for configuration */
454 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
455 SC16IS7XX_LCR_CONF_MODE_A);
457 /* Write the new divisor */
458 regcache_cache_bypass(s->regmap, true);
459 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
460 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
461 regcache_cache_bypass(s->regmap, false);
463 /* Put LCR back to the normal mode */
464 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
466 return DIV_ROUND_CLOSEST(clk / 16, div);
469 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
472 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
473 unsigned int lsr = 0, ch, flag, bytes_read, i;
474 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
476 if (unlikely(rxlen >= sizeof(s->buf))) {
477 dev_warn_ratelimited(port->dev,
478 "Port %i: Possible RX FIFO overrun: %d\n",
480 port->icount.buf_overrun++;
481 /* Ensure sanity of RX level */
482 rxlen = sizeof(s->buf);
486 /* Only read lsr if there are possible errors in FIFO */
488 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
489 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
490 read_lsr = false; /* No errors left in FIFO */
495 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
498 regcache_cache_bypass(s->regmap, true);
499 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
501 regcache_cache_bypass(s->regmap, false);
505 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
511 if (lsr & SC16IS7XX_LSR_BI_BIT) {
513 if (uart_handle_break(port))
515 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
516 port->icount.parity++;
517 else if (lsr & SC16IS7XX_LSR_FE_BIT)
518 port->icount.frame++;
519 else if (lsr & SC16IS7XX_LSR_OE_BIT)
520 port->icount.overrun++;
522 lsr &= port->read_status_mask;
523 if (lsr & SC16IS7XX_LSR_BI_BIT)
525 else if (lsr & SC16IS7XX_LSR_PE_BIT)
527 else if (lsr & SC16IS7XX_LSR_FE_BIT)
529 else if (lsr & SC16IS7XX_LSR_OE_BIT)
533 for (i = 0; i < bytes_read; ++i) {
535 if (uart_handle_sysrq_char(port, ch))
538 if (lsr & port->ignore_status_mask)
541 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
547 tty_flip_buffer_push(&port->state->port);
550 static void sc16is7xx_handle_tx(struct uart_port *port)
552 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
553 struct circ_buf *xmit = &port->state->xmit;
554 unsigned int txlen, to_send, i;
556 if (unlikely(port->x_char)) {
557 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
563 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
566 /* Get length of data pending in circular buffer */
567 to_send = uart_circ_chars_pending(xmit);
568 if (likely(to_send)) {
569 /* Limit to size of TX FIFO */
570 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
571 to_send = (to_send > txlen) ? txlen : to_send;
573 /* Add data to send */
574 port->icount.tx += to_send;
576 /* Convert to linear buffer */
577 for (i = 0; i < to_send; ++i) {
578 s->buf[i] = xmit->buf[xmit->tail];
579 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
581 regcache_cache_bypass(s->regmap, true);
582 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
583 regcache_cache_bypass(s->regmap, false);
586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
587 uart_write_wakeup(port);
590 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
592 struct uart_port *port = &s->p[portno].port;
595 unsigned int iir, msr, rxlen;
597 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
598 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
601 iir &= SC16IS7XX_IIR_ID_MASK;
604 case SC16IS7XX_IIR_RDI_SRC:
605 case SC16IS7XX_IIR_RLSE_SRC:
606 case SC16IS7XX_IIR_RTOI_SRC:
607 case SC16IS7XX_IIR_XOFFI_SRC:
608 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
610 sc16is7xx_handle_rx(port, rxlen, iir);
613 case SC16IS7XX_IIR_CTSRTS_SRC:
614 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
615 uart_handle_cts_change(port,
616 !!(msr & SC16IS7XX_MSR_CTS_BIT));
618 case SC16IS7XX_IIR_THRI_SRC:
619 mutex_lock(&s->mutex);
620 sc16is7xx_handle_tx(port);
621 mutex_unlock(&s->mutex);
624 dev_err_ratelimited(port->dev,
625 "Port %i: Unexpected interrupt: %x",
632 static irqreturn_t sc16is7xx_ist(int irq, void *dev_id)
634 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
637 for (i = 0; i < s->uart.nr; ++i)
638 sc16is7xx_port_irq(s, i);
643 static void sc16is7xx_wq_proc(struct work_struct *ws)
645 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work);
646 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
648 mutex_lock(&s->mutex);
649 sc16is7xx_handle_tx(&one->port);
650 mutex_unlock(&s->mutex);
653 static void sc16is7xx_stop_tx(struct uart_port* port)
655 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
656 SC16IS7XX_IER_THRI_BIT,
660 static void sc16is7xx_stop_rx(struct uart_port* port)
662 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
664 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
665 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
666 SC16IS7XX_LSR_DR_BIT,
670 static void sc16is7xx_start_tx(struct uart_port *port)
672 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
675 if ((port->rs485.flags & SER_RS485_ENABLED) &&
676 (port->rs485.delay_rts_before_send > 0)) {
677 mdelay(port->rs485.delay_rts_before_send);
680 if (!work_pending(&one->tx_work))
681 schedule_work(&one->tx_work);
684 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
686 unsigned int lvl, lsr;
688 lvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
689 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
691 return ((lsr & SC16IS7XX_LSR_THRE_BIT) && !lvl) ? TIOCSER_TEMT : 0;
694 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
696 /* DCD and DSR are not wired and CTS/RTS is handled automatically
697 * so just indicate DSR and CAR asserted
699 return TIOCM_DSR | TIOCM_CAR;
702 static void sc16is7xx_md_proc(struct work_struct *ws)
704 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work);
706 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
707 SC16IS7XX_MCR_LOOP_BIT,
708 (one->port.mctrl & TIOCM_LOOP) ?
709 SC16IS7XX_MCR_LOOP_BIT : 0);
712 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
714 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
716 schedule_work(&one->md_work);
719 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
721 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
722 SC16IS7XX_LCR_TXBREAK_BIT,
723 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
726 static void sc16is7xx_set_termios(struct uart_port *port,
727 struct ktermios *termios,
728 struct ktermios *old)
730 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
731 unsigned int lcr, flow = 0;
734 /* Mask termios capabilities we don't support */
735 termios->c_cflag &= ~CMSPAR;
738 switch (termios->c_cflag & CSIZE) {
740 lcr = SC16IS7XX_LCR_WORD_LEN_5;
743 lcr = SC16IS7XX_LCR_WORD_LEN_6;
746 lcr = SC16IS7XX_LCR_WORD_LEN_7;
749 lcr = SC16IS7XX_LCR_WORD_LEN_8;
752 lcr = SC16IS7XX_LCR_WORD_LEN_8;
753 termios->c_cflag &= ~CSIZE;
754 termios->c_cflag |= CS8;
759 if (termios->c_cflag & PARENB) {
760 lcr |= SC16IS7XX_LCR_PARITY_BIT;
761 if (!(termios->c_cflag & PARODD))
762 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
766 if (termios->c_cflag & CSTOPB)
767 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
769 /* Set read status mask */
770 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
771 if (termios->c_iflag & INPCK)
772 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
773 SC16IS7XX_LSR_FE_BIT;
774 if (termios->c_iflag & (BRKINT | PARMRK))
775 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
777 /* Set status ignore mask */
778 port->ignore_status_mask = 0;
779 if (termios->c_iflag & IGNBRK)
780 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
781 if (!(termios->c_cflag & CREAD))
782 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
784 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
785 SC16IS7XX_LCR_CONF_MODE_B);
787 /* Configure flow control */
788 regcache_cache_bypass(s->regmap, true);
789 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
790 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
791 if (termios->c_cflag & CRTSCTS)
792 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
793 SC16IS7XX_EFR_AUTORTS_BIT;
794 if (termios->c_iflag & IXON)
795 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
796 if (termios->c_iflag & IXOFF)
797 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
799 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
800 regcache_cache_bypass(s->regmap, false);
802 /* Update LCR register */
803 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
805 /* Get baud rate generator configuration */
806 baud = uart_get_baud_rate(port, termios, old,
807 port->uartclk / 16 / 4 / 0xffff,
810 /* Setup baudrate generator */
811 baud = sc16is7xx_set_baud(port, baud);
813 /* Update timeout according to new baud rate */
814 uart_update_timeout(port, termios->c_cflag, baud);
817 static int sc16is7xx_config_rs485(struct uart_port *port,
818 struct serial_rs485 *rs485)
820 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
821 SC16IS7XX_EFCR_RTS_INVERT_BIT;
824 if (rs485->flags & SER_RS485_ENABLED) {
825 bool rts_during_rx, rts_during_tx;
827 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
828 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
830 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
832 if (!rts_during_rx && rts_during_tx)
834 else if (rts_during_rx && !rts_during_tx)
835 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
838 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
839 rts_during_tx, rts_during_rx);
842 * RTS signal is handled by HW, it's timing can't be influenced.
843 * However, it's sometimes useful to delay TX even without RTS
844 * control therefore we try to handle .delay_rts_before_send.
846 if (rs485->delay_rts_after_send)
850 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
852 port->rs485 = *rs485;
857 static int sc16is7xx_startup(struct uart_port *port)
859 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
862 sc16is7xx_power(port, 1);
865 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
866 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
868 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
869 SC16IS7XX_FCR_FIFO_BIT);
872 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
873 SC16IS7XX_LCR_CONF_MODE_B);
875 regcache_cache_bypass(s->regmap, true);
877 /* Enable write access to enhanced features and internal clock div */
878 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
879 SC16IS7XX_EFR_ENABLE_BIT);
882 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
883 SC16IS7XX_MCR_TCRTLR_BIT,
884 SC16IS7XX_MCR_TCRTLR_BIT);
886 /* Configure flow control levels */
887 /* Flow control halt level 48, resume level 24 */
888 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
889 SC16IS7XX_TCR_RX_RESUME(24) |
890 SC16IS7XX_TCR_RX_HALT(48));
892 regcache_cache_bypass(s->regmap, false);
894 /* Now, initialize the UART */
895 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
897 /* Enable the Rx and Tx FIFO */
898 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
899 SC16IS7XX_EFCR_RXDISABLE_BIT |
900 SC16IS7XX_EFCR_TXDISABLE_BIT,
903 /* Enable RX, TX, CTS change interrupts */
904 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
905 SC16IS7XX_IER_CTSI_BIT;
906 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
911 static void sc16is7xx_shutdown(struct uart_port *port)
913 /* Disable all interrupts */
914 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
916 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
917 SC16IS7XX_EFCR_RXDISABLE_BIT |
918 SC16IS7XX_EFCR_TXDISABLE_BIT,
919 SC16IS7XX_EFCR_RXDISABLE_BIT |
920 SC16IS7XX_EFCR_TXDISABLE_BIT);
922 sc16is7xx_power(port, 0);
925 static const char *sc16is7xx_type(struct uart_port *port)
927 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
929 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
932 static int sc16is7xx_request_port(struct uart_port *port)
938 static void sc16is7xx_config_port(struct uart_port *port, int flags)
940 if (flags & UART_CONFIG_TYPE)
941 port->type = PORT_SC16IS7XX;
944 static int sc16is7xx_verify_port(struct uart_port *port,
945 struct serial_struct *s)
947 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
949 if (s->irq != port->irq)
955 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
956 unsigned int oldstate)
958 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
961 static void sc16is7xx_null_void(struct uart_port *port)
966 static const struct uart_ops sc16is7xx_ops = {
967 .tx_empty = sc16is7xx_tx_empty,
968 .set_mctrl = sc16is7xx_set_mctrl,
969 .get_mctrl = sc16is7xx_get_mctrl,
970 .stop_tx = sc16is7xx_stop_tx,
971 .start_tx = sc16is7xx_start_tx,
972 .stop_rx = sc16is7xx_stop_rx,
973 .break_ctl = sc16is7xx_break_ctl,
974 .startup = sc16is7xx_startup,
975 .shutdown = sc16is7xx_shutdown,
976 .set_termios = sc16is7xx_set_termios,
977 .type = sc16is7xx_type,
978 .request_port = sc16is7xx_request_port,
979 .release_port = sc16is7xx_null_void,
980 .config_port = sc16is7xx_config_port,
981 .verify_port = sc16is7xx_verify_port,
985 #ifdef CONFIG_GPIOLIB
986 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
989 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
991 struct uart_port *port = &s->p[0].port;
993 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
995 return !!(val & BIT(offset));
998 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1000 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1002 struct uart_port *port = &s->p[0].port;
1004 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1005 val ? BIT(offset) : 0);
1008 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1011 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1013 struct uart_port *port = &s->p[0].port;
1015 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1020 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1021 unsigned offset, int val)
1023 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1025 struct uart_port *port = &s->p[0].port;
1027 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1028 val ? BIT(offset) : 0);
1029 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1036 static int sc16is7xx_probe(struct device *dev,
1037 struct sc16is7xx_devtype *devtype,
1038 struct regmap *regmap, int irq, unsigned long flags)
1040 unsigned long freq, *pfreq = dev_get_platdata(dev);
1042 struct sc16is7xx_port *s;
1045 return PTR_ERR(regmap);
1047 /* Alloc port structure */
1048 s = devm_kzalloc(dev, sizeof(*s) +
1049 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1052 dev_err(dev, "Error allocating port structure\n");
1056 s->clk = devm_clk_get(dev, NULL);
1057 if (IS_ERR(s->clk)) {
1061 return PTR_ERR(s->clk);
1063 clk_prepare_enable(s->clk);
1064 freq = clk_get_rate(s->clk);
1068 s->devtype = devtype;
1069 dev_set_drvdata(dev, s);
1071 /* Register UART driver */
1072 s->uart.owner = THIS_MODULE;
1073 s->uart.dev_name = "ttySC";
1074 s->uart.nr = devtype->nr_uart;
1075 ret = uart_register_driver(&s->uart);
1077 dev_err(dev, "Registering UART driver failed\n");
1081 #ifdef CONFIG_GPIOLIB
1082 if (devtype->nr_gpio) {
1083 /* Setup GPIO cotroller */
1084 s->gpio.owner = THIS_MODULE;
1086 s->gpio.label = dev_name(dev);
1087 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1088 s->gpio.get = sc16is7xx_gpio_get;
1089 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1090 s->gpio.set = sc16is7xx_gpio_set;
1092 s->gpio.ngpio = devtype->nr_gpio;
1093 s->gpio.can_sleep = 1;
1094 ret = gpiochip_add(&s->gpio);
1100 mutex_init(&s->mutex);
1102 for (i = 0; i < devtype->nr_uart; ++i) {
1103 /* Initialize port data */
1104 s->p[i].port.line = i;
1105 s->p[i].port.dev = dev;
1106 s->p[i].port.irq = irq;
1107 s->p[i].port.type = PORT_SC16IS7XX;
1108 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1109 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1110 s->p[i].port.iotype = UPIO_PORT;
1111 s->p[i].port.uartclk = freq;
1112 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1113 s->p[i].port.ops = &sc16is7xx_ops;
1114 /* Disable all interrupts */
1115 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1117 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1118 SC16IS7XX_EFCR_RXDISABLE_BIT |
1119 SC16IS7XX_EFCR_TXDISABLE_BIT);
1120 /* Initialize queue for start TX */
1121 INIT_WORK(&s->p[i].tx_work, sc16is7xx_wq_proc);
1122 /* Initialize queue for changing mode */
1123 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc);
1125 uart_add_one_port(&s->uart, &s->p[i].port);
1126 /* Go to suspend mode */
1127 sc16is7xx_power(&s->p[i].port, 0);
1130 /* Setup interrupt */
1131 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_ist,
1132 IRQF_ONESHOT | flags, dev_name(dev), s);
1136 for (i = 0; i < s->uart.nr; i++)
1137 uart_remove_one_port(&s->uart, &s->p[i].port);
1139 mutex_destroy(&s->mutex);
1141 #ifdef CONFIG_GPIOLIB
1142 if (devtype->nr_gpio)
1143 gpiochip_remove(&s->gpio);
1147 uart_unregister_driver(&s->uart);
1150 if (!IS_ERR(s->clk))
1151 clk_disable_unprepare(s->clk);
1156 static int sc16is7xx_remove(struct device *dev)
1158 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1161 #ifdef CONFIG_GPIOLIB
1162 if (s->devtype->nr_gpio)
1163 gpiochip_remove(&s->gpio);
1166 for (i = 0; i < s->uart.nr; i++) {
1167 cancel_work_sync(&s->p[i].tx_work);
1168 cancel_work_sync(&s->p[i].md_work);
1169 uart_remove_one_port(&s->uart, &s->p[i].port);
1170 sc16is7xx_power(&s->p[i].port, 0);
1173 mutex_destroy(&s->mutex);
1174 uart_unregister_driver(&s->uart);
1175 if (!IS_ERR(s->clk))
1176 clk_disable_unprepare(s->clk);
1181 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1182 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1183 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1184 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1185 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1186 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1187 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1190 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1192 static struct regmap_config regcfg = {
1196 .cache_type = REGCACHE_RBTREE,
1197 .volatile_reg = sc16is7xx_regmap_volatile,
1198 .precious_reg = sc16is7xx_regmap_precious,
1201 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1202 static int sc16is7xx_spi_probe(struct spi_device *spi)
1204 struct sc16is7xx_devtype *devtype;
1205 unsigned long flags = 0;
1206 struct regmap *regmap;
1210 spi->bits_per_word = 8;
1211 /* only supports mode 0 on SC16IS762 */
1212 spi->mode = spi->mode ? : SPI_MODE_0;
1213 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1214 ret = spi_setup(spi);
1218 if (spi->dev.of_node) {
1219 const struct of_device_id *of_id =
1220 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1222 devtype = (struct sc16is7xx_devtype *)of_id->data;
1224 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1226 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1227 flags = IRQF_TRIGGER_FALLING;
1230 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1231 (devtype->nr_uart - 1);
1232 regmap = devm_regmap_init_spi(spi, ®cfg);
1234 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1237 static int sc16is7xx_spi_remove(struct spi_device *spi)
1239 return sc16is7xx_remove(&spi->dev);
1242 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1243 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1244 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1245 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1246 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1247 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1251 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1253 static struct spi_driver sc16is7xx_spi_uart_driver = {
1255 .name = SC16IS7XX_NAME,
1256 .owner = THIS_MODULE,
1257 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1259 .probe = sc16is7xx_spi_probe,
1260 .remove = sc16is7xx_spi_remove,
1261 .id_table = sc16is7xx_spi_id_table,
1264 MODULE_ALIAS("spi:sc16is7xx");
1267 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1268 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1269 const struct i2c_device_id *id)
1271 struct sc16is7xx_devtype *devtype;
1272 unsigned long flags = 0;
1273 struct regmap *regmap;
1275 if (i2c->dev.of_node) {
1276 const struct of_device_id *of_id =
1277 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1279 devtype = (struct sc16is7xx_devtype *)of_id->data;
1281 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1282 flags = IRQF_TRIGGER_FALLING;
1285 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1286 (devtype->nr_uart - 1);
1287 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1289 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1292 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1294 return sc16is7xx_remove(&client->dev);
1297 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1298 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1299 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1300 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1301 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1302 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1305 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1307 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1309 .name = SC16IS7XX_NAME,
1310 .owner = THIS_MODULE,
1311 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1313 .probe = sc16is7xx_i2c_probe,
1314 .remove = sc16is7xx_i2c_remove,
1315 .id_table = sc16is7xx_i2c_id_table,
1318 MODULE_ALIAS("i2c:sc16is7xx");
1321 static int __init sc16is7xx_init(void)
1324 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1325 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1327 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1332 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1333 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1335 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1341 module_init(sc16is7xx_init);
1343 static void __exit sc16is7xx_exit(void)
1345 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1346 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1349 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1350 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1353 module_exit(sc16is7xx_exit);
1355 MODULE_LICENSE("GPL");
1356 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1357 MODULE_DESCRIPTION("SC16IS7XX serial driver");