drivers/tty/serial/omap-serial.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for OMAP-UART controller.
   4  * Based on drivers/serial/8250.c
   5  *
   6  * Copyright (C) 2010 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Govindraj R     <govindraj.raja@ti.com>
  10  *      Thara Gopinath  <thara@ti.com>
  11  *
  12  * Note: This driver is made separate from 8250 driver as we cannot
  13  * over load 8250 driver with omap platform specific configuration for
  14  * features like DMA, it makes easier to implement features like DMA and
  15  * hardware flow control and software flow control configuration with
  16  * this driver as required for the omap-platform.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/console.h>
  22 #include <linux/serial.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/delay.h>
  25 #include <linux/slab.h>
  26 #include <linux/tty.h>
  27 #include <linux/tty_flip.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/io.h>
  30 #include <linux/clk.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/irq.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/pm_wakeirq.h>
  35 #include <linux/of.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/gpio/consumer.h>
  38 #include <linux/platform_data/serial-omap.h>
  39
  40 #define OMAP_MAX_HSUART_PORTS   10
  41
  42 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  43
  44 #define OMAP_UART_REV_42 0x0402
  45 #define OMAP_UART_REV_46 0x0406
  46 #define OMAP_UART_REV_52 0x0502
  47 #define OMAP_UART_REV_63 0x0603
  48
  49 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  50
  51 /* Feature flags */
  52 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  53
  54 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  55 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  56
  57 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
  58
  59 /* SCR register bitmasks */
  60 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  61 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  62 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  63
  64 /* FCR register bitmasks */
  65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  67
  68 /* MVR register bitmasks */
  69 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  70
  71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  73 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  74
  75 #define OMAP_UART_MVR_MAJ_MASK          0x700
  76 #define OMAP_UART_MVR_MAJ_SHIFT         8
  77 #define OMAP_UART_MVR_MIN_MASK          0x3f
  78
  79 #define OMAP_UART_DMA_CH_FREE   -1
  80
  81 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  82 #define OMAP_MODE13X_SPEED      230400
  83
  84 /* WER = 0x7F
  85  * Enable module level wakeup in WER reg
  86  */
  87 #define OMAP_UART_WER_MOD_WKUP  0x7F
  88
  89 /* Enable XON/XOFF flow control on output */
  90 #define OMAP_UART_SW_TX         0x08
  91
  92 /* Enable XON/XOFF flow control on input */
  93 #define OMAP_UART_SW_RX         0x02
  94
  95 #define OMAP_UART_SW_CLR        0xF0
  96
  97 #define OMAP_UART_TCR_TRIG      0x0F
  98
  99 struct uart_omap_dma {
 100         u8                      uart_dma_tx;
 101         u8                      uart_dma_rx;
 102         int                     rx_dma_channel;
 103         int                     tx_dma_channel;
 104         dma_addr_t              rx_buf_dma_phys;
 105         dma_addr_t              tx_buf_dma_phys;
 106         unsigned int            uart_base;
 107         /*
 108          * Buffer for rx dma. It is not required for tx because the buffer
 109          * comes from port structure.
 110          */
 111         unsigned char           *rx_buf;
 112         unsigned int            prev_rx_dma_pos;
 113         int                     tx_buf_size;
 114         int                     tx_dma_used;
 115         int                     rx_dma_used;
 116         spinlock_t              tx_lock;
 117         spinlock_t              rx_lock;
 118         /* timer to poll activity on rx dma */
 119         struct timer_list       rx_timer;
 120         unsigned int            rx_buf_size;
 121         unsigned int            rx_poll_rate;
 122         unsigned int            rx_timeout;
 123 };
 124
 125 struct uart_omap_port {
 126         struct uart_port        port;
 127         struct uart_omap_dma    uart_dma;
 128         struct device           *dev;
 129         int                     wakeirq;
 130
 131         unsigned char           ier;
 132         unsigned char           lcr;
 133         unsigned char           mcr;
 134         unsigned char           fcr;
 135         unsigned char           efr;
 136         unsigned char           dll;
 137         unsigned char           dlh;
 138         unsigned char           mdr1;
 139         unsigned char           scr;
 140         unsigned char           wer;
 141
 142         int                     use_dma;
 143         /*
 144          * Some bits in registers are cleared on a read, so they must
 145          * be saved whenever the register is read, but the bits will not
 146          * be immediately processed.
 147          */
 148         unsigned int            lsr_break_flag;
 149         unsigned char           msr_saved_flags;
 150         char                    name[20];
 151         unsigned long           port_activity;
 152         int                     context_loss_cnt;
 153         u32                     errata;
 154         u32                     features;
 155
 156         struct gpio_desc        *rts_gpiod;
 157
 158         struct pm_qos_request   pm_qos_request;
 159         u32                     latency;
 160         u32                     calc_latency;
 161         struct work_struct      qos_work;
 162         bool                    is_suspending;
 163
 164         unsigned int            rs485_tx_filter_count;
 165 };
 166
 167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 168
 169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 170
 171 /* Forward declaration of functions */
 172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 173
 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 175 {
 176         offset <<= up->port.regshift;
 177         return readw(up->port.membase + offset);
 178 }
 179
 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 181 {
 182         offset <<= up->port.regshift;
 183         writew(value, up->port.membase + offset);
 184 }
 185
 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 187 {
 188         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 189         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 190                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 191         serial_out(up, UART_FCR, 0);
 192 }
 193
 194 #ifdef CONFIG_PM
 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 196 {
 197         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 198
 199         if (!pdata || !pdata->get_context_loss_count)
 200                 return -EINVAL;
 201
 202         return pdata->get_context_loss_count(up->dev);
 203 }
 204
 205 /* REVISIT: Remove this when omap3 boots in device tree only mode */
 206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 207 {
 208         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 209
 210         if (!pdata || !pdata->enable_wakeup)
 211                 return;
 212
 213         pdata->enable_wakeup(up->dev, enable);
 214 }
 215 #endif /* CONFIG_PM */
 216
 217 /*
 218  * Calculate the absolute difference between the desired and actual baud
 219  * rate for the given mode.
 220  */
 221 static inline int calculate_baud_abs_diff(struct uart_port *port,
 222                                 unsigned int baud, unsigned int mode)
 223 {
 224         unsigned int n = port->uartclk / (mode * baud);
 225
 226         if (n == 0)
 227                 n = 1;
 228
 229         return abs_diff(baud, port->uartclk / (mode * n));
 230 }
 231
 232 /*
 233  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 234  * @port: uart port info
 235  * @baud: baudrate for which mode needs to be determined
 236  *
 237  * Returns true if baud rate is MODE16X and false if MODE13X
 238  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 239  * and Error Rates" determines modes not for all common baud rates.
 240  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 241  * table it's determined as 13x.
 242  */
 243 static bool
 244 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 245 {
 246         int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
 247         int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
 248
 249         return (abs_diff_13 >= abs_diff_16);
 250 }
 251
 252 /*
 253  * serial_omap_get_divisor - calculate divisor value
 254  * @port: uart port info
 255  * @baud: baudrate for which divisor needs to be calculated.
 256  */
 257 static unsigned int
 258 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 259 {
 260         unsigned int mode;
 261
 262         if (!serial_omap_baud_is_mode16(port, baud))
 263                 mode = 13;
 264         else
 265                 mode = 16;
 266         return port->uartclk/(mode * baud);
 267 }
 268
 269 static void serial_omap_enable_ms(struct uart_port *port)
 270 {
 271         struct uart_omap_port *up = to_uart_omap_port(port);
 272
 273         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 274
 275         up->ier |= UART_IER_MSI;
 276         serial_out(up, UART_IER, up->ier);
 277 }
 278
 279 static void serial_omap_stop_tx(struct uart_port *port)
 280 {
 281         struct uart_omap_port *up = to_uart_omap_port(port);
 282         int res;
 283
 284         /* Handle RS-485 */
 285         if (port->rs485.flags & SER_RS485_ENABLED) {
 286                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 287                         /* THR interrupt is fired when both TX FIFO and TX
 288                          * shift register are empty. This means there's nothing
 289                          * left to transmit now, so make sure the THR interrupt
 290                          * is fired when TX FIFO is below the trigger level,
 291                          * disable THR interrupts and toggle the RS-485 GPIO
 292                          * data direction pin if needed.
 293                          */
 294                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 295                         serial_out(up, UART_OMAP_SCR, up->scr);
 296                         res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
 297                                 1 : 0;
 298                         if (gpiod_get_value(up->rts_gpiod) != res) {
 299                                 if (port->rs485.delay_rts_after_send > 0)
 300                                         mdelay(
 301                                         port->rs485.delay_rts_after_send);
 302                                 gpiod_set_value(up->rts_gpiod, res);
 303                         }
 304                 } else {
 305                         /* We're asked to stop, but there's still stuff in the
 306                          * UART FIFO, so make sure the THR interrupt is fired
 307                          * when both TX FIFO and TX shift register are empty.
 308                          * The next THR interrupt (if no transmission is started
 309                          * in the meantime) will indicate the end of a
 310                          * transmission. Therefore we _don't_ disable THR
 311                          * interrupts in this situation.
 312                          */
 313                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 314                         serial_out(up, UART_OMAP_SCR, up->scr);
 315                         return;
 316                 }
 317         }
 318
 319         if (up->ier & UART_IER_THRI) {
 320                 up->ier &= ~UART_IER_THRI;
 321                 serial_out(up, UART_IER, up->ier);
 322         }
 323 }
 324
 325 static void serial_omap_stop_rx(struct uart_port *port)
 326 {
 327         struct uart_omap_port *up = to_uart_omap_port(port);
 328
 329         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 330         up->port.read_status_mask &= ~UART_LSR_DR;
 331         serial_out(up, UART_IER, up->ier);
 332 }
 333
 334 static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch)
 335 {
 336         serial_out(up, UART_TX, ch);
 337
 338         if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 339                         !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
 340                 up->rs485_tx_filter_count++;
 341 }
 342
 343 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 344 {
 345         u8 ch;
 346
 347         uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4,
 348                 true,
 349                 serial_omap_put_char(up, ch),
 350                 ({}));
 351 }
 352
 353 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 354 {
 355         if (!(up->ier & UART_IER_THRI)) {
 356                 up->ier |= UART_IER_THRI;
 357                 serial_out(up, UART_IER, up->ier);
 358         }
 359 }
 360
 361 static void serial_omap_start_tx(struct uart_port *port)
 362 {
 363         struct uart_omap_port *up = to_uart_omap_port(port);
 364         int res;
 365
 366         /* Handle RS-485 */
 367         if (port->rs485.flags & SER_RS485_ENABLED) {
 368                 /* Fire THR interrupts when FIFO is below trigger level */
 369                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 370                 serial_out(up, UART_OMAP_SCR, up->scr);
 371
 372                 /* if rts not already enabled */
 373                 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 374                 if (gpiod_get_value(up->rts_gpiod) != res) {
 375                         gpiod_set_value(up->rts_gpiod, res);
 376                         if (port->rs485.delay_rts_before_send > 0)
 377                                 mdelay(port->rs485.delay_rts_before_send);
 378                 }
 379         }
 380
 381         if ((port->rs485.flags & SER_RS485_ENABLED) &&
 382             !(port->rs485.flags & SER_RS485_RX_DURING_TX))
 383                 up->rs485_tx_filter_count = 0;
 384
 385         serial_omap_enable_ier_thri(up);
 386 }
 387
 388 static void serial_omap_throttle(struct uart_port *port)
 389 {
 390         struct uart_omap_port *up = to_uart_omap_port(port);
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&up->port.lock, flags);
 394         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 395         serial_out(up, UART_IER, up->ier);
 396         spin_unlock_irqrestore(&up->port.lock, flags);
 397 }
 398
 399 static void serial_omap_unthrottle(struct uart_port *port)
 400 {
 401         struct uart_omap_port *up = to_uart_omap_port(port);
 402         unsigned long flags;
 403
 404         spin_lock_irqsave(&up->port.lock, flags);
 405         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 406         serial_out(up, UART_IER, up->ier);
 407         spin_unlock_irqrestore(&up->port.lock, flags);
 408 }
 409
 410 static unsigned int check_modem_status(struct uart_omap_port *up)
 411 {
 412         unsigned int status;
 413
 414         status = serial_in(up, UART_MSR);
 415         status |= up->msr_saved_flags;
 416         up->msr_saved_flags = 0;
 417         if ((status & UART_MSR_ANY_DELTA) == 0)
 418                 return status;
 419
 420         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 421             up->port.state != NULL) {
 422                 if (status & UART_MSR_TERI)
 423                         up->port.icount.rng++;
 424                 if (status & UART_MSR_DDSR)
 425                         up->port.icount.dsr++;
 426                 if (status & UART_MSR_DDCD)
 427                         uart_handle_dcd_change
 428                                 (&up->port, status & UART_MSR_DCD);
 429                 if (status & UART_MSR_DCTS)
 430                         uart_handle_cts_change
 431                                 (&up->port, status & UART_MSR_CTS);
 432                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 433         }
 434
 435         return status;
 436 }
 437
 438 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 439 {
 440         unsigned int flag;
 441
 442         /*
 443          * Read one data character out to avoid stalling the receiver according
 444          * to the table 23-246 of the omap4 TRM.
 445          */
 446         if (likely(lsr & UART_LSR_DR)) {
 447                 serial_in(up, UART_RX);
 448                 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 449                     !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
 450                     up->rs485_tx_filter_count)
 451                         up->rs485_tx_filter_count--;
 452         }
 453
 454         up->port.icount.rx++;
 455         flag = TTY_NORMAL;
 456
 457         if (lsr & UART_LSR_BI) {
 458                 flag = TTY_BREAK;
 459                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 460                 up->port.icount.brk++;
 461                 /*
 462                  * We do the SysRQ and SAK checking
 463                  * here because otherwise the break
 464                  * may get masked by ignore_status_mask
 465                  * or read_status_mask.
 466                  */
 467                 if (uart_handle_break(&up->port))
 468                         return;
 469
 470         }
 471
 472         if (lsr & UART_LSR_PE) {
 473                 flag = TTY_PARITY;
 474                 up->port.icount.parity++;
 475         }
 476
 477         if (lsr & UART_LSR_FE) {
 478                 flag = TTY_FRAME;
 479                 up->port.icount.frame++;
 480         }
 481
 482         if (lsr & UART_LSR_OE)
 483                 up->port.icount.overrun++;
 484
 485 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 486         if (up->port.line == up->port.cons->index) {
 487                 /* Recover the break flag from console xmit */
 488                 lsr |= up->lsr_break_flag;
 489         }
 490 #endif
 491         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 492 }
 493
 494 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 495 {
 496         unsigned char ch = 0;
 497         unsigned int flag;
 498
 499         if (!(lsr & UART_LSR_DR))
 500                 return;
 501
 502         ch = serial_in(up, UART_RX);
 503         if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 504             !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
 505             up->rs485_tx_filter_count) {
 506                 up->rs485_tx_filter_count--;
 507                 return;
 508         }
 509
 510         flag = TTY_NORMAL;
 511         up->port.icount.rx++;
 512
 513         if (uart_handle_sysrq_char(&up->port, ch))
 514                 return;
 515
 516         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 517 }
 518
 519 /**
 520  * serial_omap_irq() - This handles the interrupt from one port
 521  * @irq: uart port irq number
 522  * @dev_id: uart port info
 523  */
 524 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 525 {
 526         struct uart_omap_port *up = dev_id;
 527         unsigned int iir, lsr;
 528         unsigned int type;
 529         irqreturn_t ret = IRQ_NONE;
 530         int max_count = 256;
 531
 532         spin_lock(&up->port.lock);
 533
 534         do {
 535                 iir = serial_in(up, UART_IIR);
 536                 if (iir & UART_IIR_NO_INT)
 537                         break;
 538
 539                 ret = IRQ_HANDLED;
 540                 lsr = serial_in(up, UART_LSR);
 541
 542                 /* extract IRQ type from IIR register */
 543                 type = iir & 0x3e;
 544
 545                 switch (type) {
 546                 case UART_IIR_MSI:
 547                         check_modem_status(up);
 548                         break;
 549                 case UART_IIR_THRI:
 550                         transmit_chars(up, lsr);
 551                         break;
 552                 case UART_IIR_RX_TIMEOUT:
 553                 case UART_IIR_RDI:
 554                         serial_omap_rdi(up, lsr);
 555                         break;
 556                 case UART_IIR_RLSI:
 557                         serial_omap_rlsi(up, lsr);
 558                         break;
 559                 case UART_IIR_CTS_RTS_DSR:
 560                         /* simply try again */
 561                         break;
 562                 case UART_IIR_XOFF:
 563                 default:
 564                         break;
 565                 }
 566         } while (max_count--);
 567
 568         spin_unlock(&up->port.lock);
 569
 570         tty_flip_buffer_push(&up->port.state->port);
 571
 572         up->port_activity = jiffies;
 573
 574         return ret;
 575 }
 576
 577 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 578 {
 579         struct uart_omap_port *up = to_uart_omap_port(port);
 580         unsigned long flags;
 581         unsigned int ret = 0;
 582
 583         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 584         spin_lock_irqsave(&up->port.lock, flags);
 585         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 586         spin_unlock_irqrestore(&up->port.lock, flags);
 587
 588         return ret;
 589 }
 590
 591 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 592 {
 593         struct uart_omap_port *up = to_uart_omap_port(port);
 594         unsigned int status;
 595         unsigned int ret = 0;
 596
 597         status = check_modem_status(up);
 598
 599         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 600
 601         if (status & UART_MSR_DCD)
 602                 ret |= TIOCM_CAR;
 603         if (status & UART_MSR_RI)
 604                 ret |= TIOCM_RNG;
 605         if (status & UART_MSR_DSR)
 606                 ret |= TIOCM_DSR;
 607         if (status & UART_MSR_CTS)
 608                 ret |= TIOCM_CTS;
 609         return ret;
 610 }
 611
 612 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 613 {
 614         struct uart_omap_port *up = to_uart_omap_port(port);
 615         unsigned char mcr = 0, old_mcr, lcr;
 616
 617         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 618         if (mctrl & TIOCM_RTS)
 619                 mcr |= UART_MCR_RTS;
 620         if (mctrl & TIOCM_DTR)
 621                 mcr |= UART_MCR_DTR;
 622         if (mctrl & TIOCM_OUT1)
 623                 mcr |= UART_MCR_OUT1;
 624         if (mctrl & TIOCM_OUT2)
 625                 mcr |= UART_MCR_OUT2;
 626         if (mctrl & TIOCM_LOOP)
 627                 mcr |= UART_MCR_LOOP;
 628
 629         old_mcr = serial_in(up, UART_MCR);
 630         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 631                      UART_MCR_DTR | UART_MCR_RTS);
 632         up->mcr = old_mcr | mcr;
 633         serial_out(up, UART_MCR, up->mcr);
 634
 635         /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
 636         lcr = serial_in(up, UART_LCR);
 637         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 638         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 639                 up->efr |= UART_EFR_RTS;
 640         else
 641                 up->efr &= ~UART_EFR_RTS;
 642         serial_out(up, UART_EFR, up->efr);
 643         serial_out(up, UART_LCR, lcr);
 644 }
 645
 646 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 647 {
 648         struct uart_omap_port *up = to_uart_omap_port(port);
 649         unsigned long flags;
 650
 651         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 652         spin_lock_irqsave(&up->port.lock, flags);
 653         if (break_state == -1)
 654                 up->lcr |= UART_LCR_SBC;
 655         else
 656                 up->lcr &= ~UART_LCR_SBC;
 657         serial_out(up, UART_LCR, up->lcr);
 658         spin_unlock_irqrestore(&up->port.lock, flags);
 659 }
 660
 661 static int serial_omap_startup(struct uart_port *port)
 662 {
 663         struct uart_omap_port *up = to_uart_omap_port(port);
 664         unsigned long flags;
 665         int retval;
 666
 667         /*
 668          * Allocate the IRQ
 669          */
 670         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 671                                 up->name, up);
 672         if (retval)
 673                 return retval;
 674
 675         /* Optional wake-up IRQ */
 676         if (up->wakeirq) {
 677                 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
 678                 if (retval) {
 679                         free_irq(up->port.irq, up);
 680                         return retval;
 681                 }
 682         }
 683
 684         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 685
 686         pm_runtime_get_sync(up->dev);
 687         /*
 688          * Clear the FIFO buffers and disable them.
 689          * (they will be reenabled in set_termios())
 690          */
 691         serial_omap_clear_fifos(up);
 692
 693         /*
 694          * Clear the interrupt registers.
 695          */
 696         (void) serial_in(up, UART_LSR);
 697         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 698                 (void) serial_in(up, UART_RX);
 699         (void) serial_in(up, UART_IIR);
 700         (void) serial_in(up, UART_MSR);
 701
 702         /*
 703          * Now, initialize the UART
 704          */
 705         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 706         spin_lock_irqsave(&up->port.lock, flags);
 707         /*
 708          * Most PC uarts need OUT2 raised to enable interrupts.
 709          */
 710         up->port.mctrl |= TIOCM_OUT2;
 711         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 712         spin_unlock_irqrestore(&up->port.lock, flags);
 713
 714         up->msr_saved_flags = 0;
 715         /*
 716          * Finally, enable interrupts. Note: Modem status interrupts
 717          * are set via set_termios(), which will be occurring imminently
 718          * anyway, so we don't enable them here.
 719          */
 720         up->ier = UART_IER_RLSI | UART_IER_RDI;
 721         serial_out(up, UART_IER, up->ier);
 722
 723         /* Enable module level wake up */
 724         up->wer = OMAP_UART_WER_MOD_WKUP;
 725         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 726                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 727
 728         serial_out(up, UART_OMAP_WER, up->wer);
 729
 730         up->port_activity = jiffies;
 731         return 0;
 732 }
 733
 734 static void serial_omap_shutdown(struct uart_port *port)
 735 {
 736         struct uart_omap_port *up = to_uart_omap_port(port);
 737         unsigned long flags;
 738
 739         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 740
 741         /*
 742          * Disable interrupts from this port
 743          */
 744         up->ier = 0;
 745         serial_out(up, UART_IER, 0);
 746
 747         spin_lock_irqsave(&up->port.lock, flags);
 748         up->port.mctrl &= ~TIOCM_OUT2;
 749         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 750         spin_unlock_irqrestore(&up->port.lock, flags);
 751
 752         /*
 753          * Disable break condition and FIFOs
 754          */
 755         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 756         serial_omap_clear_fifos(up);
 757
 758         /*
 759          * Read data port to reset things, and then free the irq
 760          */
 761         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 762                 (void) serial_in(up, UART_RX);
 763
 764         pm_runtime_put_sync(up->dev);
 765         free_irq(up->port.irq, up);
 766         dev_pm_clear_wake_irq(up->dev);
 767 }
 768
 769 static void serial_omap_uart_qos_work(struct work_struct *work)
 770 {
 771         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 772                                                 qos_work);
 773
 774         cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
 775 }
 776
 777 static void
 778 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 779                         const struct ktermios *old)
 780 {
 781         struct uart_omap_port *up = to_uart_omap_port(port);
 782         unsigned char cval = 0;
 783         unsigned long flags;
 784         unsigned int baud, quot;
 785
 786         cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
 787
 788         if (termios->c_cflag & CSTOPB)
 789                 cval |= UART_LCR_STOP;
 790         if (termios->c_cflag & PARENB)
 791                 cval |= UART_LCR_PARITY;
 792         if (!(termios->c_cflag & PARODD))
 793                 cval |= UART_LCR_EPAR;
 794         if (termios->c_cflag & CMSPAR)
 795                 cval |= UART_LCR_SPAR;
 796
 797         /*
 798          * Ask the core to calculate the divisor for us.
 799          */
 800
 801         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 802         quot = serial_omap_get_divisor(port, baud);
 803
 804         /* calculate wakeup latency constraint */
 805         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 806         up->latency = up->calc_latency;
 807         schedule_work(&up->qos_work);
 808
 809         up->dll = quot & 0xff;
 810         up->dlh = quot >> 8;
 811         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 812
 813         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 814                         UART_FCR_ENABLE_FIFO;
 815
 816         /*
 817          * Ok, we're now changing the port state. Do it with
 818          * interrupts disabled.
 819          */
 820         spin_lock_irqsave(&up->port.lock, flags);
 821
 822         /*
 823          * Update the per-port timeout.
 824          */
 825         uart_update_timeout(port, termios->c_cflag, baud);
 826
 827         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 828         if (termios->c_iflag & INPCK)
 829                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 830         if (termios->c_iflag & (BRKINT | PARMRK))
 831                 up->port.read_status_mask |= UART_LSR_BI;
 832
 833         /*
 834          * Characters to ignore
 835          */
 836         up->port.ignore_status_mask = 0;
 837         if (termios->c_iflag & IGNPAR)
 838                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 839         if (termios->c_iflag & IGNBRK) {
 840                 up->port.ignore_status_mask |= UART_LSR_BI;
 841                 /*
 842                  * If we're ignoring parity and break indicators,
 843                  * ignore overruns too (for real raw support).
 844                  */
 845                 if (termios->c_iflag & IGNPAR)
 846                         up->port.ignore_status_mask |= UART_LSR_OE;
 847         }
 848
 849         /*
 850          * ignore all characters if CREAD is not set
 851          */
 852         if ((termios->c_cflag & CREAD) == 0)
 853                 up->port.ignore_status_mask |= UART_LSR_DR;
 854
 855         /*
 856          * Modem status interrupts
 857          */
 858         up->ier &= ~UART_IER_MSI;
 859         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 860                 up->ier |= UART_IER_MSI;
 861         serial_out(up, UART_IER, up->ier);
 862         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 863         up->lcr = cval;
 864         up->scr = 0;
 865
 866         /* FIFOs and DMA Settings */
 867
 868         /* FCR can be changed only when the
 869          * baud clock is not running
 870          * DLL_REG and DLH_REG set to 0.
 871          */
 872         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 873         serial_out(up, UART_DLL, 0);
 874         serial_out(up, UART_DLM, 0);
 875         serial_out(up, UART_LCR, 0);
 876
 877         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 878
 879         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 880         up->efr &= ~UART_EFR_SCD;
 881         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 882
 883         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 884         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 885         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 886         /* FIFO ENABLE, DMA MODE */
 887
 888         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 889         /*
 890          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 891          * sets Enables the granularity of 1 for TRIGGER RX
 892          * level. Along with setting RX FIFO trigger level
 893          * to 1 (as noted below, 16 characters) and TLR[3:0]
 894          * to zero this will result RX FIFO threshold level
 895          * to 1 character, instead of 16 as noted in comment
 896          * below.
 897          */
 898
 899         /* Set receive FIFO threshold to 16 characters and
 900          * transmit FIFO threshold to 32 spaces
 901          */
 902         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 903         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 904         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 905                 UART_FCR_ENABLE_FIFO;
 906
 907         serial_out(up, UART_FCR, up->fcr);
 908         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 909
 910         serial_out(up, UART_OMAP_SCR, up->scr);
 911
 912         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 913         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 914         serial_out(up, UART_MCR, up->mcr);
 915         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 916         serial_out(up, UART_EFR, up->efr);
 917         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 918
 919         /* Protocol, Baud Rate, and Interrupt Settings */
 920
 921         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 922                 serial_omap_mdr1_errataset(up, up->mdr1);
 923         else
 924                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 925
 926         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 927         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 928
 929         serial_out(up, UART_LCR, 0);
 930         serial_out(up, UART_IER, 0);
 931         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 932
 933         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 934         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 935
 936         serial_out(up, UART_LCR, 0);
 937         serial_out(up, UART_IER, up->ier);
 938         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 939
 940         serial_out(up, UART_EFR, up->efr);
 941         serial_out(up, UART_LCR, cval);
 942
 943         if (!serial_omap_baud_is_mode16(port, baud))
 944                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 945         else
 946                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 947
 948         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 949                 serial_omap_mdr1_errataset(up, up->mdr1);
 950         else
 951                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 952
 953         /* Configure flow control */
 954         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 955
 956         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
 957         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 958         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 959
 960         /* Enable access to TCR/TLR */
 961         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 962         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 963         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 964
 965         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 966
 967         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 968
 969         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 970                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 971                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 972                 up->efr |= UART_EFR_CTS;
 973         } else {
 974                 /* Disable AUTORTS and AUTOCTS */
 975                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
 976         }
 977
 978         if (up->port.flags & UPF_SOFT_FLOW) {
 979                 /* clear SW control mode bits */
 980                 up->efr &= OMAP_UART_SW_CLR;
 981
 982                 /*
 983                  * IXON Flag:
 984                  * Enable XON/XOFF flow control on input.
 985                  * Receiver compares XON1, XOFF1.
 986                  */
 987                 if (termios->c_iflag & IXON)
 988                         up->efr |= OMAP_UART_SW_RX;
 989
 990                 /*
 991                  * IXOFF Flag:
 992                  * Enable XON/XOFF flow control on output.
 993                  * Transmit XON1, XOFF1
 994                  */
 995                 if (termios->c_iflag & IXOFF) {
 996                         up->port.status |= UPSTAT_AUTOXOFF;
 997                         up->efr |= OMAP_UART_SW_TX;
 998                 }
 999
1000                 /*
1001                  * IXANY Flag:
1002                  * Enable any character to restart output.
1003                  * Operation resumes after receiving any
1004                  * character after recognition of the XOFF character
1005                  */
1006                 if (termios->c_iflag & IXANY)
1007                         up->mcr |= UART_MCR_XONANY;
1008                 else
1009                         up->mcr &= ~UART_MCR_XONANY;
1010         }
1011         serial_out(up, UART_MCR, up->mcr);
1012         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1013         serial_out(up, UART_EFR, up->efr);
1014         serial_out(up, UART_LCR, up->lcr);
1015
1016         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1017
1018         spin_unlock_irqrestore(&up->port.lock, flags);
1019         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1020 }
1021
1022 static void
1023 serial_omap_pm(struct uart_port *port, unsigned int state,
1024                unsigned int oldstate)
1025 {
1026         struct uart_omap_port *up = to_uart_omap_port(port);
1027         unsigned char efr;
1028
1029         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1030
1031         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1032         efr = serial_in(up, UART_EFR);
1033         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1034         serial_out(up, UART_LCR, 0);
1035
1036         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1037         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1038         serial_out(up, UART_EFR, efr);
1039         serial_out(up, UART_LCR, 0);
1040 }
1041
1042 static void serial_omap_release_port(struct uart_port *port)
1043 {
1044         dev_dbg(port->dev, "serial_omap_release_port+\n");
1045 }
1046
1047 static int serial_omap_request_port(struct uart_port *port)
1048 {
1049         dev_dbg(port->dev, "serial_omap_request_port+\n");
1050         return 0;
1051 }
1052
1053 static void serial_omap_config_port(struct uart_port *port, int flags)
1054 {
1055         struct uart_omap_port *up = to_uart_omap_port(port);
1056
1057         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1058                                                         up->port.line);
1059         up->port.type = PORT_OMAP;
1060         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1061 }
1062
1063 static int
1064 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1065 {
1066         /* we don't want the core code to modify any port params */
1067         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1068         return -EINVAL;
1069 }
1070
1071 static const char *
1072 serial_omap_type(struct uart_port *port)
1073 {
1074         struct uart_omap_port *up = to_uart_omap_port(port);
1075
1076         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1077         return up->name;
1078 }
1079
1080 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1081 {
1082         unsigned int status, tmout = 10000;
1083
1084         /* Wait up to 10ms for the character(s) to be sent. */
1085         do {
1086                 status = serial_in(up, UART_LSR);
1087
1088                 if (status & UART_LSR_BI)
1089                         up->lsr_break_flag = UART_LSR_BI;
1090
1091                 if (--tmout == 0)
1092                         break;
1093                 udelay(1);
1094         } while (!uart_lsr_tx_empty(status));
1095
1096         /* Wait up to 1s for flow control if necessary */
1097         if (up->port.flags & UPF_CONS_FLOW) {
1098                 tmout = 1000000;
1099                 for (tmout = 1000000; tmout; tmout--) {
1100                         unsigned int msr = serial_in(up, UART_MSR);
1101
1102                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1103                         if (msr & UART_MSR_CTS)
1104                                 break;
1105
1106                         udelay(1);
1107                 }
1108         }
1109 }
1110
1111 #ifdef CONFIG_CONSOLE_POLL
1112
1113 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1114 {
1115         struct uart_omap_port *up = to_uart_omap_port(port);
1116
1117         wait_for_xmitr(up);
1118         serial_out(up, UART_TX, ch);
1119 }
1120
1121 static int serial_omap_poll_get_char(struct uart_port *port)
1122 {
1123         struct uart_omap_port *up = to_uart_omap_port(port);
1124         unsigned int status;
1125
1126         status = serial_in(up, UART_LSR);
1127         if (!(status & UART_LSR_DR)) {
1128                 status = NO_POLL_CHAR;
1129                 goto out;
1130         }
1131
1132         status = serial_in(up, UART_RX);
1133
1134 out:
1135         return status;
1136 }
1137
1138 #endif /* CONFIG_CONSOLE_POLL */
1139
1140 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1141
1142 #ifdef CONFIG_SERIAL_EARLYCON
1143 static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1144 {
1145         offset <<= port->regshift;
1146         return readw(port->membase + offset);
1147 }
1148
1149 static void omap_serial_early_out(struct uart_port *port, int offset,
1150                                   int value)
1151 {
1152         offset <<= port->regshift;
1153         writew(value, port->membase + offset);
1154 }
1155
1156 static void omap_serial_early_putc(struct uart_port *port, unsigned char c)
1157 {
1158         unsigned int status;
1159
1160         for (;;) {
1161                 status = omap_serial_early_in(port, UART_LSR);
1162                 if (uart_lsr_tx_empty(status))
1163                         break;
1164                 cpu_relax();
1165         }
1166         omap_serial_early_out(port, UART_TX, c);
1167 }
1168
1169 static void early_omap_serial_write(struct console *console, const char *s,
1170                                     unsigned int count)
1171 {
1172         struct earlycon_device *device = console->data;
1173         struct uart_port *port = &device->port;
1174
1175         uart_console_write(port, s, count, omap_serial_early_putc);
1176 }
1177
1178 static int __init early_omap_serial_setup(struct earlycon_device *device,
1179                                           const char *options)
1180 {
1181         struct uart_port *port = &device->port;
1182
1183         if (!(device->port.membase || device->port.iobase))
1184                 return -ENODEV;
1185
1186         port->regshift = 2;
1187         device->con->write = early_omap_serial_write;
1188         return 0;
1189 }
1190
1191 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1192 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1193 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1194 #endif /* CONFIG_SERIAL_EARLYCON */
1195
1196 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1197
1198 static struct uart_driver serial_omap_reg;
1199
1200 static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch)
1201 {
1202         struct uart_omap_port *up = to_uart_omap_port(port);
1203
1204         wait_for_xmitr(up);
1205         serial_out(up, UART_TX, ch);
1206 }
1207
1208 static void
1209 serial_omap_console_write(struct console *co, const char *s,
1210                 unsigned int count)
1211 {
1212         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1213         unsigned long flags;
1214         unsigned int ier;
1215         int locked = 1;
1216
1217         local_irq_save(flags);
1218         if (up->port.sysrq)
1219                 locked = 0;
1220         else if (oops_in_progress)
1221                 locked = spin_trylock(&up->port.lock);
1222         else
1223                 spin_lock(&up->port.lock);
1224
1225         /*
1226          * First save the IER then disable the interrupts
1227          */
1228         ier = serial_in(up, UART_IER);
1229         serial_out(up, UART_IER, 0);
1230
1231         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1232
1233         /*
1234          * Finally, wait for transmitter to become empty
1235          * and restore the IER
1236          */
1237         wait_for_xmitr(up);
1238         serial_out(up, UART_IER, ier);
1239         /*
1240          * The receive handling will happen properly because the
1241          * receive ready bit will still be set; it is not cleared
1242          * on read.  However, modem control will not, we must
1243          * call it if we have saved something in the saved flags
1244          * while processing with interrupts off.
1245          */
1246         if (up->msr_saved_flags)
1247                 check_modem_status(up);
1248
1249         if (locked)
1250                 spin_unlock(&up->port.lock);
1251         local_irq_restore(flags);
1252 }
1253
1254 static int __init
1255 serial_omap_console_setup(struct console *co, char *options)
1256 {
1257         struct uart_omap_port *up;
1258         int baud = 115200;
1259         int bits = 8;
1260         int parity = 'n';
1261         int flow = 'n';
1262
1263         if (serial_omap_console_ports[co->index] == NULL)
1264                 return -ENODEV;
1265         up = serial_omap_console_ports[co->index];
1266
1267         if (options)
1268                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1269
1270         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1271 }
1272
1273 static struct console serial_omap_console = {
1274         .name           = OMAP_SERIAL_NAME,
1275         .write          = serial_omap_console_write,
1276         .device         = uart_console_device,
1277         .setup          = serial_omap_console_setup,
1278         .flags          = CON_PRINTBUFFER,
1279         .index          = -1,
1280         .data           = &serial_omap_reg,
1281 };
1282
1283 static void serial_omap_add_console_port(struct uart_omap_port *up)
1284 {
1285         serial_omap_console_ports[up->port.line] = up;
1286 }
1287
1288 #define OMAP_CONSOLE    (&serial_omap_console)
1289
1290 #else
1291
1292 #define OMAP_CONSOLE    NULL
1293
1294 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1295 {}
1296
1297 #endif
1298
1299 /* Enable or disable the rs485 support */
1300 static int
1301 serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios,
1302                          struct serial_rs485 *rs485)
1303 {
1304         struct uart_omap_port *up = to_uart_omap_port(port);
1305         unsigned int mode;
1306         int val;
1307
1308         /* Disable interrupts from this port */
1309         mode = up->ier;
1310         up->ier = 0;
1311         serial_out(up, UART_IER, 0);
1312
1313         /* enable / disable rts */
1314         val = (rs485->flags & SER_RS485_ENABLED) ?
1315               SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1316         val = (rs485->flags & val) ? 1 : 0;
1317         gpiod_set_value(up->rts_gpiod, val);
1318
1319         /* Enable interrupts */
1320         up->ier = mode;
1321         serial_out(up, UART_IER, up->ier);
1322
1323         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1324          * TX FIFO is below the trigger level.
1325          */
1326         if (!(rs485->flags & SER_RS485_ENABLED) &&
1327             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1328                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1329                 serial_out(up, UART_OMAP_SCR, up->scr);
1330         }
1331
1332         return 0;
1333 }
1334
1335 static const struct uart_ops serial_omap_pops = {
1336         .tx_empty       = serial_omap_tx_empty,
1337         .set_mctrl      = serial_omap_set_mctrl,
1338         .get_mctrl      = serial_omap_get_mctrl,
1339         .stop_tx        = serial_omap_stop_tx,
1340         .start_tx       = serial_omap_start_tx,
1341         .throttle       = serial_omap_throttle,
1342         .unthrottle     = serial_omap_unthrottle,
1343         .stop_rx        = serial_omap_stop_rx,
1344         .enable_ms      = serial_omap_enable_ms,
1345         .break_ctl      = serial_omap_break_ctl,
1346         .startup        = serial_omap_startup,
1347         .shutdown       = serial_omap_shutdown,
1348         .set_termios    = serial_omap_set_termios,
1349         .pm             = serial_omap_pm,
1350         .type           = serial_omap_type,
1351         .release_port   = serial_omap_release_port,
1352         .request_port   = serial_omap_request_port,
1353         .config_port    = serial_omap_config_port,
1354         .verify_port    = serial_omap_verify_port,
1355 #ifdef CONFIG_CONSOLE_POLL
1356         .poll_put_char  = serial_omap_poll_put_char,
1357         .poll_get_char  = serial_omap_poll_get_char,
1358 #endif
1359 };
1360
1361 static struct uart_driver serial_omap_reg = {
1362         .owner          = THIS_MODULE,
1363         .driver_name    = "OMAP-SERIAL",
1364         .dev_name       = OMAP_SERIAL_NAME,
1365         .nr             = OMAP_MAX_HSUART_PORTS,
1366         .cons           = OMAP_CONSOLE,
1367 };
1368
1369 #ifdef CONFIG_PM_SLEEP
1370 static int serial_omap_prepare(struct device *dev)
1371 {
1372         struct uart_omap_port *up = dev_get_drvdata(dev);
1373
1374         up->is_suspending = true;
1375
1376         return 0;
1377 }
1378
1379 static void serial_omap_complete(struct device *dev)
1380 {
1381         struct uart_omap_port *up = dev_get_drvdata(dev);
1382
1383         up->is_suspending = false;
1384 }
1385
1386 static int serial_omap_suspend(struct device *dev)
1387 {
1388         struct uart_omap_port *up = dev_get_drvdata(dev);
1389
1390         uart_suspend_port(&serial_omap_reg, &up->port);
1391         flush_work(&up->qos_work);
1392
1393         if (device_may_wakeup(dev))
1394                 serial_omap_enable_wakeup(up, true);
1395         else
1396                 serial_omap_enable_wakeup(up, false);
1397
1398         return 0;
1399 }
1400
1401 static int serial_omap_resume(struct device *dev)
1402 {
1403         struct uart_omap_port *up = dev_get_drvdata(dev);
1404
1405         if (device_may_wakeup(dev))
1406                 serial_omap_enable_wakeup(up, false);
1407
1408         uart_resume_port(&serial_omap_reg, &up->port);
1409
1410         return 0;
1411 }
1412 #else
1413 #define serial_omap_prepare NULL
1414 #define serial_omap_complete NULL
1415 #endif /* CONFIG_PM_SLEEP */
1416
1417 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1418 {
1419         u32 mvr, scheme;
1420         u16 revision, major, minor;
1421
1422         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1423
1424         /* Check revision register scheme */
1425         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1426
1427         switch (scheme) {
1428         case 0: /* Legacy Scheme: OMAP2/3 */
1429                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1430                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1431                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1432                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1433                 break;
1434         case 1:
1435                 /* New Scheme: OMAP4+ */
1436                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1437                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1438                                         OMAP_UART_MVR_MAJ_SHIFT;
1439                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1440                 break;
1441         default:
1442                 dev_warn(up->dev,
1443                         "Unknown %s revision, defaulting to highest\n",
1444                         up->name);
1445                 /* highest possible revision */
1446                 major = 0xff;
1447                 minor = 0xff;
1448         }
1449
1450         /* normalize revision for the driver */
1451         revision = UART_BUILD_REVISION(major, minor);
1452
1453         switch (revision) {
1454         case OMAP_UART_REV_46:
1455                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1456                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1457                 break;
1458         case OMAP_UART_REV_52:
1459                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1460                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1461                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1462                 break;
1463         case OMAP_UART_REV_63:
1464                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1465                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1466                 break;
1467         default:
1468                 break;
1469         }
1470 }
1471
1472 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1473 {
1474         struct omap_uart_port_info *omap_up_info;
1475
1476         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1477         if (!omap_up_info)
1478                 return NULL; /* out of memory */
1479
1480         of_property_read_u32(dev->of_node, "clock-frequency",
1481                                          &omap_up_info->uartclk);
1482
1483         omap_up_info->flags = UPF_BOOT_AUTOCONF;
1484
1485         return omap_up_info;
1486 }
1487
1488 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1489                                    struct device *dev)
1490 {
1491         struct serial_rs485 *rs485conf = &up->port.rs485;
1492         struct device_node *np = dev->of_node;
1493         enum gpiod_flags gflags;
1494         int ret;
1495
1496         rs485conf->flags = 0;
1497         up->rts_gpiod = NULL;
1498
1499         if (!np)
1500                 return 0;
1501
1502         ret = uart_get_rs485_mode(&up->port);
1503         if (ret)
1504                 return ret;
1505
1506         if (of_property_read_bool(np, "rs485-rts-active-high")) {
1507                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1508                 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1509         } else {
1510                 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1511                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1512         }
1513
1514         /* check for tx enable gpio */
1515         gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1516                 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1517         up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1518         if (IS_ERR(up->rts_gpiod)) {
1519                 ret = PTR_ERR(up->rts_gpiod);
1520                 if (ret == -EPROBE_DEFER)
1521                         return ret;
1522
1523                 up->rts_gpiod = NULL;
1524                 up->port.rs485_supported = (const struct serial_rs485) { };
1525                 if (rs485conf->flags & SER_RS485_ENABLED) {
1526                         dev_err(dev, "disabling RS-485 (rts-gpio missing in device tree)\n");
1527                         memset(rs485conf, 0, sizeof(*rs485conf));
1528                 }
1529         } else {
1530                 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1531         }
1532
1533         return 0;
1534 }
1535
1536 static const struct serial_rs485 serial_omap_rs485_supported = {
1537         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1538                  SER_RS485_RX_DURING_TX,
1539         .delay_rts_before_send = 1,
1540         .delay_rts_after_send = 1,
1541 };
1542
1543 static int serial_omap_probe(struct platform_device *pdev)
1544 {
1545         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1546         struct uart_omap_port *up;
1547         struct resource *mem;
1548         void __iomem *base;
1549         int uartirq = 0;
1550         int wakeirq = 0;
1551         int ret;
1552
1553         /* The optional wakeirq may be specified in the board dts file */
1554         if (pdev->dev.of_node) {
1555                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1556                 if (!uartirq)
1557                         return -EPROBE_DEFER;
1558                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1559                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1560                 pdev->dev.platform_data = omap_up_info;
1561         } else {
1562                 uartirq = platform_get_irq(pdev, 0);
1563                 if (uartirq < 0)
1564                         return -EPROBE_DEFER;
1565         }
1566
1567         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1568         if (!up)
1569                 return -ENOMEM;
1570
1571         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1572         base = devm_ioremap_resource(&pdev->dev, mem);
1573         if (IS_ERR(base))
1574                 return PTR_ERR(base);
1575
1576         up->dev = &pdev->dev;
1577         up->port.dev = &pdev->dev;
1578         up->port.type = PORT_OMAP;
1579         up->port.iotype = UPIO_MEM;
1580         up->port.irq = uartirq;
1581         up->port.regshift = 2;
1582         up->port.fifosize = 64;
1583         up->port.ops = &serial_omap_pops;
1584         up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1585
1586         if (pdev->dev.of_node)
1587                 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1588         else
1589                 ret = pdev->id;
1590
1591         if (ret < 0) {
1592                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1593                         ret);
1594                 goto err_port_line;
1595         }
1596         up->port.line = ret;
1597
1598         if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1599                 dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
1600                         OMAP_MAX_HSUART_PORTS);
1601                 ret = -ENXIO;
1602                 goto err_port_line;
1603         }
1604
1605         up->wakeirq = wakeirq;
1606         if (!up->wakeirq)
1607                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1608                          up->port.line);
1609
1610         ret = serial_omap_probe_rs485(up, &pdev->dev);
1611         if (ret < 0)
1612                 goto err_rs485;
1613
1614         sprintf(up->name, "OMAP UART%d", up->port.line);
1615         up->port.mapbase = mem->start;
1616         up->port.membase = base;
1617         up->port.flags = omap_up_info->flags;
1618         up->port.uartclk = omap_up_info->uartclk;
1619         up->port.rs485_config = serial_omap_config_rs485;
1620         up->port.rs485_supported = serial_omap_rs485_supported;
1621         if (!up->port.uartclk) {
1622                 up->port.uartclk = DEFAULT_CLK_SPEED;
1623                 dev_warn(&pdev->dev,
1624                          "No clock speed specified: using default: %d\n",
1625                          DEFAULT_CLK_SPEED);
1626         }
1627
1628         up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1629         up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1630         cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1631         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1632
1633         platform_set_drvdata(pdev, up);
1634         if (omap_up_info->autosuspend_timeout == 0)
1635                 omap_up_info->autosuspend_timeout = -1;
1636
1637         device_init_wakeup(up->dev, true);
1638
1639         pm_runtime_enable(&pdev->dev);
1640
1641         pm_runtime_get_sync(&pdev->dev);
1642
1643         omap_serial_fill_features_erratas(up);
1644
1645         ui[up->port.line] = up;
1646         serial_omap_add_console_port(up);
1647
1648         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1649         if (ret != 0)
1650                 goto err_add_port;
1651
1652         return 0;
1653
1654 err_add_port:
1655         pm_runtime_put_sync(&pdev->dev);
1656         pm_runtime_disable(&pdev->dev);
1657         cpu_latency_qos_remove_request(&up->pm_qos_request);
1658         device_init_wakeup(up->dev, false);
1659 err_rs485:
1660 err_port_line:
1661         return ret;
1662 }
1663
1664 static int serial_omap_remove(struct platform_device *dev)
1665 {
1666         struct uart_omap_port *up = platform_get_drvdata(dev);
1667
1668         pm_runtime_get_sync(up->dev);
1669
1670         uart_remove_one_port(&serial_omap_reg, &up->port);
1671
1672         pm_runtime_put_sync(up->dev);
1673         pm_runtime_disable(up->dev);
1674         cpu_latency_qos_remove_request(&up->pm_qos_request);
1675         device_init_wakeup(&dev->dev, false);
1676
1677         return 0;
1678 }
1679
1680 /*
1681  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1682  * The access to uart register after MDR1 Access
1683  * causes UART to corrupt data.
1684  *
1685  * Need a delay =
1686  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1687  * give 10 times as much
1688  */
1689 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1690 {
1691         u8 timeout = 255;
1692
1693         serial_out(up, UART_OMAP_MDR1, mdr1);
1694         udelay(2);
1695         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1696                         UART_FCR_CLEAR_RCVR);
1697         /*
1698          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1699          * TX_FIFO_E bit is 1.
1700          */
1701         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1702                                 (UART_LSR_THRE | UART_LSR_DR))) {
1703                 timeout--;
1704                 if (!timeout) {
1705                         /* Should *never* happen. we warn and carry on */
1706                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1707                                                 serial_in(up, UART_LSR));
1708                         break;
1709                 }
1710                 udelay(1);
1711         }
1712 }
1713
1714 #ifdef CONFIG_PM
1715 static void serial_omap_restore_context(struct uart_omap_port *up)
1716 {
1717         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1718                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1719         else
1720                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1721
1722         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1723         serial_out(up, UART_EFR, UART_EFR_ECB);
1724         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1725         serial_out(up, UART_IER, 0x0);
1726         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1727         serial_out(up, UART_DLL, up->dll);
1728         serial_out(up, UART_DLM, up->dlh);
1729         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1730         serial_out(up, UART_IER, up->ier);
1731         serial_out(up, UART_FCR, up->fcr);
1732         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1733         serial_out(up, UART_MCR, up->mcr);
1734         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1735         serial_out(up, UART_OMAP_SCR, up->scr);
1736         serial_out(up, UART_EFR, up->efr);
1737         serial_out(up, UART_LCR, up->lcr);
1738         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1739                 serial_omap_mdr1_errataset(up, up->mdr1);
1740         else
1741                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1742         serial_out(up, UART_OMAP_WER, up->wer);
1743 }
1744
1745 static int serial_omap_runtime_suspend(struct device *dev)
1746 {
1747         struct uart_omap_port *up = dev_get_drvdata(dev);
1748
1749         if (!up)
1750                 return -EINVAL;
1751
1752         /*
1753         * When using 'no_console_suspend', the console UART must not be
1754         * suspended. Since driver suspend is managed by runtime suspend,
1755         * preventing runtime suspend (by returning error) will keep device
1756         * active during suspend.
1757         */
1758         if (up->is_suspending && !console_suspend_enabled &&
1759             uart_console(&up->port))
1760                 return -EBUSY;
1761
1762         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1763
1764         serial_omap_enable_wakeup(up, true);
1765
1766         up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1767         schedule_work(&up->qos_work);
1768
1769         return 0;
1770 }
1771
1772 static int serial_omap_runtime_resume(struct device *dev)
1773 {
1774         struct uart_omap_port *up = dev_get_drvdata(dev);
1775
1776         int loss_cnt = serial_omap_get_context_loss_count(up);
1777
1778         serial_omap_enable_wakeup(up, false);
1779
1780         if (loss_cnt < 0) {
1781                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1782                         loss_cnt);
1783                 serial_omap_restore_context(up);
1784         } else if (up->context_loss_cnt != loss_cnt) {
1785                 serial_omap_restore_context(up);
1786         }
1787         up->latency = up->calc_latency;
1788         schedule_work(&up->qos_work);
1789
1790         return 0;
1791 }
1792 #endif
1793
1794 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1795         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1796         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1797                                 serial_omap_runtime_resume, NULL)
1798         .prepare        = serial_omap_prepare,
1799         .complete       = serial_omap_complete,
1800 };
1801
1802 #if defined(CONFIG_OF)
1803 static const struct of_device_id omap_serial_of_match[] = {
1804         { .compatible = "ti,omap2-uart" },
1805         { .compatible = "ti,omap3-uart" },
1806         { .compatible = "ti,omap4-uart" },
1807         {},
1808 };
1809 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1810 #endif
1811
1812 static struct platform_driver serial_omap_driver = {
1813         .probe          = serial_omap_probe,
1814         .remove         = serial_omap_remove,
1815         .driver         = {
1816                 .name   = OMAP_SERIAL_DRIVER_NAME,
1817                 .pm     = &serial_omap_dev_pm_ops,
1818                 .of_match_table = of_match_ptr(omap_serial_of_match),
1819         },
1820 };
1821
1822 static int __init serial_omap_init(void)
1823 {
1824         int ret;
1825
1826         ret = uart_register_driver(&serial_omap_reg);
1827         if (ret != 0)
1828                 return ret;
1829         ret = platform_driver_register(&serial_omap_driver);
1830         if (ret != 0)
1831                 uart_unregister_driver(&serial_omap_reg);
1832         return ret;
1833 }
1834
1835 static void __exit serial_omap_exit(void)
1836 {
1837         platform_driver_unregister(&serial_omap_driver);
1838         uart_unregister_driver(&serial_omap_reg);
1839 }
1840
1841 module_init(serial_omap_init);
1842 module_exit(serial_omap_exit);
1843
1844 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1845 MODULE_LICENSE("GPL");
1846 MODULE_AUTHOR("Texas Instruments Inc");