1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
7 #include <linux/spi/spi.h>
9 #include "wilc_wfi_netdevice.h"
10 #include "wilc_wfi_cfgoperations.h"
18 static const struct wilc_hif_func wilc_hif_spi;
20 /********************************************
24 ********************************************/
26 static const u8 crc7_syndrome_table[256] = {
27 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
28 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
29 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
30 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
31 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
32 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
33 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
34 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
35 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
36 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
37 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
38 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
39 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
40 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
41 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
42 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
43 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
44 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
45 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
46 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
47 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
48 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
49 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
50 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
51 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
52 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
53 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
54 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
55 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
56 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
57 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
58 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
61 static u8 crc7_byte(u8 crc, u8 data)
63 return crc7_syndrome_table[(crc << 1) ^ data];
66 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
69 crc = crc7_byte(crc, *buffer++);
73 /********************************************
75 * Spi protocol Function
77 ********************************************/
79 #define CMD_DMA_WRITE 0xc1
80 #define CMD_DMA_READ 0xc2
81 #define CMD_INTERNAL_WRITE 0xc3
82 #define CMD_INTERNAL_READ 0xc4
83 #define CMD_TERMINATE 0xc5
84 #define CMD_REPEAT 0xc6
85 #define CMD_DMA_EXT_WRITE 0xc7
86 #define CMD_DMA_EXT_READ 0xc8
87 #define CMD_SINGLE_WRITE 0xc9
88 #define CMD_SINGLE_READ 0xca
89 #define CMD_RESET 0xcf
96 #define DATA_PKT_SZ_256 256
97 #define DATA_PKT_SZ_512 512
98 #define DATA_PKT_SZ_1K 1024
99 #define DATA_PKT_SZ_4K (4 * 1024)
100 #define DATA_PKT_SZ_8K (8 * 1024)
101 #define DATA_PKT_SZ DATA_PKT_SZ_8K
103 #define USE_SPI_DMA 0
105 static int wilc_bus_probe(struct spi_device *spi)
109 struct gpio_desc *gpio;
110 struct wilc_spi *spi_priv;
112 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
116 gpio = gpiod_get(&spi->dev, "irq", GPIOD_IN);
118 /* get the GPIO descriptor from hardcode GPIO number */
119 gpio = gpio_to_desc(GPIO_NUM);
121 dev_err(&spi->dev, "failed to get the irq gpio\n");
124 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
130 spi_set_drvdata(spi, wilc);
131 wilc->dev = &spi->dev;
132 wilc->bus_data = spi_priv;
133 wilc->gpio_irq = gpio;
138 static int wilc_bus_remove(struct spi_device *spi)
140 struct wilc *wilc = spi_get_drvdata(spi);
142 /* free the GPIO in module remove */
144 gpiod_put(wilc->gpio_irq);
145 wilc_netdev_cleanup(wilc);
149 static const struct of_device_id wilc_of_match[] = {
150 { .compatible = "microchip,wilc1000-spi", },
153 MODULE_DEVICE_TABLE(of, wilc_of_match);
155 static struct spi_driver wilc_spi_driver = {
158 .of_match_table = wilc_of_match,
160 .probe = wilc_bus_probe,
161 .remove = wilc_bus_remove,
163 module_spi_driver(wilc_spi_driver);
164 MODULE_LICENSE("GPL");
166 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
168 struct spi_device *spi = to_spi_device(wilc->dev);
170 struct spi_message msg;
173 struct spi_transfer tr = {
178 char *r_buffer = kzalloc(len, GFP_KERNEL);
183 tr.rx_buf = r_buffer;
184 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
186 memset(&msg, 0, sizeof(msg));
187 spi_message_init(&msg);
189 msg.is_dma_mapped = USE_SPI_DMA;
190 spi_message_add_tail(&tr, &msg);
192 ret = spi_sync(spi, &msg);
194 dev_err(&spi->dev, "SPI transaction failed\n");
199 "can't write data with the following length: %d\n",
207 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
209 struct spi_device *spi = to_spi_device(wilc->dev);
213 struct spi_message msg;
214 struct spi_transfer tr = {
220 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
225 tr.tx_buf = t_buffer;
227 memset(&msg, 0, sizeof(msg));
228 spi_message_init(&msg);
230 msg.is_dma_mapped = USE_SPI_DMA;
231 spi_message_add_tail(&tr, &msg);
233 ret = spi_sync(spi, &msg);
235 dev_err(&spi->dev, "SPI transaction failed\n");
239 "can't read data with the following length: %u\n",
247 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
249 struct spi_device *spi = to_spi_device(wilc->dev);
253 struct spi_message msg;
254 struct spi_transfer tr = {
263 memset(&msg, 0, sizeof(msg));
264 spi_message_init(&msg);
266 msg.is_dma_mapped = USE_SPI_DMA;
268 spi_message_add_tail(&tr, &msg);
269 ret = spi_sync(spi, &msg);
271 dev_err(&spi->dev, "SPI transaction failed\n");
274 "can't read data with the following length: %u\n",
282 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
285 struct spi_device *spi = to_spi_device(wilc->dev);
286 struct wilc_spi *spi_priv = wilc->bus_data;
298 case CMD_SINGLE_READ: /* single word (4 bytes) read */
299 wb[1] = (u8)(adr >> 16);
300 wb[2] = (u8)(adr >> 8);
305 case CMD_INTERNAL_READ: /* internal register read */
306 wb[1] = (u8)(adr >> 8);
335 case CMD_DMA_WRITE: /* dma write */
336 case CMD_DMA_READ: /* dma read */
337 wb[1] = (u8)(adr >> 16);
338 wb[2] = (u8)(adr >> 8);
340 wb[4] = (u8)(sz >> 8);
345 case CMD_DMA_EXT_WRITE: /* dma extended write */
346 case CMD_DMA_EXT_READ: /* dma extended read */
347 wb[1] = (u8)(adr >> 16);
348 wb[2] = (u8)(adr >> 8);
350 wb[4] = (u8)(sz >> 16);
351 wb[5] = (u8)(sz >> 8);
356 case CMD_INTERNAL_WRITE: /* internal register write */
357 wb[1] = (u8)(adr >> 8);
368 case CMD_SINGLE_WRITE: /* single word write */
369 wb[1] = (u8)(adr >> 16);
370 wb[2] = (u8)(adr >> 8);
387 if (!spi_priv->crc_off)
388 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
392 #define NUM_SKIP_BYTES (1)
393 #define NUM_RSP_BYTES (2)
394 #define NUM_DATA_HDR_BYTES (1)
395 #define NUM_DATA_BYTES (4)
396 #define NUM_CRC_BYTES (2)
397 #define NUM_DUMMY_BYTES (3)
398 if (cmd == CMD_RESET ||
399 cmd == CMD_TERMINATE ||
401 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
402 } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
403 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
405 if (!spi_priv->crc_off)
406 len2 = len + tmp + NUM_CRC_BYTES;
410 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
412 #undef NUM_DUMMY_BYTES
414 if (len2 > ARRAY_SIZE(wb)) {
415 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
416 len2, ARRAY_SIZE(wb));
419 /* zero spi write buffers. */
420 for (wix = len; wix < len2; wix++)
424 if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
425 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
430 * Command/Control response
432 if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
433 rix++; /* skip 1 byte */
439 "Failed cmd response, cmd (%02x), resp (%02x)\n",
449 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
454 if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
455 cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
457 * Data Respnose header
462 * ensure there is room in buffer later
463 * to read data and crc
471 if (((rsp >> 4) & 0xf) == 0xf)
477 "Error, data read response (%02x)\n", rsp);
482 if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
486 if ((rix + 3) < len2) {
493 "buffer overrun when reading data.\n");
497 if (!spi_priv->crc_off) {
501 if ((rix + 1) < len2) {
506 "buffer overrun when reading crc.\n");
510 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
513 /* some data may be read in response to dummy bytes. */
514 for (ix = 0; (rix < len2) && (ix < sz); )
522 if (sz <= (DATA_PKT_SZ - ix))
525 nbytes = DATA_PKT_SZ - ix;
530 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
532 "Failed block read, bus err\n");
539 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
541 "Failed block crc read, bus err\n");
550 * if any data in left unread,
551 * then read the rest using normal DMA code.
556 if (sz <= DATA_PKT_SZ)
559 nbytes = DATA_PKT_SZ;
562 * read data response only on the next DMA cycles not
563 * the first DMA since data response header is already
564 * handled above for the first DMA.
567 * Data Respnose header
571 if (wilc_spi_rx(wilc, &rsp, 1)) {
573 "Failed resp read, bus err\n");
577 if (((rsp >> 4) & 0xf) == 0xf)
581 if (result == N_FAIL)
587 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
589 "Failed block read, bus err\n");
597 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
599 "Failed block crc read, bus err\n");
611 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
613 struct spi_device *spi = to_spi_device(wilc->dev);
614 struct wilc_spi *spi_priv = wilc->bus_data;
617 u8 cmd, order, crc[2] = {0};
624 if (sz <= DATA_PKT_SZ) {
628 nbytes = DATA_PKT_SZ;
641 if (wilc_spi_tx(wilc, &cmd, 1)) {
643 "Failed data block cmd write, bus error...\n");
651 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
653 "Failed data block write, bus error...\n");
661 if (!spi_priv->crc_off) {
662 if (wilc_spi_tx(wilc, crc, 2)) {
663 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
670 * No need to wait for response
679 /********************************************
681 * Spi Internal Read/Write Function
683 ********************************************/
685 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
687 struct spi_device *spi = to_spi_device(wilc->dev);
691 result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
694 dev_err(&spi->dev, "Failed internal write cmd...\n");
699 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
701 struct spi_device *spi = to_spi_device(wilc->dev);
704 result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
706 if (result != N_OK) {
707 dev_err(&spi->dev, "Failed internal read cmd...\n");
716 /********************************************
720 ********************************************/
722 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
724 struct spi_device *spi = to_spi_device(wilc->dev);
726 u8 cmd = CMD_SINGLE_WRITE;
731 /* Clockless register */
732 cmd = CMD_INTERNAL_WRITE;
736 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
738 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
743 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
745 struct spi_device *spi = to_spi_device(wilc->dev);
749 * has to be greated than 4
754 result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
755 if (result != N_OK) {
757 "Failed cmd, write block (%08x)...\n", addr);
764 result = spi_data_write(wilc, buf, size);
766 dev_err(&spi->dev, "Failed block data write...\n");
771 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
773 struct spi_device *spi = to_spi_device(wilc->dev);
775 u8 cmd = CMD_SINGLE_READ;
779 /* Clockless register */
780 cmd = CMD_INTERNAL_READ;
784 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
785 if (result != N_OK) {
786 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
795 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
797 struct spi_device *spi = to_spi_device(wilc->dev);
803 result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
804 if (result != N_OK) {
805 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
812 /********************************************
816 ********************************************/
818 static int wilc_spi_deinit(struct wilc *wilc)
826 static int wilc_spi_init(struct wilc *wilc, bool resume)
828 struct spi_device *spi = to_spi_device(wilc->dev);
829 struct wilc_spi *spi_priv = wilc->bus_data;
835 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
836 dev_err(&spi->dev, "Fail cmd read chip id...\n");
847 * TODO: We can remove the CRC trials if there is a definite
850 /* the SPI to it's initial value. */
851 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
853 * Read failed. Try with CRC off. This might happen when module
854 * is removed but chip isn't reset
856 spi_priv->crc_off = 1;
858 "Failed read with CRC on, retrying with CRC off\n");
859 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
861 * Read failed with both CRC on and off,
864 dev_err(&spi->dev, "Failed internal read protocol\n");
868 if (spi_priv->crc_off == 0) {
869 reg &= ~0xc; /* disable crc checking */
872 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
874 "[wilc spi %d]: Failed internal write reg\n",
878 spi_priv->crc_off = 1;
882 * make sure can read back chip id correctly
884 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
885 dev_err(&spi->dev, "Fail cmd read chip id...\n");
889 spi_priv->has_thrpt_enh = 1;
896 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
898 struct spi_device *spi = to_spi_device(wilc->dev);
899 struct wilc_spi *spi_priv = wilc->bus_data;
902 if (spi_priv->has_thrpt_enh) {
903 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
905 *size = *size & IRQ_DMA_WD_CNT_MASK;
910 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
914 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
917 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
924 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
926 struct spi_device *spi = to_spi_device(wilc->dev);
927 struct wilc_spi *spi_priv = wilc->bus_data;
935 int k = IRG_FLAGS_OFFSET + 5;
937 if (spi_priv->has_thrpt_enh)
938 return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
940 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
943 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
946 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
950 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
951 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
953 if (spi_priv->nint > 5) {
954 wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
955 tmp |= (((irq_flags >> 0) & 0x7) << k);
958 unknown_mask = ~((1ul << spi_priv->nint) - 1);
960 unexpected_irq = (tmp >> IRG_FLAGS_OFFSET) & unknown_mask;
961 if (unexpected_irq) {
963 "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
964 j, tmp, unknown_mask);
968 } while (unexpected_irq);
975 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
977 struct spi_device *spi = to_spi_device(wilc->dev);
978 struct wilc_spi *spi_priv = wilc->bus_data;
983 if (spi_priv->has_thrpt_enh) {
984 return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
988 flags = val & (BIT(MAX_NUM_INT) - 1);
993 for (i = 0; i < spi_priv->nint; i++) {
995 * No matter what you write 1 or 0,
996 * it will clear interrupt.
999 ret = wilc_spi_write_reg(wilc,
1007 "Failed wilc_spi_write_reg, set reg %x ...\n",
1011 for (i = spi_priv->nint; i < MAX_NUM_INT; i++) {
1014 "Unexpected interrupt cleared %d...\n",
1021 /* select VMM table 0 */
1022 if (val & SEL_VMM_TBL0)
1024 /* select VMM table 1 */
1025 if (val & SEL_VMM_TBL1)
1028 ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
1030 dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
1036 * enable vmm transfer.
1038 ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
1040 dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1048 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1050 struct spi_device *spi = to_spi_device(wilc->dev);
1051 struct wilc_spi *spi_priv = wilc->bus_data;
1055 if (nint > MAX_NUM_INT) {
1056 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1060 spi_priv->nint = nint;
1063 * interrupt pin mux select
1065 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1067 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1072 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1074 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1082 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1084 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1089 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1090 reg |= (BIT((27 + i)));
1092 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1094 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1099 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1101 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1106 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1109 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1111 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1120 /* Global spi HIF function table */
1121 static const struct wilc_hif_func wilc_hif_spi = {
1122 .hif_init = wilc_spi_init,
1123 .hif_deinit = wilc_spi_deinit,
1124 .hif_read_reg = wilc_spi_read_reg,
1125 .hif_write_reg = wilc_spi_write_reg,
1126 .hif_block_rx = wilc_spi_read,
1127 .hif_block_tx = wilc_spi_write,
1128 .hif_read_int = wilc_spi_read_int,
1129 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1130 .hif_read_size = wilc_spi_read_size,
1131 .hif_block_tx_ext = wilc_spi_write,
1132 .hif_block_rx_ext = wilc_spi_read,
1133 .hif_sync_ext = wilc_spi_sync_ext,