1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DDK750_SII164_H__
3 #define DDK750_SII164_H__
7 /* Hot Plug detection mode structure */
8 typedef enum _sii164_hot_plug_mode_t {
9 SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */
10 SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */
11 SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */
12 SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */
13 } sii164_hot_plug_mode_t;
16 /* Silicon Image SiI164 chip prototype */
17 long sii164InitChip(unsigned char edgeSelect,
18 unsigned char busSelect,
19 unsigned char dualEdgeClkSelect,
20 unsigned char hsyncEnable,
21 unsigned char vsyncEnable,
22 unsigned char deskewEnable,
23 unsigned char deskewSetting,
24 unsigned char continuousSyncEnable,
25 unsigned char pllFilterEnable,
26 unsigned char pllFilterValue);
28 unsigned short sii164GetVendorID(void);
29 unsigned short sii164GetDeviceID(void);
32 #ifdef SII164_FULL_FUNCTIONS
33 void sii164ResetChip(void);
34 char *sii164GetChipString(void);
35 void sii164SetPower(unsigned char powerUp);
36 void sii164EnableHotPlugDetection(unsigned char enableHotPlug);
37 unsigned char sii164IsConnected(void);
38 unsigned char sii164CheckInterrupt(void);
39 void sii164ClearInterrupt(void);
42 * below register definition is used for
43 * Silicon Image SiI164 DVI controller chip
48 #define SII164_VENDOR_ID_LOW 0x00
49 #define SII164_VENDOR_ID_HIGH 0x01
54 #define SII164_DEVICE_ID_LOW 0x02
55 #define SII164_DEVICE_ID_HIGH 0x03
60 #define SII164_DEVICE_REVISION 0x04
63 * Frequency Limitation registers
65 #define SII164_FREQUENCY_LIMIT_LOW 0x06
66 #define SII164_FREQUENCY_LIMIT_HIGH 0x07
69 * Power Down and Input Signal Configuration registers
71 #define SII164_CONFIGURATION 0x08
74 #define SII164_CONFIGURATION_POWER_DOWN 0x00
75 #define SII164_CONFIGURATION_POWER_NORMAL 0x01
76 #define SII164_CONFIGURATION_POWER_MASK 0x01
78 /* Input Edge Latch Select (EDGE) */
79 #define SII164_CONFIGURATION_LATCH_FALLING 0x00
80 #define SII164_CONFIGURATION_LATCH_RISING 0x02
82 /* Bus Select (BSEL) */
83 #define SII164_CONFIGURATION_BUS_12BITS 0x00
84 #define SII164_CONFIGURATION_BUS_24BITS 0x04
86 /* Dual Edge Clock Select (DSEL) */
87 #define SII164_CONFIGURATION_CLOCK_SINGLE 0x00
88 #define SII164_CONFIGURATION_CLOCK_DUAL 0x08
90 /* Horizontal Sync Enable (HEN) */
91 #define SII164_CONFIGURATION_HSYNC_FORCE_LOW 0x00
92 #define SII164_CONFIGURATION_HSYNC_AS_IS 0x10
94 /* Vertical Sync Enable (VEN) */
95 #define SII164_CONFIGURATION_VSYNC_FORCE_LOW 0x00
96 #define SII164_CONFIGURATION_VSYNC_AS_IS 0x20
101 #define SII164_DETECT 0x09
103 /* Monitor Detect Interrupt (MDI) */
104 #define SII164_DETECT_MONITOR_STATE_CHANGE 0x00
105 #define SII164_DETECT_MONITOR_STATE_NO_CHANGE 0x01
106 #define SII164_DETECT_MONITOR_STATE_CLEAR 0x01
107 #define SII164_DETECT_MONITOR_STATE_MASK 0x01
109 /* Hot Plug detect Input (HTPLG) */
110 #define SII164_DETECT_HOT_PLUG_STATUS_OFF 0x00
111 #define SII164_DETECT_HOT_PLUG_STATUS_ON 0x02
112 #define SII164_DETECT_HOT_PLUG_STATUS_MASK 0x02
114 /* Receiver Sense (RSEN) */
115 #define SII164_DETECT_RECEIVER_SENSE_NOT_DETECTED 0x00
116 #define SII164_DETECT_RECEIVER_SENSE_DETECTED 0x04
118 /* Interrupt Generation Method (TSEL) */
119 #define SII164_DETECT_INTERRUPT_BY_RSEN_PIN 0x00
120 #define SII164_DETECT_INTERRUPT_BY_HTPLG_PIN 0x08
121 #define SII164_DETECT_INTERRUPT_MASK 0x08
123 /* Monitor Sense Output (MSEN) */
124 #define SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH 0x00
125 #define SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI 0x10
126 #define SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN 0x20
127 #define SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG 0x30
128 #define SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG 0x30
133 #define SII164_DESKEW 0x0A
135 /* General Purpose Input (CTL[3:1]) */
136 #define SII164_DESKEW_GENERAL_PURPOSE_INPUT_MASK 0x0E
138 /* De-skewing Enable bit (DKEN) */
139 #define SII164_DESKEW_DISABLE 0x00
140 #define SII164_DESKEW_ENABLE 0x10
142 /* De-skewing Setting (DK[3:1])*/
143 #define SII164_DESKEW_1_STEP 0x00
144 #define SII164_DESKEW_2_STEP 0x20
145 #define SII164_DESKEW_3_STEP 0x40
146 #define SII164_DESKEW_4_STEP 0x60
147 #define SII164_DESKEW_5_STEP 0x80
148 #define SII164_DESKEW_6_STEP 0xA0
149 #define SII164_DESKEW_7_STEP 0xC0
150 #define SII164_DESKEW_8_STEP 0xE0
153 * User Configuration Data registers (CFG 7:0)
155 #define SII164_USER_CONFIGURATION 0x0B
160 #define SII164_PLL 0x0C
162 /* PLL Filter Value (PLLF) */
163 #define SII164_PLL_FILTER_VALUE_MASK 0x0E
165 /* PLL Filter Enable (PFEN) */
166 #define SII164_PLL_FILTER_DISABLE 0x00
167 #define SII164_PLL_FILTER_ENABLE 0x01
169 /* Sync Continuous (SCNT) */
170 #define SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE 0x00
171 #define SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE 0x80