1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm_qos.h>
25 #include <linux/timer.h>
26 #include <linux/delay.h>
27 #include <linux/dmi.h>
28 #include <linux/interrupt.h>
29 #include <linux/bits.h>
30 #include <media/v4l2-fwnode.h>
32 #include <asm/iosf_mbi.h>
34 #include "../../include/linux/atomisp_gmin_platform.h"
36 #include "atomisp_cmd.h"
37 #include "atomisp_common.h"
38 #include "atomisp_fops.h"
39 #include "atomisp_ioctl.h"
40 #include "atomisp_internal.h"
41 #include "atomisp-regs.h"
42 #include "atomisp_dfs_tables.h"
43 #include "atomisp_drvfs.h"
45 #include "atomisp_trace_event.h"
47 #include "sh_css_firmware.h"
49 #include "device_access.h"
51 /* Timeouts to wait for all subdevs to be registered */
52 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
53 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
55 /* G-Min addition: pull this in from intel_mid_pm.h */
56 #define CSTATE_EXIT_LATENCY_C1 1
58 /* cross componnet debug message flag */
60 module_param(dbg_level, int, 0644);
61 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
63 /* log function switch */
65 module_param(dbg_func, int, 0644);
66 MODULE_PARM_DESC(dbg_func,
67 "log function switch non/printk (default:printk)");
70 module_param(mipicsi_flag, int, 0644);
71 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
73 static char firmware_name[256];
74 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
75 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
78 * Set to 16x16 since this is the amount of lines and pixels the sensor
79 * exports extra. If these are kept at the 10x8 that they were on, in yuv
80 * downscaling modes incorrect resolutions where requested to the sensor
81 * driver with strange outcomes as a result. The proper way tot do this
82 * would be to have a list of tables the specify the sensor res, mipi rec,
83 * output res, and isp output res. however since we do not have this yet,
84 * the chosen solution is the next best thing.
87 module_param(pad_w, int, 0644);
88 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
91 module_param(pad_h, int, 0644);
92 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
95 * FIXME: this is a hack to make easier to support ISP2401 variant.
96 * As a given system will either be ISP2401 or not, we can just use
97 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
99 * Once this driver gets into a better shape, however, the best would
100 * be to replace this to something stored inside atomisp allocated
104 struct device *atomisp_dev;
106 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
108 .width = ISP_FREQ_RULE_ANY,
109 .height = ISP_FREQ_RULE_ANY,
110 .fps = ISP_FREQ_RULE_ANY,
111 .isp_freq = ISP_FREQ_400MHZ,
112 .run_mode = ATOMISP_RUN_MODE_VIDEO,
115 .width = ISP_FREQ_RULE_ANY,
116 .height = ISP_FREQ_RULE_ANY,
117 .fps = ISP_FREQ_RULE_ANY,
118 .isp_freq = ISP_FREQ_400MHZ,
119 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
122 .width = ISP_FREQ_RULE_ANY,
123 .height = ISP_FREQ_RULE_ANY,
124 .fps = ISP_FREQ_RULE_ANY,
125 .isp_freq = ISP_FREQ_400MHZ,
126 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
130 /* Merrifield and Moorefield DFS rules */
131 static const struct atomisp_dfs_config dfs_config_merr = {
132 .lowest_freq = ISP_FREQ_200MHZ,
133 .max_freq_at_vmin = ISP_FREQ_400MHZ,
134 .highest_freq = ISP_FREQ_457MHZ,
135 .dfs_table = dfs_rules_merr,
136 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
139 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
141 .width = ISP_FREQ_RULE_ANY,
142 .height = ISP_FREQ_RULE_ANY,
143 .fps = ISP_FREQ_RULE_ANY,
144 .isp_freq = ISP_FREQ_400MHZ,
145 .run_mode = ATOMISP_RUN_MODE_VIDEO,
148 .width = ISP_FREQ_RULE_ANY,
149 .height = ISP_FREQ_RULE_ANY,
150 .fps = ISP_FREQ_RULE_ANY,
151 .isp_freq = ISP_FREQ_400MHZ,
152 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
155 .width = ISP_FREQ_RULE_ANY,
156 .height = ISP_FREQ_RULE_ANY,
157 .fps = ISP_FREQ_RULE_ANY,
158 .isp_freq = ISP_FREQ_400MHZ,
159 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
163 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
164 .lowest_freq = ISP_FREQ_200MHZ,
165 .max_freq_at_vmin = ISP_FREQ_400MHZ,
166 .highest_freq = ISP_FREQ_400MHZ,
167 .dfs_table = dfs_rules_merr_1179,
168 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
171 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
176 .isp_freq = ISP_FREQ_266MHZ,
177 .run_mode = ATOMISP_RUN_MODE_VIDEO,
183 .isp_freq = ISP_FREQ_266MHZ,
184 .run_mode = ATOMISP_RUN_MODE_VIDEO,
190 .isp_freq = ISP_FREQ_320MHZ,
191 .run_mode = ATOMISP_RUN_MODE_VIDEO,
197 .isp_freq = ISP_FREQ_320MHZ,
198 .run_mode = ATOMISP_RUN_MODE_VIDEO,
201 .width = ISP_FREQ_RULE_ANY,
202 .height = ISP_FREQ_RULE_ANY,
204 .isp_freq = ISP_FREQ_356MHZ,
205 .run_mode = ATOMISP_RUN_MODE_VIDEO,
208 .width = ISP_FREQ_RULE_ANY,
209 .height = ISP_FREQ_RULE_ANY,
210 .fps = ISP_FREQ_RULE_ANY,
211 .isp_freq = ISP_FREQ_200MHZ,
212 .run_mode = ATOMISP_RUN_MODE_VIDEO,
215 .width = ISP_FREQ_RULE_ANY,
216 .height = ISP_FREQ_RULE_ANY,
217 .fps = ISP_FREQ_RULE_ANY,
218 .isp_freq = ISP_FREQ_400MHZ,
219 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
222 .width = ISP_FREQ_RULE_ANY,
223 .height = ISP_FREQ_RULE_ANY,
224 .fps = ISP_FREQ_RULE_ANY,
225 .isp_freq = ISP_FREQ_200MHZ,
226 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
230 static struct atomisp_dfs_config dfs_config_merr_117a = {
231 .lowest_freq = ISP_FREQ_200MHZ,
232 .max_freq_at_vmin = ISP_FREQ_200MHZ,
233 .highest_freq = ISP_FREQ_400MHZ,
234 .dfs_table = dfs_rules_merr_117a,
235 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
238 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
240 .width = ISP_FREQ_RULE_ANY,
241 .height = ISP_FREQ_RULE_ANY,
242 .fps = ISP_FREQ_RULE_ANY,
243 .isp_freq = ISP_FREQ_400MHZ,
244 .run_mode = ATOMISP_RUN_MODE_VIDEO,
247 .width = ISP_FREQ_RULE_ANY,
248 .height = ISP_FREQ_RULE_ANY,
249 .fps = ISP_FREQ_RULE_ANY,
250 .isp_freq = ISP_FREQ_400MHZ,
251 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
254 .width = ISP_FREQ_RULE_ANY,
255 .height = ISP_FREQ_RULE_ANY,
256 .fps = ISP_FREQ_RULE_ANY,
257 .isp_freq = ISP_FREQ_400MHZ,
258 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
262 static const struct atomisp_dfs_config dfs_config_byt = {
263 .lowest_freq = ISP_FREQ_200MHZ,
264 .max_freq_at_vmin = ISP_FREQ_400MHZ,
265 .highest_freq = ISP_FREQ_400MHZ,
266 .dfs_table = dfs_rules_byt,
267 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
270 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
272 .width = ISP_FREQ_RULE_ANY,
273 .height = ISP_FREQ_RULE_ANY,
274 .fps = ISP_FREQ_RULE_ANY,
275 .isp_freq = ISP_FREQ_320MHZ,
276 .run_mode = ATOMISP_RUN_MODE_VIDEO,
279 .width = ISP_FREQ_RULE_ANY,
280 .height = ISP_FREQ_RULE_ANY,
281 .fps = ISP_FREQ_RULE_ANY,
282 .isp_freq = ISP_FREQ_356MHZ,
283 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
286 .width = ISP_FREQ_RULE_ANY,
287 .height = ISP_FREQ_RULE_ANY,
288 .fps = ISP_FREQ_RULE_ANY,
289 .isp_freq = ISP_FREQ_320MHZ,
290 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
294 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
296 .width = ISP_FREQ_RULE_ANY,
297 .height = ISP_FREQ_RULE_ANY,
298 .fps = ISP_FREQ_RULE_ANY,
299 .isp_freq = ISP_FREQ_356MHZ,
300 .run_mode = ATOMISP_RUN_MODE_VIDEO,
303 .width = ISP_FREQ_RULE_ANY,
304 .height = ISP_FREQ_RULE_ANY,
305 .fps = ISP_FREQ_RULE_ANY,
306 .isp_freq = ISP_FREQ_356MHZ,
307 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
310 .width = ISP_FREQ_RULE_ANY,
311 .height = ISP_FREQ_RULE_ANY,
312 .fps = ISP_FREQ_RULE_ANY,
313 .isp_freq = ISP_FREQ_320MHZ,
314 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
318 static const struct atomisp_dfs_config dfs_config_cht = {
319 .lowest_freq = ISP_FREQ_100MHZ,
320 .max_freq_at_vmin = ISP_FREQ_356MHZ,
321 .highest_freq = ISP_FREQ_356MHZ,
322 .dfs_table = dfs_rules_cht,
323 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
326 /* This one should be visible also by atomisp_cmd.c */
327 const struct atomisp_dfs_config dfs_config_cht_soc = {
328 .lowest_freq = ISP_FREQ_100MHZ,
329 .max_freq_at_vmin = ISP_FREQ_356MHZ,
330 .highest_freq = ISP_FREQ_356MHZ,
331 .dfs_table = dfs_rules_cht_soc,
332 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
335 int atomisp_video_init(struct atomisp_video_pipe *video)
339 video->pad.flags = MEDIA_PAD_FL_SINK;
340 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
344 /* Initialize the video device. */
345 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name));
346 video->vdev.fops = &atomisp_fops;
347 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
348 video->vdev.lock = &video->isp->mutex;
349 video->vdev.release = video_device_release_empty;
350 video_set_drvdata(&video->vdev, video->isp);
355 void atomisp_video_unregister(struct atomisp_video_pipe *video)
357 if (video_is_registered(&video->vdev)) {
358 media_entity_cleanup(&video->vdev.entity);
359 video_unregister_device(&video->vdev);
363 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
365 struct pci_dev *pdev = to_pci_dev(isp->dev);
367 dev_dbg(isp->dev, "%s\n", __func__);
369 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
370 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
371 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
372 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
373 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
374 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
375 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
377 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
378 /* Ensure read/write combining is enabled. */
379 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
380 isp->saved_regs.i_control |=
381 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
382 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
383 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
384 &isp->saved_regs.csi_access_viol);
385 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
386 &isp->saved_regs.csi_rcomp_config);
388 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
389 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
390 * and sensor sending "continuous clock".
391 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
392 * is missed, and IUNIT can hang.
393 * For both issues, setting this bit is a workaround.
395 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
396 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
397 &isp->saved_regs.csi_afe_dly);
398 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
399 &isp->saved_regs.csi_control);
400 if (isp->media_dev.hw_revision >=
401 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
402 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
404 * On CHT CSI_READY bit should be enabled before stream on
406 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
407 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
408 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
409 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
410 &isp->saved_regs.csi_afe_rcomp_config);
411 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
412 &isp->saved_regs.csi_afe_hs_control);
413 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
414 &isp->saved_regs.csi_deadline_control);
418 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
420 struct pci_dev *pdev = to_pci_dev(isp->dev);
422 dev_dbg(isp->dev, "%s\n", __func__);
424 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
425 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
426 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
427 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
428 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
429 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
430 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
431 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
433 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
434 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
435 isp->saved_regs.csi_access_viol);
436 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
437 isp->saved_regs.csi_rcomp_config);
438 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
439 isp->saved_regs.csi_afe_dly);
440 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
441 isp->saved_regs.csi_control);
442 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
443 isp->saved_regs.csi_afe_rcomp_config);
444 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
445 isp->saved_regs.csi_afe_hs_control);
446 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
447 isp->saved_regs.csi_deadline_control);
450 * for MRFLD, Software/firmware needs to write a 1 to bit0
451 * of the register at CSI_RECEIVER_SELECTION_REG to enable
452 * SH CSI backend write 0 will enable Arasan CSI backend,
453 * which has bugs(like sighting:4567697 and 4567699) and
454 * will be removed in B0
456 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
460 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
462 struct pci_dev *pdev = to_pci_dev(isp->dev);
466 spin_lock_irqsave(&isp->lock, flags);
469 * MRFLD HAS requirement: cannot power off i-unit if
470 * ISP has IRQ not serviced.
471 * So, here we need to check if there is any pending
472 * IRQ, if so, waiting for it to be served
474 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
475 irq &= BIT(INTR_IIR);
476 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
478 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
479 if (!(irq & BIT(INTR_IIR)))
482 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
483 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
486 "%s: fail to clear isp interrupt status reg=0x%x\n",
488 spin_unlock_irqrestore(&isp->lock, flags);
491 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
492 irq &= BIT(INTR_IIR);
493 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
495 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
496 if (!(irq & BIT(INTR_IIR))) {
497 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
501 "%s: error in iunit interrupt. status reg=0x%x\n",
503 spin_unlock_irqrestore(&isp->lock, flags);
509 * before powering off IUNIT, clear the pending interrupts
510 * and disable the interrupt. driver should avoid writing 0
511 * to IIR. It could block subsequent interrupt messages.
512 * HW sighting:4568410.
514 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
515 irq &= ~BIT(INTR_IER);
516 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
518 atomisp_msi_irq_uninit(isp);
519 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
520 spin_unlock_irqrestore(&isp->lock, flags);
526 * WA for DDR DVFS enable/disable
527 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
529 static void punit_ddr_dvfs_enable(bool enable)
533 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
535 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
538 reg &= ~(MRFLD_BIT0);
540 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
543 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
545 struct pci_dev *pdev = to_pci_dev(isp->dev);
546 unsigned long timeout;
547 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
548 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
550 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
552 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
553 if (IS_CHT && enable && !isp->pm_only) {
554 punit_ddr_dvfs_enable(false);
558 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
559 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
560 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
563 if (IS_CHT && !enable && !isp->pm_only)
564 punit_ddr_dvfs_enable(true);
567 * There should be no IUNIT access while power-down is
568 * in progress. HW sighting: 4567865.
569 * Wait up to 50 ms for the IUNIT to shut down.
570 * And we do the same for power on.
572 timeout = jiffies + msecs_to_jiffies(50);
576 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
577 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
578 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
580 trace_ipu_cstate(enable);
581 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
585 if (time_after(jiffies, timeout))
588 /* FIXME: experienced value for delay */
589 usleep_range(100, 150);
592 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
596 int atomisp_power_off(struct device *dev)
598 struct atomisp_device *isp = dev_get_drvdata(dev);
599 struct pci_dev *pdev = to_pci_dev(dev);
604 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, 0);
606 atomisp_css_uninit(isp);
608 ret = atomisp_mrfld_pre_power_down(isp);
614 * MRFLD IUNIT DPHY is located in an always-power-on island
615 * MRFLD HW design need all CSI ports are disabled before
616 * powering down the IUNIT.
618 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
619 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
620 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
622 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
623 pci_save_state(pdev);
624 return atomisp_mrfld_power(isp, false);
627 int atomisp_power_on(struct device *dev)
629 struct atomisp_device *isp = (struct atomisp_device *)
630 dev_get_drvdata(dev);
633 ret = atomisp_mrfld_power(isp, true);
637 pci_restore_state(to_pci_dev(dev));
638 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
643 /*restore register values for iUnit and iUnitPHY registers*/
644 if (isp->saved_regs.pcicmdsts)
645 atomisp_restore_iunit_reg(isp);
647 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
649 return atomisp_css_init(isp);
652 static int atomisp_suspend(struct device *dev)
654 struct atomisp_device *isp = (struct atomisp_device *)
655 dev_get_drvdata(dev);
658 /* FIXME: Suspend is not supported by sensors. Abort if streaming. */
659 spin_lock_irqsave(&isp->lock, flags);
660 if (isp->asd.streaming) {
661 spin_unlock_irqrestore(&isp->lock, flags);
662 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
665 spin_unlock_irqrestore(&isp->lock, flags);
667 pm_runtime_resume(dev);
669 isp->asd.recreate_streams_on_resume = isp->asd.stream_prepared;
670 atomisp_destroy_pipes_stream(&isp->asd);
672 return atomisp_power_off(dev);
675 static int atomisp_resume(struct device *dev)
677 struct atomisp_device *isp = dev_get_drvdata(dev);
680 ret = atomisp_power_on(dev);
684 if (isp->asd.recreate_streams_on_resume)
685 ret = atomisp_create_pipes_stream(&isp->asd);
690 int atomisp_csi_lane_config(struct atomisp_device *isp)
692 struct pci_dev *pdev = to_pci_dev(isp->dev);
693 static const struct {
695 u8 lanes[N_MIPI_PORT_ID];
697 /* Tangier/Merrifield available lane configurations */
698 { 0x00, { 4, 1, 0 } }, /* 00000 */
699 { 0x01, { 3, 1, 0 } }, /* 00001 */
700 { 0x02, { 2, 1, 0 } }, /* 00010 */
701 { 0x03, { 1, 1, 0 } }, /* 00011 */
702 { 0x04, { 2, 1, 2 } }, /* 00100 */
703 { 0x08, { 3, 1, 1 } }, /* 01000 */
704 { 0x09, { 2, 1, 1 } }, /* 01001 */
705 { 0x0a, { 1, 1, 1 } }, /* 01010 */
707 /* Anniedale/Moorefield only configurations */
708 { 0x10, { 4, 2, 0 } }, /* 10000 */
709 { 0x11, { 3, 2, 0 } }, /* 10001 */
710 { 0x12, { 2, 2, 0 } }, /* 10010 */
711 { 0x13, { 1, 2, 0 } }, /* 10011 */
712 { 0x14, { 2, 2, 2 } }, /* 10100 */
713 { 0x18, { 3, 2, 1 } }, /* 11000 */
714 { 0x19, { 2, 2, 1 } }, /* 11001 */
715 { 0x1a, { 1, 2, 1 } }, /* 11010 */
721 u32 port_config_mask;
722 int port3_lanes_shift;
724 if (isp->media_dev.hw_revision <
725 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
726 ATOMISP_HW_REVISION_SHIFT) {
728 port_config_mask = MRFLD_PORT_CONFIG_MASK;
729 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
731 /* Moorefield / Cherryview */
732 port_config_mask = CHV_PORT_CONFIG_MASK;
733 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
736 if (isp->media_dev.hw_revision <
737 ATOMISP_HW_REVISION_ISP2401 <<
738 ATOMISP_HW_REVISION_SHIFT) {
739 /* Merrifield / Moorefield legacy input system */
740 nportconfigs = MRFLD_PORT_CONFIG_NUM;
742 /* Moorefield / Cherryview new input system */
743 nportconfigs = ARRAY_SIZE(portconfigs);
746 for (i = 0; i < nportconfigs; i++) {
747 for (j = 0; j < N_MIPI_PORT_ID; j++)
748 if (isp->sensor_lanes[j] &&
749 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
752 if (j == N_MIPI_PORT_ID)
753 break; /* Found matching setting */
756 if (i >= nportconfigs) {
758 "%s: could not find the CSI port setting for %d-%d-%d\n",
760 isp->sensor_lanes[0], isp->sensor_lanes[1], isp->sensor_lanes[2]);
764 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
765 csi_control &= ~port_config_mask;
766 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
767 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
768 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
769 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
770 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
771 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
772 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
774 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
777 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
778 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
779 portconfigs[i].lanes[2], csi_control);
784 static int atomisp_subdev_probe(struct atomisp_device *isp)
786 const struct intel_v4l2_subdev_table *subdevs;
789 ret = atomisp_csi2_bridge_parse_firmware(isp);
794 * TODO: this is left here for now to allow testing atomisp-sensor
795 * drivers which are still using the atomisp_gmin_platform infra before
796 * converting them to standard v4l2 sensor drivers using runtime-pm +
797 * ACPI for pm and v4l2_async_register_subdev_sensor() registration.
799 for (subdevs = atomisp_platform_get_subdevs(); subdevs->subdev; subdevs++) {
800 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
804 if (subdevs->port >= ATOMISP_CAMERA_NR_PORTS) {
805 dev_err(isp->dev, "port %d not supported\n", subdevs->port);
809 if (isp->sensor_subdevs[subdevs->port]) {
810 dev_err(isp->dev, "port %d already has a sensor attached\n",
815 mipi_port = atomisp_port_to_mipi_port(isp, subdevs->port);
816 isp->sensor_lanes[mipi_port] = subdevs->lanes;
817 isp->sensor_subdevs[subdevs->port] = subdevs->subdev;
820 return atomisp_csi_lane_config(isp);
823 static void atomisp_unregister_entities(struct atomisp_device *isp)
826 struct v4l2_subdev *sd, *next;
828 atomisp_subdev_unregister_entities(&isp->asd);
829 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
830 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
832 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
833 v4l2_device_unregister_subdev(sd);
835 v4l2_device_unregister(&isp->v4l2_dev);
836 media_device_unregister(&isp->media_dev);
837 media_device_cleanup(&isp->media_dev);
839 for (i = 0; i < isp->input_cnt; i++)
840 __v4l2_subdev_state_free(isp->inputs[i].try_sd_state);
843 static int atomisp_register_entities(struct atomisp_device *isp)
848 isp->media_dev.dev = isp->dev;
850 strscpy(isp->media_dev.model, "Intel Atom ISP",
851 sizeof(isp->media_dev.model));
853 media_device_init(&isp->media_dev);
854 isp->v4l2_dev.mdev = &isp->media_dev;
855 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
857 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
859 goto v4l2_device_failed;
862 ret = atomisp_subdev_probe(isp);
864 goto csi_and_subdev_probe_failed;
866 /* Register internal entities */
867 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
868 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
874 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
875 /* deregister all registered CSI ports */
877 atomisp_mipi_csi2_unregister_entities(
880 goto csi_and_subdev_probe_failed;
883 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev);
885 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
886 goto subdev_register_failed;
891 subdev_register_failed:
892 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
893 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
894 csi_and_subdev_probe_failed:
895 v4l2_device_unregister(&isp->v4l2_dev);
897 media_device_unregister(&isp->media_dev);
898 media_device_cleanup(&isp->media_dev);
902 static void atomisp_init_sensor(struct atomisp_input_subdev *input)
904 static struct lock_class_key try_sd_state_key;
905 struct v4l2_subdev_mbus_code_enum mbus_code_enum = { };
906 struct v4l2_subdev_frame_size_enum fse = { };
907 struct v4l2_subdev_selection sel = { };
908 struct v4l2_subdev_state *try_sd_state, *act_sd_state;
912 * FIXME: Drivers are not supposed to use __v4l2_subdev_state_alloc()
913 * but atomisp needs this for try_fmt on its /dev/video# node since
914 * it emulates a normal v4l2 device there, passing through try_fmt /
915 * set_fmt to the sensor.
917 try_sd_state = __v4l2_subdev_state_alloc(input->camera,
918 "atomisp:try_sd_state->lock", &try_sd_state_key);
919 if (IS_ERR(try_sd_state))
922 input->try_sd_state = try_sd_state;
924 act_sd_state = v4l2_subdev_lock_and_get_active_state(input->camera);
926 mbus_code_enum.which = V4L2_SUBDEV_FORMAT_ACTIVE;
927 err = v4l2_subdev_call(input->camera, pad, enum_mbus_code,
928 act_sd_state, &mbus_code_enum);
930 input->code = mbus_code_enum.code;
932 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
933 sel.target = V4L2_SEL_TGT_NATIVE_SIZE;
934 err = v4l2_subdev_call(input->camera, pad, get_selection,
937 goto unlock_act_sd_state;
939 input->native_rect = sel.r;
941 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
942 sel.target = V4L2_SEL_TGT_CROP_DEFAULT;
943 err = v4l2_subdev_call(input->camera, pad, get_selection,
946 goto unlock_act_sd_state;
948 input->active_rect = sel.r;
951 * Check for a framesize with half active_rect width and height,
952 * if found assume the sensor supports binning.
953 * Do this before changing the crop-rect since that may influence
954 * enum_frame_size results.
958 fse.code = input->code;
959 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
961 err = v4l2_subdev_call(input->camera, pad, enum_frame_size,
966 if (fse.min_width <= (input->active_rect.width / 2) &&
967 fse.min_height <= (input->active_rect.height / 2)) {
968 input->binning_support = true;
974 * The ISP also wants the non-active pixels at the border of the sensor
975 * for padding, set the crop rect to cover the entire sensor instead
976 * of only the default active area.
978 * Do this for both try and active formats since the crop rect in
979 * try_sd_state may influence (clamp size) in calls with which == try.
981 sel.which = V4L2_SUBDEV_FORMAT_TRY;
982 sel.target = V4L2_SEL_TGT_CROP;
983 sel.r = input->native_rect;
984 v4l2_subdev_lock_state(input->try_sd_state);
985 err = v4l2_subdev_call(input->camera, pad, set_selection,
986 input->try_sd_state, &sel);
987 v4l2_subdev_unlock_state(input->try_sd_state);
989 goto unlock_act_sd_state;
991 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
992 sel.target = V4L2_SEL_TGT_CROP;
993 sel.r = input->native_rect;
994 err = v4l2_subdev_call(input->camera, pad, set_selection,
997 goto unlock_act_sd_state;
999 dev_info(input->camera->dev, "Supports crop native %dx%d active %dx%d binning %d\n",
1000 input->native_rect.width, input->native_rect.height,
1001 input->active_rect.width, input->active_rect.height,
1002 input->binning_support);
1004 input->crop_support = true;
1006 unlock_act_sd_state:
1008 v4l2_subdev_unlock_state(act_sd_state);
1011 int atomisp_register_device_nodes(struct atomisp_device *isp)
1013 struct atomisp_input_subdev *input;
1016 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1017 err = media_create_pad_link(&isp->csi2_port[i].subdev.entity,
1018 CSI2_PAD_SOURCE, &isp->asd.subdev.entity,
1019 ATOMISP_SUBDEV_PAD_SINK, 0);
1023 if (!isp->sensor_subdevs[i])
1026 input = &isp->inputs[isp->input_cnt];
1029 input->camera = isp->sensor_subdevs[i];
1030 input->csi_port = &isp->csi2_port[i].subdev;
1032 atomisp_init_sensor(input);
1034 err = media_create_pad_link(&input->camera->entity, 0,
1035 &isp->csi2_port[i].subdev.entity,
1037 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1044 if (!isp->input_cnt)
1045 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1047 dev_info(isp->dev, "detected %d camera sensors\n", isp->input_cnt);
1049 mutex_lock(&isp->media_dev.graph_mutex);
1050 atomisp_setup_input_links(isp);
1051 mutex_unlock(&isp->media_dev.graph_mutex);
1053 isp->asd.video_out.vdev.v4l2_dev = &isp->v4l2_dev;
1054 isp->asd.video_out.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1055 err = video_register_device(&isp->asd.video_out.vdev, VFL_TYPE_VIDEO, -1);
1059 err = media_create_pad_link(&isp->asd.subdev.entity, ATOMISP_SUBDEV_PAD_SOURCE,
1060 &isp->asd.video_out.vdev.entity, 0,
1061 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1065 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1069 return media_device_register(&isp->media_dev);
1072 static int atomisp_initialize_modules(struct atomisp_device *isp)
1076 ret = atomisp_mipi_csi2_init(isp);
1078 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1079 goto error_mipi_csi2;
1082 ret = atomisp_subdev_init(isp);
1084 dev_err(isp->dev, "ISP subdev initialization failed\n");
1085 goto error_isp_subdev;
1092 atomisp_mipi_csi2_cleanup(isp);
1096 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1098 atomisp_mipi_csi2_cleanup(isp);
1101 const struct firmware *
1102 atomisp_load_firmware(struct atomisp_device *isp)
1104 const struct firmware *fw;
1106 char *fw_path = NULL;
1108 if (firmware_name[0] != '\0') {
1109 fw_path = firmware_name;
1111 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT)
1112 == ATOMISP_HW_REVISION_ISP2401)
1113 fw_path = "shisp_2401a0_v21.bin";
1115 if (isp->media_dev.hw_revision ==
1116 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1117 | ATOMISP_HW_STEPPING_A0))
1118 fw_path = "shisp_2401a0_legacy_v21.bin";
1120 if (isp->media_dev.hw_revision ==
1121 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1122 | ATOMISP_HW_STEPPING_B0))
1123 fw_path = "shisp_2400b0_v21.bin";
1127 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1128 isp->media_dev.hw_revision);
1132 rc = request_firmware(&fw, fw_path, isp->dev);
1135 "atomisp: Error %d while requesting firmware %s\n",
1143 static void atomisp_pm_init(struct atomisp_device *isp)
1146 * The atomisp does not use standard PCI power-management through the
1147 * PCI config space. Instead this driver directly tells the P-Unit to
1148 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1149 * try to access the config space before (resume) / after (suspend) this
1150 * driver has turned the ISP on / off, resulting in the following errors:
1152 * "Unable to change power state from D0 to D3hot, device inaccessible"
1153 * "Unable to change power state from D3cold to D0, device inaccessible"
1155 * To avoid these errors override the pm_domain so that all the PCI
1156 * subsys suspend / resume handling is skipped.
1158 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1159 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1160 isp->pm_domain.ops.suspend = atomisp_suspend;
1161 isp->pm_domain.ops.resume = atomisp_resume;
1163 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1164 dev_pm_domain_set(isp->dev, &isp->pm_domain);
1166 pm_runtime_allow(isp->dev);
1167 pm_runtime_put_sync_suspend(isp->dev);
1170 static void atomisp_pm_uninit(struct atomisp_device *isp)
1172 pm_runtime_get_sync(isp->dev);
1173 pm_runtime_forbid(isp->dev);
1174 dev_pm_domain_set(isp->dev, NULL);
1175 cpu_latency_qos_remove_request(&isp->pm_qos);
1178 #define ATOM_ISP_PCI_BAR 0
1180 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1182 struct atomisp_device *isp;
1187 /* Pointer to struct device. */
1188 atomisp_dev = &pdev->dev;
1190 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1191 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1193 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1197 isp->dev = &pdev->dev;
1198 isp->saved_regs.ispmmadr = start;
1201 mutex_init(&isp->mutex);
1202 spin_lock_init(&isp->lock);
1204 /* This is not a true PCI device on SoC, so the delay is not needed. */
1205 pdev->d3hot_delay = 0;
1207 pci_set_drvdata(pdev, isp);
1209 switch (id->device) {
1210 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1211 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1212 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1213 isp->media_dev.hw_revision =
1214 (ATOMISP_HW_REVISION_ISP2400
1215 << ATOMISP_HW_REVISION_SHIFT) |
1216 ATOMISP_HW_STEPPING_B0;
1218 switch (id->device) {
1219 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1220 isp->dfs = &dfs_config_merr_1179;
1222 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1223 isp->dfs = &dfs_config_merr_117a;
1227 isp->dfs = &dfs_config_merr;
1230 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1232 case ATOMISP_PCI_DEVICE_SOC_BYT:
1233 isp->media_dev.hw_revision =
1234 (ATOMISP_HW_REVISION_ISP2400
1235 << ATOMISP_HW_REVISION_SHIFT) |
1236 ATOMISP_HW_STEPPING_B0;
1239 * Note: some Intel-based tablets with Android use a different
1240 * DFS table. Based on the comments at the Yocto Aero meta
1241 * version of this driver (at the ssid.h header), they're
1242 * identified via a "spid" var:
1244 * androidboot.spid=vend:cust:manu:plat:prod:hard
1246 * As we don't have this upstream, nor we know enough details
1247 * to use a DMI or PCI match table, the old code was just
1248 * removed, but let's keep a note here as a reminder that,
1249 * for certain devices, we may need to limit the max DFS
1250 * frequency to be below certain values, adjusting the
1251 * resolution accordingly.
1253 isp->dfs = &dfs_config_byt;
1256 * HPLL frequency is known to be device-specific, but we don't
1257 * have specs yet for exactly how it varies. Default to
1258 * BYT-CR but let provisioning set it via EFI variable
1260 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1263 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1264 * in power off. Set d3cold_delay to 0 since default 100ms is not
1267 pdev->d3cold_delay = 0;
1269 case ATOMISP_PCI_DEVICE_SOC_ANN:
1270 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1271 << ATOMISP_HW_REVISION_SHIFT);
1272 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1273 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1274 isp->dfs = &dfs_config_merr;
1275 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1277 case ATOMISP_PCI_DEVICE_SOC_CHT:
1278 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1279 << ATOMISP_HW_REVISION_SHIFT);
1280 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1281 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1283 isp->dfs = &dfs_config_cht;
1284 pdev->d3cold_delay = 0;
1286 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1287 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1289 isp->hpll_freq = HPLL_FREQ_800MHZ;
1292 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1295 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1298 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1299 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1303 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1307 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1308 dev_err(&pdev->dev, "revision %d is not supported\n", pdev->revision);
1312 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1314 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1316 /* Load isp firmware from user space */
1317 isp->firmware = atomisp_load_firmware(isp);
1318 if (!isp->firmware) {
1319 /* No firmware continue in pm-only mode for S0i3 support */
1320 dev_info(&pdev->dev, "Continuing in power-management only mode\n");
1321 isp->pm_only = true;
1322 atomisp_pm_init(isp);
1326 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1328 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1329 goto error_release_firmware;
1332 err = pcim_enable_device(pdev);
1334 dev_err(&pdev->dev, "Failed to enable ISP PCI device (%d)\n", err);
1335 goto error_release_firmware;
1338 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1340 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1341 goto error_release_firmware;
1344 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1346 pci_set_master(pdev);
1348 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1350 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1351 goto error_release_firmware;
1354 atomisp_msi_irq_init(isp);
1357 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1358 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1359 * backend write 0 will enable Arasan CSI backend, which has
1360 * bugs(like sighting:4567697 and 4567699) and will be removed
1363 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1365 switch (id->device) {
1366 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1367 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1368 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1370 * Workaround for imbalance data eye issue which is observed
1373 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &val);
1374 val &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1375 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1376 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1377 val |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1378 (MRFLD_PCI_CSI2_HSRXCLKTRIM << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1379 (MRFLD_PCI_CSI3_HSRXCLKTRIM << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1380 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, val);
1386 err = atomisp_initialize_modules(isp);
1388 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1389 goto error_irq_uninit;
1392 err = atomisp_register_entities(isp);
1394 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1395 goto error_uninitialize_modules;
1398 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1400 /* save the iunit context only once after all the values are init'ed. */
1401 atomisp_save_iunit_reg(isp);
1403 /* Init ISP memory management */
1406 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1407 atomisp_isr, atomisp_isr_thread,
1408 IRQF_SHARED, "isp_irq", isp);
1410 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1411 goto error_unregister_entities;
1414 /* Load firmware into ISP memory */
1415 err = atomisp_css_load_firmware(isp);
1417 dev_err(&pdev->dev, "Failed to init css.\n");
1418 goto error_free_irq;
1420 /* Clear FW image from memory */
1421 release_firmware(isp->firmware);
1422 isp->firmware = NULL;
1423 isp->css_env.isp_css_fw.data = NULL;
1425 atomisp_pm_init(isp);
1427 err = v4l2_async_nf_register(&isp->notifier);
1429 dev_err(isp->dev, "failed to register async notifier : %d\n", err);
1430 goto error_unload_firmware;
1435 error_unload_firmware:
1436 atomisp_pm_uninit(isp);
1437 ia_css_unload_firmware();
1439 devm_free_irq(&pdev->dev, pdev->irq, isp);
1440 error_unregister_entities:
1442 atomisp_unregister_entities(isp);
1443 error_uninitialize_modules:
1444 atomisp_uninitialize_modules(isp);
1446 atomisp_msi_irq_uninit(isp);
1447 pci_free_irq_vectors(pdev);
1448 error_release_firmware:
1449 release_firmware(isp->firmware);
1453 static void atomisp_pci_remove(struct pci_dev *pdev)
1455 struct atomisp_device *isp = pci_get_drvdata(pdev);
1457 atomisp_pm_uninit(isp);
1462 /* Undo ia_css_init() from atomisp_power_on() */
1463 atomisp_css_uninit(isp);
1464 ia_css_unload_firmware();
1465 devm_free_irq(&pdev->dev, pdev->irq, isp);
1468 atomisp_unregister_entities(isp);
1469 atomisp_uninitialize_modules(isp);
1470 atomisp_msi_irq_uninit(isp);
1471 pci_free_irq_vectors(pdev);
1474 static const struct pci_device_id atomisp_pci_tbl[] = {
1476 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1477 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1478 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1480 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1481 /* Anniedale (Merrifield+ / Moorefield) */
1482 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1484 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1487 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1489 static struct pci_driver atomisp_pci_driver = {
1491 .dev_groups = dbg_attr_groups,
1493 .name = "atomisp-isp2",
1494 .id_table = atomisp_pci_tbl,
1495 .probe = atomisp_pci_probe,
1496 .remove = atomisp_pci_remove,
1499 module_pci_driver(atomisp_pci_driver);
1501 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1502 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1503 MODULE_LICENSE("GPL");
1504 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1505 MODULE_IMPORT_NS(INTEL_IPU_BRIDGE);