2 * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
10 * See industrialio/accels/sca3000.h for comments.
13 #include <linux/interrupt.h>
15 #include <linux/device.h>
16 #include <linux/slab.h>
17 #include <linux/kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/sysfs.h>
20 #include <linux/module.h>
21 #include <linux/uaccess.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/events.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/kfifo_buf.h>
28 #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
29 #define SCA3000_READ_REG(a) ((a) << 2)
31 #define SCA3000_REG_REVID_ADDR 0x00
32 #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
33 #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
35 #define SCA3000_REG_STATUS_ADDR 0x02
36 #define SCA3000_LOCKED BIT(5)
37 #define SCA3000_EEPROM_CS_ERROR BIT(1)
38 #define SCA3000_SPI_FRAME_ERROR BIT(0)
40 /* All reads done using register decrement so no need to directly access LSBs */
41 #define SCA3000_REG_X_MSB_ADDR 0x05
42 #define SCA3000_REG_Y_MSB_ADDR 0x07
43 #define SCA3000_REG_Z_MSB_ADDR 0x09
45 #define SCA3000_REG_RING_OUT_ADDR 0x0f
47 /* Temp read untested - the e05 doesn't have the sensor */
48 #define SCA3000_REG_TEMP_MSB_ADDR 0x13
50 #define SCA3000_REG_MODE_ADDR 0x14
51 #define SCA3000_MODE_PROT_MASK 0x28
52 #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
53 #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
56 * Free fall detection triggers an interrupt if the acceleration
57 * is below a threshold for equivalent of 25cm drop
59 #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
60 #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
61 #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
62 #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
65 * In motion detection mode the accelerations are band pass filtered
66 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
69 #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
70 #define SCA3000_REG_MODE_MODE_MASK 0x03
72 #define SCA3000_REG_BUF_COUNT_ADDR 0x15
74 #define SCA3000_REG_INT_STATUS_ADDR 0x16
75 #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
76 #define SCA3000_REG_INT_STATUS_HALF BIT(6)
78 #define SCA3000_INT_STATUS_FREE_FALL BIT(3)
79 #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
80 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
81 #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
83 /* Used to allow access to multiplexed registers */
84 #define SCA3000_REG_CTRL_SEL_ADDR 0x18
85 /* Only available for SCA3000-D03 and SCA3000-D01 */
86 #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
87 #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
88 #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
89 #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
90 #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
92 * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
95 #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
97 #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
98 #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
99 #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
100 #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
101 #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
102 #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
103 #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
107 * Control which motion detector interrupts are on.
108 * For now only OR combinations are supported.
110 #define SCA3000_MD_CTRL_PROT_MASK 0xC0
111 #define SCA3000_MD_CTRL_OR_Y BIT(0)
112 #define SCA3000_MD_CTRL_OR_X BIT(1)
113 #define SCA3000_MD_CTRL_OR_Z BIT(2)
114 /* Currently unsupported */
115 #define SCA3000_MD_CTRL_AND_Y BIT(3)
116 #define SCA3000_MD_CTRL_AND_X BIT(4)
117 #define SAC3000_MD_CTRL_AND_Z BIT(5)
120 * Some control registers of complex access methods requiring this register to
121 * be used to remove a lock.
123 #define SCA3000_REG_UNLOCK_ADDR 0x1e
125 #define SCA3000_REG_INT_MASK_ADDR 0x21
126 #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
128 #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
129 #define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
131 #define SCA3000_REG_INT_MASK_ALL_INTS 0x02
132 #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
133 #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
134 /* Values of multiplexed registers (write to ctrl_data after select) */
135 #define SCA3000_REG_CTRL_DATA_ADDR 0x22
138 * Measurement modes available on some sca3000 series chips. Code assumes others
139 * may become available in the future.
141 * Bypass - Bypass the low-pass filter in the signal channel so as to increase
144 * Narrow - Narrow low-pass filtering of the signal channel and half output
145 * data rate by decimation.
147 * Wide - Widen low-pass filtering of signal channel to increase bandwidth
149 #define SCA3000_OP_MODE_BYPASS 0x01
150 #define SCA3000_OP_MODE_NARROW 0x02
151 #define SCA3000_OP_MODE_WIDE 0x04
152 #define SCA3000_MAX_TX 6
153 #define SCA3000_MAX_RX 2
156 * struct sca3000_state - device instance state information
157 * @us: the associated spi device
158 * @info: chip variant information
159 * @last_timestamp: the timestamp of the last event
160 * @mo_det_use_count: reference counter for the motion detection unit
161 * @lock: lock used to protect elements of sca3000_state
162 * and the underlying device state.
163 * @tx: dma-able transmit buffer
164 * @rx: dma-able receive buffer
166 struct sca3000_state {
167 struct spi_device *us;
168 const struct sca3000_chip_info *info;
170 int mo_det_use_count;
172 /* Can these share a cacheline ? */
173 u8 rx[384] ____cacheline_aligned;
174 u8 tx[6] ____cacheline_aligned;
178 * struct sca3000_chip_info - model dependent parameters
179 * @scale: scale * 10^-6
180 * @temp_output: some devices have temperature sensors.
181 * @measurement_mode_freq: normal mode sampling frequency
182 * @option_mode_1: first optional mode. Not all models have one
183 * @option_mode_1_freq: option mode 1 sampling frequency
184 * @option_mode_2: second optional mode. Not all chips have one
185 * @option_mode_2_freq: option mode 2 sampling frequency
187 * This structure is used to hold information about the functionality of a given
190 struct sca3000_chip_info {
193 int measurement_mode_freq;
194 int measurement_mode_3db_freq;
196 int option_mode_1_freq;
197 int option_mode_1_3db_freq;
199 int option_mode_2_freq;
200 int option_mode_2_3db_freq;
201 int mot_det_mult_xz[6];
202 int mot_det_mult_y[7];
205 enum sca3000_variant {
213 * Note where option modes are not defined, the chip simply does not
215 * Other chips in the sca3000 series use i2c and are not included here.
217 * Some of these devices are only listed in the family data sheet and
218 * do not actually appear to be available.
220 static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
224 .measurement_mode_freq = 250,
225 .measurement_mode_3db_freq = 45,
226 .option_mode_1 = SCA3000_OP_MODE_BYPASS,
227 .option_mode_1_freq = 250,
228 .option_mode_1_3db_freq = 70,
229 .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
230 .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
234 .measurement_mode_freq = 125,
235 .measurement_mode_3db_freq = 40,
236 .option_mode_1 = SCA3000_OP_MODE_NARROW,
237 .option_mode_1_freq = 63,
238 .option_mode_1_3db_freq = 11,
239 .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
240 .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
244 .measurement_mode_freq = 100,
245 .measurement_mode_3db_freq = 38,
246 .option_mode_1 = SCA3000_OP_MODE_NARROW,
247 .option_mode_1_freq = 50,
248 .option_mode_1_3db_freq = 9,
249 .option_mode_2 = SCA3000_OP_MODE_WIDE,
250 .option_mode_2_freq = 400,
251 .option_mode_2_3db_freq = 70,
252 .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
253 .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
257 .measurement_mode_freq = 200,
258 .measurement_mode_3db_freq = 60,
259 .option_mode_1 = SCA3000_OP_MODE_NARROW,
260 .option_mode_1_freq = 50,
261 .option_mode_1_3db_freq = 9,
262 .option_mode_2 = SCA3000_OP_MODE_WIDE,
263 .option_mode_2_freq = 400,
264 .option_mode_2_3db_freq = 75,
265 .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
266 .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
270 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
272 st->tx[0] = SCA3000_WRITE_REG(address);
274 return spi_write(st->us, st->tx, 2);
277 static int sca3000_read_data_short(struct sca3000_state *st,
281 struct spi_transfer xfer[2] = {
290 st->tx[0] = SCA3000_READ_REG(reg_address_high);
292 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
296 * sca3000_reg_lock_on() test if the ctrl register lock is on
300 static int sca3000_reg_lock_on(struct sca3000_state *st)
304 ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
308 return !(st->rx[0] & SCA3000_LOCKED);
312 * __sca3000_unlock_reg_lock() unlock the control registers
314 * Note the device does not appear to support doing this in a single transfer.
315 * This should only ever be used as part of ctrl reg read.
316 * Lock must be held before calling this
318 static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
320 struct spi_transfer xfer[3] = {
328 .tx_buf = st->tx + 2,
331 .tx_buf = st->tx + 4,
334 st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
336 st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
338 st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
341 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
345 * sca3000_write_ctrl_reg() write to a lock protect ctrl register
346 * @sel: selects which registers we wish to write to
347 * @val: the value to be written
349 * Certain control registers are protected against overwriting by the lock
350 * register and use a shared write address. This function allows writing of
354 static int sca3000_write_ctrl_reg(struct sca3000_state *st,
360 ret = sca3000_reg_lock_on(st);
364 ret = __sca3000_unlock_reg_lock(st);
369 /* Set the control select register */
370 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
374 /* Write the actual value into the register */
375 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
382 * sca3000_read_ctrl_reg() read from lock protected control register.
386 static int sca3000_read_ctrl_reg(struct sca3000_state *st,
391 ret = sca3000_reg_lock_on(st);
395 ret = __sca3000_unlock_reg_lock(st);
399 /* Set the control select register */
400 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
403 ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
412 * sca3000_show_rev() - sysfs interface to read the chip revision number
414 static ssize_t sca3000_show_rev(struct device *dev,
415 struct device_attribute *attr,
419 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
420 struct sca3000_state *st = iio_priv(indio_dev);
422 mutex_lock(&st->lock);
423 ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
426 len += sprintf(buf + len,
427 "major=%lu, minor=%lu\n",
428 st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
429 st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
431 mutex_unlock(&st->lock);
433 return ret ? ret : len;
437 sca3000_show_available_3db_freqs(struct device *dev,
438 struct device_attribute *attr,
441 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
442 struct sca3000_state *st = iio_priv(indio_dev);
445 len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
446 if (st->info->option_mode_1)
447 len += sprintf(buf + len, " %d",
448 st->info->option_mode_1_3db_freq);
449 if (st->info->option_mode_2)
450 len += sprintf(buf + len, " %d",
451 st->info->option_mode_2_3db_freq);
452 len += sprintf(buf + len, "\n");
457 * sca3000_show_available_measurement_modes() display available modes
459 * This is all read from chip specific data in the driver. Not all
460 * of the sca3000 series support modes other than normal.
463 sca3000_show_available_measurement_modes(struct device *dev,
464 struct device_attribute *attr,
467 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
468 struct sca3000_state *st = iio_priv(indio_dev);
471 len += sprintf(buf + len, "0 - normal mode");
472 switch (st->info->option_mode_1) {
473 case SCA3000_OP_MODE_NARROW:
474 len += sprintf(buf + len, ", 1 - narrow mode");
476 case SCA3000_OP_MODE_BYPASS:
477 len += sprintf(buf + len, ", 1 - bypass mode");
480 switch (st->info->option_mode_2) {
481 case SCA3000_OP_MODE_WIDE:
482 len += sprintf(buf + len, ", 2 - wide mode");
485 /* always supported */
486 len += sprintf(buf + len, " 3 - motion detection\n");
492 * sca3000_show_measurement_mode() sysfs read of current mode
495 sca3000_show_measurement_mode(struct device *dev,
496 struct device_attribute *attr,
499 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
500 struct sca3000_state *st = iio_priv(indio_dev);
503 mutex_lock(&st->lock);
504 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
507 /* mask bottom 2 bits - only ones that are relevant */
508 st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
510 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
511 len += sprintf(buf + len, "0 - normal mode\n");
513 case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
514 len += sprintf(buf + len, "3 - motion detection\n");
516 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
517 switch (st->info->option_mode_1) {
518 case SCA3000_OP_MODE_NARROW:
519 len += sprintf(buf + len, "1 - narrow mode\n");
521 case SCA3000_OP_MODE_BYPASS:
522 len += sprintf(buf + len, "1 - bypass mode\n");
526 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
527 switch (st->info->option_mode_2) {
528 case SCA3000_OP_MODE_WIDE:
529 len += sprintf(buf + len, "2 - wide mode\n");
536 mutex_unlock(&st->lock);
538 return ret ? ret : len;
542 * sca3000_store_measurement_mode() set the current mode
545 sca3000_store_measurement_mode(struct device *dev,
546 struct device_attribute *attr,
550 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
551 struct sca3000_state *st = iio_priv(indio_dev);
555 mutex_lock(&st->lock);
556 ret = kstrtou8(buf, 10, &val);
563 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
566 st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
567 st->rx[0] |= (val & SCA3000_REG_MODE_MODE_MASK);
568 ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
571 mutex_unlock(&st->lock);
576 mutex_unlock(&st->lock);
582 * Not even vaguely standard attributes so defined here rather than
583 * in the relevant IIO core headers
585 static IIO_DEVICE_ATTR(measurement_mode_available, S_IRUGO,
586 sca3000_show_available_measurement_modes,
589 static IIO_DEVICE_ATTR(measurement_mode, S_IRUGO | S_IWUSR,
590 sca3000_show_measurement_mode,
591 sca3000_store_measurement_mode,
594 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
595 S_IRUGO, sca3000_show_available_3db_freqs,
597 /* More standard attributes */
599 static IIO_DEVICE_ATTR(revision, S_IRUGO, sca3000_show_rev, NULL, 0);
601 static const struct iio_event_spec sca3000_event = {
602 .type = IIO_EV_TYPE_MAG,
603 .dir = IIO_EV_DIR_RISING,
604 .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
608 * Note the hack in the number of bits to pretend we have 2 more than
611 #define SCA3000_CHAN(index, mod) \
616 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
617 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
618 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
619 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
621 .scan_index = index, \
627 .endianness = IIO_BE, \
629 .event_spec = &sca3000_event, \
630 .num_event_specs = 1, \
633 static const struct iio_event_spec sca3000_freefall_event_spec = {
634 .type = IIO_EV_TYPE_MAG,
635 .dir = IIO_EV_DIR_FALLING,
636 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
637 BIT(IIO_EV_INFO_PERIOD),
640 static const struct iio_chan_spec sca3000_channels[] = {
641 SCA3000_CHAN(0, IIO_MOD_X),
642 SCA3000_CHAN(1, IIO_MOD_Y),
643 SCA3000_CHAN(2, IIO_MOD_Z),
647 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
648 .scan_index = -1, /* Fake channel */
649 .event_spec = &sca3000_freefall_event_spec,
650 .num_event_specs = 1,
654 static const struct iio_chan_spec sca3000_channels_with_temp[] = {
655 SCA3000_CHAN(0, IIO_MOD_X),
656 SCA3000_CHAN(1, IIO_MOD_Y),
657 SCA3000_CHAN(2, IIO_MOD_Z),
660 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
661 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
662 BIT(IIO_CHAN_INFO_OFFSET),
663 /* No buffer support */
669 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
670 .scan_index = -1, /* Fake channel */
671 .event_spec = &sca3000_freefall_event_spec,
672 .num_event_specs = 1,
676 static u8 sca3000_addresses[3][3] = {
677 [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
678 SCA3000_MD_CTRL_OR_X},
679 [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
680 SCA3000_MD_CTRL_OR_Y},
681 [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
682 SCA3000_MD_CTRL_OR_Z},
686 * __sca3000_get_base_freq() obtain mode specific base frequency
690 static inline int __sca3000_get_base_freq(struct sca3000_state *st,
691 const struct sca3000_chip_info *info,
696 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
699 switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
700 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
701 *base_freq = info->measurement_mode_freq;
703 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
704 *base_freq = info->option_mode_1_freq;
706 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
707 *base_freq = info->option_mode_2_freq;
717 * read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
721 static int read_raw_samp_freq(struct sca3000_state *st, int *val)
725 ret = __sca3000_get_base_freq(st, st->info, val);
729 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
734 ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
736 case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
739 case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
749 * write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
753 static int write_raw_samp_freq(struct sca3000_state *st, int val)
755 int ret, base_freq, ctrlval;
757 ret = __sca3000_get_base_freq(st, st->info, &base_freq);
761 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
765 ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
767 if (val == base_freq / 2)
768 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
769 if (val == base_freq / 4)
770 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
771 else if (val != base_freq)
774 return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
778 static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
782 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
786 /* mask bottom 2 bits - only ones that are relevant */
787 st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
789 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
790 *val = st->info->measurement_mode_3db_freq;
792 case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
794 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
795 *val = st->info->option_mode_1_3db_freq;
797 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
798 *val = st->info->option_mode_2_3db_freq;
805 static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
810 if (val == st->info->measurement_mode_3db_freq)
811 mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
812 else if (st->info->option_mode_1 &&
813 (val == st->info->option_mode_1_3db_freq))
814 mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
815 else if (st->info->option_mode_2 &&
816 (val == st->info->option_mode_2_3db_freq))
817 mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
820 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
824 st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
825 st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
827 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
830 static int sca3000_read_raw(struct iio_dev *indio_dev,
831 struct iio_chan_spec const *chan,
836 struct sca3000_state *st = iio_priv(indio_dev);
841 case IIO_CHAN_INFO_RAW:
842 mutex_lock(&st->lock);
843 if (chan->type == IIO_ACCEL) {
844 if (st->mo_det_use_count) {
845 mutex_unlock(&st->lock);
848 address = sca3000_addresses[chan->address][0];
849 ret = sca3000_read_data_short(st, address, 2);
851 mutex_unlock(&st->lock);
854 *val = (be16_to_cpup((__be16 *)st->rx) >> 3) & 0x1FFF;
855 *val = ((*val) << (sizeof(*val) * 8 - 13)) >>
856 (sizeof(*val) * 8 - 13);
858 /* get the temperature when available */
859 ret = sca3000_read_data_short(st,
860 SCA3000_REG_TEMP_MSB_ADDR,
863 mutex_unlock(&st->lock);
866 *val = ((st->rx[0] & 0x3F) << 3) |
867 ((st->rx[1] & 0xE0) >> 5);
869 mutex_unlock(&st->lock);
871 case IIO_CHAN_INFO_SCALE:
873 if (chan->type == IIO_ACCEL)
874 *val2 = st->info->scale;
875 else /* temperature */
877 return IIO_VAL_INT_PLUS_MICRO;
878 case IIO_CHAN_INFO_OFFSET:
881 return IIO_VAL_INT_PLUS_MICRO;
882 case IIO_CHAN_INFO_SAMP_FREQ:
883 mutex_lock(&st->lock);
884 ret = read_raw_samp_freq(st, val);
885 mutex_unlock(&st->lock);
886 return ret ? ret : IIO_VAL_INT;
887 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
888 mutex_lock(&st->lock);
889 ret = sca3000_read_3db_freq(st, val);
890 mutex_unlock(&st->lock);
897 static int sca3000_write_raw(struct iio_dev *indio_dev,
898 struct iio_chan_spec const *chan,
899 int val, int val2, long mask)
901 struct sca3000_state *st = iio_priv(indio_dev);
905 case IIO_CHAN_INFO_SAMP_FREQ:
908 mutex_lock(&st->lock);
909 ret = write_raw_samp_freq(st, val);
910 mutex_unlock(&st->lock);
912 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
915 mutex_lock(&st->lock);
916 ret = sca3000_write_3db_freq(st, val);
917 mutex_unlock(&st->lock);
926 * sca3000_read_av_freq() sysfs function to get available frequencies
928 * The later modes are only relevant to the ring buffer - and depend on current
929 * mode. Note that data sheet gives rather wide tolerances for these so integer
930 * division will give good enough answer and not all chips have them specified
933 static ssize_t sca3000_read_av_freq(struct device *dev,
934 struct device_attribute *attr,
937 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
938 struct sca3000_state *st = iio_priv(indio_dev);
939 int len = 0, ret, val;
941 mutex_lock(&st->lock);
942 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
944 mutex_unlock(&st->lock);
948 switch (val & SCA3000_REG_MODE_MODE_MASK) {
949 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
950 len += sprintf(buf + len, "%d %d %d\n",
951 st->info->measurement_mode_freq,
952 st->info->measurement_mode_freq / 2,
953 st->info->measurement_mode_freq / 4);
955 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
956 len += sprintf(buf + len, "%d %d %d\n",
957 st->info->option_mode_1_freq,
958 st->info->option_mode_1_freq / 2,
959 st->info->option_mode_1_freq / 4);
961 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
962 len += sprintf(buf + len, "%d %d %d\n",
963 st->info->option_mode_2_freq,
964 st->info->option_mode_2_freq / 2,
965 st->info->option_mode_2_freq / 4);
974 * Should only really be registered if ring buffer support is compiled in.
975 * Does no harm however and doing it right would add a fair bit of complexity
977 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
980 * sca3000_read_event_value() - query of a threshold or period
982 static int sca3000_read_event_value(struct iio_dev *indio_dev,
983 const struct iio_chan_spec *chan,
984 enum iio_event_type type,
985 enum iio_event_direction dir,
986 enum iio_event_info info,
990 struct sca3000_state *st = iio_priv(indio_dev);
993 case IIO_EV_INFO_VALUE:
994 mutex_lock(&st->lock);
995 ret = sca3000_read_ctrl_reg(st,
996 sca3000_addresses[chan->address][1]);
997 mutex_unlock(&st->lock);
1001 if (chan->channel2 == IIO_MOD_Y)
1002 for_each_set_bit(i, (unsigned long *)&ret,
1003 ARRAY_SIZE(st->info->mot_det_mult_y))
1004 *val += st->info->mot_det_mult_y[i];
1006 for_each_set_bit(i, (unsigned long *)&ret,
1007 ARRAY_SIZE(st->info->mot_det_mult_xz))
1008 *val += st->info->mot_det_mult_xz[i];
1011 case IIO_EV_INFO_PERIOD:
1014 return IIO_VAL_INT_PLUS_MICRO;
1021 * sca3000_write_value() control of threshold and period
1023 static int sca3000_write_event_value(struct iio_dev *indio_dev,
1024 const struct iio_chan_spec *chan,
1025 enum iio_event_type type,
1026 enum iio_event_direction dir,
1027 enum iio_event_info info,
1030 struct sca3000_state *st = iio_priv(indio_dev);
1035 if (chan->channel2 == IIO_MOD_Y) {
1036 i = ARRAY_SIZE(st->info->mot_det_mult_y);
1038 if (val >= st->info->mot_det_mult_y[--i]) {
1039 nonlinear |= (1 << i);
1040 val -= st->info->mot_det_mult_y[i];
1043 i = ARRAY_SIZE(st->info->mot_det_mult_xz);
1045 if (val >= st->info->mot_det_mult_xz[--i]) {
1046 nonlinear |= (1 << i);
1047 val -= st->info->mot_det_mult_xz[i];
1051 mutex_lock(&st->lock);
1052 ret = sca3000_write_ctrl_reg(st,
1053 sca3000_addresses[chan->address][1],
1055 mutex_unlock(&st->lock);
1060 static struct attribute *sca3000_attributes[] = {
1061 &iio_dev_attr_revision.dev_attr.attr,
1062 &iio_dev_attr_measurement_mode_available.dev_attr.attr,
1063 &iio_dev_attr_measurement_mode.dev_attr.attr,
1064 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
1065 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1069 static const struct attribute_group sca3000_attribute_group = {
1070 .attrs = sca3000_attributes,
1073 static int sca3000_read_data(struct sca3000_state *st,
1074 u8 reg_address_high,
1079 struct spi_transfer xfer[2] = {
1089 st->tx[0] = SCA3000_READ_REG(reg_address_high);
1090 ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
1092 dev_err(get_device(&st->us->dev), "problem reading register");
1100 * sca3000_ring_int_process() ring specific interrupt handling.
1102 * This is only split from the main interrupt handler so as to
1103 * reduce the amount of code if the ring buffer is not enabled.
1105 static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
1107 struct sca3000_state *st = iio_priv(indio_dev);
1108 int ret, i, num_available;
1110 mutex_lock(&st->lock);
1112 if (val & SCA3000_REG_INT_STATUS_HALF) {
1113 ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
1117 num_available = st->rx[0];
1119 * num_available is the total number of samples available
1120 * i.e. number of time points * number of channels.
1122 ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
1126 for (i = 0; i < num_available / 3; i++) {
1128 * Dirty hack to cover for 11 bit in fifo, 13 bit
1131 * In theory the bottom two bits are undefined.
1132 * In reality they appear to always be 0.
1134 iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
1138 mutex_unlock(&st->lock);
1142 * sca3000_event_handler() - handling ring and non ring events
1144 * Ring related interrupt handler. Depending on event, push to
1145 * the ring buffer event chrdev or the event one.
1147 * This function is complicated by the fact that the devices can signify ring
1148 * and non ring events via the same interrupt line and they can only
1149 * be distinguished via a read of the relevant status register.
1151 static irqreturn_t sca3000_event_handler(int irq, void *private)
1153 struct iio_dev *indio_dev = private;
1154 struct sca3000_state *st = iio_priv(indio_dev);
1156 s64 last_timestamp = iio_get_time_ns(indio_dev);
1159 * Could lead if badly timed to an extra read of status reg,
1160 * but ensures no interrupt is missed.
1162 mutex_lock(&st->lock);
1163 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1165 mutex_unlock(&st->lock);
1169 sca3000_ring_int_process(val, indio_dev);
1171 if (val & SCA3000_INT_STATUS_FREE_FALL)
1172 iio_push_event(indio_dev,
1173 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1175 IIO_MOD_X_AND_Y_AND_Z,
1177 IIO_EV_DIR_FALLING),
1180 if (val & SCA3000_INT_STATUS_Y_TRIGGER)
1181 iio_push_event(indio_dev,
1182 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1189 if (val & SCA3000_INT_STATUS_X_TRIGGER)
1190 iio_push_event(indio_dev,
1191 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1198 if (val & SCA3000_INT_STATUS_Z_TRIGGER)
1199 iio_push_event(indio_dev,
1200 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1212 * sca3000_read_event_config() what events are enabled
1214 static int sca3000_read_event_config(struct iio_dev *indio_dev,
1215 const struct iio_chan_spec *chan,
1216 enum iio_event_type type,
1217 enum iio_event_direction dir)
1219 struct sca3000_state *st = iio_priv(indio_dev);
1221 /* read current value of mode register */
1222 mutex_lock(&st->lock);
1224 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1228 switch (chan->channel2) {
1229 case IIO_MOD_X_AND_Y_AND_Z:
1230 ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
1236 * Motion detection mode cannot run at the same time as
1237 * acceleration data being read.
1239 if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1240 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
1243 ret = sca3000_read_ctrl_reg(st,
1244 SCA3000_REG_CTRL_SEL_MD_CTRL);
1247 /* only supporting logical or's for now */
1248 ret = !!(ret & sca3000_addresses[chan->address][2]);
1256 mutex_unlock(&st->lock);
1261 static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
1263 struct sca3000_state *st = iio_priv(indio_dev);
1266 /* read current value of mode register */
1267 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1271 /* if off and should be on */
1272 if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1273 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1274 st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
1275 /* if on and should be off */
1276 else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1277 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1278 st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
1283 static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
1286 struct sca3000_state *st = iio_priv(indio_dev);
1290 * First read the motion detector config to find out if
1293 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1297 /* if off and should be on */
1298 if (state && !(ctrlval & sca3000_addresses[axis][2])) {
1299 ret = sca3000_write_ctrl_reg(st,
1300 SCA3000_REG_CTRL_SEL_MD_CTRL,
1302 sca3000_addresses[axis][2]);
1305 st->mo_det_use_count++;
1306 } else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
1307 ret = sca3000_write_ctrl_reg(st,
1308 SCA3000_REG_CTRL_SEL_MD_CTRL,
1310 ~(sca3000_addresses[axis][2]));
1313 st->mo_det_use_count--;
1316 /* read current value of mode register */
1317 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1320 /* if off and should be on */
1321 if ((st->mo_det_use_count) &&
1322 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1323 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1324 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1325 (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
1326 | SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
1327 /* if on and should be off */
1328 else if (!(st->mo_det_use_count) &&
1329 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1330 == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1331 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1332 st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
1338 * sca3000_write_event_config() simple on off control for motion detector
1340 * This is a per axis control, but enabling any will result in the
1341 * motion detector unit being enabled.
1342 * N.B. enabling motion detector stops normal data acquisition.
1343 * There is a complexity in knowing which mode to return to when
1344 * this mode is disabled. Currently normal mode is assumed.
1346 static int sca3000_write_event_config(struct iio_dev *indio_dev,
1347 const struct iio_chan_spec *chan,
1348 enum iio_event_type type,
1349 enum iio_event_direction dir,
1352 struct sca3000_state *st = iio_priv(indio_dev);
1355 mutex_lock(&st->lock);
1356 switch (chan->channel2) {
1357 case IIO_MOD_X_AND_Y_AND_Z:
1358 ret = sca3000_freefall_set_state(indio_dev, state);
1364 ret = sca3000_motion_detect_set_state(indio_dev,
1372 mutex_unlock(&st->lock);
1377 static int sca3000_configure_ring(struct iio_dev *indio_dev)
1379 struct iio_buffer *buffer;
1381 buffer = iio_kfifo_allocate();
1385 iio_device_attach_buffer(indio_dev, buffer);
1386 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1391 static void sca3000_unconfigure_ring(struct iio_dev *indio_dev)
1393 iio_kfifo_free(indio_dev->buffer);
1397 int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
1399 struct sca3000_state *st = iio_priv(indio_dev);
1402 mutex_lock(&st->lock);
1403 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1407 dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
1408 ret = sca3000_write_reg(st,
1409 SCA3000_REG_MODE_ADDR,
1410 (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
1412 ret = sca3000_write_reg(st,
1413 SCA3000_REG_MODE_ADDR,
1414 (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
1416 mutex_unlock(&st->lock);
1422 * sca3000_hw_ring_preenable() hw ring buffer preenable function
1424 * Very simple enable function as the chip will allows normal reads
1425 * during ring buffer operation so as long as it is indeed running
1426 * before we notify the core, the precise ordering does not matter.
1428 static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
1431 struct sca3000_state *st = iio_priv(indio_dev);
1433 mutex_lock(&st->lock);
1435 /* Enable the 50% full interrupt */
1436 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1439 ret = sca3000_write_reg(st,
1440 SCA3000_REG_INT_MASK_ADDR,
1441 st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
1445 mutex_unlock(&st->lock);
1447 return __sca3000_hw_ring_state_set(indio_dev, 1);
1450 mutex_unlock(&st->lock);
1455 static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
1458 struct sca3000_state *st = iio_priv(indio_dev);
1460 ret = __sca3000_hw_ring_state_set(indio_dev, 0);
1464 /* Disable the 50% full interrupt */
1465 mutex_lock(&st->lock);
1467 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1470 ret = sca3000_write_reg(st,
1471 SCA3000_REG_INT_MASK_ADDR,
1472 st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
1474 mutex_unlock(&st->lock);
1478 static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
1479 .preenable = &sca3000_hw_ring_preenable,
1480 .postdisable = &sca3000_hw_ring_postdisable,
1484 * sca3000_clean_setup() get the device into a predictable state
1486 * Devices use flash memory to store many of the register values
1487 * and hence can come up in somewhat unpredictable states.
1488 * Hence reset everything on driver load.
1490 static int sca3000_clean_setup(struct sca3000_state *st)
1494 mutex_lock(&st->lock);
1495 /* Ensure all interrupts have been acknowledged */
1496 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1500 /* Turn off all motion detection channels */
1501 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1504 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
1505 ret & SCA3000_MD_CTRL_PROT_MASK);
1509 /* Disable ring buffer */
1510 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
1513 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
1514 (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
1515 | SCA3000_REG_OUT_CTRL_BUF_X_EN
1516 | SCA3000_REG_OUT_CTRL_BUF_Y_EN
1517 | SCA3000_REG_OUT_CTRL_BUF_Z_EN
1518 | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
1521 /* Enable interrupts, relevant to mode and set up as active low */
1522 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1525 ret = sca3000_write_reg(st,
1526 SCA3000_REG_INT_MASK_ADDR,
1527 (ret & SCA3000_REG_INT_MASK_PROT_MASK)
1528 | SCA3000_REG_INT_MASK_ACTIVE_LOW);
1532 * Select normal measurement mode, free fall off, ring off
1533 * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
1534 * as that occurs in one of the example on the datasheet
1536 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1539 ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1540 (st->rx[0] & SCA3000_MODE_PROT_MASK));
1543 mutex_unlock(&st->lock);
1547 static const struct iio_info sca3000_info = {
1548 .attrs = &sca3000_attribute_group,
1549 .read_raw = &sca3000_read_raw,
1550 .write_raw = &sca3000_write_raw,
1551 .read_event_value = &sca3000_read_event_value,
1552 .write_event_value = &sca3000_write_event_value,
1553 .read_event_config = &sca3000_read_event_config,
1554 .write_event_config = &sca3000_write_event_config,
1555 .driver_module = THIS_MODULE,
1558 static int sca3000_probe(struct spi_device *spi)
1561 struct sca3000_state *st;
1562 struct iio_dev *indio_dev;
1564 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1568 st = iio_priv(indio_dev);
1569 spi_set_drvdata(spi, indio_dev);
1571 mutex_init(&st->lock);
1572 st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
1575 indio_dev->dev.parent = &spi->dev;
1576 indio_dev->name = spi_get_device_id(spi)->name;
1577 indio_dev->info = &sca3000_info;
1578 if (st->info->temp_output) {
1579 indio_dev->channels = sca3000_channels_with_temp;
1580 indio_dev->num_channels =
1581 ARRAY_SIZE(sca3000_channels_with_temp);
1583 indio_dev->channels = sca3000_channels;
1584 indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
1586 indio_dev->modes = INDIO_DIRECT_MODE;
1588 sca3000_configure_ring(indio_dev);
1589 ret = iio_device_register(indio_dev);
1594 ret = request_threaded_irq(spi->irq,
1596 &sca3000_event_handler,
1597 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1601 goto error_unregister_dev;
1603 indio_dev->setup_ops = &sca3000_ring_setup_ops;
1604 ret = sca3000_clean_setup(st);
1606 goto error_free_irq;
1611 free_irq(spi->irq, indio_dev);
1612 error_unregister_dev:
1613 iio_device_unregister(indio_dev);
1617 static int sca3000_stop_all_interrupts(struct sca3000_state *st)
1621 mutex_lock(&st->lock);
1622 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1625 ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
1627 ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
1628 SCA3000_REG_INT_MASK_RING_HALF |
1629 SCA3000_REG_INT_MASK_ALL_INTS)));
1631 mutex_unlock(&st->lock);
1635 static int sca3000_remove(struct spi_device *spi)
1637 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1638 struct sca3000_state *st = iio_priv(indio_dev);
1640 /* Must ensure no interrupts can be generated after this! */
1641 sca3000_stop_all_interrupts(st);
1643 free_irq(spi->irq, indio_dev);
1644 iio_device_unregister(indio_dev);
1645 sca3000_unconfigure_ring(indio_dev);
1650 static const struct spi_device_id sca3000_id[] = {
1651 {"sca3000_d01", d01},
1652 {"sca3000_e02", e02},
1653 {"sca3000_e04", e04},
1654 {"sca3000_e05", e05},
1657 MODULE_DEVICE_TABLE(spi, sca3000_id);
1659 static struct spi_driver sca3000_driver = {
1663 .probe = sca3000_probe,
1664 .remove = sca3000_remove,
1665 .id_table = sca3000_id,
1667 module_spi_driver(sca3000_driver);
1669 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1670 MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
1671 MODULE_LICENSE("GPL v2");