2 * comedi/drivers/daqboard2000.c
3 * hardware driver for IOtech DAQboard/2000
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 * Driver: daqboard2000
20 * Description: IOTech DAQBoard/2000
21 * Author: Anders Blomdell <anders.blomdell@control.lth.se>
23 * Updated: Mon, 14 Apr 2008 15:28:52 +0100
24 * Devices: [IOTech] DAQBoard/2000 (daqboard2000)
26 * Much of the functionality of this driver was determined from reading
27 * the source code for the Windows driver.
29 * The FPGA on the board requires firmware, which is available from
30 * http://www.comedi.org in the comedi_nonfree_firmware tarball.
32 * Configuration options: not applicable, uses PCI auto config
35 * This card was obviously never intended to leave the Windows world,
36 * since it lacked all kind of hardware documentation (except for cable
37 * pinouts, plug and pray has something to catch up with yet).
39 * With some help from our swedish distributor, we got the Windows sourcecode
40 * for the card, and here are the findings so far.
42 * 1. A good document that describes the PCI interface chip is 9080db-106.pdf
43 * available from http://www.plxtech.com/products/io/pci9080
45 * 2. The initialization done so far is:
46 * a. program the FPGA (windows code sans a lot of error messages)
49 * 3. Analog out seems to work OK with DAC's disabled, if DAC's are enabled,
50 * you have to output values to all enabled DAC's until result appears, I
51 * guess that it has something to do with pacer clocks, but the source
52 * gives me no clues. I'll keep it simple so far.
55 * Each channel in the scanlist seems to be controlled by four
59 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * ! | | | ! | | | ! | | | ! | | | !
61 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
64 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
65 * ! | | | ! | | | ! | | | ! | | | !
66 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
68 * +------+------+ | | | | +-- Digital input (??)
69 * | | | | +---- 10 us settling time
70 * | | | +------ Suspend acquisition (last to scan)
71 * | | +-------- Simultaneous sample and hold
72 * | +---------- Signed data format
73 * +------------------------- Correction offset low
76 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
77 * ! | | | ! | | | ! | | | ! | | | !
78 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
80 * +-----+ +--+--+ +++ +++ +--+--+
81 * | | | | +----- Expansion channel
82 * | | | +----------- Expansion gain
83 * | | +--------------- Channel (low)
84 * | +--------------------- Correction offset high
85 * +----------------------------- Correction gain low
87 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
88 * ! | | | ! | | | ! | | | ! | | | !
89 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
91 * +------+------+ | | +-+-+ | | +-- Low bank enable
92 * | | | | | +---- High bank enable
93 * | | | | +------ Hi/low select
94 * | | | +---------- Gain (1,?,2,4,8,16,32,64)
95 * | | +-------------- differential/single ended
96 * | +---------------- Unipolar
97 * +------------------------- Correction gain high
99 * 999. The card seems to have an incredible amount of capabilities, but
100 * trying to reverse engineer them from the Windows source is beyond my
105 #include <linux/module.h>
106 #include <linux/delay.h>
107 #include <linux/interrupt.h>
109 #include "../comedi_pci.h"
114 #define DB2K_FIRMWARE "daqboard2000_firmware.bin"
116 #define DB2K_SUBSYSTEM_IDS2 0x0002 /* Daqboard/2000 - 2 Dacs */
117 #define DB2K_SUBSYSTEM_IDS4 0x0004 /* Daqboard/2000 - 4 Dacs */
119 static const struct comedi_lrange db2k_ai_range = {
138 * Register Memory Map
140 #define DB2K_REG_ACQ_CONTROL 0x00 /* u16 (w) */
141 #define DB2K_REG_ACQ_STATUS 0x00 /* u16 (r) */
142 #define DB2K_REG_ACQ_SCAN_LIST_FIFO 0x02 /* u16 */
143 #define DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW 0x04 /* u32 */
144 #define DB2K_REG_ACQ_SCAN_COUNTER 0x08 /* u16 */
145 #define DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH 0x0a /* u16 */
146 #define DB2K_REG_ACQ_TRIGGER_COUNT 0x0c /* u16 */
147 #define DB2K_REG_ACQ_RESULTS_FIFO 0x10 /* u16 */
148 #define DB2K_REG_ACQ_RESULTS_SHADOW 0x14 /* u16 */
149 #define DB2K_REG_ACQ_ADC_RESULT 0x18 /* u16 */
150 #define DB2K_REG_DAC_SCAN_COUNTER 0x1c /* u16 */
151 #define DB2K_REG_DAC_CONTROL 0x20 /* u16 (w) */
152 #define DB2K_REG_DAC_STATUS 0x20 /* u16 (r) */
153 #define DB2K_REG_DAC_FIFO 0x24 /* s16 */
154 #define DB2K_REG_DAC_PACER_CLOCK_DIV 0x2a /* u16 */
155 #define DB2K_REG_REF_DACS 0x2c /* u16 */
156 #define DB2K_REG_DIO_CONTROL 0x30 /* u16 */
157 #define DB2K_REG_P3_HSIO_DATA 0x32 /* s16 */
158 #define DB2K_REG_P3_CONTROL 0x34 /* u16 */
159 #define DB2K_REG_CAL_EEPROM_CONTROL 0x36 /* u16 */
160 #define DB2K_REG_DAC_SETTING(x) (0x38 + (x) * 2) /* s16 */
161 #define DB2K_REG_DIO_P2_EXP_IO_8_BIT 0x40 /* s16 */
162 #define DB2K_REG_COUNTER_TIMER_CONTROL 0x80 /* u16 */
163 #define DB2K_REG_COUNTER_INPUT(x) (0x88 + (x) * 2) /* s16 */
164 #define DB2K_REG_TIMER_DIV(x) (0xa0 + (x) * 2) /* u16 */
165 #define DB2K_REG_DMA_CONTROL 0xb0 /* u16 */
166 #define DB2K_REG_TRIG_CONTROL 0xb2 /* u16 */
167 #define DB2K_REG_CAL_EEPROM 0xb8 /* u16 */
168 #define DB2K_REG_ACQ_DIGITAL_MARK 0xba /* u16 */
169 #define DB2K_REG_TRIG_DACS 0xbc /* u16 */
170 #define DB2K_REG_DIO_P2_EXP_IO_16_BIT(x) (0xc0 + (x) * 2) /* s16 */
173 #define DB2K_REG_CPLD_STATUS 0x1000 /* u16 (r) */
174 #define DB2K_REG_CPLD_WDATA 0x1000 /* u16 (w) */
176 /* Scan Sequencer programming */
177 #define DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST 0x0011
178 #define DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST 0x0010
180 /* Prepare for acquisition */
181 #define DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO 0x0004
182 #define DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO 0x0002
183 #define DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE 0x0001
185 /* Pacer Clock Control */
186 #define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL 0x0030
187 #define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL 0x0032
188 #define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE 0x0031
189 #define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE_DAC_PACER 0x0034
190 #define DB2K_ACQ_CONTROL_ADC_PACER_DISABLE 0x0030
191 #define DB2K_ACQ_CONTROL_ADC_PACER_NORMAL_MODE 0x0060
192 #define DB2K_ACQ_CONTROL_ADC_PACER_COMPATIBILITY_MODE 0x0061
193 #define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL_OUT_ENABLE 0x0008
194 #define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL_RISING 0x0100
196 /* Acquisition status bits */
197 #define DB2K_ACQ_STATUS_RESULTS_FIFO_MORE_1_SAMPLE 0x0001
198 #define DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA 0x0002
199 #define DB2K_ACQ_STATUS_RESULTS_FIFO_OVERRUN 0x0004
200 #define DB2K_ACQ_STATUS_LOGIC_SCANNING 0x0008
201 #define DB2K_ACQ_STATUS_CONFIG_PIPE_FULL 0x0010
202 #define DB2K_ACQ_STATUS_SCAN_LIST_FIFO_EMPTY 0x0020
203 #define DB2K_ACQ_STATUS_ADC_NOT_READY 0x0040
204 #define DB2K_ACQ_STATUS_ARBITRATION_FAILURE 0x0080
205 #define DB2K_ACQ_STATUS_ADC_PACER_OVERRUN 0x0100
206 #define DB2K_ACQ_STATUS_DAC_PACER_OVERRUN 0x0200
209 #define DB2K_DAC_STATUS_DAC_FULL 0x0001
210 #define DB2K_DAC_STATUS_REF_BUSY 0x0002
211 #define DB2K_DAC_STATUS_TRIG_BUSY 0x0004
212 #define DB2K_DAC_STATUS_CAL_BUSY 0x0008
213 #define DB2K_DAC_STATUS_DAC_BUSY(x) (0x0010 << (x))
216 #define DB2K_DAC_CONTROL_ENABLE_BIT 0x0001
217 #define DB2K_DAC_CONTROL_DATA_IS_SIGNED 0x0002
218 #define DB2K_DAC_CONTROL_RESET_FIFO 0x0004
219 #define DB2K_DAC_CONTROL_DAC_DISABLE(x) (0x0020 + ((x) << 4))
220 #define DB2K_DAC_CONTROL_DAC_ENABLE(x) (0x0021 + ((x) << 4))
221 #define DB2K_DAC_CONTROL_PATTERN_DISABLE 0x0060
222 #define DB2K_DAC_CONTROL_PATTERN_ENABLE 0x0061
224 /* Trigger Control */
225 #define DB2K_TRIG_CONTROL_TYPE_ANALOG 0x0000
226 #define DB2K_TRIG_CONTROL_TYPE_TTL 0x0010
227 #define DB2K_TRIG_CONTROL_EDGE_HI_LO 0x0004
228 #define DB2K_TRIG_CONTROL_EDGE_LO_HI 0x0000
229 #define DB2K_TRIG_CONTROL_LEVEL_ABOVE 0x0000
230 #define DB2K_TRIG_CONTROL_LEVEL_BELOW 0x0004
231 #define DB2K_TRIG_CONTROL_SENSE_LEVEL 0x0002
232 #define DB2K_TRIG_CONTROL_SENSE_EDGE 0x0000
233 #define DB2K_TRIG_CONTROL_ENABLE 0x0001
234 #define DB2K_TRIG_CONTROL_DISABLE 0x0000
236 /* Reference Dac Selection */
237 #define DB2K_REF_DACS_SET 0x0080
238 #define DB2K_REF_DACS_SELECT_POS_REF 0x0100
239 #define DB2K_REF_DACS_SELECT_NEG_REF 0x0000
241 /* CPLD status bits */
242 #define DB2K_CPLD_STATUS_INIT 0x0002
243 #define DB2K_CPLD_STATUS_TXREADY 0x0004
244 #define DB2K_CPLD_VERSION_MASK 0xf000
245 /* "New CPLD" signature. */
246 #define DB2K_CPLD_VERSION_NEW 0x5000
248 struct db2k_boardtype {
253 static const struct db2k_boardtype db2k_boardtypes[] = {
256 .id = DB2K_SUBSYSTEM_IDS2,
260 .id = DB2K_SUBSYSTEM_IDS4,
264 struct db2k_private {
268 static void db2k_write_acq_scan_list_entry(struct comedi_device *dev, u16 entry)
270 writew(entry & 0x00ff, dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO);
271 writew((entry >> 8) & 0x00ff,
272 dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO);
275 static void db2k_setup_sampling(struct comedi_device *dev, int chan, int gain)
277 u16 word0, word1, word2, word3;
279 /* Channel 0-7 diff, channel 8-23 single ended */
281 word1 = 0x0004; /* Last scan */
282 word2 = (chan << 6) & 0x00c0;
306 /* These should be read from EEPROM */
307 word2 |= 0x0800; /* offset */
308 word3 |= 0xc000; /* gain */
309 db2k_write_acq_scan_list_entry(dev, word0);
310 db2k_write_acq_scan_list_entry(dev, word1);
311 db2k_write_acq_scan_list_entry(dev, word2);
312 db2k_write_acq_scan_list_entry(dev, word3);
315 static int db2k_ai_status(struct comedi_device *dev, struct comedi_subdevice *s,
316 struct comedi_insn *insn, unsigned long context)
320 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS);
321 if (status & context)
326 static int db2k_ai_insn_read(struct comedi_device *dev,
327 struct comedi_subdevice *s,
328 struct comedi_insn *insn, unsigned int *data)
334 writew(DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO |
335 DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO |
336 DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE,
337 dev->mmio + DB2K_REG_ACQ_CONTROL);
340 * If pacer clock is not set to some high value (> 10 us), we
341 * risk multiple samples to be put into the result FIFO.
343 /* 1 second, should be long enough */
344 writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW);
345 writew(0, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH);
347 gain = CR_RANGE(insn->chanspec);
348 chan = CR_CHAN(insn->chanspec);
351 * This doesn't look efficient. I decided to take the conservative
352 * approach when I did the insn conversion. Perhaps it would be
353 * better to have broken it completely, then someone would have been
354 * forced to fix it. --ds
356 for (i = 0; i < insn->n; i++) {
357 db2k_setup_sampling(dev, chan, gain);
358 /* Enable reading from the scanlist FIFO */
359 writew(DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST,
360 dev->mmio + DB2K_REG_ACQ_CONTROL);
362 ret = comedi_timeout(dev, s, insn, db2k_ai_status,
363 DB2K_ACQ_STATUS_CONFIG_PIPE_FULL);
367 writew(DB2K_ACQ_CONTROL_ADC_PACER_ENABLE,
368 dev->mmio + DB2K_REG_ACQ_CONTROL);
370 ret = comedi_timeout(dev, s, insn, db2k_ai_status,
371 DB2K_ACQ_STATUS_LOGIC_SCANNING);
376 comedi_timeout(dev, s, insn, db2k_ai_status,
377 DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA);
381 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO);
382 writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE,
383 dev->mmio + DB2K_REG_ACQ_CONTROL);
384 writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST,
385 dev->mmio + DB2K_REG_ACQ_CONTROL);
391 static int db2k_ao_eoc(struct comedi_device *dev, struct comedi_subdevice *s,
392 struct comedi_insn *insn, unsigned long context)
394 unsigned int chan = CR_CHAN(insn->chanspec);
397 status = readw(dev->mmio + DB2K_REG_DAC_STATUS);
398 if ((status & DB2K_DAC_STATUS_DAC_BUSY(chan)) == 0)
403 static int db2k_ao_insn_write(struct comedi_device *dev,
404 struct comedi_subdevice *s,
405 struct comedi_insn *insn, unsigned int *data)
407 unsigned int chan = CR_CHAN(insn->chanspec);
410 for (i = 0; i < insn->n; i++) {
411 unsigned int val = data[i];
414 writew(val, dev->mmio + DB2K_REG_DAC_SETTING(chan));
416 ret = comedi_timeout(dev, s, insn, db2k_ao_eoc, 0);
420 s->readback[chan] = val;
426 static void db2k_reset_local_bus(struct comedi_device *dev)
428 struct db2k_private *devpriv = dev->private;
431 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
432 cntrl |= PLX_CNTRL_RESET;
433 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
435 cntrl &= ~PLX_CNTRL_RESET;
436 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
440 static void db2k_reload_plx(struct comedi_device *dev)
442 struct db2k_private *devpriv = dev->private;
445 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
446 cntrl &= ~PLX_CNTRL_EERELOAD;
447 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
449 cntrl |= PLX_CNTRL_EERELOAD;
450 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
452 cntrl &= ~PLX_CNTRL_EERELOAD;
453 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
457 static void db2k_pulse_prog_pin(struct comedi_device *dev)
459 struct db2k_private *devpriv = dev->private;
462 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
463 cntrl |= PLX_CNTRL_USERO;
464 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
466 cntrl &= ~PLX_CNTRL_USERO;
467 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
468 mdelay(10); /* Not in the original code, but I like symmetry... */
471 static int db2k_wait_cpld_init(struct comedi_device *dev)
473 int result = -ETIMEDOUT;
477 /* timeout after 50 tries -> 5ms */
478 for (i = 0; i < 50; i++) {
479 cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS);
480 if (cpld & DB2K_CPLD_STATUS_INIT) {
484 usleep_range(100, 1000);
490 static int db2k_wait_cpld_txready(struct comedi_device *dev)
494 for (i = 0; i < 100; i++) {
495 if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) &
496 DB2K_CPLD_STATUS_TXREADY) {
504 static int db2k_write_cpld(struct comedi_device *dev, u16 data, bool new_cpld)
509 result = db2k_wait_cpld_txready(dev);
513 usleep_range(10, 20);
515 writew(data, dev->mmio + DB2K_REG_CPLD_WDATA);
516 if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT))
522 static int db2k_wait_fpga_programmed(struct comedi_device *dev)
524 struct db2k_private *devpriv = dev->private;
527 /* Time out after 200 tries -> 20ms */
528 for (i = 0; i < 200; i++) {
529 u32 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
530 /* General Purpose Input (USERI) set on FPGA "DONE". */
531 if (cntrl & PLX_CNTRL_USERI)
534 usleep_range(100, 1000);
539 static int db2k_load_firmware(struct comedi_device *dev, const u8 *cpld_array,
540 size_t len, unsigned long context)
542 struct db2k_private *devpriv = dev->private;
549 /* Look for FPGA start sequence in firmware. */
550 for (i = 0; i + 1 < len; i++) {
551 if (cpld_array[i] == 0xff && cpld_array[i + 1] == 0x20)
555 dev_err(dev->class_dev, "bad firmware - no start sequence\n");
558 /* Check length is even. */
560 dev_err(dev->class_dev,
561 "bad firmware - odd length (%zu = %zu - %zu)\n",
565 /* Strip firmware header. */
569 /* Check to make sure the serial eeprom is present on the board */
570 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
571 if (!(cntrl & PLX_CNTRL_EEPRESENT))
574 for (retry = 0; retry < 3; retry++) {
575 db2k_reset_local_bus(dev);
576 db2k_reload_plx(dev);
577 db2k_pulse_prog_pin(dev);
578 result = db2k_wait_cpld_init(dev);
582 new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) &
583 DB2K_CPLD_VERSION_MASK) == DB2K_CPLD_VERSION_NEW;
584 for (; i < len; i += 2) {
585 u16 data = (cpld_array[i] << 8) + cpld_array[i + 1];
587 result = db2k_write_cpld(dev, data, new_cpld);
592 result = db2k_wait_fpga_programmed(dev);
594 db2k_reset_local_bus(dev);
595 db2k_reload_plx(dev);
602 static void db2k_adc_stop_dma_transfer(struct comedi_device *dev)
606 static void db2k_adc_disarm(struct comedi_device *dev)
608 /* Disable hardware triggers */
610 writew(DB2K_TRIG_CONTROL_TYPE_ANALOG | DB2K_TRIG_CONTROL_DISABLE,
611 dev->mmio + DB2K_REG_TRIG_CONTROL);
613 writew(DB2K_TRIG_CONTROL_TYPE_TTL | DB2K_TRIG_CONTROL_DISABLE,
614 dev->mmio + DB2K_REG_TRIG_CONTROL);
616 /* Stop the scan list FIFO from loading the configuration pipe */
618 writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST,
619 dev->mmio + DB2K_REG_ACQ_CONTROL);
621 /* Stop the pacer clock */
623 writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE,
624 dev->mmio + DB2K_REG_ACQ_CONTROL);
626 /* Stop the input dma (abort channel 1) */
627 db2k_adc_stop_dma_transfer(dev);
630 static void db2k_activate_reference_dacs(struct comedi_device *dev)
635 /* Set the + reference dac value in the FPGA */
636 writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_POS_REF,
637 dev->mmio + DB2K_REG_REF_DACS);
638 for (timeout = 0; timeout < 20; timeout++) {
639 val = readw(dev->mmio + DB2K_REG_DAC_STATUS);
640 if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0)
645 /* Set the - reference dac value in the FPGA */
646 writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_NEG_REF,
647 dev->mmio + DB2K_REG_REF_DACS);
648 for (timeout = 0; timeout < 20; timeout++) {
649 val = readw(dev->mmio + DB2K_REG_DAC_STATUS);
650 if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0)
656 static void db2k_initialize_ctrs(struct comedi_device *dev)
660 static void db2k_initialize_tmrs(struct comedi_device *dev)
664 static void db2k_dac_disarm(struct comedi_device *dev)
668 static void db2k_initialize_adc(struct comedi_device *dev)
670 db2k_adc_disarm(dev);
671 db2k_activate_reference_dacs(dev);
672 db2k_initialize_ctrs(dev);
673 db2k_initialize_tmrs(dev);
676 static void db2k_initialize_dac(struct comedi_device *dev)
678 db2k_dac_disarm(dev);
681 static int db2k_8255_cb(struct comedi_device *dev, int dir, int port, int data,
682 unsigned long iobase)
685 writew(data, dev->mmio + iobase + port * 2);
688 return readw(dev->mmio + iobase + port * 2);
691 static const void *db2k_find_boardinfo(struct comedi_device *dev,
692 struct pci_dev *pcidev)
694 const struct db2k_boardtype *board;
697 if (pcidev->subsystem_vendor != PCI_VENDOR_ID_IOTECH)
700 for (i = 0; i < ARRAY_SIZE(db2k_boardtypes); i++) {
701 board = &db2k_boardtypes[i];
702 if (pcidev->subsystem_device == board->id)
708 static int db2k_auto_attach(struct comedi_device *dev,
709 unsigned long context_unused)
711 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
712 const struct db2k_boardtype *board;
713 struct db2k_private *devpriv;
714 struct comedi_subdevice *s;
717 board = db2k_find_boardinfo(dev, pcidev);
720 dev->board_ptr = board;
721 dev->board_name = board->name;
723 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
727 result = comedi_pci_enable(dev);
731 devpriv->plx = pci_ioremap_bar(pcidev, 0);
732 dev->mmio = pci_ioremap_bar(pcidev, 2);
733 if (!devpriv->plx || !dev->mmio)
736 result = comedi_alloc_subdevices(dev, 3);
740 result = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
741 DB2K_FIRMWARE, db2k_load_firmware, 0);
745 db2k_initialize_adc(dev);
746 db2k_initialize_dac(dev);
748 s = &dev->subdevices[0];
750 s->type = COMEDI_SUBD_AI;
751 s->subdev_flags = SDF_READABLE | SDF_GROUND;
754 s->insn_read = db2k_ai_insn_read;
755 s->range_table = &db2k_ai_range;
757 s = &dev->subdevices[1];
759 s->type = COMEDI_SUBD_AO;
760 s->subdev_flags = SDF_WRITABLE;
763 s->insn_write = db2k_ao_insn_write;
764 s->range_table = &range_bipolar10;
766 result = comedi_alloc_subdev_readback(s);
770 s = &dev->subdevices[2];
771 return subdev_8255_init(dev, s, db2k_8255_cb,
772 DB2K_REG_DIO_P2_EXP_IO_8_BIT);
775 static void db2k_detach(struct comedi_device *dev)
777 struct db2k_private *devpriv = dev->private;
779 if (devpriv && devpriv->plx)
780 iounmap(devpriv->plx);
781 comedi_pci_detach(dev);
784 static struct comedi_driver db2k_driver = {
785 .driver_name = "daqboard2000",
786 .module = THIS_MODULE,
787 .auto_attach = db2k_auto_attach,
788 .detach = db2k_detach,
791 static int db2k_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
793 return comedi_pci_auto_config(dev, &db2k_driver, id->driver_data);
796 static const struct pci_device_id db2k_pci_table[] = {
797 { PCI_DEVICE(PCI_VENDOR_ID_IOTECH, 0x0409) },
800 MODULE_DEVICE_TABLE(pci, db2k_pci_table);
802 static struct pci_driver db2k_pci_driver = {
803 .name = "daqboard2000",
804 .id_table = db2k_pci_table,
805 .probe = db2k_pci_probe,
806 .remove = comedi_pci_auto_unconfig,
808 module_comedi_pci_driver(db2k_driver, db2k_pci_driver);
810 MODULE_AUTHOR("Comedi http://www.comedi.org");
811 MODULE_DESCRIPTION("Comedi low-level driver");
812 MODULE_LICENSE("GPL");
813 MODULE_FIRMWARE(DB2K_FIRMWARE);