2 * comedi/drivers/adv_pci_dio.c
4 * Author: Michal Dobes <dobes@tesnet.cz>
6 * Hardware driver for Advantech PCI DIO cards.
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
22 This driver supports now only insn interface for DI/DO/DIO.
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
36 #include "../comedidev.h"
41 /* hardware types of the cards */
43 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
48 TYPE_PCI1753, TYPE_PCI1753E,
49 TYPE_PCI1754, TYPE_PCI1756,
54 /* which I/O instructions to use */
59 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
60 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
61 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
63 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
65 /* (could be more than one 8254 per
68 #define SIZE_8254 4 /* 8254 IO space length */
69 #define SIZE_8255 4 /* 8255 IO space length */
71 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
73 /* Register offset definitions */
74 /* Advantech PCI-1730/3/4 */
75 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
76 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
77 #define PCI1730_DI 2 /* R: Digital input 0-15 */
78 #define PCI1730_DO 2 /* W: Digital output 0-15 */
79 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
80 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
81 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
83 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
84 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
85 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
87 /* Advantech PCI-1735U */
88 #define PCI1735_DI 0 /* R: Digital input 0-31 */
89 #define PCI1735_DO 0 /* W: Digital output 0-31 */
90 #define PCI1735_C8254 4 /* R/W: 8254 counter */
91 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
93 /* Advantech PCI-1736UP */
94 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
95 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
96 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
97 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
99 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
100 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
101 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
103 /* Advantech PCI-1739U */
104 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
105 #define PCI1739_ICR 32 /* W: Interrupt control register */
106 #define PCI1739_ISR 32 /* R: Interrupt status register */
107 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
109 /* Advantech PCI-1750 */
110 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
111 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
112 #define PCI1750_ICR 32 /* W: Interrupt control register */
113 #define PCI1750_ISR 32 /* R: Interrupt status register */
115 /* Advantech PCI-1751/3/3E */
116 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
117 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
118 #define PCI1751_ICR 32 /* W: Interrupt control register */
119 #define PCI1751_ISR 32 /* R: Interrupt status register */
120 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
121 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
122 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
123 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
124 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
125 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
126 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
127 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
128 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
129 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
131 /* Advantech PCI-1752/4/6 */
132 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
133 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
134 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
135 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
136 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
137 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
138 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
139 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
140 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
141 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
142 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
143 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
145 /* Advantech PCI-1762 registers */
146 #define PCI1762_RO 0 /* R/W: Relays status/output */
147 #define PCI1762_IDI 2 /* R: Isolated input status */
148 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
149 #define PCI1762_ICR 6 /* W: Interrupt control register */
150 #define PCI1762_ISR 6 /* R: Interrupt status register */
152 /* Advantech PCI-1760 registers */
153 #define OMB0 0x0c /* W: Mailbox outgoing registers */
157 #define IMB0 0x1c /* R: Mailbox incoming registers */
161 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
166 /* PCI-1760 mailbox commands */
167 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
168 * DI status in IMB3 */
169 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
170 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
171 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
172 * register in OMB0, result in IMB0 */
173 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
175 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
177 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
179 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
181 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
183 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
185 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
186 * OMB0 to its reset values */
187 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
188 * interrupts based on bits in OMB0 */
189 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
190 * interrupts based on bits in OMB0 */
191 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
192 * - rising, =1 - falling) */
193 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
195 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
197 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
199 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
201 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
203 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
205 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
207 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
209 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
211 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
213 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
215 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
217 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
219 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
221 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
223 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
225 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
228 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
230 struct diosubd_data {
231 int chans; /* num of chans */
232 int addr; /* PCI address ofset */
233 int regs; /* number of registers to read or 8255
234 subdevices or 8254 chips */
235 unsigned int specflags; /* addon subdevice flags */
238 struct dio_boardtype {
239 const char *name; /* board name */
240 int main_pci_region; /* main I/O PCI region */
241 enum hw_cards_id cardtype;
243 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
244 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
245 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
246 struct diosubd_data boardid; /* card supports board ID switch */
247 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
248 enum hw_io_access io_access;
251 static const struct dio_boardtype boardtypes[] = {
254 .main_pci_region = PCIDIO_MAINREG,
255 .cardtype = TYPE_PCI1730,
257 .sdi[0] = { 16, PCI1730_DI, 2, 0, },
258 .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
259 .sdo[0] = { 16, PCI1730_DO, 2, 0, },
260 .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
261 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
266 .main_pci_region = PCIDIO_MAINREG,
267 .cardtype = TYPE_PCI1733,
269 .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
270 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
275 .main_pci_region = PCIDIO_MAINREG,
276 .cardtype = TYPE_PCI1734,
278 .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
279 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
284 .main_pci_region = PCIDIO_MAINREG,
285 .cardtype = TYPE_PCI1735,
287 .sdi[0] = { 32, PCI1735_DI, 4, 0, },
288 .sdo[0] = { 32, PCI1735_DO, 4, 0, },
289 .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
290 .s8254[0] = { 3, PCI1735_C8254, 1, 0, },
295 .main_pci_region = PCI1736_MAINREG,
296 .cardtype = TYPE_PCI1736,
298 .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
299 .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
300 .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
305 .main_pci_region = PCIDIO_MAINREG,
306 .cardtype = TYPE_PCI1739,
308 .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
313 .main_pci_region = PCIDIO_MAINREG,
314 .cardtype = TYPE_PCI1750,
316 .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
317 .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
322 .main_pci_region = PCIDIO_MAINREG,
323 .cardtype = TYPE_PCI1751,
325 .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
326 .s8254[0] = { 3, PCI1751_CNT, 1, 0, },
331 .main_pci_region = PCIDIO_MAINREG,
332 .cardtype = TYPE_PCI1752,
334 .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
335 .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
336 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
341 .main_pci_region = PCIDIO_MAINREG,
342 .cardtype = TYPE_PCI1753,
344 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
349 .main_pci_region = PCIDIO_MAINREG,
350 .cardtype = TYPE_PCI1753E,
352 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
353 .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
358 .main_pci_region = PCIDIO_MAINREG,
359 .cardtype = TYPE_PCI1754,
361 .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
362 .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
363 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
368 .main_pci_region = PCIDIO_MAINREG,
369 .cardtype = TYPE_PCI1756,
371 .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
372 .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
373 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
377 /* This card has its own 'attach' */
379 .main_pci_region = 0,
380 .cardtype = TYPE_PCI1760,
386 .main_pci_region = PCIDIO_MAINREG,
387 .cardtype = TYPE_PCI1762,
389 .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
390 .sdo[1] = { 16, PCI1762_RO, 1, 0, },
391 .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
396 struct pci_dio_private {
397 char valid; /* card is usable */
398 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
399 /* PCI-1760 specific data */
400 unsigned char IDICntEnable; /* counter's counting enable status */
401 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
403 unsigned char IDICntMatchEnable; /* counter's match interrupts
405 unsigned char IDICntEdge; /* counter's count edge value
406 * (bit=0 - rising, =1 - falling) */
407 unsigned short CntResValue[8]; /* counters' reset value */
408 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
409 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
410 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
411 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
412 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
413 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
417 ==============================================================================
419 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
420 struct comedi_subdevice *s,
421 struct comedi_insn *insn, unsigned int *data)
423 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
427 for (i = 0; i < d->regs; i++)
428 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
435 ==============================================================================
437 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
438 struct comedi_subdevice *s,
439 struct comedi_insn *insn, unsigned int *data)
441 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
445 for (i = 0; i < d->regs; i++)
446 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
451 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
452 struct comedi_subdevice *s,
453 struct comedi_insn *insn,
456 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
459 if (comedi_dio_update_state(s, data)) {
460 for (i = 0; i < d->regs; i++)
461 outb((s->state >> (8 * i)) & 0xff,
462 dev->iobase + d->addr + i);
470 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
471 struct comedi_subdevice *s,
472 struct comedi_insn *insn,
475 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
478 if (comedi_dio_update_state(s, data)) {
479 for (i = 0; i < d->regs; i++)
480 outw((s->state >> (16 * i)) & 0xffff,
481 dev->iobase + d->addr + 2 * i);
490 ==============================================================================
492 static int pci_8254_insn_read(struct comedi_device *dev,
493 struct comedi_subdevice *s,
494 struct comedi_insn *insn, unsigned int *data)
496 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
497 unsigned int chan, chip, chipchan;
500 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
501 chip = chan / 3; /* chip on subdevice */
502 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
503 spin_lock_irqsave(&s->spin_lock, flags);
504 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
506 spin_unlock_irqrestore(&s->spin_lock, flags);
511 ==============================================================================
513 static int pci_8254_insn_write(struct comedi_device *dev,
514 struct comedi_subdevice *s,
515 struct comedi_insn *insn, unsigned int *data)
517 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
518 unsigned int chan, chip, chipchan;
521 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
522 chip = chan / 3; /* chip on subdevice */
523 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
524 spin_lock_irqsave(&s->spin_lock, flags);
525 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
526 0, chipchan, data[0]);
527 spin_unlock_irqrestore(&s->spin_lock, flags);
532 ==============================================================================
534 static int pci_8254_insn_config(struct comedi_device *dev,
535 struct comedi_subdevice *s,
536 struct comedi_insn *insn, unsigned int *data)
538 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
539 unsigned int chan, chip, chipchan;
540 unsigned long iobase;
544 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
545 chip = chan / 3; /* chip on subdevice */
546 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
547 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
548 spin_lock_irqsave(&s->spin_lock, flags);
550 case INSN_CONFIG_SET_COUNTER_MODE:
551 ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
555 case INSN_CONFIG_8254_READ_STATUS:
556 data[1] = i8254_status(iobase, 0, chipchan);
562 spin_unlock_irqrestore(&s->spin_lock, flags);
563 return ret < 0 ? ret : insn->n;
567 ==============================================================================
569 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
570 unsigned char *omb, unsigned char *imb,
573 int cnt, tout, ok = 0;
575 for (cnt = 0; cnt < repeats; cnt++) {
576 outb(omb[0], dev->iobase + OMB0);
577 outb(omb[1], dev->iobase + OMB1);
578 outb(omb[2], dev->iobase + OMB2);
579 outb(omb[3], dev->iobase + OMB3);
580 for (tout = 0; tout < 251; tout++) {
581 imb[2] = inb(dev->iobase + IMB2);
582 if (imb[2] == omb[2]) {
583 imb[0] = inb(dev->iobase + IMB0);
584 imb[1] = inb(dev->iobase + IMB1);
585 imb[3] = inb(dev->iobase + IMB3);
595 comedi_error(dev, "PCI-1760 mailbox request timeout!");
599 static int pci1760_clear_imb2(struct comedi_device *dev)
601 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
602 unsigned char imb[4];
603 /* check if imb2 is already clear */
604 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
606 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
609 static int pci1760_mbxrequest(struct comedi_device *dev,
610 unsigned char *omb, unsigned char *imb)
612 if (omb[2] == CMD_ClearIMB2) {
614 "bug! this function should not be used for CMD_ClearIMB2 command");
617 if (inb(dev->iobase + IMB2) == omb[2]) {
619 retval = pci1760_clear_imb2(dev);
623 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
627 ==============================================================================
629 static int pci1760_insn_bits_di(struct comedi_device *dev,
630 struct comedi_subdevice *s,
631 struct comedi_insn *insn, unsigned int *data)
633 data[1] = inb(dev->iobase + IMB3);
638 static int pci1760_insn_bits_do(struct comedi_device *dev,
639 struct comedi_subdevice *s,
640 struct comedi_insn *insn,
644 unsigned char omb[4] = {
650 unsigned char imb[4];
652 if (comedi_dio_update_state(s, data)) {
654 ret = pci1760_mbxrequest(dev, omb, imb);
665 ==============================================================================
667 static int pci1760_insn_cnt_read(struct comedi_device *dev,
668 struct comedi_subdevice *s,
669 struct comedi_insn *insn, unsigned int *data)
672 unsigned char omb[4] = {
673 CR_CHAN(insn->chanspec) & 0x07,
675 CMD_GetIDICntCurValue,
678 unsigned char imb[4];
680 for (n = 0; n < insn->n; n++) {
681 ret = pci1760_mbxrequest(dev, omb, imb);
684 data[n] = (imb[1] << 8) + imb[0];
691 ==============================================================================
693 static int pci1760_insn_cnt_write(struct comedi_device *dev,
694 struct comedi_subdevice *s,
695 struct comedi_insn *insn, unsigned int *data)
697 struct pci_dio_private *devpriv = dev->private;
699 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
700 unsigned char bitmask = 1 << chan;
701 unsigned char omb[4] = {
703 (data[0] >> 8) & 0xff,
704 CMD_SetIDI0CntResetValue + chan,
707 unsigned char imb[4];
709 /* Set reset value if different */
710 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
711 ret = pci1760_mbxrequest(dev, omb, imb);
714 devpriv->CntResValue[chan] = data[0] & 0xffff;
717 omb[0] = bitmask; /* reset counter to it reset value */
718 omb[2] = CMD_ResetIDICounters;
719 ret = pci1760_mbxrequest(dev, omb, imb);
723 /* start counter if it don't run */
724 if (!(bitmask & devpriv->IDICntEnable)) {
726 omb[2] = CMD_EnableIDICounters;
727 ret = pci1760_mbxrequest(dev, omb, imb);
730 devpriv->IDICntEnable |= bitmask;
736 ==============================================================================
738 static int pci1760_reset(struct comedi_device *dev)
740 struct pci_dio_private *devpriv = dev->private;
742 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
743 unsigned char imb[4];
745 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
746 outb(0, dev->iobase + INTCSR1);
747 outb(0, dev->iobase + INTCSR2);
748 outb(0, dev->iobase + INTCSR3);
749 devpriv->GlobalIrqEnabled = 0;
752 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
753 pci1760_mbxrequest(dev, omb, imb);
756 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
757 pci1760_mbxrequest(dev, omb, imb);
758 devpriv->IDICntEnable = 0;
761 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
763 pci1760_mbxrequest(dev, omb, imb);
764 devpriv->IDICntOverEnable = 0;
767 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
769 pci1760_mbxrequest(dev, omb, imb);
770 devpriv->IDICntMatchEnable = 0;
774 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
775 omb[2] = CMD_SetIDI0CntMatchValue + i;
776 pci1760_mbxrequest(dev, omb, imb);
777 devpriv->CntMatchValue[i] = 0x8000;
782 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
783 omb[2] = CMD_SetIDI0CntResetValue + i;
784 pci1760_mbxrequest(dev, omb, imb);
785 devpriv->CntResValue[i] = 0x0000;
789 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
791 pci1760_mbxrequest(dev, omb, imb);
794 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
795 pci1760_mbxrequest(dev, omb, imb);
796 devpriv->IDICntEdge = 0x00;
799 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
800 pci1760_mbxrequest(dev, omb, imb);
801 devpriv->IDIFiltersEn = 0x00;
804 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
805 pci1760_mbxrequest(dev, omb, imb);
806 devpriv->IDIPatMatchEn = 0x00;
809 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
810 pci1760_mbxrequest(dev, omb, imb);
811 devpriv->IDIPatMatchValue = 0x00;
817 ==============================================================================
819 static int pci_dio_reset(struct comedi_device *dev)
821 const struct dio_boardtype *this_board = comedi_board(dev);
823 switch (this_board->cardtype) {
825 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
826 outb(0, dev->iobase + PCI1730_DO + 1);
827 outb(0, dev->iobase + PCI1730_IDO);
828 outb(0, dev->iobase + PCI1730_IDO + 1);
829 /* NO break there! */
831 /* disable interrupts */
832 outb(0, dev->iobase + PCI1730_3_INT_EN);
833 /* clear interrupts */
834 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
835 /* set rising edge trigger */
836 outb(0, dev->iobase + PCI1730_3_INT_RF);
839 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
840 outb(0, dev->iobase + PCI1734_IDO + 1);
841 outb(0, dev->iobase + PCI1734_IDO + 2);
842 outb(0, dev->iobase + PCI1734_IDO + 3);
845 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
846 outb(0, dev->iobase + PCI1735_DO + 1);
847 outb(0, dev->iobase + PCI1735_DO + 2);
848 outb(0, dev->iobase + PCI1735_DO + 3);
849 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
850 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
851 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
855 outb(0, dev->iobase + PCI1736_IDO);
856 outb(0, dev->iobase + PCI1736_IDO + 1);
857 /* disable interrupts */
858 outb(0, dev->iobase + PCI1736_3_INT_EN);
859 /* clear interrupts */
860 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
861 /* set rising edge trigger */
862 outb(0, dev->iobase + PCI1736_3_INT_RF);
866 /* disable & clear interrupts */
867 outb(0x88, dev->iobase + PCI1739_ICR);
872 /* disable & clear interrupts */
873 outb(0x88, dev->iobase + PCI1750_ICR);
876 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
878 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
879 outw(0, dev->iobase + PCI1752_IDO + 2);
880 outw(0, dev->iobase + PCI1752_IDO2);
881 outw(0, dev->iobase + PCI1752_IDO2 + 2);
884 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
886 outb(0x80, dev->iobase + PCI1753E_ICR1);
887 outb(0x80, dev->iobase + PCI1753E_ICR2);
888 outb(0x80, dev->iobase + PCI1753E_ICR3);
889 /* NO break there! */
891 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
893 outb(0x80, dev->iobase + PCI1753_ICR1);
894 outb(0x80, dev->iobase + PCI1753_ICR2);
895 outb(0x80, dev->iobase + PCI1753_ICR3);
898 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
900 outw(0x08, dev->iobase + PCI1754_6_ICR1);
901 outw(0x08, dev->iobase + PCI1754_ICR2);
902 outw(0x08, dev->iobase + PCI1754_ICR3);
905 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
907 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
909 outw(0x08, dev->iobase + PCI1754_6_ICR1);
910 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
911 outw(0, dev->iobase + PCI1756_IDO + 2);
917 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
926 ==============================================================================
928 static int pci1760_attach(struct comedi_device *dev)
930 struct comedi_subdevice *s;
932 s = &dev->subdevices[0];
933 s->type = COMEDI_SUBD_DI;
934 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
938 s->range_table = &range_digital;
939 s->insn_bits = pci1760_insn_bits_di;
941 s = &dev->subdevices[1];
942 s->type = COMEDI_SUBD_DO;
943 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
947 s->range_table = &range_digital;
949 s->insn_bits = pci1760_insn_bits_do;
951 s = &dev->subdevices[2];
952 s->type = COMEDI_SUBD_TIMER;
953 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
955 s->maxdata = 0xffffffff;
957 /* s->insn_config=pci1760_insn_pwm_cfg; */
959 s = &dev->subdevices[3];
960 s->type = COMEDI_SUBD_COUNTER;
961 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
965 s->insn_read = pci1760_insn_cnt_read;
966 s->insn_write = pci1760_insn_cnt_write;
967 /* s->insn_config=pci1760_insn_cnt_cfg; */
973 ==============================================================================
975 static int pci_dio_add_di(struct comedi_device *dev,
976 struct comedi_subdevice *s,
977 const struct diosubd_data *d)
979 const struct dio_boardtype *this_board = comedi_board(dev);
981 s->type = COMEDI_SUBD_DI;
982 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
984 s->subdev_flags |= SDF_LSAMPL;
985 s->n_chan = d->chans;
987 s->len_chanlist = d->chans;
988 s->range_table = &range_digital;
989 switch (this_board->io_access) {
991 s->insn_bits = pci_dio_insn_bits_di_b;
994 s->insn_bits = pci_dio_insn_bits_di_w;
997 s->private = (void *)d;
1003 ==============================================================================
1005 static int pci_dio_add_do(struct comedi_device *dev,
1006 struct comedi_subdevice *s,
1007 const struct diosubd_data *d)
1009 const struct dio_boardtype *this_board = comedi_board(dev);
1011 s->type = COMEDI_SUBD_DO;
1012 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1014 s->subdev_flags |= SDF_LSAMPL;
1015 s->n_chan = d->chans;
1017 s->len_chanlist = d->chans;
1018 s->range_table = &range_digital;
1020 switch (this_board->io_access) {
1022 s->insn_bits = pci_dio_insn_bits_do_b;
1025 s->insn_bits = pci_dio_insn_bits_do_w;
1028 s->private = (void *)d;
1034 ==============================================================================
1036 static int pci_dio_add_8254(struct comedi_device *dev,
1037 struct comedi_subdevice *s,
1038 const struct diosubd_data *d)
1040 s->type = COMEDI_SUBD_COUNTER;
1041 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1042 s->n_chan = d->chans;
1044 s->len_chanlist = d->chans;
1045 s->insn_read = pci_8254_insn_read;
1046 s->insn_write = pci_8254_insn_write;
1047 s->insn_config = pci_8254_insn_config;
1048 s->private = (void *)d;
1053 static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
1054 unsigned long cardtype)
1057 * Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
1058 * board available. Need to enable PCI device and request the main
1059 * registers PCI BAR temporarily to perform the test.
1061 if (cardtype != TYPE_PCI1753)
1063 if (pci_enable_device(pcidev) < 0)
1065 if (pci_request_region(pcidev, PCIDIO_MAINREG, "adv_pci_dio") == 0) {
1067 * This test is based on Advantech's "advdaq" driver source
1068 * (which declares its module licence as "GPL" although the
1069 * driver source does not include a "COPYING" file).
1072 pci_resource_start(pcidev, PCIDIO_MAINREG) + 53;
1075 if ((inb(reg) & 0x07) == 0x02) {
1077 if ((inb(reg) & 0x07) == 0x05)
1078 cardtype = TYPE_PCI1753E;
1080 pci_release_region(pcidev, PCIDIO_MAINREG);
1082 pci_disable_device(pcidev);
1086 static int pci_dio_auto_attach(struct comedi_device *dev,
1087 unsigned long context)
1089 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1090 const struct dio_boardtype *this_board = NULL;
1091 struct pci_dio_private *devpriv;
1092 struct comedi_subdevice *s;
1093 int ret, subdev, i, j;
1095 if (context < ARRAY_SIZE(boardtypes))
1096 this_board = &boardtypes[context];
1099 dev->board_ptr = this_board;
1100 dev->board_name = this_board->name;
1102 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1106 ret = comedi_pci_enable(dev);
1109 dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1111 ret = comedi_alloc_subdevices(dev, this_board->nsubdevs);
1116 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1117 if (this_board->sdi[i].chans) {
1118 s = &dev->subdevices[subdev];
1119 pci_dio_add_di(dev, s, &this_board->sdi[i]);
1123 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1124 if (this_board->sdo[i].chans) {
1125 s = &dev->subdevices[subdev];
1126 pci_dio_add_do(dev, s, &this_board->sdo[i]);
1130 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1131 for (j = 0; j < this_board->sdio[i].regs; j++) {
1132 s = &dev->subdevices[subdev];
1133 subdev_8255_init(dev, s, NULL,
1135 this_board->sdio[i].addr +
1140 if (this_board->boardid.chans) {
1141 s = &dev->subdevices[subdev];
1142 s->type = COMEDI_SUBD_DI;
1143 pci_dio_add_di(dev, s, &this_board->boardid);
1147 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1148 if (this_board->s8254[i].chans) {
1149 s = &dev->subdevices[subdev];
1150 pci_dio_add_8254(dev, s, &this_board->s8254[i]);
1154 if (this_board->cardtype == TYPE_PCI1760)
1155 pci1760_attach(dev);
1164 static void pci_dio_detach(struct comedi_device *dev)
1166 struct pci_dio_private *devpriv = dev->private;
1172 comedi_pci_disable(dev);
1175 static struct comedi_driver adv_pci_dio_driver = {
1176 .driver_name = "adv_pci_dio",
1177 .module = THIS_MODULE,
1178 .auto_attach = pci_dio_auto_attach,
1179 .detach = pci_dio_detach,
1182 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
1183 const struct pci_device_id *id)
1185 unsigned long cardtype;
1187 cardtype = pci_dio_override_cardtype(dev, id->driver_data);
1188 return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
1191 static const struct pci_device_id adv_pci_dio_pci_table[] = {
1192 { PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
1193 { PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
1194 { PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
1195 { PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
1196 { PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
1197 { PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
1198 { PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
1199 { PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
1200 { PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
1201 { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
1202 { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
1203 { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
1204 { PCI_VDEVICE(ADVANTECH, 0x1760), TYPE_PCI1760 },
1205 { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
1208 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1210 static struct pci_driver adv_pci_dio_pci_driver = {
1211 .name = "adv_pci_dio",
1212 .id_table = adv_pci_dio_pci_table,
1213 .probe = adv_pci_dio_pci_probe,
1214 .remove = comedi_pci_auto_unconfig,
1216 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1218 MODULE_AUTHOR("Comedi http://www.comedi.org");
1219 MODULE_DESCRIPTION("Comedi low-level driver");
1220 MODULE_LICENSE("GPL");