drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/mfd/syscon.h>
  35 #include <linux/regmap.h>
  36 #include <linux/sizes.h>
  37
  38 #include <linux/spi/spi.h>
  39
  40 struct ti_qspi_regs {
  41         u32 clkctrl;
  42 };
  43
  44 struct ti_qspi {
  45         struct completion       transfer_complete;
  46
  47         /* list synchronization */
  48         struct mutex            list_lock;
  49
  50         struct spi_master       *master;
  51         void __iomem            *base;
  52         void __iomem            *mmap_base;
  53         struct regmap           *ctrl_base;
  54         unsigned int            ctrl_reg;
  55         struct clk              *fclk;
  56         struct device           *dev;
  57
  58         struct ti_qspi_regs     ctx_reg;
  59
  60         dma_addr_t              mmap_phys_base;
  61         dma_addr_t              rx_bb_dma_addr;
  62         void                    *rx_bb_addr;
  63         struct dma_chan         *rx_chan;
  64
  65         u32 spi_max_frequency;
  66         u32 cmd;
  67         u32 dc;
  68
  69         bool mmap_enabled;
  70 };
  71
  72 #define QSPI_PID                        (0x0)
  73 #define QSPI_SYSCONFIG                  (0x10)
  74 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  75 #define QSPI_SPI_DC_REG                 (0x44)
  76 #define QSPI_SPI_CMD_REG                (0x48)
  77 #define QSPI_SPI_STATUS_REG             (0x4c)
  78 #define QSPI_SPI_DATA_REG               (0x50)
  79 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
  80 #define QSPI_SPI_SWITCH_REG             (0x64)
  81 #define QSPI_SPI_DATA_REG_1             (0x68)
  82 #define QSPI_SPI_DATA_REG_2             (0x6c)
  83 #define QSPI_SPI_DATA_REG_3             (0x70)
  84
  85 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  86
  87 #define QSPI_FCLK                       192000000
  88
  89 /* Clock Control */
  90 #define QSPI_CLK_EN                     (1 << 31)
  91 #define QSPI_CLK_DIV_MAX                0xffff
  92
  93 /* Command */
  94 #define QSPI_EN_CS(n)                   (n << 28)
  95 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  96 #define QSPI_3_PIN                      (1 << 18)
  97 #define QSPI_RD_SNGL                    (1 << 16)
  98 #define QSPI_WR_SNGL                    (2 << 16)
  99 #define QSPI_RD_DUAL                    (3 << 16)
 100 #define QSPI_RD_QUAD                    (7 << 16)
 101 #define QSPI_INVAL                      (4 << 16)
 102 #define QSPI_FLEN(n)                    ((n - 1) << 0)
 103 #define QSPI_WLEN_MAX_BITS              128
 104 #define QSPI_WLEN_MAX_BYTES             16
 105 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
 106
 107 /* STATUS REGISTER */
 108 #define BUSY                            0x01
 109 #define WC                              0x02
 110
 111 /* Device Control */
 112 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 113 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 114 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 115 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 116
 117 #define QSPI_FRAME                      4096
 118
 119 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 120
 121 #define MEM_CS_EN(n)                    ((n + 1) << 8)
 122 #define MEM_CS_MASK                     (7 << 8)
 123
 124 #define MM_SWITCH                       0x1
 125
 126 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
 127 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
 128 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
 129 #define QSPI_SETUP_ADDR_SHIFT           8
 130 #define QSPI_SETUP_DUMMY_SHIFT          10
 131
 132 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
 133
 134 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 135                 unsigned long reg)
 136 {
 137         return readl(qspi->base + reg);
 138 }
 139
 140 static inline void ti_qspi_write(struct ti_qspi *qspi,
 141                 unsigned long val, unsigned long reg)
 142 {
 143         writel(val, qspi->base + reg);
 144 }
 145
 146 static int ti_qspi_setup(struct spi_device *spi)
 147 {
 148         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 149         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 150         int clk_div = 0, ret;
 151         u32 clk_ctrl_reg, clk_rate, clk_mask;
 152
 153         if (spi->master->busy) {
 154                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
 155                 return -EBUSY;
 156         }
 157
 158         if (!qspi->spi_max_frequency) {
 159                 dev_err(qspi->dev, "spi max frequency not defined\n");
 160                 return -EINVAL;
 161         }
 162
 163         clk_rate = clk_get_rate(qspi->fclk);
 164
 165         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 166
 167         if (clk_div < 0) {
 168                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 169                 return -EINVAL;
 170         }
 171
 172         if (clk_div > QSPI_CLK_DIV_MAX) {
 173                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 174                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 175                 return -EINVAL;
 176         }
 177
 178         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 179                         qspi->spi_max_frequency, clk_div);
 180
 181         ret = pm_runtime_get_sync(qspi->dev);
 182         if (ret < 0) {
 183                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 184                 return ret;
 185         }
 186
 187         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 188
 189         clk_ctrl_reg &= ~QSPI_CLK_EN;
 190
 191         /* disable SCLK */
 192         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 193
 194         /* enable SCLK */
 195         clk_mask = QSPI_CLK_EN | clk_div;
 196         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 197         ctx_reg->clkctrl = clk_mask;
 198
 199         pm_runtime_mark_last_busy(qspi->dev);
 200         ret = pm_runtime_put_autosuspend(qspi->dev);
 201         if (ret < 0) {
 202                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 203                 return ret;
 204         }
 205
 206         return 0;
 207 }
 208
 209 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 210 {
 211         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 212
 213         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 214 }
 215
 216 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 217 {
 218         u32 stat;
 219         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 220
 221         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 222         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 223                 cpu_relax();
 224                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 225         }
 226
 227         WARN(stat & BUSY, "qspi busy\n");
 228         return stat & BUSY;
 229 }
 230
 231 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 232 {
 233         u32 stat;
 234         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 235
 236         do {
 237                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 238                 if (stat & WC)
 239                         return 0;
 240                 cpu_relax();
 241         } while (time_after(timeout, jiffies));
 242
 243         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 244         if (stat & WC)
 245                 return 0;
 246         return  -ETIMEDOUT;
 247 }
 248
 249 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 250                           int count)
 251 {
 252         int wlen, xfer_len;
 253         unsigned int cmd;
 254         const u8 *txbuf;
 255         u32 data;
 256
 257         txbuf = t->tx_buf;
 258         cmd = qspi->cmd | QSPI_WR_SNGL;
 259         wlen = t->bits_per_word >> 3;   /* in bytes */
 260         xfer_len = wlen;
 261
 262         while (count) {
 263                 if (qspi_is_busy(qspi))
 264                         return -EBUSY;
 265
 266                 switch (wlen) {
 267                 case 1:
 268                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 269                                         cmd, qspi->dc, *txbuf);
 270                         if (count >= QSPI_WLEN_MAX_BYTES) {
 271                                 u32 *txp = (u32 *)txbuf;
 272
 273                                 data = cpu_to_be32(*txp++);
 274                                 writel(data, qspi->base +
 275                                        QSPI_SPI_DATA_REG_3);
 276                                 data = cpu_to_be32(*txp++);
 277                                 writel(data, qspi->base +
 278                                        QSPI_SPI_DATA_REG_2);
 279                                 data = cpu_to_be32(*txp++);
 280                                 writel(data, qspi->base +
 281                                        QSPI_SPI_DATA_REG_1);
 282                                 data = cpu_to_be32(*txp++);
 283                                 writel(data, qspi->base +
 284                                        QSPI_SPI_DATA_REG);
 285                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 286                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 287                         } else {
 288                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 289                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 290                                 xfer_len = wlen;
 291                                 cmd |= QSPI_WLEN(wlen);
 292                         }
 293                         break;
 294                 case 2:
 295                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 296                                         cmd, qspi->dc, *txbuf);
 297                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 298                         break;
 299                 case 4:
 300                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 301                                         cmd, qspi->dc, *txbuf);
 302                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 303                         break;
 304                 }
 305
 306                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 307                 if (ti_qspi_poll_wc(qspi)) {
 308                         dev_err(qspi->dev, "write timed out\n");
 309                         return -ETIMEDOUT;
 310                 }
 311                 txbuf += xfer_len;
 312                 count -= xfer_len;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 319                          int count)
 320 {
 321         int wlen;
 322         unsigned int cmd;
 323         u8 *rxbuf;
 324
 325         rxbuf = t->rx_buf;
 326         cmd = qspi->cmd;
 327         switch (t->rx_nbits) {
 328         case SPI_NBITS_DUAL:
 329                 cmd |= QSPI_RD_DUAL;
 330                 break;
 331         case SPI_NBITS_QUAD:
 332                 cmd |= QSPI_RD_QUAD;
 333                 break;
 334         default:
 335                 cmd |= QSPI_RD_SNGL;
 336                 break;
 337         }
 338         wlen = t->bits_per_word >> 3;   /* in bytes */
 339
 340         while (count) {
 341                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 342                 if (qspi_is_busy(qspi))
 343                         return -EBUSY;
 344
 345                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 346                 if (ti_qspi_poll_wc(qspi)) {
 347                         dev_err(qspi->dev, "read timed out\n");
 348                         return -ETIMEDOUT;
 349                 }
 350                 switch (wlen) {
 351                 case 1:
 352                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 353                         break;
 354                 case 2:
 355                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 356                         break;
 357                 case 4:
 358                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 359                         break;
 360                 }
 361                 rxbuf += wlen;
 362                 count -= wlen;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 369                              int count)
 370 {
 371         int ret;
 372
 373         if (t->tx_buf) {
 374                 ret = qspi_write_msg(qspi, t, count);
 375                 if (ret) {
 376                         dev_dbg(qspi->dev, "Error while writing\n");
 377                         return ret;
 378                 }
 379         }
 380
 381         if (t->rx_buf) {
 382                 ret = qspi_read_msg(qspi, t, count);
 383                 if (ret) {
 384                         dev_dbg(qspi->dev, "Error while reading\n");
 385                         return ret;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 static void ti_qspi_dma_callback(void *param)
 393 {
 394         struct ti_qspi *qspi = param;
 395
 396         complete(&qspi->transfer_complete);
 397 }
 398
 399 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
 400                             dma_addr_t dma_src, size_t len)
 401 {
 402         struct dma_chan *chan = qspi->rx_chan;
 403         dma_cookie_t cookie;
 404         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 405         struct dma_async_tx_descriptor *tx;
 406         int ret;
 407
 408         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
 409         if (!tx) {
 410                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
 411                 return -EIO;
 412         }
 413
 414         tx->callback = ti_qspi_dma_callback;
 415         tx->callback_param = qspi;
 416         cookie = tx->tx_submit(tx);
 417         reinit_completion(&qspi->transfer_complete);
 418
 419         ret = dma_submit_error(cookie);
 420         if (ret) {
 421                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
 422                 return -EIO;
 423         }
 424
 425         dma_async_issue_pending(chan);
 426         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 427                                           msecs_to_jiffies(len));
 428         if (ret <= 0) {
 429                 dmaengine_terminate_sync(chan);
 430                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
 431                 return -ETIMEDOUT;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi,
 438                                      struct spi_flash_read_message *msg)
 439 {
 440         size_t readsize = msg->len;
 441         void *to = msg->buf;
 442         dma_addr_t dma_src = qspi->mmap_phys_base + msg->from;
 443         int ret = 0;
 444
 445         /*
 446          * Use bounce buffer as FS like jffs2, ubifs may pass
 447          * buffers that does not belong to kernel lowmem region.
 448          */
 449         while (readsize != 0) {
 450                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
 451                                         readsize);
 452
 453                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
 454                                        dma_src, xfer_len);
 455                 if (ret != 0)
 456                         return ret;
 457                 memcpy(to, qspi->rx_bb_addr, xfer_len);
 458                 readsize -= xfer_len;
 459                 dma_src += xfer_len;
 460                 to += xfer_len;
 461         }
 462
 463         return ret;
 464 }
 465
 466 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
 467                                loff_t from)
 468 {
 469         struct scatterlist *sg;
 470         dma_addr_t dma_src = qspi->mmap_phys_base + from;
 471         dma_addr_t dma_dst;
 472         int i, len, ret;
 473
 474         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
 475                 dma_dst = sg_dma_address(sg);
 476                 len = sg_dma_len(sg);
 477                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
 478                 if (ret)
 479                         return ret;
 480                 dma_src += len;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static void ti_qspi_enable_memory_map(struct spi_device *spi)
 487 {
 488         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 489
 490         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 491         if (qspi->ctrl_base) {
 492                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 493                                    MEM_CS_EN(spi->chip_select),
 494                                    MEM_CS_MASK);
 495         }
 496         qspi->mmap_enabled = true;
 497 }
 498
 499 static void ti_qspi_disable_memory_map(struct spi_device *spi)
 500 {
 501         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 502
 503         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 504         if (qspi->ctrl_base)
 505                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 506                                    0, MEM_CS_MASK);
 507         qspi->mmap_enabled = false;
 508 }
 509
 510 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
 511                                     struct spi_flash_read_message *msg)
 512 {
 513         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 514         u32 memval = msg->read_opcode;
 515
 516         switch (msg->data_nbits) {
 517         case SPI_NBITS_QUAD:
 518                 memval |= QSPI_SETUP_RD_QUAD;
 519                 break;
 520         case SPI_NBITS_DUAL:
 521                 memval |= QSPI_SETUP_RD_DUAL;
 522                 break;
 523         default:
 524                 memval |= QSPI_SETUP_RD_NORMAL;
 525                 break;
 526         }
 527         memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
 528                    msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
 529         ti_qspi_write(qspi, memval,
 530                       QSPI_SPI_SETUP_REG(spi->chip_select));
 531 }
 532
 533 static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi,
 534                                       struct spi_flash_read_message *msg)
 535 {
 536         return virt_addr_valid(msg->buf);
 537 }
 538
 539 static int ti_qspi_spi_flash_read(struct spi_device *spi,
 540                                   struct spi_flash_read_message *msg)
 541 {
 542         struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
 543         int ret = 0;
 544
 545         mutex_lock(&qspi->list_lock);
 546
 547         if (!qspi->mmap_enabled)
 548                 ti_qspi_enable_memory_map(spi);
 549         ti_qspi_setup_mmap_read(spi, msg);
 550
 551         if (qspi->rx_chan) {
 552                 if (msg->cur_msg_mapped)
 553                         ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
 554                 else
 555                         ret = ti_qspi_dma_bounce_buffer(qspi, msg);
 556                 if (ret)
 557                         goto err_unlock;
 558         } else {
 559                 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
 560         }
 561         msg->retlen = msg->len;
 562
 563 err_unlock:
 564         mutex_unlock(&qspi->list_lock);
 565
 566         return ret;
 567 }
 568
 569 static int ti_qspi_start_transfer_one(struct spi_master *master,
 570                 struct spi_message *m)
 571 {
 572         struct ti_qspi *qspi = spi_master_get_devdata(master);
 573         struct spi_device *spi = m->spi;
 574         struct spi_transfer *t;
 575         int status = 0, ret;
 576         unsigned int frame_len_words, transfer_len_words;
 577         int wlen;
 578
 579         /* setup device control reg */
 580         qspi->dc = 0;
 581
 582         if (spi->mode & SPI_CPHA)
 583                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 584         if (spi->mode & SPI_CPOL)
 585                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 586         if (spi->mode & SPI_CS_HIGH)
 587                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 588
 589         frame_len_words = 0;
 590         list_for_each_entry(t, &m->transfers, transfer_list)
 591                 frame_len_words += t->len / (t->bits_per_word >> 3);
 592         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 593
 594         /* setup command reg */
 595         qspi->cmd = 0;
 596         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 597         qspi->cmd |= QSPI_FLEN(frame_len_words);
 598
 599         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 600
 601         mutex_lock(&qspi->list_lock);
 602
 603         if (qspi->mmap_enabled)
 604                 ti_qspi_disable_memory_map(spi);
 605
 606         list_for_each_entry(t, &m->transfers, transfer_list) {
 607                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 608                              QSPI_WLEN(t->bits_per_word));
 609
 610                 wlen = t->bits_per_word >> 3;
 611                 transfer_len_words = min(t->len / wlen, frame_len_words);
 612
 613                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 614                 if (ret) {
 615                         dev_dbg(qspi->dev, "transfer message failed\n");
 616                         mutex_unlock(&qspi->list_lock);
 617                         return -EINVAL;
 618                 }
 619
 620                 m->actual_length += transfer_len_words * wlen;
 621                 frame_len_words -= transfer_len_words;
 622                 if (frame_len_words == 0)
 623                         break;
 624         }
 625
 626         mutex_unlock(&qspi->list_lock);
 627
 628         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 629         m->status = status;
 630         spi_finalize_current_message(master);
 631
 632         return status;
 633 }
 634
 635 static int ti_qspi_runtime_resume(struct device *dev)
 636 {
 637         struct ti_qspi      *qspi;
 638
 639         qspi = dev_get_drvdata(dev);
 640         ti_qspi_restore_ctx(qspi);
 641
 642         return 0;
 643 }
 644
 645 static const struct of_device_id ti_qspi_match[] = {
 646         {.compatible = "ti,dra7xxx-qspi" },
 647         {.compatible = "ti,am4372-qspi" },
 648         {},
 649 };
 650 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 651
 652 static int ti_qspi_probe(struct platform_device *pdev)
 653 {
 654         struct  ti_qspi *qspi;
 655         struct spi_master *master;
 656         struct resource         *r, *res_mmap;
 657         struct device_node *np = pdev->dev.of_node;
 658         u32 max_freq;
 659         int ret = 0, num_cs, irq;
 660         dma_cap_mask_t mask;
 661
 662         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 663         if (!master)
 664                 return -ENOMEM;
 665
 666         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 667
 668         master->flags = SPI_MASTER_HALF_DUPLEX;
 669         master->setup = ti_qspi_setup;
 670         master->auto_runtime_pm = true;
 671         master->transfer_one_message = ti_qspi_start_transfer_one;
 672         master->dev.of_node = pdev->dev.of_node;
 673         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 674                                      SPI_BPW_MASK(8);
 675         master->spi_flash_read = ti_qspi_spi_flash_read;
 676
 677         if (!of_property_read_u32(np, "num-cs", &num_cs))
 678                 master->num_chipselect = num_cs;
 679
 680         qspi = spi_master_get_devdata(master);
 681         qspi->master = master;
 682         qspi->dev = &pdev->dev;
 683         platform_set_drvdata(pdev, qspi);
 684
 685         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 686         if (r == NULL) {
 687                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 688                 if (r == NULL) {
 689                         dev_err(&pdev->dev, "missing platform data\n");
 690                         ret = -ENODEV;
 691                         goto free_master;
 692                 }
 693         }
 694
 695         res_mmap = platform_get_resource_byname(pdev,
 696                         IORESOURCE_MEM, "qspi_mmap");
 697         if (res_mmap == NULL) {
 698                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 699                 if (res_mmap == NULL) {
 700                         dev_err(&pdev->dev,
 701                                 "memory mapped resource not required\n");
 702                 }
 703         }
 704
 705         irq = platform_get_irq(pdev, 0);
 706         if (irq < 0) {
 707                 dev_err(&pdev->dev, "no irq resource?\n");
 708                 ret = irq;
 709                 goto free_master;
 710         }
 711
 712         mutex_init(&qspi->list_lock);
 713
 714         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 715         if (IS_ERR(qspi->base)) {
 716                 ret = PTR_ERR(qspi->base);
 717                 goto free_master;
 718         }
 719
 720
 721         if (of_property_read_bool(np, "syscon-chipselects")) {
 722                 qspi->ctrl_base =
 723                 syscon_regmap_lookup_by_phandle(np,
 724                                                 "syscon-chipselects");
 725                 if (IS_ERR(qspi->ctrl_base)) {
 726                         ret = PTR_ERR(qspi->ctrl_base);
 727                         goto free_master;
 728                 }
 729                 ret = of_property_read_u32_index(np,
 730                                                  "syscon-chipselects",
 731                                                  1, &qspi->ctrl_reg);
 732                 if (ret) {
 733                         dev_err(&pdev->dev,
 734                                 "couldn't get ctrl_mod reg index\n");
 735                         goto free_master;
 736                 }
 737         }
 738
 739         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 740         if (IS_ERR(qspi->fclk)) {
 741                 ret = PTR_ERR(qspi->fclk);
 742                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 743         }
 744
 745         pm_runtime_use_autosuspend(&pdev->dev);
 746         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 747         pm_runtime_enable(&pdev->dev);
 748
 749         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 750                 qspi->spi_max_frequency = max_freq;
 751
 752         dma_cap_zero(mask);
 753         dma_cap_set(DMA_MEMCPY, mask);
 754
 755         qspi->rx_chan = dma_request_chan_by_mask(&mask);
 756         if (IS_ERR(qspi->rx_chan)) {
 757                 dev_err(qspi->dev,
 758                         "No Rx DMA available, trying mmap mode\n");
 759                 qspi->rx_chan = NULL;
 760                 ret = 0;
 761                 goto no_dma;
 762         }
 763         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
 764                                               QSPI_DMA_BUFFER_SIZE,
 765                                               &qspi->rx_bb_dma_addr,
 766                                               GFP_KERNEL | GFP_DMA);
 767         if (!qspi->rx_bb_addr) {
 768                 dev_err(qspi->dev,
 769                         "dma_alloc_coherent failed, using PIO mode\n");
 770                 dma_release_channel(qspi->rx_chan);
 771                 goto no_dma;
 772         }
 773         master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma;
 774         master->dma_rx = qspi->rx_chan;
 775         init_completion(&qspi->transfer_complete);
 776         if (res_mmap)
 777                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
 778
 779 no_dma:
 780         if (!qspi->rx_chan && res_mmap) {
 781                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 782                 if (IS_ERR(qspi->mmap_base)) {
 783                         dev_info(&pdev->dev,
 784                                  "mmap failed with error %ld using PIO mode\n",
 785                                  PTR_ERR(qspi->mmap_base));
 786                         qspi->mmap_base = NULL;
 787                         master->spi_flash_read = NULL;
 788                 }
 789         }
 790         qspi->mmap_enabled = false;
 791
 792         ret = devm_spi_register_master(&pdev->dev, master);
 793         if (!ret)
 794                 return 0;
 795
 796         pm_runtime_disable(&pdev->dev);
 797 free_master:
 798         spi_master_put(master);
 799         return ret;
 800 }
 801
 802 static int ti_qspi_remove(struct platform_device *pdev)
 803 {
 804         struct ti_qspi *qspi = platform_get_drvdata(pdev);
 805         int rc;
 806
 807         rc = spi_master_suspend(qspi->master);
 808         if (rc)
 809                 return rc;
 810
 811         pm_runtime_put_sync(&pdev->dev);
 812         pm_runtime_disable(&pdev->dev);
 813
 814         if (qspi->rx_bb_addr)
 815                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
 816                                   qspi->rx_bb_addr,
 817                                   qspi->rx_bb_dma_addr);
 818         if (qspi->rx_chan)
 819                 dma_release_channel(qspi->rx_chan);
 820
 821         return 0;
 822 }
 823
 824 static const struct dev_pm_ops ti_qspi_pm_ops = {
 825         .runtime_resume = ti_qspi_runtime_resume,
 826 };
 827
 828 static struct platform_driver ti_qspi_driver = {
 829         .probe  = ti_qspi_probe,
 830         .remove = ti_qspi_remove,
 831         .driver = {
 832                 .name   = "ti-qspi",
 833                 .pm =   &ti_qspi_pm_ops,
 834                 .of_match_table = ti_qspi_match,
 835         }
 836 };
 837
 838 module_platform_driver(ti_qspi_driver);
 839
 840 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 841 MODULE_LICENSE("GPL v2");
 842 MODULE_DESCRIPTION("TI QSPI controller driver");
 843 MODULE_ALIAS("platform:ti-qspi");