drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of.h>
  32 #include <linux/of_gpio.h>
  33
  34 #include <mach/dma.h>
  35 #include <plat/s3c64xx-spi.h>
  36
  37 #define MAX_SPI_PORTS           3
  38
  39 /* Registers and bit-fields */
  40
  41 #define S3C64XX_SPI_CH_CFG              0x00
  42 #define S3C64XX_SPI_CLK_CFG             0x04
  43 #define S3C64XX_SPI_MODE_CFG    0x08
  44 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  45 #define S3C64XX_SPI_INT_EN              0x10
  46 #define S3C64XX_SPI_STATUS              0x14
  47 #define S3C64XX_SPI_TX_DATA             0x18
  48 #define S3C64XX_SPI_RX_DATA             0x1C
  49 #define S3C64XX_SPI_PACKET_CNT  0x20
  50 #define S3C64XX_SPI_PENDING_CLR 0x24
  51 #define S3C64XX_SPI_SWAP_CFG    0x28
  52 #define S3C64XX_SPI_FB_CLK              0x2C
  53
  54 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  55 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  56 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  57 #define S3C64XX_SPI_CPOL_L              (1<<3)
  58 #define S3C64XX_SPI_CPHA_B              (1<<2)
  59 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  60 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  61
  62 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  63 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  64 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  65 #define S3C64XX_SPI_PSR_MASK            0xff
  66
  67 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  69 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  70 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  73 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  74 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  75 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  76 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  77 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  78
  79 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  80 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  81
  82 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  83
  84 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
  85                                         (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  86
  87 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  88 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  89 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  90 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  91 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  92 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  93 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  94
  95 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  96 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  97 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  98 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  99 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 100 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 101
 102 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 103
 104 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 105 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 106 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 107 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 108 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 109
 110 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 111 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 112 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 113 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 114 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 115 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 116 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 117 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 118
 119 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 120
 121 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 122 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 123                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 124 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 125 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 126                                         FIFO_LVL_MASK(i))
 127
 128 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 129 #define S3C64XX_SPI_TRAILCNT_OFF        19
 130
 131 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 132
 133 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 134
 135 #define RXBUSY    (1<<2)
 136 #define TXBUSY    (1<<3)
 137
 138 struct s3c64xx_spi_dma_data {
 139         unsigned                ch;
 140         enum dma_data_direction direction;
 141         enum dma_ch     dmach;
 142         struct property         *dma_prop;
 143 };
 144
 145 /**
 146  * struct s3c64xx_spi_info - SPI Controller hardware info
 147  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 148  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 149  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 150  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 151  * @clk_from_cmu: True, if the controller does not include a clock mux and
 152  *      prescaler unit.
 153  *
 154  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 155  * differ in some aspects such as the size of the fifo and spi bus clock
 156  * setup. Such differences are specified to the driver using this structure
 157  * which is provided as driver data to the driver.
 158  */
 159 struct s3c64xx_spi_port_config {
 160         int     fifo_lvl_mask[MAX_SPI_PORTS];
 161         int     rx_lvl_offset;
 162         int     tx_st_done;
 163         bool    high_speed;
 164         bool    clk_from_cmu;
 165 };
 166
 167 /**
 168  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 169  * @clk: Pointer to the spi clock.
 170  * @src_clk: Pointer to the clock used to generate SPI signals.
 171  * @master: Pointer to the SPI Protocol master.
 172  * @cntrlr_info: Platform specific data for the controller this driver manages.
 173  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 174  * @queue: To log SPI xfer requests.
 175  * @lock: Controller specific lock.
 176  * @state: Set of FLAGS to indicate status.
 177  * @rx_dmach: Controller's DMA channel for Rx.
 178  * @tx_dmach: Controller's DMA channel for Tx.
 179  * @sfr_start: BUS address of SPI controller regs.
 180  * @regs: Pointer to ioremap'ed controller registers.
 181  * @irq: interrupt
 182  * @xfer_completion: To indicate completion of xfer task.
 183  * @cur_mode: Stores the active configuration of the controller.
 184  * @cur_bpw: Stores the active bits per word settings.
 185  * @cur_speed: Stores the active xfer clock speed.
 186  */
 187 struct s3c64xx_spi_driver_data {
 188         void __iomem                    *regs;
 189         struct clk                      *clk;
 190         struct clk                      *src_clk;
 191         struct platform_device          *pdev;
 192         struct spi_master               *master;
 193         struct s3c64xx_spi_info  *cntrlr_info;
 194         struct spi_device               *tgl_spi;
 195         struct list_head                queue;
 196         spinlock_t                      lock;
 197         unsigned long                   sfr_start;
 198         struct completion               xfer_completion;
 199         unsigned                        state;
 200         unsigned                        cur_mode, cur_bpw;
 201         unsigned                        cur_speed;
 202         struct s3c64xx_spi_dma_data     rx_dma;
 203         struct s3c64xx_spi_dma_data     tx_dma;
 204         struct samsung_dma_ops          *ops;
 205         struct s3c64xx_spi_port_config  *port_conf;
 206         unsigned int                    port_id;
 207         unsigned long                   gpios[4];
 208 };
 209
 210 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 211         .name = "samsung-spi-dma",
 212 };
 213
 214 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 215 {
 216         void __iomem *regs = sdd->regs;
 217         unsigned long loops;
 218         u32 val;
 219
 220         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 221
 222         val = readl(regs + S3C64XX_SPI_CH_CFG);
 223         val |= S3C64XX_SPI_CH_SW_RST;
 224         val &= ~S3C64XX_SPI_CH_HS_EN;
 225         writel(val, regs + S3C64XX_SPI_CH_CFG);
 226
 227         /* Flush TxFIFO*/
 228         loops = msecs_to_loops(1);
 229         do {
 230                 val = readl(regs + S3C64XX_SPI_STATUS);
 231         } while (TX_FIFO_LVL(val, sdd) && loops--);
 232
 233         if (loops == 0)
 234                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 235
 236         /* Flush RxFIFO*/
 237         loops = msecs_to_loops(1);
 238         do {
 239                 val = readl(regs + S3C64XX_SPI_STATUS);
 240                 if (RX_FIFO_LVL(val, sdd))
 241                         readl(regs + S3C64XX_SPI_RX_DATA);
 242                 else
 243                         break;
 244         } while (loops--);
 245
 246         if (loops == 0)
 247                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 248
 249         val = readl(regs + S3C64XX_SPI_CH_CFG);
 250         val &= ~S3C64XX_SPI_CH_SW_RST;
 251         writel(val, regs + S3C64XX_SPI_CH_CFG);
 252
 253         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 254         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 255         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 256
 257         val = readl(regs + S3C64XX_SPI_CH_CFG);
 258         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 259         writel(val, regs + S3C64XX_SPI_CH_CFG);
 260 }
 261
 262 static void s3c64xx_spi_dmacb(void *data)
 263 {
 264         struct s3c64xx_spi_driver_data *sdd;
 265         struct s3c64xx_spi_dma_data *dma = data;
 266         unsigned long flags;
 267
 268         if (dma->direction == DMA_DEV_TO_MEM)
 269                 sdd = container_of(data,
 270                         struct s3c64xx_spi_driver_data, rx_dma);
 271         else
 272                 sdd = container_of(data,
 273                         struct s3c64xx_spi_driver_data, tx_dma);
 274
 275         spin_lock_irqsave(&sdd->lock, flags);
 276
 277         if (dma->direction == DMA_DEV_TO_MEM) {
 278                 sdd->state &= ~RXBUSY;
 279                 if (!(sdd->state & TXBUSY))
 280                         complete(&sdd->xfer_completion);
 281         } else {
 282                 sdd->state &= ~TXBUSY;
 283                 if (!(sdd->state & RXBUSY))
 284                         complete(&sdd->xfer_completion);
 285         }
 286
 287         spin_unlock_irqrestore(&sdd->lock, flags);
 288 }
 289
 290 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 291                                         unsigned len, dma_addr_t buf)
 292 {
 293         struct s3c64xx_spi_driver_data *sdd;
 294         struct samsung_dma_prep info;
 295         struct samsung_dma_config config;
 296
 297         if (dma->direction == DMA_DEV_TO_MEM) {
 298                 sdd = container_of((void *)dma,
 299                         struct s3c64xx_spi_driver_data, rx_dma);
 300                 config.direction = sdd->rx_dma.direction;
 301                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 302                 config.width = sdd->cur_bpw / 8;
 303                 sdd->ops->config(sdd->rx_dma.ch, &config);
 304         } else {
 305                 sdd = container_of((void *)dma,
 306                         struct s3c64xx_spi_driver_data, tx_dma);
 307                 config.direction =  sdd->tx_dma.direction;
 308                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 309                 config.width = sdd->cur_bpw / 8;
 310                 sdd->ops->config(sdd->tx_dma.ch, &config);
 311         }
 312
 313         info.cap = DMA_SLAVE;
 314         info.len = len;
 315         info.fp = s3c64xx_spi_dmacb;
 316         info.fp_param = dma;
 317         info.direction = dma->direction;
 318         info.buf = buf;
 319
 320         sdd->ops->prepare(dma->ch, &info);
 321         sdd->ops->trigger(dma->ch);
 322 }
 323
 324 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 325 {
 326         struct samsung_dma_req req;
 327
 328         sdd->ops = samsung_dma_get_ops();
 329
 330         req.cap = DMA_SLAVE;
 331         req.client = &s3c64xx_spi_dma_client;
 332
 333         req.dt_dmach_prop = sdd->rx_dma.dma_prop;
 334         sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req);
 335         req.dt_dmach_prop = sdd->tx_dma.dma_prop;
 336         sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req);
 337
 338         return 1;
 339 }
 340
 341 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 342                                 struct spi_device *spi,
 343                                 struct spi_transfer *xfer, int dma_mode)
 344 {
 345         void __iomem *regs = sdd->regs;
 346         u32 modecfg, chcfg;
 347
 348         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 349         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 350
 351         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 352         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 353
 354         if (dma_mode) {
 355                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 356         } else {
 357                 /* Always shift in data in FIFO, even if xfer is Tx only,
 358                  * this helps setting PCKT_CNT value for generating clocks
 359                  * as exactly needed.
 360                  */
 361                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 362                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 363                                         | S3C64XX_SPI_PACKET_CNT_EN,
 364                                         regs + S3C64XX_SPI_PACKET_CNT);
 365         }
 366
 367         if (xfer->tx_buf != NULL) {
 368                 sdd->state |= TXBUSY;
 369                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 370                 if (dma_mode) {
 371                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 372                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 373                 } else {
 374                         switch (sdd->cur_bpw) {
 375                         case 32:
 376                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 377                                         xfer->tx_buf, xfer->len / 4);
 378                                 break;
 379                         case 16:
 380                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 381                                         xfer->tx_buf, xfer->len / 2);
 382                                 break;
 383                         default:
 384                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 385                                         xfer->tx_buf, xfer->len);
 386                                 break;
 387                         }
 388                 }
 389         }
 390
 391         if (xfer->rx_buf != NULL) {
 392                 sdd->state |= RXBUSY;
 393
 394                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 395                                         && !(sdd->cur_mode & SPI_CPHA))
 396                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 397
 398                 if (dma_mode) {
 399                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 400                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 401                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 402                                         | S3C64XX_SPI_PACKET_CNT_EN,
 403                                         regs + S3C64XX_SPI_PACKET_CNT);
 404                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 405                 }
 406         }
 407
 408         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 409         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 410 }
 411
 412 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 413                                                 struct spi_device *spi)
 414 {
 415         struct s3c64xx_spi_csinfo *cs;
 416
 417         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 418                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 419                         /* Deselect the last toggled device */
 420                         cs = sdd->tgl_spi->controller_data;
 421                         gpio_set_value(cs->line,
 422                                 spi->mode & SPI_CS_HIGH ? 0 : 1);
 423                 }
 424                 sdd->tgl_spi = NULL;
 425         }
 426
 427         cs = spi->controller_data;
 428         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 429 }
 430
 431 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 432                                 struct spi_transfer *xfer, int dma_mode)
 433 {
 434         void __iomem *regs = sdd->regs;
 435         unsigned long val;
 436         int ms;
 437
 438         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 439         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 440         ms += 10; /* some tolerance */
 441
 442         if (dma_mode) {
 443                 val = msecs_to_jiffies(ms) + 10;
 444                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 445         } else {
 446                 u32 status;
 447                 val = msecs_to_loops(ms);
 448                 do {
 449                         status = readl(regs + S3C64XX_SPI_STATUS);
 450                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 451         }
 452
 453         if (!val)
 454                 return -EIO;
 455
 456         if (dma_mode) {
 457                 u32 status;
 458
 459                 /*
 460                  * DmaTx returns after simply writing data in the FIFO,
 461                  * w/o waiting for real transmission on the bus to finish.
 462                  * DmaRx returns only after Dma read data from FIFO which
 463                  * needs bus transmission to finish, so we don't worry if
 464                  * Xfer involved Rx(with or without Tx).
 465                  */
 466                 if (xfer->rx_buf == NULL) {
 467                         val = msecs_to_loops(10);
 468                         status = readl(regs + S3C64XX_SPI_STATUS);
 469                         while ((TX_FIFO_LVL(status, sdd)
 470                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 471                                         && --val) {
 472                                 cpu_relax();
 473                                 status = readl(regs + S3C64XX_SPI_STATUS);
 474                         }
 475
 476                         if (!val)
 477                                 return -EIO;
 478                 }
 479         } else {
 480                 /* If it was only Tx */
 481                 if (xfer->rx_buf == NULL) {
 482                         sdd->state &= ~TXBUSY;
 483                         return 0;
 484                 }
 485
 486                 switch (sdd->cur_bpw) {
 487                 case 32:
 488                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 489                                 xfer->rx_buf, xfer->len / 4);
 490                         break;
 491                 case 16:
 492                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 493                                 xfer->rx_buf, xfer->len / 2);
 494                         break;
 495                 default:
 496                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 497                                 xfer->rx_buf, xfer->len);
 498                         break;
 499                 }
 500                 sdd->state &= ~RXBUSY;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 507                                                 struct spi_device *spi)
 508 {
 509         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 510
 511         if (sdd->tgl_spi == spi)
 512                 sdd->tgl_spi = NULL;
 513
 514         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 515 }
 516
 517 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 518 {
 519         void __iomem *regs = sdd->regs;
 520         u32 val;
 521
 522         /* Disable Clock */
 523         if (sdd->port_conf->clk_from_cmu) {
 524                 clk_disable(sdd->src_clk);
 525         } else {
 526                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 527                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 528                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 529         }
 530
 531         /* Set Polarity and Phase */
 532         val = readl(regs + S3C64XX_SPI_CH_CFG);
 533         val &= ~(S3C64XX_SPI_CH_SLAVE |
 534                         S3C64XX_SPI_CPOL_L |
 535                         S3C64XX_SPI_CPHA_B);
 536
 537         if (sdd->cur_mode & SPI_CPOL)
 538                 val |= S3C64XX_SPI_CPOL_L;
 539
 540         if (sdd->cur_mode & SPI_CPHA)
 541                 val |= S3C64XX_SPI_CPHA_B;
 542
 543         writel(val, regs + S3C64XX_SPI_CH_CFG);
 544
 545         /* Set Channel & DMA Mode */
 546         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 547         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 548                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 549
 550         switch (sdd->cur_bpw) {
 551         case 32:
 552                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 553                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 554                 break;
 555         case 16:
 556                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 557                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 558                 break;
 559         default:
 560                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 561                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 562                 break;
 563         }
 564
 565         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 566
 567         if (sdd->port_conf->clk_from_cmu) {
 568                 /* Configure Clock */
 569                 /* There is half-multiplier before the SPI */
 570                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 571                 /* Enable Clock */
 572                 clk_enable(sdd->src_clk);
 573         } else {
 574                 /* Configure Clock */
 575                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 576                 val &= ~S3C64XX_SPI_PSR_MASK;
 577                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 578                                 & S3C64XX_SPI_PSR_MASK);
 579                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 580
 581                 /* Enable Clock */
 582                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 583                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 584                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 585         }
 586 }
 587
 588 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 589
 590 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 591                                                 struct spi_message *msg)
 592 {
 593         struct device *dev = &sdd->pdev->dev;
 594         struct spi_transfer *xfer;
 595
 596         if (msg->is_dma_mapped)
 597                 return 0;
 598
 599         /* First mark all xfer unmapped */
 600         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 601                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 602                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 603         }
 604
 605         /* Map until end or first fail */
 606         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 607
 608                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 609                         continue;
 610
 611                 if (xfer->tx_buf != NULL) {
 612                         xfer->tx_dma = dma_map_single(dev,
 613                                         (void *)xfer->tx_buf, xfer->len,
 614                                         DMA_TO_DEVICE);
 615                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 616                                 dev_err(dev, "dma_map_single Tx failed\n");
 617                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 618                                 return -ENOMEM;
 619                         }
 620                 }
 621
 622                 if (xfer->rx_buf != NULL) {
 623                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 624                                                 xfer->len, DMA_FROM_DEVICE);
 625                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 626                                 dev_err(dev, "dma_map_single Rx failed\n");
 627                                 dma_unmap_single(dev, xfer->tx_dma,
 628                                                 xfer->len, DMA_TO_DEVICE);
 629                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 630                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 631                                 return -ENOMEM;
 632                         }
 633                 }
 634         }
 635
 636         return 0;
 637 }
 638
 639 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 640                                                 struct spi_message *msg)
 641 {
 642         struct device *dev = &sdd->pdev->dev;
 643         struct spi_transfer *xfer;
 644
 645         if (msg->is_dma_mapped)
 646                 return;
 647
 648         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 649
 650                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 651                         continue;
 652
 653                 if (xfer->rx_buf != NULL
 654                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 655                         dma_unmap_single(dev, xfer->rx_dma,
 656                                                 xfer->len, DMA_FROM_DEVICE);
 657
 658                 if (xfer->tx_buf != NULL
 659                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 660                         dma_unmap_single(dev, xfer->tx_dma,
 661                                                 xfer->len, DMA_TO_DEVICE);
 662         }
 663 }
 664
 665 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 666                                             struct spi_message *msg)
 667 {
 668         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 669         struct spi_device *spi = msg->spi;
 670         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 671         struct spi_transfer *xfer;
 672         int status = 0, cs_toggle = 0;
 673         u32 speed;
 674         u8 bpw;
 675
 676         /* If Master's(controller) state differs from that needed by Slave */
 677         if (sdd->cur_speed != spi->max_speed_hz
 678                         || sdd->cur_mode != spi->mode
 679                         || sdd->cur_bpw != spi->bits_per_word) {
 680                 sdd->cur_bpw = spi->bits_per_word;
 681                 sdd->cur_speed = spi->max_speed_hz;
 682                 sdd->cur_mode = spi->mode;
 683                 s3c64xx_spi_config(sdd);
 684         }
 685
 686         /* Map all the transfers if needed */
 687         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 688                 dev_err(&spi->dev,
 689                         "Xfer: Unable to map message buffers!\n");
 690                 status = -ENOMEM;
 691                 goto out;
 692         }
 693
 694         /* Configure feedback delay */
 695         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 696
 697         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 698
 699                 unsigned long flags;
 700                 int use_dma;
 701
 702                 INIT_COMPLETION(sdd->xfer_completion);
 703
 704                 /* Only BPW and Speed may change across transfers */
 705                 bpw = xfer->bits_per_word ? : spi->bits_per_word;
 706                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 707
 708                 if (xfer->len % (bpw / 8)) {
 709                         dev_err(&spi->dev,
 710                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 711                                 xfer->len, bpw / 8);
 712                         status = -EIO;
 713                         goto out;
 714                 }
 715
 716                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 717                         sdd->cur_bpw = bpw;
 718                         sdd->cur_speed = speed;
 719                         s3c64xx_spi_config(sdd);
 720                 }
 721
 722                 /* Polling method for xfers not bigger than FIFO capacity */
 723                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 724                         use_dma = 0;
 725                 else
 726                         use_dma = 1;
 727
 728                 spin_lock_irqsave(&sdd->lock, flags);
 729
 730                 /* Pending only which is to be done */
 731                 sdd->state &= ~RXBUSY;
 732                 sdd->state &= ~TXBUSY;
 733
 734                 enable_datapath(sdd, spi, xfer, use_dma);
 735
 736                 /* Slave Select */
 737                 enable_cs(sdd, spi);
 738
 739                 /* Start the signals */
 740                 S3C64XX_SPI_ACT(sdd);
 741
 742                 spin_unlock_irqrestore(&sdd->lock, flags);
 743
 744                 status = wait_for_xfer(sdd, xfer, use_dma);
 745
 746                 /* Quiese the signals */
 747                 S3C64XX_SPI_DEACT(sdd);
 748
 749                 if (status) {
 750                         dev_err(&spi->dev, "I/O Error: "
 751                                 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 752                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 753                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 754                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 755                                 xfer->len);
 756
 757                         if (use_dma) {
 758                                 if (xfer->tx_buf != NULL
 759                                                 && (sdd->state & TXBUSY))
 760                                         sdd->ops->stop(sdd->tx_dma.ch);
 761                                 if (xfer->rx_buf != NULL
 762                                                 && (sdd->state & RXBUSY))
 763                                         sdd->ops->stop(sdd->rx_dma.ch);
 764                         }
 765
 766                         goto out;
 767                 }
 768
 769                 if (xfer->delay_usecs)
 770                         udelay(xfer->delay_usecs);
 771
 772                 if (xfer->cs_change) {
 773                         /* Hint that the next mssg is gonna be
 774                            for the same device */
 775                         if (list_is_last(&xfer->transfer_list,
 776                                                 &msg->transfers))
 777                                 cs_toggle = 1;
 778                         else
 779                                 disable_cs(sdd, spi);
 780                 }
 781
 782                 msg->actual_length += xfer->len;
 783
 784                 flush_fifo(sdd);
 785         }
 786
 787 out:
 788         if (!cs_toggle || status)
 789                 disable_cs(sdd, spi);
 790         else
 791                 sdd->tgl_spi = spi;
 792
 793         s3c64xx_spi_unmap_mssg(sdd, msg);
 794
 795         msg->status = status;
 796
 797         spi_finalize_current_message(master);
 798
 799         return 0;
 800 }
 801
 802 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 803 {
 804         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 805
 806         /* Acquire DMA channels */
 807         while (!acquire_dma(sdd))
 808                 msleep(10);
 809
 810         pm_runtime_get_sync(&sdd->pdev->dev);
 811
 812         return 0;
 813 }
 814
 815 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 816 {
 817         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 818
 819         /* Free DMA channels */
 820         sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
 821         sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
 822
 823         pm_runtime_put(&sdd->pdev->dev);
 824
 825         return 0;
 826 }
 827
 828 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 829                                 struct s3c64xx_spi_driver_data *sdd,
 830                                 struct spi_device *spi)
 831 {
 832         struct s3c64xx_spi_csinfo *cs;
 833         struct device_node *slave_np, *data_np;
 834         u32 fb_delay = 0;
 835
 836         slave_np = spi->dev.of_node;
 837         if (!slave_np) {
 838                 dev_err(&spi->dev, "device node not found\n");
 839                 return ERR_PTR(-EINVAL);
 840         }
 841
 842         for_each_child_of_node(slave_np, data_np)
 843                 if (!strcmp(data_np->name, "controller-data"))
 844                         break;
 845         if (!data_np) {
 846                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 847                 return ERR_PTR(-EINVAL);
 848         }
 849
 850         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 851         if (!cs) {
 852                 dev_err(&spi->dev, "could not allocate memory for controller"
 853                                         " data\n");
 854                 return ERR_PTR(-ENOMEM);
 855         }
 856
 857         cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 858         if (!gpio_is_valid(cs->line)) {
 859                 dev_err(&spi->dev, "chip select gpio is not specified or "
 860                                         "invalid\n");
 861                 kfree(cs);
 862                 return ERR_PTR(-EINVAL);
 863         }
 864
 865         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 866         cs->fb_delay = fb_delay;
 867         return cs;
 868 }
 869
 870 /*
 871  * Here we only check the validity of requested configuration
 872  * and save the configuration in a local data-structure.
 873  * The controller is actually configured only just before we
 874  * get a message to transfer.
 875  */
 876 static int s3c64xx_spi_setup(struct spi_device *spi)
 877 {
 878         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 879         struct s3c64xx_spi_driver_data *sdd;
 880         struct s3c64xx_spi_info *sci;
 881         struct spi_message *msg;
 882         unsigned long flags;
 883         int err;
 884
 885         sdd = spi_master_get_devdata(spi->master);
 886         if (!cs && spi->dev.of_node) {
 887                 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
 888                 spi->controller_data = cs;
 889         }
 890
 891         if (IS_ERR_OR_NULL(cs)) {
 892                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 893                 return -ENODEV;
 894         }
 895
 896         if (!spi_get_ctldata(spi)) {
 897                 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
 898                                        dev_name(&spi->dev));
 899                 if (err) {
 900                         dev_err(&spi->dev,
 901                                 "Failed to get /CS gpio [%d]: %d\n",
 902                                 cs->line, err);
 903                         goto err_gpio_req;
 904                 }
 905                 spi_set_ctldata(spi, cs);
 906         }
 907
 908         sci = sdd->cntrlr_info;
 909
 910         spin_lock_irqsave(&sdd->lock, flags);
 911
 912         list_for_each_entry(msg, &sdd->queue, queue) {
 913                 /* Is some mssg is already queued for this device */
 914                 if (msg->spi == spi) {
 915                         dev_err(&spi->dev,
 916                                 "setup: attempt while mssg in queue!\n");
 917                         spin_unlock_irqrestore(&sdd->lock, flags);
 918                         err = -EBUSY;
 919                         goto err_msgq;
 920                 }
 921         }
 922
 923         spin_unlock_irqrestore(&sdd->lock, flags);
 924
 925         if (spi->bits_per_word != 8
 926                         && spi->bits_per_word != 16
 927                         && spi->bits_per_word != 32) {
 928                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 929                                                         spi->bits_per_word);
 930                 err = -EINVAL;
 931                 goto setup_exit;
 932         }
 933
 934         pm_runtime_get_sync(&sdd->pdev->dev);
 935
 936         /* Check if we can provide the requested rate */
 937         if (!sdd->port_conf->clk_from_cmu) {
 938                 u32 psr, speed;
 939
 940                 /* Max possible */
 941                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 942
 943                 if (spi->max_speed_hz > speed)
 944                         spi->max_speed_hz = speed;
 945
 946                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 947                 psr &= S3C64XX_SPI_PSR_MASK;
 948                 if (psr == S3C64XX_SPI_PSR_MASK)
 949                         psr--;
 950
 951                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 952                 if (spi->max_speed_hz < speed) {
 953                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 954                                 psr++;
 955                         } else {
 956                                 err = -EINVAL;
 957                                 goto setup_exit;
 958                         }
 959                 }
 960
 961                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 962                 if (spi->max_speed_hz >= speed) {
 963                         spi->max_speed_hz = speed;
 964                 } else {
 965                         err = -EINVAL;
 966                         goto setup_exit;
 967                 }
 968         }
 969
 970         pm_runtime_put(&sdd->pdev->dev);
 971         disable_cs(sdd, spi);
 972         return 0;
 973
 974 setup_exit:
 975         /* setup() returns with device de-selected */
 976         disable_cs(sdd, spi);
 977
 978 err_msgq:
 979         gpio_free(cs->line);
 980         spi_set_ctldata(spi, NULL);
 981
 982 err_gpio_req:
 983         kfree(cs);
 984
 985         return err;
 986 }
 987
 988 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 989 {
 990         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 991
 992         if (cs) {
 993                 gpio_free(cs->line);
 994                 if (spi->dev.of_node)
 995                         kfree(cs);
 996         }
 997         spi_set_ctldata(spi, NULL);
 998 }
 999
1000 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1001 {
1002         struct s3c64xx_spi_driver_data *sdd = data;
1003         struct spi_master *spi = sdd->master;
1004         unsigned int val;
1005
1006         val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
1007
1008         val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1009                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1010                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1011                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1012
1013         writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1014
1015         if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
1016                 dev_err(&spi->dev, "RX overrun\n");
1017         if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
1018                 dev_err(&spi->dev, "RX underrun\n");
1019         if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
1020                 dev_err(&spi->dev, "TX overrun\n");
1021         if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
1022                 dev_err(&spi->dev, "TX underrun\n");
1023
1024         return IRQ_HANDLED;
1025 }
1026
1027 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1028 {
1029         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1030         void __iomem *regs = sdd->regs;
1031         unsigned int val;
1032
1033         sdd->cur_speed = 0;
1034
1035         S3C64XX_SPI_DEACT(sdd);
1036
1037         /* Disable Interrupts - we use Polling if not DMA mode */
1038         writel(0, regs + S3C64XX_SPI_INT_EN);
1039
1040         if (!sdd->port_conf->clk_from_cmu)
1041                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1042                                 regs + S3C64XX_SPI_CLK_CFG);
1043         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1044         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1045
1046         /* Clear any irq pending bits */
1047         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1048                                 regs + S3C64XX_SPI_PENDING_CLR);
1049
1050         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1051
1052         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1053         val &= ~S3C64XX_SPI_MODE_4BURST;
1054         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1055         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1056         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1057
1058         flush_fifo(sdd);
1059 }
1060
1061 static int __devinit s3c64xx_spi_get_dmares(
1062                         struct s3c64xx_spi_driver_data *sdd, bool tx)
1063 {
1064         struct platform_device *pdev = sdd->pdev;
1065         struct s3c64xx_spi_dma_data *dma_data;
1066         struct property *prop;
1067         struct resource *res;
1068         char prop_name[15], *chan_str;
1069
1070         if (tx) {
1071                 dma_data = &sdd->tx_dma;
1072                 dma_data->direction = DMA_TO_DEVICE;
1073                 chan_str = "tx";
1074         } else {
1075                 dma_data = &sdd->rx_dma;
1076                 dma_data->direction = DMA_FROM_DEVICE;
1077                 chan_str = "rx";
1078         }
1079
1080         if (!sdd->pdev->dev.of_node) {
1081                 res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
1082                 if (!res) {
1083                         dev_err(&pdev->dev, "Unable to get SPI-%s dma "
1084                                         "resource\n", chan_str);
1085                         return -ENXIO;
1086                 }
1087                 dma_data->dmach = res->start;
1088                 return 0;
1089         }
1090
1091         sprintf(prop_name, "%s-dma-channel", chan_str);
1092         prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
1093         if (!prop) {
1094                 dev_err(&pdev->dev, "%s dma channel property not specified\n",
1095                                         chan_str);
1096                 return -ENXIO;
1097         }
1098
1099         dma_data->dmach = DMACH_DT_PROP;
1100         dma_data->dma_prop = prop;
1101         return 0;
1102 }
1103
1104 #ifdef CONFIG_OF
1105 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1106 {
1107         struct device *dev = &sdd->pdev->dev;
1108         int idx, gpio, ret;
1109
1110         /* find gpios for mosi, miso and clock lines */
1111         for (idx = 0; idx < 3; idx++) {
1112                 gpio = of_get_gpio(dev->of_node, idx);
1113                 if (!gpio_is_valid(gpio)) {
1114                         dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1115                         goto free_gpio;
1116                 }
1117
1118                 ret = gpio_request(gpio, "spi-bus");
1119                 if (ret) {
1120                         dev_err(dev, "gpio [%d] request failed: %d\n",
1121                                 gpio, ret);
1122                         goto free_gpio;
1123                 }
1124         }
1125         return 0;
1126
1127 free_gpio:
1128         while (--idx >= 0)
1129                 gpio_free(sdd->gpios[idx]);
1130         return -EINVAL;
1131 }
1132
1133 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1134 {
1135         unsigned int idx;
1136         for (idx = 0; idx < 3; idx++)
1137                 gpio_free(sdd->gpios[idx]);
1138 }
1139
1140 static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
1141                                                 struct device *dev)
1142 {
1143         struct s3c64xx_spi_info *sci;
1144         u32 temp;
1145
1146         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1147         if (!sci) {
1148                 dev_err(dev, "memory allocation for spi_info failed\n");
1149                 return ERR_PTR(-ENOMEM);
1150         }
1151
1152         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1153                 dev_warn(dev, "spi bus clock parent not specified, using "
1154                                 "clock at index 0 as parent\n");
1155                 sci->src_clk_nr = 0;
1156         } else {
1157                 sci->src_clk_nr = temp;
1158         }
1159
1160         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1161                 dev_warn(dev, "number of chip select lines not specified, "
1162                                 "assuming 1 chip select line\n");
1163                 sci->num_cs = 1;
1164         } else {
1165                 sci->num_cs = temp;
1166         }
1167
1168         return sci;
1169 }
1170 #else
1171 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1172 {
1173         return dev->platform_data;
1174 }
1175
1176 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1177 {
1178         return -EINVAL;
1179 }
1180
1181 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1182 {
1183 }
1184 #endif
1185
1186 static const struct of_device_id s3c64xx_spi_dt_match[];
1187
1188 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1189                                                 struct platform_device *pdev)
1190 {
1191 #ifdef CONFIG_OF
1192         if (pdev->dev.of_node) {
1193                 const struct of_device_id *match;
1194                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1195                 return (struct s3c64xx_spi_port_config *)match->data;
1196         }
1197 #endif
1198         return (struct s3c64xx_spi_port_config *)
1199                          platform_get_device_id(pdev)->driver_data;
1200 }
1201
1202 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1203 {
1204         struct resource *mem_res;
1205         struct s3c64xx_spi_driver_data *sdd;
1206         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1207         struct spi_master *master;
1208         int ret, irq;
1209         char clk_name[16];
1210
1211         if (!sci && pdev->dev.of_node) {
1212                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1213                 if (IS_ERR(sci))
1214                         return PTR_ERR(sci);
1215         }
1216
1217         if (!sci) {
1218                 dev_err(&pdev->dev, "platform_data missing!\n");
1219                 return -ENODEV;
1220         }
1221
1222         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223         if (mem_res == NULL) {
1224                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1225                 return -ENXIO;
1226         }
1227
1228         irq = platform_get_irq(pdev, 0);
1229         if (irq < 0) {
1230                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1231                 return irq;
1232         }
1233
1234         master = spi_alloc_master(&pdev->dev,
1235                                 sizeof(struct s3c64xx_spi_driver_data));
1236         if (master == NULL) {
1237                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1238                 return -ENOMEM;
1239         }
1240
1241         platform_set_drvdata(pdev, master);
1242
1243         sdd = spi_master_get_devdata(master);
1244         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1245         sdd->master = master;
1246         sdd->cntrlr_info = sci;
1247         sdd->pdev = pdev;
1248         sdd->sfr_start = mem_res->start;
1249         if (pdev->dev.of_node) {
1250                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1251                 if (ret < 0) {
1252                         dev_err(&pdev->dev, "failed to get alias id, "
1253                                                 "errno %d\n", ret);
1254                         goto err0;
1255                 }
1256                 sdd->port_id = ret;
1257         } else {
1258                 sdd->port_id = pdev->id;
1259         }
1260
1261         sdd->cur_bpw = 8;
1262
1263         ret = s3c64xx_spi_get_dmares(sdd, true);
1264         if (ret)
1265                 goto err0;
1266
1267         ret = s3c64xx_spi_get_dmares(sdd, false);
1268         if (ret)
1269                 goto err0;
1270
1271         master->dev.of_node = pdev->dev.of_node;
1272         master->bus_num = sdd->port_id;
1273         master->setup = s3c64xx_spi_setup;
1274         master->cleanup = s3c64xx_spi_cleanup;
1275         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1276         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1277         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1278         master->num_chipselect = sci->num_cs;
1279         master->dma_alignment = 8;
1280         /* the spi->mode bits understood by this driver: */
1281         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1282
1283         if (request_mem_region(mem_res->start,
1284                         resource_size(mem_res), pdev->name) == NULL) {
1285                 dev_err(&pdev->dev, "Req mem region failed\n");
1286                 ret = -ENXIO;
1287                 goto err0;
1288         }
1289
1290         sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1291         if (sdd->regs == NULL) {
1292                 dev_err(&pdev->dev, "Unable to remap IO\n");
1293                 ret = -ENXIO;
1294                 goto err1;
1295         }
1296
1297         if (!sci->cfg_gpio && pdev->dev.of_node) {
1298                 if (s3c64xx_spi_parse_dt_gpio(sdd))
1299                         return -EBUSY;
1300         } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1301                 dev_err(&pdev->dev, "Unable to config gpio\n");
1302                 ret = -EBUSY;
1303                 goto err2;
1304         }
1305
1306         /* Setup clocks */
1307         sdd->clk = clk_get(&pdev->dev, "spi");
1308         if (IS_ERR(sdd->clk)) {
1309                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1310                 ret = PTR_ERR(sdd->clk);
1311                 goto err3;
1312         }
1313
1314         if (clk_enable(sdd->clk)) {
1315                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1316                 ret = -EBUSY;
1317                 goto err4;
1318         }
1319
1320         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1321         sdd->src_clk = clk_get(&pdev->dev, clk_name);
1322         if (IS_ERR(sdd->src_clk)) {
1323                 dev_err(&pdev->dev,
1324                         "Unable to acquire clock '%s'\n", clk_name);
1325                 ret = PTR_ERR(sdd->src_clk);
1326                 goto err5;
1327         }
1328
1329         if (clk_enable(sdd->src_clk)) {
1330                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1331                 ret = -EBUSY;
1332                 goto err6;
1333         }
1334
1335         /* Setup Deufult Mode */
1336         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1337
1338         spin_lock_init(&sdd->lock);
1339         init_completion(&sdd->xfer_completion);
1340         INIT_LIST_HEAD(&sdd->queue);
1341
1342         ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1343         if (ret != 0) {
1344                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1345                         irq, ret);
1346                 goto err7;
1347         }
1348
1349         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1350                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1351                sdd->regs + S3C64XX_SPI_INT_EN);
1352
1353         if (spi_register_master(master)) {
1354                 dev_err(&pdev->dev, "cannot register SPI master\n");
1355                 ret = -EBUSY;
1356                 goto err8;
1357         }
1358
1359         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1360                                         "with %d Slaves attached\n",
1361                                         sdd->port_id, master->num_chipselect);
1362         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1363                                         mem_res->end, mem_res->start,
1364                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1365
1366         pm_runtime_enable(&pdev->dev);
1367
1368         return 0;
1369
1370 err8:
1371         free_irq(irq, sdd);
1372 err7:
1373         clk_disable(sdd->src_clk);
1374 err6:
1375         clk_put(sdd->src_clk);
1376 err5:
1377         clk_disable(sdd->clk);
1378 err4:
1379         clk_put(sdd->clk);
1380 err3:
1381         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1382                 s3c64xx_spi_dt_gpio_free(sdd);
1383 err2:
1384         iounmap((void *) sdd->regs);
1385 err1:
1386         release_mem_region(mem_res->start, resource_size(mem_res));
1387 err0:
1388         platform_set_drvdata(pdev, NULL);
1389         spi_master_put(master);
1390
1391         return ret;
1392 }
1393
1394 static int s3c64xx_spi_remove(struct platform_device *pdev)
1395 {
1396         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1397         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1398         struct resource *mem_res;
1399
1400         pm_runtime_disable(&pdev->dev);
1401
1402         spi_unregister_master(master);
1403
1404         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1405
1406         free_irq(platform_get_irq(pdev, 0), sdd);
1407
1408         clk_disable(sdd->src_clk);
1409         clk_put(sdd->src_clk);
1410
1411         clk_disable(sdd->clk);
1412         clk_put(sdd->clk);
1413
1414         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1415                 s3c64xx_spi_dt_gpio_free(sdd);
1416
1417         iounmap((void *) sdd->regs);
1418
1419         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1420         if (mem_res != NULL)
1421                 release_mem_region(mem_res->start, resource_size(mem_res));
1422
1423         platform_set_drvdata(pdev, NULL);
1424         spi_master_put(master);
1425
1426         return 0;
1427 }
1428
1429 #ifdef CONFIG_PM
1430 static int s3c64xx_spi_suspend(struct device *dev)
1431 {
1432         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1433         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1434
1435         spi_master_suspend(master);
1436
1437         /* Disable the clock */
1438         clk_disable(sdd->src_clk);
1439         clk_disable(sdd->clk);
1440
1441         if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1442                 s3c64xx_spi_dt_gpio_free(sdd);
1443
1444         sdd->cur_speed = 0; /* Output Clock is stopped */
1445
1446         return 0;
1447 }
1448
1449 static int s3c64xx_spi_resume(struct device *dev)
1450 {
1451         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1452         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1453         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1454
1455         if (!sci->cfg_gpio && dev->of_node)
1456                 s3c64xx_spi_parse_dt_gpio(sdd);
1457         else
1458                 sci->cfg_gpio();
1459
1460         /* Enable the clock */
1461         clk_enable(sdd->src_clk);
1462         clk_enable(sdd->clk);
1463
1464         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1465
1466         spi_master_resume(master);
1467
1468         return 0;
1469 }
1470 #endif /* CONFIG_PM */
1471
1472 #ifdef CONFIG_PM_RUNTIME
1473 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1474 {
1475         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1476         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1477
1478         clk_disable(sdd->clk);
1479         clk_disable(sdd->src_clk);
1480
1481         return 0;
1482 }
1483
1484 static int s3c64xx_spi_runtime_resume(struct device *dev)
1485 {
1486         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1487         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1488
1489         clk_enable(sdd->src_clk);
1490         clk_enable(sdd->clk);
1491
1492         return 0;
1493 }
1494 #endif /* CONFIG_PM_RUNTIME */
1495
1496 static const struct dev_pm_ops s3c64xx_spi_pm = {
1497         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1498         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1499                            s3c64xx_spi_runtime_resume, NULL)
1500 };
1501
1502 struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1503         .fifo_lvl_mask  = { 0x7f },
1504         .rx_lvl_offset  = 13,
1505         .tx_st_done     = 21,
1506         .high_speed     = true,
1507 };
1508
1509 struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1510         .fifo_lvl_mask  = { 0x7f, 0x7F },
1511         .rx_lvl_offset  = 13,
1512         .tx_st_done     = 21,
1513 };
1514
1515 struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1516         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1517         .rx_lvl_offset  = 15,
1518         .tx_st_done     = 25,
1519 };
1520
1521 struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1522         .fifo_lvl_mask  = { 0x7f, 0x7F },
1523         .rx_lvl_offset  = 13,
1524         .tx_st_done     = 21,
1525         .high_speed     = true,
1526 };
1527
1528 struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1529         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1530         .rx_lvl_offset  = 15,
1531         .tx_st_done     = 25,
1532         .high_speed     = true,
1533 };
1534
1535 struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1536         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1537         .rx_lvl_offset  = 15,
1538         .tx_st_done     = 25,
1539         .high_speed     = true,
1540         .clk_from_cmu   = true,
1541 };
1542
1543 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1544         {
1545                 .name           = "s3c2443-spi",
1546                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1547         }, {
1548                 .name           = "s3c6410-spi",
1549                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1550         }, {
1551                 .name           = "s5p64x0-spi",
1552                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1553         }, {
1554                 .name           = "s5pc100-spi",
1555                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1556         }, {
1557                 .name           = "s5pv210-spi",
1558                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1559         }, {
1560                 .name           = "exynos4210-spi",
1561                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1562         },
1563         { },
1564 };
1565
1566 #ifdef CONFIG_OF
1567 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1568         { .compatible = "samsung,exynos4210-spi",
1569                         .data = (void *)&exynos4_spi_port_config,
1570         },
1571         { },
1572 };
1573 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1574 #endif /* CONFIG_OF */
1575
1576 static struct platform_driver s3c64xx_spi_driver = {
1577         .driver = {
1578                 .name   = "s3c64xx-spi",
1579                 .owner = THIS_MODULE,
1580                 .pm = &s3c64xx_spi_pm,
1581                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1582         },
1583         .remove = s3c64xx_spi_remove,
1584         .id_table = s3c64xx_spi_driver_ids,
1585 };
1586 MODULE_ALIAS("platform:s3c64xx-spi");
1587
1588 static int __init s3c64xx_spi_init(void)
1589 {
1590         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1591 }
1592 subsys_initcall(s3c64xx_spi_init);
1593
1594 static void __exit s3c64xx_spi_exit(void)
1595 {
1596         platform_driver_unregister(&s3c64xx_spi_driver);
1597 }
1598 module_exit(s3c64xx_spi_exit);
1599
1600 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1601 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1602 MODULE_LICENSE("GPL");