2 * R-Car SYSC Power management support
4 * Copyright (C) 2014 Magnus Damm
5 * Copyright (C) 2015-2017 Glider bvba
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/clk/renesas.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/of_address.h>
17 #include <linux/pm_domain.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
21 #include <linux/soc/renesas/rcar-sysc.h>
23 #include "rcar-sysc.h"
26 #define SYSCSR 0x00 /* SYSC Status Register */
27 #define SYSCISR 0x04 /* Interrupt Status Register */
28 #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
29 #define SYSCIER 0x0c /* Interrupt Enable Register */
30 #define SYSCIMR 0x10 /* Interrupt Mask Register */
32 /* SYSC Status Register */
33 #define SYSCSR_PONENB 1 /* Ready for power resume requests */
34 #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
37 * Power Control Register Offsets inside the register block for each domain
38 * Note: The "CR" registers for ARM cores exist on H1 only
39 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
40 * Use PSCI on R-Car Gen3
42 #define PWRSR_OFFS 0x00 /* Power Status Register */
43 #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
44 #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
45 #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
46 #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
47 #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
50 #define SYSCSR_RETRIES 100
51 #define SYSCSR_DELAY_US 1
53 #define PWRER_RETRIES 100
54 #define PWRER_DELAY_US 1
56 #define SYSCISR_RETRIES 1000
57 #define SYSCISR_DELAY_US 1
59 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
61 static void __iomem *rcar_sysc_base;
62 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
64 static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
66 unsigned int sr_bit, reg_offs;
70 sr_bit = SYSCSR_PONENB;
71 reg_offs = PWRONCR_OFFS;
73 sr_bit = SYSCSR_POFFENB;
74 reg_offs = PWROFFCR_OFFS;
77 /* Wait until SYSC is ready to accept a power request */
78 for (k = 0; k < SYSCSR_RETRIES; k++) {
79 if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
81 udelay(SYSCSR_DELAY_US);
84 if (k == SYSCSR_RETRIES)
87 /* Submit power shutoff or power resume request */
88 iowrite32(BIT(sysc_ch->chan_bit),
89 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
94 static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
96 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
97 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
103 spin_lock_irqsave(&rcar_sysc_lock, flags);
105 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
107 /* Submit power shutoff or resume request until it was accepted */
108 for (k = 0; k < PWRER_RETRIES; k++) {
109 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
113 status = ioread32(rcar_sysc_base +
114 sysc_ch->chan_offs + PWRER_OFFS);
115 if (!(status & chan_mask))
118 udelay(PWRER_DELAY_US);
121 if (k == PWRER_RETRIES) {
126 /* Wait until the power shutoff or resume request has completed * */
127 for (k = 0; k < SYSCISR_RETRIES; k++) {
128 if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
130 udelay(SYSCISR_DELAY_US);
133 if (k == SYSCISR_RETRIES)
136 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
139 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
141 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
142 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
146 int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
148 return rcar_sysc_power(sysc_ch, false);
151 int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
153 return rcar_sysc_power(sysc_ch, true);
156 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
160 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
161 if (st & BIT(sysc_ch->chan_bit))
167 struct rcar_sysc_pd {
168 struct generic_pm_domain genpd;
169 struct rcar_sysc_ch ch;
174 static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
176 return container_of(d, struct rcar_sysc_pd, genpd);
179 static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
181 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
183 pr_debug("%s: %s\n", __func__, genpd->name);
184 return rcar_sysc_power_down(&pd->ch);
187 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
189 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
191 pr_debug("%s: %s\n", __func__, genpd->name);
192 return rcar_sysc_power_up(&pd->ch);
195 static bool has_cpg_mstp;
197 static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
199 struct generic_pm_domain *genpd = &pd->genpd;
200 const char *name = pd->genpd.name;
201 struct dev_power_governor *gov = &simple_qos_governor;
204 if (pd->flags & PD_CPU) {
206 * This domain contains a CPU core and therefore it should
207 * only be turned off if the CPU is not in use.
209 pr_debug("PM domain %s contains %s\n", name, "CPU");
210 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
211 } else if (pd->flags & PD_SCU) {
213 * This domain contains an SCU and cache-controller, and
214 * therefore it should only be turned off if the CPU cores are
217 pr_debug("PM domain %s contains %s\n", name, "SCU");
218 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
219 } else if (pd->flags & PD_NO_CR) {
221 * This domain cannot be turned off.
223 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
226 if (!(pd->flags & (PD_CPU | PD_SCU))) {
227 /* Enable Clock Domain for I/O devices */
228 genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
230 genpd->attach_dev = cpg_mstp_attach_dev;
231 genpd->detach_dev = cpg_mstp_detach_dev;
233 genpd->attach_dev = cpg_mssr_attach_dev;
234 genpd->detach_dev = cpg_mssr_detach_dev;
238 genpd->power_off = rcar_sysc_pd_power_off;
239 genpd->power_on = rcar_sysc_pd_power_on;
241 if (pd->flags & (PD_CPU | PD_NO_CR)) {
242 /* Skip CPUs (handled by SMP code) and areas without control */
243 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
247 if (!rcar_sysc_power_is_off(&pd->ch)) {
248 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
252 rcar_sysc_power_up(&pd->ch);
255 error = pm_genpd_init(genpd, gov, false);
257 pr_err("Failed to init PM domain %s: %d\n", name, error);
262 static const struct of_device_id rcar_sysc_matches[] __initconst = {
263 #ifdef CONFIG_SYSC_R8A7743
264 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
266 #ifdef CONFIG_SYSC_R8A7745
267 { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
269 #ifdef CONFIG_SYSC_R8A77470
270 { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
272 #ifdef CONFIG_SYSC_R8A7779
273 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
275 #ifdef CONFIG_SYSC_R8A7790
276 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
278 #ifdef CONFIG_SYSC_R8A7791
279 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
280 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
281 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
283 #ifdef CONFIG_SYSC_R8A7792
284 { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
286 #ifdef CONFIG_SYSC_R8A7794
287 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
289 #ifdef CONFIG_SYSC_R8A7795
290 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
292 #ifdef CONFIG_SYSC_R8A7796
293 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
295 #ifdef CONFIG_SYSC_R8A77965
296 { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
298 #ifdef CONFIG_SYSC_R8A77970
299 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
301 #ifdef CONFIG_SYSC_R8A77980
302 { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
304 #ifdef CONFIG_SYSC_R8A77990
305 { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
307 #ifdef CONFIG_SYSC_R8A77995
308 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
313 struct rcar_pm_domains {
314 struct genpd_onecell_data onecell_data;
315 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
318 static int __init rcar_sysc_pd_init(void)
320 const struct rcar_sysc_info *info;
321 const struct of_device_id *match;
322 struct rcar_pm_domains *domains;
323 struct device_node *np;
324 u32 syscier, syscimr;
332 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
339 error = info->init();
344 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
345 "renesas,cpg-mstp-clocks");
347 base = of_iomap(np, 0);
349 pr_warn("%pOF: Cannot map regs\n", np);
354 rcar_sysc_base = base;
356 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
362 domains->onecell_data.domains = domains->domains;
363 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
365 for (i = 0, syscier = 0; i < info->num_areas; i++)
366 syscier |= BIT(info->areas[i].isr_bit);
369 * Mask all interrupt sources to prevent the CPU from receiving them.
370 * Make sure not to clear reserved bits that were set before.
372 syscimr = ioread32(base + SYSCIMR);
374 pr_debug("%pOF: syscimr = 0x%08x\n", np, syscimr);
375 iowrite32(syscimr, base + SYSCIMR);
378 * SYSC needs all interrupt sources enabled to control power.
380 pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
381 iowrite32(syscier, base + SYSCIER);
384 * First, create all PM domains
386 for (i = 0; i < info->num_areas; i++) {
387 const struct rcar_sysc_area *area = &info->areas[i];
388 struct rcar_sysc_pd *pd;
391 /* Skip NULLified area */
395 pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
401 strcpy(pd->name, area->name);
402 pd->genpd.name = pd->name;
403 pd->ch.chan_offs = area->chan_offs;
404 pd->ch.chan_bit = area->chan_bit;
405 pd->ch.isr_bit = area->isr_bit;
406 pd->flags = area->flags;
408 error = rcar_sysc_pd_setup(pd);
412 domains->domains[area->isr_bit] = &pd->genpd;
416 * Second, link all PM domains to their parents
418 for (i = 0; i < info->num_areas; i++) {
419 const struct rcar_sysc_area *area = &info->areas[i];
421 if (!area->name || area->parent < 0)
424 error = pm_genpd_add_subdomain(domains->domains[area->parent],
425 domains->domains[area->isr_bit]);
427 pr_warn("Failed to add PM subdomain %s to parent %u\n",
428 area->name, area->parent);
431 error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
437 early_initcall(rcar_sysc_pd_init);
439 void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
440 unsigned int num_areas, u8 id)
444 for (i = 0; i < num_areas; i++)
445 if (areas[i].isr_bit == id) {
446 areas[i].name = NULL;
451 void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
455 if (!rcar_sysc_pd_init())
458 rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
461 * Mask all interrupt sources to prevent the CPU from receiving them.
462 * Make sure not to clear reserved bits that were set before.
464 syscimr = ioread32(rcar_sysc_base + SYSCIMR);
466 pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
467 iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
470 * SYSC needs all interrupt sources enabled to control power.
472 pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
473 iowrite32(syscier, rcar_sysc_base + SYSCIER);