drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2005 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <asm/uaccess.h>
  11
  12 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  13 static void qla2x00_nv_deselect(scsi_qla_host_t *);
  14 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  15
  16 /*
  17  * NVRAM support routines
  18  */
  19
  20 /**
  21  * qla2x00_lock_nvram_access() -
  22  * @ha: HA context
  23  */
  24 void
  25 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  26 {
  27         uint16_t data;
  28         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  29
  30         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  31                 data = RD_REG_WORD(&reg->nvram);
  32                 while (data & NVR_BUSY) {
  33                         udelay(100);
  34                         data = RD_REG_WORD(&reg->nvram);
  35                 }
  36
  37                 /* Lock resource */
  38                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  39                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                 udelay(5);
  41                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  42                 while ((data & BIT_0) == 0) {
  43                         /* Lock failed */
  44                         udelay(100);
  45                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  46                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                         udelay(5);
  48                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  49                 }
  50         }
  51 }
  52
  53 /**
  54  * qla2x00_unlock_nvram_access() -
  55  * @ha: HA context
  56  */
  57 void
  58 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  59 {
  60         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  61
  62         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  63                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  64                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  65         }
  66 }
  67
  68 /**
  69  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  70  *      request routine to get the word from NVRAM.
  71  * @ha: HA context
  72  * @addr: Address in NVRAM to read
  73  *
  74  * Returns the word read from nvram @addr.
  75  */
  76 uint16_t
  77 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  78 {
  79         uint16_t        data;
  80         uint32_t        nv_cmd;
  81
  82         nv_cmd = addr << 16;
  83         nv_cmd |= NV_READ_OP;
  84         data = qla2x00_nvram_request(ha, nv_cmd);
  85
  86         return (data);
  87 }
  88
  89 /**
  90  * qla2x00_write_nvram_word() - Write NVRAM data.
  91  * @ha: HA context
  92  * @addr: Address in NVRAM to write
  93  * @data: word to program
  94  */
  95 void
  96 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  97 {
  98         int count;
  99         uint16_t word;
 100         uint32_t nv_cmd;
 101         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 102
 103         qla2x00_nv_write(ha, NVR_DATA_OUT);
 104         qla2x00_nv_write(ha, 0);
 105         qla2x00_nv_write(ha, 0);
 106
 107         for (word = 0; word < 8; word++)
 108                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 109
 110         qla2x00_nv_deselect(ha);
 111
 112         /* Write data */
 113         nv_cmd = (addr << 16) | NV_WRITE_OP;
 114         nv_cmd |= data;
 115         nv_cmd <<= 5;
 116         for (count = 0; count < 27; count++) {
 117                 if (nv_cmd & BIT_31)
 118                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 119                 else
 120                         qla2x00_nv_write(ha, 0);
 121
 122                 nv_cmd <<= 1;
 123         }
 124
 125         qla2x00_nv_deselect(ha);
 126
 127         /* Wait for NVRAM to become ready */
 128         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 129         do {
 130                 NVRAM_DELAY();
 131                 word = RD_REG_WORD(&reg->nvram);
 132         } while ((word & NVR_DATA_IN) == 0);
 133
 134         qla2x00_nv_deselect(ha);
 135
 136         /* Disable writes */
 137         qla2x00_nv_write(ha, NVR_DATA_OUT);
 138         for (count = 0; count < 10; count++)
 139                 qla2x00_nv_write(ha, 0);
 140
 141         qla2x00_nv_deselect(ha);
 142 }
 143
 144 static int
 145 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 146     uint32_t tmo)
 147 {
 148         int ret, count;
 149         uint16_t word;
 150         uint32_t nv_cmd;
 151         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 152
 153         ret = QLA_SUCCESS;
 154
 155         qla2x00_nv_write(ha, NVR_DATA_OUT);
 156         qla2x00_nv_write(ha, 0);
 157         qla2x00_nv_write(ha, 0);
 158
 159         for (word = 0; word < 8; word++)
 160                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 161
 162         qla2x00_nv_deselect(ha);
 163
 164         /* Write data */
 165         nv_cmd = (addr << 16) | NV_WRITE_OP;
 166         nv_cmd |= data;
 167         nv_cmd <<= 5;
 168         for (count = 0; count < 27; count++) {
 169                 if (nv_cmd & BIT_31)
 170                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 171                 else
 172                         qla2x00_nv_write(ha, 0);
 173
 174                 nv_cmd <<= 1;
 175         }
 176
 177         qla2x00_nv_deselect(ha);
 178
 179         /* Wait for NVRAM to become ready */
 180         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 181         do {
 182                 NVRAM_DELAY();
 183                 word = RD_REG_WORD(&reg->nvram);
 184                 if (!--tmo) {
 185                         ret = QLA_FUNCTION_FAILED;
 186                         break;
 187                 }
 188         } while ((word & NVR_DATA_IN) == 0);
 189
 190         qla2x00_nv_deselect(ha);
 191
 192         /* Disable writes */
 193         qla2x00_nv_write(ha, NVR_DATA_OUT);
 194         for (count = 0; count < 10; count++)
 195                 qla2x00_nv_write(ha, 0);
 196
 197         qla2x00_nv_deselect(ha);
 198
 199         return ret;
 200 }
 201
 202 /**
 203  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
 204  *      NVRAM.
 205  * @ha: HA context
 206  * @nv_cmd: NVRAM command
 207  *
 208  * Bit definitions for NVRAM command:
 209  *
 210  *      Bit 26     = start bit
 211  *      Bit 25, 24 = opcode
 212  *      Bit 23-16  = address
 213  *      Bit 15-0   = write data
 214  *
 215  * Returns the word read from nvram @addr.
 216  */
 217 static uint16_t
 218 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
 219 {
 220         uint8_t         cnt;
 221         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 222         uint16_t        data = 0;
 223         uint16_t        reg_data;
 224
 225         /* Send command to NVRAM. */
 226         nv_cmd <<= 5;
 227         for (cnt = 0; cnt < 11; cnt++) {
 228                 if (nv_cmd & BIT_31)
 229                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 230                 else
 231                         qla2x00_nv_write(ha, 0);
 232                 nv_cmd <<= 1;
 233         }
 234
 235         /* Read data from NVRAM. */
 236         for (cnt = 0; cnt < 16; cnt++) {
 237                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 238                 NVRAM_DELAY();
 239                 data <<= 1;
 240                 reg_data = RD_REG_WORD(&reg->nvram);
 241                 if (reg_data & NVR_DATA_IN)
 242                         data |= BIT_0;
 243                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 244                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 245                 NVRAM_DELAY();
 246         }
 247
 248         /* Deselect chip. */
 249         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 250         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 251         NVRAM_DELAY();
 252
 253         return (data);
 254 }
 255
 256 /**
 257  * qla2x00_nv_write() - Clean NVRAM operations.
 258  * @ha: HA context
 259  */
 260 static void
 261 qla2x00_nv_deselect(scsi_qla_host_t *ha)
 262 {
 263         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 264
 265         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 266         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 267         NVRAM_DELAY();
 268 }
 269
 270 /**
 271  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
 272  * @ha: HA context
 273  * @data: Serial interface selector
 274  */
 275 static void
 276 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
 277 {
 278         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 279
 280         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 281         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 282         NVRAM_DELAY();
 283         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
 284             NVR_WRT_ENABLE);
 285         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 286         NVRAM_DELAY();
 287         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 288         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 289         NVRAM_DELAY();
 290 }
 291
 292 /**
 293  * qla2x00_clear_nvram_protection() -
 294  * @ha: HA context
 295  */
 296 static int
 297 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 298 {
 299         int ret, stat;
 300         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 301         uint32_t word;
 302         uint16_t wprot, wprot_old;
 303
 304         /* Clear NVRAM write protection. */
 305         ret = QLA_FUNCTION_FAILED;
 306         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
 307         stat = qla2x00_write_nvram_word_tmo(ha, 0,
 308             __constant_cpu_to_le16(0x1234), 100000);
 309         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
 310         if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
 311                 /* Write enable. */
 312                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 313                 qla2x00_nv_write(ha, 0);
 314                 qla2x00_nv_write(ha, 0);
 315                 for (word = 0; word < 8; word++)
 316                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 317
 318                 qla2x00_nv_deselect(ha);
 319
 320                 /* Enable protection register. */
 321                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 322                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 323                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 324                 for (word = 0; word < 8; word++)
 325                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 326
 327                 qla2x00_nv_deselect(ha);
 328
 329                 /* Clear protection register (ffff is cleared). */
 330                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 331                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 for (word = 0; word < 8; word++)
 334                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 335
 336                 qla2x00_nv_deselect(ha);
 337
 338                 /* Wait for NVRAM to become ready. */
 339                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 340                 do {
 341                         NVRAM_DELAY();
 342                         word = RD_REG_WORD(&reg->nvram);
 343                 } while ((word & NVR_DATA_IN) == 0);
 344
 345                 ret = QLA_SUCCESS;
 346         } else
 347                 qla2x00_write_nvram_word(ha, 0, wprot_old);
 348
 349         return ret;
 350 }
 351
 352 static void
 353 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 354 {
 355         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 356         uint32_t word;
 357
 358         if (stat != QLA_SUCCESS)
 359                 return;
 360
 361         /* Set NVRAM write protection. */
 362         /* Write enable. */
 363         qla2x00_nv_write(ha, NVR_DATA_OUT);
 364         qla2x00_nv_write(ha, 0);
 365         qla2x00_nv_write(ha, 0);
 366         for (word = 0; word < 8; word++)
 367                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 368
 369         qla2x00_nv_deselect(ha);
 370
 371         /* Enable protection register. */
 372         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 373         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 374         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 375         for (word = 0; word < 8; word++)
 376                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 377
 378         qla2x00_nv_deselect(ha);
 379
 380         /* Enable protection register. */
 381         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 382         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 383         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 384         for (word = 0; word < 8; word++)
 385                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 386
 387         qla2x00_nv_deselect(ha);
 388
 389         /* Wait for NVRAM to become ready. */
 390         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 391         do {
 392                 NVRAM_DELAY();
 393                 word = RD_REG_WORD(&reg->nvram);
 394         } while ((word & NVR_DATA_IN) == 0);
 395 }
 396
 397
 398 /*****************************************************************************/
 399 /* Flash Manipulation Routines                                               */
 400 /*****************************************************************************/
 401
 402 static inline uint32_t
 403 flash_conf_to_access_addr(uint32_t faddr)
 404 {
 405         return FARX_ACCESS_FLASH_CONF | faddr;
 406 }
 407
 408 static inline uint32_t
 409 flash_data_to_access_addr(uint32_t faddr)
 410 {
 411         return FARX_ACCESS_FLASH_DATA | faddr;
 412 }
 413
 414 static inline uint32_t
 415 nvram_conf_to_access_addr(uint32_t naddr)
 416 {
 417         return FARX_ACCESS_NVRAM_CONF | naddr;
 418 }
 419
 420 static inline uint32_t
 421 nvram_data_to_access_addr(uint32_t naddr)
 422 {
 423         return FARX_ACCESS_NVRAM_DATA | naddr;
 424 }
 425
 426 uint32_t
 427 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
 428 {
 429         int rval;
 430         uint32_t cnt, data;
 431         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 432
 433         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 434         /* Wait for READ cycle to complete. */
 435         rval = QLA_SUCCESS;
 436         for (cnt = 3000;
 437             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 438             rval == QLA_SUCCESS; cnt--) {
 439                 if (cnt)
 440                         udelay(10);
 441                 else
 442                         rval = QLA_FUNCTION_TIMEOUT;
 443         }
 444
 445         /* TODO: What happens if we time out? */
 446         data = 0xDEADDEAD;
 447         if (rval == QLA_SUCCESS)
 448                 data = RD_REG_DWORD(&reg->flash_data);
 449
 450         return data;
 451 }
 452
 453 uint32_t *
 454 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 455     uint32_t dwords)
 456 {
 457         uint32_t i;
 458
 459         /* Dword reads to flash. */
 460         for (i = 0; i < dwords; i++, faddr++)
 461                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 462                     flash_data_to_access_addr(faddr)));
 463
 464         return dwptr;
 465 }
 466
 467 int
 468 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
 469 {
 470         int rval;
 471         uint32_t cnt;
 472         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 473
 474         WRT_REG_DWORD(&reg->flash_data, data);
 475         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 476         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 477         /* Wait for Write cycle to complete. */
 478         rval = QLA_SUCCESS;
 479         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 480             rval == QLA_SUCCESS; cnt--) {
 481                 if (cnt)
 482                         udelay(10);
 483                 else
 484                         rval = QLA_FUNCTION_TIMEOUT;
 485         }
 486         return rval;
 487 }
 488
 489 void
 490 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
 491     uint8_t *flash_id)
 492 {
 493         uint32_t ids;
 494
 495         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
 496         *man_id = LSB(ids);
 497         *flash_id = MSB(ids);
 498 }
 499
 500 int
 501 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 502     uint32_t dwords)
 503 {
 504         int ret;
 505         uint32_t liter;
 506         uint32_t sec_mask, rest_addr, conf_addr;
 507         uint32_t fdata;
 508         uint8_t man_id, flash_id;
 509         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 510
 511         ret = QLA_SUCCESS;
 512
 513         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 514         DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
 515             ha->host_no, man_id, flash_id));
 516
 517         conf_addr = flash_conf_to_access_addr(0x03d8);
 518         switch (man_id) {
 519         case 0xbf: /* STT flash. */
 520                 rest_addr = 0x1fff;
 521                 sec_mask = 0x3e000;
 522                 if (flash_id == 0x80)
 523                         conf_addr = flash_conf_to_access_addr(0x0352);
 524                 break;
 525         case 0x13: /* ST M25P80. */
 526                 rest_addr = 0x3fff;
 527                 sec_mask = 0x3c000;
 528                 break;
 529         default:
 530                 /* Default to 64 kb sector size. */
 531                 rest_addr = 0x3fff;
 532                 sec_mask = 0x3c000;
 533                 break;
 534         }
 535
 536         /* Enable flash write. */
 537         WRT_REG_DWORD(&reg->ctrl_status,
 538             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 539         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 540
 541         /* Disable flash write-protection. */
 542         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 543
 544         do {    /* Loop once to provide quick error exit. */
 545                 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
 546                         /* Are we at the beginning of a sector? */
 547                         if ((faddr & rest_addr) == 0) {
 548                                 fdata = (faddr & sec_mask) << 2;
 549                                 ret = qla24xx_write_flash_dword(ha, conf_addr,
 550                                     (fdata & 0xff00) |((fdata << 16) &
 551                                     0xff0000) | ((fdata >> 16) & 0xff));
 552                                 if (ret != QLA_SUCCESS) {
 553                                         DEBUG9(printk("%s(%ld) Unable to flash "
 554                                             "sector: address=%x.\n", __func__,
 555                                             ha->host_no, faddr));
 556                                         break;
 557                                 }
 558                         }
 559                         ret = qla24xx_write_flash_dword(ha,
 560                             flash_data_to_access_addr(faddr),
 561                             cpu_to_le32(*dwptr));
 562                         if (ret != QLA_SUCCESS) {
 563                                 DEBUG9(printk("%s(%ld) Unable to program flash "
 564                                     "address=%x data=%x.\n", __func__,
 565                                     ha->host_no, faddr, *dwptr));
 566                                 break;
 567                         }
 568                 }
 569         } while (0);
 570
 571         /* Disable flash write. */
 572         WRT_REG_DWORD(&reg->ctrl_status,
 573             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 574         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 575
 576         return ret;
 577 }
 578
 579 uint8_t *
 580 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 581     uint32_t bytes)
 582 {
 583         uint32_t i;
 584         uint16_t *wptr;
 585
 586         /* Word reads to NVRAM via registers. */
 587         wptr = (uint16_t *)buf;
 588         qla2x00_lock_nvram_access(ha);
 589         for (i = 0; i < bytes >> 1; i++, naddr++)
 590                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
 591                     naddr));
 592         qla2x00_unlock_nvram_access(ha);
 593
 594         return buf;
 595 }
 596
 597 uint8_t *
 598 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 599     uint32_t bytes)
 600 {
 601         uint32_t i;
 602         uint32_t *dwptr;
 603
 604         /* Dword reads to flash. */
 605         dwptr = (uint32_t *)buf;
 606         for (i = 0; i < bytes >> 2; i++, naddr++)
 607                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 608                     nvram_data_to_access_addr(naddr)));
 609
 610         return buf;
 611 }
 612
 613 int
 614 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 615     uint32_t bytes)
 616 {
 617         int ret, stat;
 618         uint32_t i;
 619         uint16_t *wptr;
 620
 621         ret = QLA_SUCCESS;
 622
 623         qla2x00_lock_nvram_access(ha);
 624
 625         /* Disable NVRAM write-protection. */
 626         stat = qla2x00_clear_nvram_protection(ha);
 627
 628         wptr = (uint16_t *)buf;
 629         for (i = 0; i < bytes >> 1; i++, naddr++) {
 630                 qla2x00_write_nvram_word(ha, naddr,
 631                     cpu_to_le16(*wptr));
 632                 wptr++;
 633         }
 634
 635         /* Enable NVRAM write-protection. */
 636         qla2x00_set_nvram_protection(ha, stat);
 637
 638         qla2x00_unlock_nvram_access(ha);
 639
 640         return ret;
 641 }
 642
 643 int
 644 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 645     uint32_t bytes)
 646 {
 647         int ret;
 648         uint32_t i;
 649         uint32_t *dwptr;
 650         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 651
 652         ret = QLA_SUCCESS;
 653
 654         /* Enable flash write. */
 655         WRT_REG_DWORD(&reg->ctrl_status,
 656             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 657         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 658
 659         /* Disable NVRAM write-protection. */
 660         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 661             0);
 662         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 663             0);
 664
 665         /* Dword writes to flash. */
 666         dwptr = (uint32_t *)buf;
 667         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
 668                 ret = qla24xx_write_flash_dword(ha,
 669                     nvram_data_to_access_addr(naddr),
 670                     cpu_to_le32(*dwptr));
 671                 if (ret != QLA_SUCCESS) {
 672                         DEBUG9(printk("%s(%ld) Unable to program "
 673                             "nvram address=%x data=%x.\n", __func__,
 674                             ha->host_no, naddr, *dwptr));
 675                         break;
 676                 }
 677         }
 678
 679         /* Enable NVRAM write-protection. */
 680         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 681             0x8c);
 682
 683         /* Disable flash write. */
 684         WRT_REG_DWORD(&reg->ctrl_status,
 685             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 686         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 687
 688         return ret;
 689 }