2 * Copyright (c) 2000-2009 LSI Corporation.
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
11 * mpi2.h Version: 02.00.13
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
54 * Added RAID Accelerator functionality.
55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
56 * --------------------------------------------------------------------------
63 /*****************************************************************************
65 * MPI Version Definitions
67 *****************************************************************************/
69 #define MPI2_VERSION_MAJOR (0x02)
70 #define MPI2_VERSION_MINOR (0x00)
71 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
72 #define MPI2_VERSION_MAJOR_SHIFT (8)
73 #define MPI2_VERSION_MINOR_MASK (0x00FF)
74 #define MPI2_VERSION_MINOR_SHIFT (0)
75 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
78 #define MPI2_VERSION_02_00 (0x0200)
80 /* versioning for this MPI header set */
81 #define MPI2_HEADER_VERSION_UNIT (0x0D)
82 #define MPI2_HEADER_VERSION_DEV (0x00)
83 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
84 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
85 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
86 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
87 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
90 /*****************************************************************************
92 * IOC State Definitions
94 *****************************************************************************/
96 #define MPI2_IOC_STATE_RESET (0x00000000)
97 #define MPI2_IOC_STATE_READY (0x10000000)
98 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
99 #define MPI2_IOC_STATE_FAULT (0x40000000)
101 #define MPI2_IOC_STATE_MASK (0xF0000000)
102 #define MPI2_IOC_STATE_SHIFT (28)
104 /* Fault state range for prodcut specific codes */
105 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
106 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
109 /*****************************************************************************
111 * System Interface Register Definitions
113 *****************************************************************************/
115 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
117 U32 Doorbell; /* 0x00 */
118 U32 WriteSequence; /* 0x04 */
119 U32 HostDiagnostic; /* 0x08 */
120 U32 Reserved1; /* 0x0C */
121 U32 DiagRWData; /* 0x10 */
122 U32 DiagRWAddressLow; /* 0x14 */
123 U32 DiagRWAddressHigh; /* 0x18 */
124 U32 Reserved2[5]; /* 0x1C */
125 U32 HostInterruptStatus; /* 0x30 */
126 U32 HostInterruptMask; /* 0x34 */
127 U32 DCRData; /* 0x38 */
128 U32 DCRAddress; /* 0x3C */
129 U32 Reserved3[2]; /* 0x40 */
130 U32 ReplyFreeHostIndex; /* 0x48 */
131 U32 Reserved4[8]; /* 0x4C */
132 U32 ReplyPostHostIndex; /* 0x6C */
133 U32 Reserved5; /* 0x70 */
134 U32 HCBSize; /* 0x74 */
135 U32 HCBAddressLow; /* 0x78 */
136 U32 HCBAddressHigh; /* 0x7C */
137 U32 Reserved6[16]; /* 0x80 */
138 U32 RequestDescriptorPostLow; /* 0xC0 */
139 U32 RequestDescriptorPostHigh; /* 0xC4 */
140 U32 Reserved7[14]; /* 0xC8 */
141 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
142 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
145 * Defines for working with the Doorbell register.
147 #define MPI2_DOORBELL_OFFSET (0x00000000)
149 /* IOC --> System values */
150 #define MPI2_DOORBELL_USED (0x08000000)
151 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
152 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
153 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
154 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
156 /* System --> IOC values */
157 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
158 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
159 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
160 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
164 * Defines for the WriteSequence register
166 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
167 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
168 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
169 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
170 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
171 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
172 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
173 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
174 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
177 * Defines for the HostDiagnostic register
179 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
181 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
182 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
183 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
185 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
186 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
187 #define MPI2_DIAG_HCB_MODE (0x00000100)
188 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
189 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
190 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
191 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
192 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
193 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
196 * Offsets for DiagRWData and address
198 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
199 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
200 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
203 * Defines for the HostInterruptStatus register
205 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
206 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
207 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
208 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
209 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
210 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
211 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
214 * Defines for the HostInterruptMask register
216 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
217 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
218 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
219 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
220 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
221 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
224 * Offsets for DCRData and address
226 #define MPI2_DCR_DATA_OFFSET (0x00000038)
227 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
230 * Offset for the Reply Free Queue
232 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
235 * Offset for the Reply Descriptor Post Queue
237 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
240 * Defines for the HCBSize and address
242 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
243 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
244 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
246 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
247 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
250 * Offsets for the Request Queue
252 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
253 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
256 /*****************************************************************************
258 * Message Descriptors
260 *****************************************************************************/
262 /* Request Descriptors */
264 /* Default Request Descriptor */
265 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
267 U8 RequestFlags; /* 0x00 */
268 U8 MSIxIndex; /* 0x01 */
271 U16 DescriptorTypeDependent; /* 0x06 */
272 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
273 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
274 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
276 /* defines for the RequestFlags field */
277 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
278 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
279 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
280 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
281 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
282 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
284 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
287 /* High Priority Request Descriptor */
288 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
290 U8 RequestFlags; /* 0x00 */
291 U8 MSIxIndex; /* 0x01 */
294 U16 Reserved1; /* 0x06 */
295 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
296 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
297 Mpi2HighPriorityRequestDescriptor_t,
298 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
301 /* SCSI IO Request Descriptor */
302 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
304 U8 RequestFlags; /* 0x00 */
305 U8 MSIxIndex; /* 0x01 */
308 U16 DevHandle; /* 0x06 */
309 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
310 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
311 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
314 /* SCSI Target Request Descriptor */
315 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
317 U8 RequestFlags; /* 0x00 */
318 U8 MSIxIndex; /* 0x01 */
321 U16 IoIndex; /* 0x06 */
322 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
323 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
324 Mpi2SCSITargetRequestDescriptor_t,
325 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
328 /* RAID Accelerator Request Descriptor */
329 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
330 U8 RequestFlags; /* 0x00 */
331 U8 MSIxIndex; /* 0x01 */
334 U16 Reserved; /* 0x06 */
335 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
336 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
337 Mpi2RAIDAcceleratorRequestDescriptor_t,
338 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
341 /* union of Request Descriptors */
342 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
344 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
345 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
346 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
347 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
348 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
350 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
351 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
354 /* Reply Descriptors */
356 /* Default Reply Descriptor */
357 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
359 U8 ReplyFlags; /* 0x00 */
360 U8 MSIxIndex; /* 0x01 */
361 U16 DescriptorTypeDependent1; /* 0x02 */
362 U32 DescriptorTypeDependent2; /* 0x04 */
363 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
364 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
366 /* defines for the ReplyFlags field */
367 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
368 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
369 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
370 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
371 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
372 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
373 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
375 /* values for marking a reply descriptor as unused */
376 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
377 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
379 /* Address Reply Descriptor */
380 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
382 U8 ReplyFlags; /* 0x00 */
383 U8 MSIxIndex; /* 0x01 */
385 U32 ReplyFrameAddress; /* 0x04 */
386 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
387 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
389 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
392 /* SCSI IO Success Reply Descriptor */
393 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
395 U8 ReplyFlags; /* 0x00 */
396 U8 MSIxIndex; /* 0x01 */
398 U16 TaskTag; /* 0x04 */
399 U16 Reserved1; /* 0x06 */
400 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
401 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
402 Mpi2SCSIIOSuccessReplyDescriptor_t,
403 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
406 /* TargetAssist Success Reply Descriptor */
407 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
409 U8 ReplyFlags; /* 0x00 */
410 U8 MSIxIndex; /* 0x01 */
412 U8 SequenceNumber; /* 0x04 */
413 U8 Reserved1; /* 0x05 */
414 U16 IoIndex; /* 0x06 */
415 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
416 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
417 Mpi2TargetAssistSuccessReplyDescriptor_t,
418 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
421 /* Target Command Buffer Reply Descriptor */
422 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
424 U8 ReplyFlags; /* 0x00 */
425 U8 MSIxIndex; /* 0x01 */
428 U16 InitiatorDevHandle; /* 0x04 */
429 U16 IoIndex; /* 0x06 */
430 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
431 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
432 Mpi2TargetCommandBufferReplyDescriptor_t,
433 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
435 /* defines for Flags field */
436 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
439 /* RAID Accelerator Success Reply Descriptor */
440 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
441 U8 ReplyFlags; /* 0x00 */
442 U8 MSIxIndex; /* 0x01 */
444 U32 Reserved; /* 0x04 */
445 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
446 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
447 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
448 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
451 /* union of Reply Descriptors */
452 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
454 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
455 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
456 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
457 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
458 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
459 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
461 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
462 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
466 /*****************************************************************************
469 * 0x80 -> 0x8F reserved for private message use per product
472 *****************************************************************************/
474 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
475 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
476 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
477 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
478 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
479 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
480 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
481 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
482 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
483 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
484 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
485 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
486 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
487 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
488 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
489 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
490 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
491 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
492 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
493 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
494 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
495 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
496 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
497 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
498 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
499 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
503 /* Doorbell functions */
504 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
505 /* #define MPI2_FUNCTION_IO_UNIT_RESET (0x41) */
506 #define MPI2_FUNCTION_HANDSHAKE (0x42)
509 /*****************************************************************************
513 *****************************************************************************/
515 /* mask for IOCStatus status value */
516 #define MPI2_IOCSTATUS_MASK (0x7FFF)
518 /****************************************************************************
519 * Common IOCStatus values for all replies
520 ****************************************************************************/
522 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
523 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
524 #define MPI2_IOCSTATUS_BUSY (0x0002)
525 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
526 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
527 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
528 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
529 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
530 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
531 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
533 /****************************************************************************
534 * Config IOCStatus values
535 ****************************************************************************/
537 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
538 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
539 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
540 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
541 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
542 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
544 /****************************************************************************
546 ****************************************************************************/
548 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
549 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
550 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
551 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
552 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
553 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
554 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
555 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
556 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
557 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
558 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
559 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
561 /****************************************************************************
562 * For use by SCSI Initiator and SCSI Target end-to-end data protection
563 ****************************************************************************/
565 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
566 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
567 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
569 /****************************************************************************
571 ****************************************************************************/
573 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
574 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
575 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
576 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
577 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
578 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
579 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
580 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
581 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
582 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
584 /****************************************************************************
585 * Serial Attached SCSI values
586 ****************************************************************************/
588 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
589 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
591 /****************************************************************************
592 * Diagnostic Buffer Post / Diagnostic Release values
593 ****************************************************************************/
595 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
597 /****************************************************************************
598 * RAID Accelerator values
599 ****************************************************************************/
601 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
603 /****************************************************************************
604 * IOCStatus flag to indicate that log info is available
605 ****************************************************************************/
607 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
609 /****************************************************************************
611 ****************************************************************************/
613 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
614 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
615 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
616 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
617 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
618 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
619 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
620 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
623 /*****************************************************************************
625 * Standard Message Structures
627 *****************************************************************************/
629 /****************************************************************************
630 * Request Message Header for all request messages
631 ****************************************************************************/
633 typedef struct _MPI2_REQUEST_HEADER
635 U16 FunctionDependent1; /* 0x00 */
636 U8 ChainOffset; /* 0x02 */
637 U8 Function; /* 0x03 */
638 U16 FunctionDependent2; /* 0x04 */
639 U8 FunctionDependent3; /* 0x06 */
640 U8 MsgFlags; /* 0x07 */
643 U16 Reserved1; /* 0x0A */
644 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
645 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
648 /****************************************************************************
650 ****************************************************************************/
652 typedef struct _MPI2_DEFAULT_REPLY
654 U16 FunctionDependent1; /* 0x00 */
655 U8 MsgLength; /* 0x02 */
656 U8 Function; /* 0x03 */
657 U16 FunctionDependent2; /* 0x04 */
658 U8 FunctionDependent3; /* 0x06 */
659 U8 MsgFlags; /* 0x07 */
662 U16 Reserved1; /* 0x0A */
663 U16 FunctionDependent5; /* 0x0C */
664 U16 IOCStatus; /* 0x0E */
665 U32 IOCLogInfo; /* 0x10 */
666 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
667 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
670 /* common version structure/union used in messages and configuration pages */
672 typedef struct _MPI2_VERSION_STRUCT
678 } MPI2_VERSION_STRUCT;
680 typedef union _MPI2_VERSION_UNION
682 MPI2_VERSION_STRUCT Struct;
684 } MPI2_VERSION_UNION;
687 /* LUN field defines, common to many structures */
688 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
689 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
690 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
691 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
692 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
693 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
696 /*****************************************************************************
698 * Fusion-MPT MPI Scatter Gather Elements
700 *****************************************************************************/
702 /****************************************************************************
703 * MPI Simple Element structures
704 ****************************************************************************/
706 typedef struct _MPI2_SGE_SIMPLE32
710 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
711 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
713 typedef struct _MPI2_SGE_SIMPLE64
717 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
718 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
720 typedef struct _MPI2_SGE_SIMPLE_UNION
728 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
729 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
732 /****************************************************************************
733 * MPI Chain Element structures
734 ****************************************************************************/
736 typedef struct _MPI2_SGE_CHAIN32
742 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
743 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
745 typedef struct _MPI2_SGE_CHAIN64
751 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
752 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
754 typedef struct _MPI2_SGE_CHAIN_UNION
764 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
765 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
768 /****************************************************************************
769 * MPI Transaction Context Element structures
770 ****************************************************************************/
772 typedef struct _MPI2_SGE_TRANSACTION32
778 U32 TransactionContext[1];
779 U32 TransactionDetails[1];
780 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
781 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
783 typedef struct _MPI2_SGE_TRANSACTION64
789 U32 TransactionContext[2];
790 U32 TransactionDetails[1];
791 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
792 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
794 typedef struct _MPI2_SGE_TRANSACTION96
800 U32 TransactionContext[3];
801 U32 TransactionDetails[1];
802 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
803 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
805 typedef struct _MPI2_SGE_TRANSACTION128
811 U32 TransactionContext[4];
812 U32 TransactionDetails[1];
813 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
814 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
816 typedef struct _MPI2_SGE_TRANSACTION_UNION
824 U32 TransactionContext32[1];
825 U32 TransactionContext64[2];
826 U32 TransactionContext96[3];
827 U32 TransactionContext128[4];
829 U32 TransactionDetails[1];
830 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
831 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
834 /****************************************************************************
835 * MPI SGE union for IO SGL's
836 ****************************************************************************/
838 typedef struct _MPI2_MPI_SGE_IO_UNION
842 MPI2_SGE_SIMPLE_UNION Simple;
843 MPI2_SGE_CHAIN_UNION Chain;
845 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
846 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
849 /****************************************************************************
850 * MPI SGE union for SGL's with Simple and Transaction elements
851 ****************************************************************************/
853 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
857 MPI2_SGE_SIMPLE_UNION Simple;
858 MPI2_SGE_TRANSACTION_UNION Transaction;
860 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
861 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
864 /****************************************************************************
865 * All MPI SGE types union
866 ****************************************************************************/
868 typedef struct _MPI2_MPI_SGE_UNION
872 MPI2_SGE_SIMPLE_UNION Simple;
873 MPI2_SGE_CHAIN_UNION Chain;
874 MPI2_SGE_TRANSACTION_UNION Transaction;
876 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
877 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
880 /****************************************************************************
881 * MPI SGE field definition and masks
882 ****************************************************************************/
884 /* Flags field bit definitions */
886 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
887 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
888 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
889 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
890 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
891 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
892 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
894 #define MPI2_SGE_FLAGS_SHIFT (24)
896 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
897 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
901 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
902 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
903 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
904 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
906 /* Address location */
908 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
912 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
913 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
917 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
918 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
922 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
923 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
924 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
925 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
927 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
928 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
930 /****************************************************************************
931 * MPI SGE operation Macros
932 ****************************************************************************/
934 /* SIMPLE FlagsLength manipulations... */
935 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
936 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
937 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
938 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
940 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
942 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
943 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
944 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
946 /* CAUTION - The following are READ-MODIFY-WRITE! */
947 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
948 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
950 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
953 /*****************************************************************************
955 * Fusion-MPT IEEE Scatter Gather Elements
957 *****************************************************************************/
959 /****************************************************************************
960 * IEEE Simple Element structures
961 ****************************************************************************/
963 typedef struct _MPI2_IEEE_SGE_SIMPLE32
967 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
968 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
970 typedef struct _MPI2_IEEE_SGE_SIMPLE64
977 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
978 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
980 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
982 MPI2_IEEE_SGE_SIMPLE32 Simple32;
983 MPI2_IEEE_SGE_SIMPLE64 Simple64;
984 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
985 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
988 /****************************************************************************
989 * IEEE Chain Element structures
990 ****************************************************************************/
992 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
994 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
996 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
998 MPI2_IEEE_SGE_CHAIN32 Chain32;
999 MPI2_IEEE_SGE_CHAIN64 Chain64;
1000 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1001 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1004 /****************************************************************************
1005 * All IEEE SGE types union
1006 ****************************************************************************/
1008 typedef struct _MPI2_IEEE_SGE_UNION
1012 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1013 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1015 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1016 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1019 /****************************************************************************
1020 * IEEE SGE field definitions and masks
1021 ****************************************************************************/
1023 /* Flags field bit definitions */
1025 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1027 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1029 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1033 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1034 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1036 /* Data Location Address Space */
1038 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1039 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1040 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1041 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1042 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1045 /****************************************************************************
1046 * IEEE SGE operation Macros
1047 ****************************************************************************/
1049 /* SIMPLE FlagsLength manipulations... */
1050 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1051 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1052 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1054 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1056 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1057 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1058 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1060 /* CAUTION - The following are READ-MODIFY-WRITE! */
1061 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1062 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1067 /*****************************************************************************
1069 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1071 *****************************************************************************/
1073 typedef union _MPI2_SIMPLE_SGE_UNION
1075 MPI2_SGE_SIMPLE_UNION MpiSimple;
1076 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1077 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1078 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1081 typedef union _MPI2_SGE_IO_UNION
1083 MPI2_SGE_SIMPLE_UNION MpiSimple;
1084 MPI2_SGE_CHAIN_UNION MpiChain;
1085 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1086 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1087 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1088 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1091 /****************************************************************************
1093 * Values for SGLFlags field, used in many request messages with an SGL
1095 ****************************************************************************/
1097 /* values for MPI SGL Data Location Address Space subfield */
1098 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1099 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1100 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1101 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1102 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1103 /* values for SGL Type subfield */
1104 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1105 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1106 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1107 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)