drivers/scsi/megaraid/megaraid_sas_fusion.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2009-2013  LSI Corporation
   5  *  Copyright (c) 2013-2014  Avago Technologies
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  FILE: megaraid_sas_fusion.h
  21  *
  22  *  Authors: Avago Technologies
  23  *           Manoj Jose
  24  *           Sumant Patro
  25  *           Kashyap Desai <kashyap.desai@avagotech.com>
  26  *           Sumit Saxena <sumit.saxena@avagotech.com>
  27  *
  28  *  Send feedback to: megaraidlinux.pdl@avagotech.com
  29  *
  30  *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
  31  *  San Jose, California 95131
  32  */
  33
  34 #ifndef _MEGARAID_SAS_FUSION_H_
  35 #define _MEGARAID_SAS_FUSION_H_
  36
  37 /* Fusion defines */
  38 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
  39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
  40 #define MEGASAS_MAX_CHAIN_SHIFT                 5
  41 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK       0x400000
  42 #define MEGASAS_MAX_CHAIN_SIZE_MASK             0x3E0
  43 #define MEGASAS_256K_IO                         128
  44 #define MEGASAS_1MB_IO                          (MEGASAS_256K_IO * 4)
  45 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
  46 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST   0xF0
  47 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST         0xF1
  48 #define MEGASAS_LOAD_BALANCE_FLAG                   0x1
  49 #define MEGASAS_DCMD_MBOX_PEND_FLAG                 0x1
  50 #define HOST_DIAG_WRITE_ENABLE                      0x80
  51 #define HOST_DIAG_RESET_ADAPTER                     0x4
  52 #define MEGASAS_FUSION_MAX_RESET_TRIES              3
  53 #define MAX_MSIX_QUEUES_FUSION                      128
  54
  55 /* Invader defines */
  56 #define MPI2_TYPE_CUDA                              0x2
  57 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH   0x4000
  58 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0          0x00
  59 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1          0x10
  60 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA          0x80
  61 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                  0x8
  62 #define MR_RL_WRITE_THROUGH_MODE                    0x00
  63 #define MR_RL_WRITE_BACK_MODE                       0x01
  64
  65 /* T10 PI defines */
  66 #define MR_PROT_INFO_TYPE_CONTROLLER                0x8
  67 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD            0x7f
  68 #define MEGASAS_SCSI_SERVICE_ACTION_READ32          0x9
  69 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32         0xB
  70 #define MEGASAS_SCSI_ADDL_CDB_LEN                   0x18
  71 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL             0x20
  72 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE            0x60
  73
  74 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
  75 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
  76
  77 /*
  78  * Raid context flags
  79  */
  80
  81 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT   0x4
  82 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK    0x30
  83 enum MR_RAID_FLAGS_IO_SUB_TYPE {
  84         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
  85         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
  86         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA     = 2,
  87         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P        = 3,
  88         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q        = 4,
  89         MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
  90         MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
  91 };
  92
  93 /*
  94  * Request descriptor types
  95  */
  96 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO           0x7
  97 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA             0x1
  98 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK         0x2
  99 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT      1
 100
 101 #define MEGASAS_FP_CMD_LEN      16
 102 #define MEGASAS_FUSION_IN_RESET 0
 103 #define THRESHOLD_REPLY_COUNT 50
 104 #define RAID_1_PEER_CMDS 2
 105 #define JBOD_MAPS_COUNT 2
 106
 107 /*
 108  * Raid Context structure which describes MegaRAID specific IO Parameters
 109  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 110  */
 111
 112 struct RAID_CONTEXT {
 113 #if   defined(__BIG_ENDIAN_BITFIELD)
 114         u8 nseg:4;
 115         u8 type:4;
 116 #else
 117         u8 type:4;
 118         u8 nseg:4;
 119 #endif
 120         u8 resvd0;
 121         __le16 timeout_value;
 122         u8 reg_lock_flags;
 123         u8 resvd1;
 124         __le16 virtual_disk_tgt_id;
 125         __le64 reg_lock_row_lba;
 126         __le32 reg_lock_length;
 127         __le16 next_lmid;
 128         u8 ex_status;
 129         u8 status;
 130         u8 raid_flags;
 131         u8 num_sge;
 132         __le16 config_seq_num;
 133         u8 span_arm;
 134         u8 priority;
 135         u8 num_sge_ext;
 136         u8 resvd2;
 137 };
 138
 139 /*
 140  * Raid Context structure which describes ventura MegaRAID specific
 141  * IO Paramenters ,This resides at offset 0x60 where the SGL normally
 142  * starts in MPT IO Frames
 143  */
 144 struct RAID_CONTEXT_G35 {
 145         #define RAID_CONTEXT_NSEG_MASK  0x00F0
 146         #define RAID_CONTEXT_NSEG_SHIFT 4
 147         #define RAID_CONTEXT_TYPE_MASK  0x000F
 148         #define RAID_CONTEXT_TYPE_SHIFT 0
 149         u16             nseg_type;
 150         u16 timeout_value; /* 0x02 -0x03 */
 151         u16             routing_flags;  // 0x04 -0x05 routing flags
 152         u16 virtual_disk_tgt_id;   /* 0x06 -0x07 */
 153         u64 reg_lock_row_lba;      /* 0x08 - 0x0F */
 154         u32 reg_lock_length;      /* 0x10 - 0x13 */
 155         union {
 156                 u16 next_lmid; /* 0x14 - 0x15 */
 157                 u16     peer_smid;      /* used for the raid 1/10 fp writes */
 158         } smid;
 159         u8 ex_status;       /* 0x16 : OUT */
 160         u8 status;          /* 0x17 status */
 161         u8 raid_flags;          /* 0x18 resvd[7:6], ioSubType[5:4],
 162                                  * resvd[3:1], preferredCpu[0]
 163                                  */
 164         u8 span_arm;            /* 0x1C span[7:5], arm[4:0] */
 165         u16     config_seq_num;           /* 0x1A -0x1B */
 166         union {
 167                 /*
 168                  * Bit format:
 169                  *       ---------------------------------
 170                  *       | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
 171                  *       ---------------------------------
 172                  * Byte0 |    numSGE[7]- numSGE[0]       |
 173                  *       ---------------------------------
 174                  * Byte1 |SD | resvd     | numSGE 8-11   |
 175                  *        --------------------------------
 176                  */
 177                 #define NUM_SGE_MASK_LOWER      0xFF
 178                 #define NUM_SGE_MASK_UPPER      0x0F
 179                 #define NUM_SGE_SHIFT_UPPER     8
 180                 #define STREAM_DETECT_SHIFT     7
 181                 #define STREAM_DETECT_MASK      0x80
 182                 struct {
 183 #if   defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
 184                         u16 stream_detected:1;
 185                         u16 reserved:3;
 186                         u16 num_sge:12;
 187 #else
 188                         u16 num_sge:12;
 189                         u16 reserved:3;
 190                         u16 stream_detected:1;
 191 #endif
 192                 } bits;
 193                 u8 bytes[2];
 194         } u;
 195         u8 resvd2[2];          /* 0x1E-0x1F */
 196 };
 197
 198 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT      1
 199 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT      2
 200 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT      3
 201 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT      4
 202 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT      5
 203 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT       6
 204 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT      7
 205 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT   8
 206 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK    0x0F00
 207 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT        12
 208 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
 209
 210 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
 211                                u16 sge_count)
 212 {
 213         rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
 214         rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
 215                                                         & NUM_SGE_MASK_UPPER);
 216 }
 217
 218 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
 219 {
 220         u16 sge_count;
 221
 222         sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
 223                         << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
 224         return sge_count;
 225 }
 226
 227 #define SET_STREAM_DETECTED(rctx_g35) \
 228         (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
 229
 230 #define CLEAR_STREAM_DETECTED(rctx_g35) \
 231         (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
 232
 233 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
 234 {
 235         return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
 236 }
 237
 238 union RAID_CONTEXT_UNION {
 239         struct RAID_CONTEXT raid_context;
 240         struct RAID_CONTEXT_G35 raid_context_g35;
 241 };
 242
 243 #define RAID_CTX_SPANARM_ARM_SHIFT      (0)
 244 #define RAID_CTX_SPANARM_ARM_MASK       (0x1f)
 245
 246 #define RAID_CTX_SPANARM_SPAN_SHIFT     (5)
 247 #define RAID_CTX_SPANARM_SPAN_MASK      (0xE0)
 248
 249 /* number of bits per index in U32 TrackStream */
 250 #define BITS_PER_INDEX_STREAM           4
 251 #define INVALID_STREAM_NUM              16
 252 #define MR_STREAM_BITMAP                0x76543210
 253 #define STREAM_MASK                     ((1 << BITS_PER_INDEX_STREAM) - 1)
 254 #define ZERO_LAST_STREAM                0x0fffffff
 255 #define MAX_STREAMS_TRACKED             8
 256
 257 /*
 258  * define region lock types
 259  */
 260 enum REGION_TYPE {
 261         REGION_TYPE_UNUSED       = 0,
 262         REGION_TYPE_SHARED_READ  = 1,
 263         REGION_TYPE_SHARED_WRITE = 2,
 264         REGION_TYPE_EXCLUSIVE    = 3,
 265 };
 266
 267 /* MPI2 defines */
 268 #define MPI2_FUNCTION_IOC_INIT              (0x02) /* IOC Init */
 269 #define MPI2_WHOINIT_HOST_DRIVER            (0x04)
 270 #define MPI2_VERSION_MAJOR                  (0x02)
 271 #define MPI2_VERSION_MINOR                  (0x00)
 272 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 273 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 274 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 275 #define MPI2_VERSION_MINOR_SHIFT            (0)
 276 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 277                       MPI2_VERSION_MINOR)
 278 #define MPI2_HEADER_VERSION_UNIT            (0x10)
 279 #define MPI2_HEADER_VERSION_DEV             (0x00)
 280 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 281 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 282 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 283 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 284 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
 285                              MPI2_HEADER_VERSION_DEV)
 286 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
 287 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG        (0x8000)
 288 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG          (0x0400)
 289 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP       (0x0003)
 290 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG          (0x0200)
 291 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD           (0x0100)
 292 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP             (0x0004)
 293 /* EEDP escape mode */
 294 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE  (0x0040)
 295 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 296 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01)
 297 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY       (0x03)
 298 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO               (0x06)
 299 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 300 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 301 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
 302 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
 303 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK       (0x0E)
 304 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED          (0x0F)
 305 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 306 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK       (0x0F)
 307 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 308 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 309 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 310 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 311 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 312 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 313 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 314 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 315
 316 struct MPI25_IEEE_SGE_CHAIN64 {
 317         __le64                  Address;
 318         __le32                  Length;
 319         __le16                  Reserved1;
 320         u8                      NextChainOffset;
 321         u8                      Flags;
 322 };
 323
 324 struct MPI2_SGE_SIMPLE_UNION {
 325         __le32                     FlagsLength;
 326         union {
 327                 __le32                 Address32;
 328                 __le64                 Address64;
 329         } u;
 330 };
 331
 332 struct MPI2_SCSI_IO_CDB_EEDP32 {
 333         u8                      CDB[20];                    /* 0x00 */
 334         __be32                  PrimaryReferenceTag;        /* 0x14 */
 335         __be16                  PrimaryApplicationTag;      /* 0x18 */
 336         __be16                  PrimaryApplicationTagMask;  /* 0x1A */
 337         __le32                  TransferLength;             /* 0x1C */
 338 };
 339
 340 struct MPI2_SGE_CHAIN_UNION {
 341         __le16                  Length;
 342         u8                      NextChainOffset;
 343         u8                      Flags;
 344         union {
 345                 __le32          Address32;
 346                 __le64          Address64;
 347         } u;
 348 };
 349
 350 struct MPI2_IEEE_SGE_SIMPLE32 {
 351         __le32                  Address;
 352         __le32                  FlagsLength;
 353 };
 354
 355 struct MPI2_IEEE_SGE_CHAIN32 {
 356         __le32                  Address;
 357         __le32                  FlagsLength;
 358 };
 359
 360 struct MPI2_IEEE_SGE_SIMPLE64 {
 361         __le64                  Address;
 362         __le32                  Length;
 363         __le16                  Reserved1;
 364         u8                      Reserved2;
 365         u8                      Flags;
 366 };
 367
 368 struct MPI2_IEEE_SGE_CHAIN64 {
 369         __le64                  Address;
 370         __le32                  Length;
 371         __le16                  Reserved1;
 372         u8                      Reserved2;
 373         u8                      Flags;
 374 };
 375
 376 union MPI2_IEEE_SGE_SIMPLE_UNION {
 377         struct MPI2_IEEE_SGE_SIMPLE32  Simple32;
 378         struct MPI2_IEEE_SGE_SIMPLE64  Simple64;
 379 };
 380
 381 union MPI2_IEEE_SGE_CHAIN_UNION {
 382         struct MPI2_IEEE_SGE_CHAIN32   Chain32;
 383         struct MPI2_IEEE_SGE_CHAIN64   Chain64;
 384 };
 385
 386 union MPI2_SGE_IO_UNION {
 387         struct MPI2_SGE_SIMPLE_UNION       MpiSimple;
 388         struct MPI2_SGE_CHAIN_UNION        MpiChain;
 389         union MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
 390         union MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
 391 };
 392
 393 union MPI2_SCSI_IO_CDB_UNION {
 394         u8                      CDB32[32];
 395         struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 396         struct MPI2_SGE_SIMPLE_UNION SGE;
 397 };
 398
 399 /****************************************************************************
 400 *  SCSI Task Management messages
 401 ****************************************************************************/
 402
 403 /*SCSI Task Management Request Message */
 404 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
 405         u16 DevHandle;          /*0x00 */
 406         u8 ChainOffset;         /*0x02 */
 407         u8 Function;            /*0x03 */
 408         u8 Reserved1;           /*0x04 */
 409         u8 TaskType;            /*0x05 */
 410         u8 Reserved2;           /*0x06 */
 411         u8 MsgFlags;            /*0x07 */
 412         u8 VP_ID;               /*0x08 */
 413         u8 VF_ID;               /*0x09 */
 414         u16 Reserved3;          /*0x0A */
 415         u8 LUN[8];              /*0x0C */
 416         u32 Reserved4[7];       /*0x14 */
 417         u16 TaskMID;            /*0x30 */
 418         u16 Reserved5;          /*0x32 */
 419 };
 420
 421
 422 /*SCSI Task Management Reply Message */
 423 struct MPI2_SCSI_TASK_MANAGE_REPLY {
 424         u16 DevHandle;          /*0x00 */
 425         u8 MsgLength;           /*0x02 */
 426         u8 Function;            /*0x03 */
 427         u8 ResponseCode;        /*0x04 */
 428         u8 TaskType;            /*0x05 */
 429         u8 Reserved1;           /*0x06 */
 430         u8 MsgFlags;            /*0x07 */
 431         u8 VP_ID;               /*0x08 */
 432         u8 VF_ID;               /*0x09 */
 433         u16 Reserved2;          /*0x0A */
 434         u16 Reserved3;          /*0x0C */
 435         u16 IOCStatus;          /*0x0E */
 436         u32 IOCLogInfo;         /*0x10 */
 437         u32 TerminationCount;   /*0x14 */
 438         u32 ResponseInfo;       /*0x18 */
 439 };
 440
 441 struct MR_TM_REQUEST {
 442         char request[128];
 443 };
 444
 445 struct MR_TM_REPLY {
 446         char reply[128];
 447 };
 448
 449 /* SCSI Task Management Request Message */
 450 struct MR_TASK_MANAGE_REQUEST {
 451         /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
 452         struct MR_TM_REQUEST         TmRequest;
 453         union {
 454                 struct {
 455 #if   defined(__BIG_ENDIAN_BITFIELD)
 456                         u32 reserved1:30;
 457                         u32 isTMForPD:1;
 458                         u32 isTMForLD:1;
 459 #else
 460                         u32 isTMForLD:1;
 461                         u32 isTMForPD:1;
 462                         u32 reserved1:30;
 463 #endif
 464                         u32 reserved2;
 465                 } tmReqFlags;
 466                 struct MR_TM_REPLY   TMReply;
 467         };
 468 };
 469
 470 /* TaskType values */
 471
 472 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK           (0x01)
 473 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET        (0x02)
 474 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET         (0x03)
 475 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET   (0x05)
 476 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET       (0x06)
 477 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK           (0x07)
 478 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA              (0x08)
 479 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET         (0x09)
 480 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT      (0x0A)
 481
 482 /* ResponseCode values */
 483
 484 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE               (0x00)
 485 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME             (0x02)
 486 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED          (0x04)
 487 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED                 (0x05)
 488 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED              (0x08)
 489 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN            (0x09)
 490 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG         (0x0A)
 491 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC          (0x80)
 492
 493 /*
 494  * RAID SCSI IO Request Message
 495  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
 496  */
 497 struct MPI2_RAID_SCSI_IO_REQUEST {
 498         __le16                  DevHandle;                      /* 0x00 */
 499         u8                      ChainOffset;                    /* 0x02 */
 500         u8                      Function;                       /* 0x03 */
 501         __le16                  Reserved1;                      /* 0x04 */
 502         u8                      Reserved2;                      /* 0x06 */
 503         u8                      MsgFlags;                       /* 0x07 */
 504         u8                      VP_ID;                          /* 0x08 */
 505         u8                      VF_ID;                          /* 0x09 */
 506         __le16                  Reserved3;                      /* 0x0A */
 507         __le32                  SenseBufferLowAddress;          /* 0x0C */
 508         __le16                  SGLFlags;                       /* 0x10 */
 509         u8                      SenseBufferLength;              /* 0x12 */
 510         u8                      Reserved4;                      /* 0x13 */
 511         u8                      SGLOffset0;                     /* 0x14 */
 512         u8                      SGLOffset1;                     /* 0x15 */
 513         u8                      SGLOffset2;                     /* 0x16 */
 514         u8                      SGLOffset3;                     /* 0x17 */
 515         __le32                  SkipCount;                      /* 0x18 */
 516         __le32                  DataLength;                     /* 0x1C */
 517         __le32                  BidirectionalDataLength;        /* 0x20 */
 518         __le16                  IoFlags;                        /* 0x24 */
 519         __le16                  EEDPFlags;                      /* 0x26 */
 520         __le32                  EEDPBlockSize;                  /* 0x28 */
 521         __le32                  SecondaryReferenceTag;          /* 0x2C */
 522         __le16                  SecondaryApplicationTag;        /* 0x30 */
 523         __le16                  ApplicationTagTranslationMask;  /* 0x32 */
 524         u8                      LUN[8];                         /* 0x34 */
 525         __le32                  Control;                        /* 0x3C */
 526         union MPI2_SCSI_IO_CDB_UNION  CDB;                      /* 0x40 */
 527         union RAID_CONTEXT_UNION RaidContext;  /* 0x60 */
 528         union MPI2_SGE_IO_UNION       SGL;                      /* 0x80 */
 529 };
 530
 531 /*
 532  * MPT RAID MFA IO Descriptor.
 533  */
 534 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
 535         u32     RequestFlags:8;
 536         u32     MessageAddress1:24;
 537         u32     MessageAddress2;
 538 };
 539
 540 /* Default Request Descriptor */
 541 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 542         u8              RequestFlags;               /* 0x00 */
 543         u8              MSIxIndex;                  /* 0x01 */
 544         __le16          SMID;                       /* 0x02 */
 545         __le16          LMID;                       /* 0x04 */
 546         __le16          DescriptorTypeDependent;    /* 0x06 */
 547 };
 548
 549 /* High Priority Request Descriptor */
 550 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 551         u8              RequestFlags;               /* 0x00 */
 552         u8              MSIxIndex;                  /* 0x01 */
 553         __le16          SMID;                       /* 0x02 */
 554         __le16          LMID;                       /* 0x04 */
 555         __le16          Reserved1;                  /* 0x06 */
 556 };
 557
 558 /* SCSI IO Request Descriptor */
 559 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 560         u8              RequestFlags;               /* 0x00 */
 561         u8              MSIxIndex;                  /* 0x01 */
 562         __le16          SMID;                       /* 0x02 */
 563         __le16          LMID;                       /* 0x04 */
 564         __le16          DevHandle;                  /* 0x06 */
 565 };
 566
 567 /* SCSI Target Request Descriptor */
 568 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 569         u8              RequestFlags;               /* 0x00 */
 570         u8              MSIxIndex;                  /* 0x01 */
 571         __le16          SMID;                       /* 0x02 */
 572         __le16          LMID;                       /* 0x04 */
 573         __le16          IoIndex;                    /* 0x06 */
 574 };
 575
 576 /* RAID Accelerator Request Descriptor */
 577 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 578         u8              RequestFlags;               /* 0x00 */
 579         u8              MSIxIndex;                  /* 0x01 */
 580         __le16          SMID;                       /* 0x02 */
 581         __le16          LMID;                       /* 0x04 */
 582         __le16          Reserved;                   /* 0x06 */
 583 };
 584
 585 /* union of Request Descriptors */
 586 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
 587         struct MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 588         struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 589         struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 590         struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 591         struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 592         struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR      MFAIo;
 593         union {
 594                 struct {
 595                         __le32 low;
 596                         __le32 high;
 597                 } u;
 598                 __le64 Words;
 599         };
 600 };
 601
 602 /* Default Reply Descriptor */
 603 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
 604         u8              ReplyFlags;                 /* 0x00 */
 605         u8              MSIxIndex;                  /* 0x01 */
 606         __le16          DescriptorTypeDependent1;   /* 0x02 */
 607         __le32          DescriptorTypeDependent2;   /* 0x04 */
 608 };
 609
 610 /* Address Reply Descriptor */
 611 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
 612         u8              ReplyFlags;                 /* 0x00 */
 613         u8              MSIxIndex;                  /* 0x01 */
 614         __le16          SMID;                       /* 0x02 */
 615         __le32          ReplyFrameAddress;          /* 0x04 */
 616 };
 617
 618 /* SCSI IO Success Reply Descriptor */
 619 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 620         u8              ReplyFlags;                 /* 0x00 */
 621         u8              MSIxIndex;                  /* 0x01 */
 622         __le16          SMID;                       /* 0x02 */
 623         __le16          TaskTag;                    /* 0x04 */
 624         __le16          Reserved1;                  /* 0x06 */
 625 };
 626
 627 /* TargetAssist Success Reply Descriptor */
 628 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 629         u8              ReplyFlags;                 /* 0x00 */
 630         u8              MSIxIndex;                  /* 0x01 */
 631         __le16          SMID;                       /* 0x02 */
 632         u8              SequenceNumber;             /* 0x04 */
 633         u8              Reserved1;                  /* 0x05 */
 634         __le16          IoIndex;                    /* 0x06 */
 635 };
 636
 637 /* Target Command Buffer Reply Descriptor */
 638 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 639         u8              ReplyFlags;                 /* 0x00 */
 640         u8              MSIxIndex;                  /* 0x01 */
 641         u8              VP_ID;                      /* 0x02 */
 642         u8              Flags;                      /* 0x03 */
 643         __le16          InitiatorDevHandle;         /* 0x04 */
 644         __le16          IoIndex;                    /* 0x06 */
 645 };
 646
 647 /* RAID Accelerator Success Reply Descriptor */
 648 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 649         u8              ReplyFlags;                 /* 0x00 */
 650         u8              MSIxIndex;                  /* 0x01 */
 651         __le16          SMID;                       /* 0x02 */
 652         __le32          Reserved;                   /* 0x04 */
 653 };
 654
 655 /* union of Reply Descriptors */
 656 union MPI2_REPLY_DESCRIPTORS_UNION {
 657         struct MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 658         struct MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 659         struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 660         struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 661         struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 662         struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
 663         RAIDAcceleratorSuccess;
 664         __le64                                             Words;
 665 };
 666
 667 /* IOCInit Request message */
 668 struct MPI2_IOC_INIT_REQUEST {
 669         u8                      WhoInit;                        /* 0x00 */
 670         u8                      Reserved1;                      /* 0x01 */
 671         u8                      ChainOffset;                    /* 0x02 */
 672         u8                      Function;                       /* 0x03 */
 673         __le16                  Reserved2;                      /* 0x04 */
 674         u8                      Reserved3;                      /* 0x06 */
 675         u8                      MsgFlags;                       /* 0x07 */
 676         u8                      VP_ID;                          /* 0x08 */
 677         u8                      VF_ID;                          /* 0x09 */
 678         __le16                  Reserved4;                      /* 0x0A */
 679         __le16                  MsgVersion;                     /* 0x0C */
 680         __le16                  HeaderVersion;                  /* 0x0E */
 681         u32                     Reserved5;                      /* 0x10 */
 682         __le16                  Reserved6;                      /* 0x14 */
 683         u8                      HostPageSize;                   /* 0x16 */
 684         u8                      HostMSIxVectors;                /* 0x17 */
 685         __le16                  Reserved8;                      /* 0x18 */
 686         __le16                  SystemRequestFrameSize;         /* 0x1A */
 687         __le16                  ReplyDescriptorPostQueueDepth;  /* 0x1C */
 688         __le16                  ReplyFreeQueueDepth;            /* 0x1E */
 689         __le32                  SenseBufferAddressHigh;         /* 0x20 */
 690         __le32                  SystemReplyAddressHigh;         /* 0x24 */
 691         __le64                  SystemRequestFrameBaseAddress;  /* 0x28 */
 692         __le64                  ReplyDescriptorPostQueueAddress;/* 0x30 */
 693         __le64                  ReplyFreeQueueAddress;          /* 0x38 */
 694         __le64                  TimeStamp;                      /* 0x40 */
 695 };
 696
 697 /* mrpriv defines */
 698 #define MR_PD_INVALID 0xFFFF
 699 #define MR_DEVHANDLE_INVALID 0xFFFF
 700 #define MAX_SPAN_DEPTH 8
 701 #define MAX_QUAD_DEPTH  MAX_SPAN_DEPTH
 702 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
 703 #define MAX_ROW_SIZE 32
 704 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
 705 #define MAX_LOGICAL_DRIVES 64
 706 #define MAX_LOGICAL_DRIVES_EXT 256
 707 #define MAX_LOGICAL_DRIVES_DYN 512
 708 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
 709 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
 710 #define MAX_ARRAYS 128
 711 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
 712 #define MAX_ARRAYS_EXT  256
 713 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
 714 #define MAX_API_ARRAYS_DYN 512
 715 #define MAX_PHYSICAL_DEVICES 256
 716 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
 717 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
 718 #define MR_DCMD_LD_MAP_GET_INFO             0x0300e101
 719 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO      0x0200e102
 720 #define MR_DCMD_DRV_GET_TARGET_PROP         0x0200e103
 721 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC  0x010e8485   /* SR-IOV HB alloc*/
 722 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111   0x03200200
 723 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS       0x03150200
 724
 725 struct MR_DEV_HANDLE_INFO {
 726         __le16  curDevHdl;
 727         u8      validHandles;
 728         u8      interfaceType;
 729         __le16  devHandle[2];
 730 };
 731
 732 struct MR_ARRAY_INFO {
 733         __le16  pd[MAX_RAIDMAP_ROW_SIZE];
 734 };
 735
 736 struct MR_QUAD_ELEMENT {
 737         __le64     logStart;
 738         __le64     logEnd;
 739         __le64     offsetInSpan;
 740         __le32     diff;
 741         __le32     reserved1;
 742 };
 743
 744 struct MR_SPAN_INFO {
 745         __le32             noElements;
 746         __le32             reserved1;
 747         struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 748 };
 749
 750 struct MR_LD_SPAN {
 751         __le64   startBlk;
 752         __le64   numBlks;
 753         __le16   arrayRef;
 754         u8       spanRowSize;
 755         u8       spanRowDataSize;
 756         u8       reserved[4];
 757 };
 758
 759 struct MR_SPAN_BLOCK_INFO {
 760         __le64          num_rows;
 761         struct MR_LD_SPAN   span;
 762         struct MR_SPAN_INFO block_span_info;
 763 };
 764
 765 #define MR_RAID_CTX_CPUSEL_0            0
 766 #define MR_RAID_CTX_CPUSEL_1            1
 767 #define MR_RAID_CTX_CPUSEL_2            2
 768 #define MR_RAID_CTX_CPUSEL_3            3
 769 #define MR_RAID_CTX_CPUSEL_FCFS         0xF
 770
 771 struct MR_CPU_AFFINITY_MASK {
 772         union {
 773                 struct {
 774 #ifndef MFI_BIG_ENDIAN
 775                 u8 hw_path:1;
 776                 u8 cpu0:1;
 777                 u8 cpu1:1;
 778                 u8 cpu2:1;
 779                 u8 cpu3:1;
 780                 u8 reserved:3;
 781 #else
 782                 u8 reserved:3;
 783                 u8 cpu3:1;
 784                 u8 cpu2:1;
 785                 u8 cpu1:1;
 786                 u8 cpu0:1;
 787                 u8 hw_path:1;
 788 #endif
 789                 };
 790                 u8 core_mask;
 791         };
 792 };
 793
 794 struct MR_IO_AFFINITY {
 795         union {
 796                 struct {
 797                         struct MR_CPU_AFFINITY_MASK pdRead;
 798                         struct MR_CPU_AFFINITY_MASK pdWrite;
 799                         struct MR_CPU_AFFINITY_MASK ldRead;
 800                         struct MR_CPU_AFFINITY_MASK ldWrite;
 801                         };
 802                 u32 word;
 803                 };
 804         u8 maxCores;    /* Total cores + HW Path in ROC */
 805         u8 reserved[3];
 806 };
 807
 808 struct MR_LD_RAID {
 809         struct {
 810 #if   defined(__BIG_ENDIAN_BITFIELD)
 811                 u32 reserved4:2;
 812                 u32 fp_cache_bypass_capable:1;
 813                 u32 fp_rmw_capable:1;
 814                 u32 disable_coalescing:1;
 815                 u32     fpBypassRegionLock:1;
 816                 u32     tmCapable:1;
 817                 u32     fpNonRWCapable:1;
 818                 u32     fpReadAcrossStripe:1;
 819                 u32     fpWriteAcrossStripe:1;
 820                 u32     fpReadCapable:1;
 821                 u32     fpWriteCapable:1;
 822                 u32     encryptionType:8;
 823                 u32     pdPiMode:4;
 824                 u32     ldPiMode:4;
 825                 u32 reserved5:2;
 826                 u32 ra_capable:1;
 827                 u32     fpCapable:1;
 828 #else
 829                 u32     fpCapable:1;
 830                 u32 ra_capable:1;
 831                 u32 reserved5:2;
 832                 u32     ldPiMode:4;
 833                 u32     pdPiMode:4;
 834                 u32     encryptionType:8;
 835                 u32     fpWriteCapable:1;
 836                 u32     fpReadCapable:1;
 837                 u32     fpWriteAcrossStripe:1;
 838                 u32     fpReadAcrossStripe:1;
 839                 u32     fpNonRWCapable:1;
 840                 u32     tmCapable:1;
 841                 u32     fpBypassRegionLock:1;
 842                 u32 disable_coalescing:1;
 843                 u32 fp_rmw_capable:1;
 844                 u32 fp_cache_bypass_capable:1;
 845                 u32 reserved4:2;
 846 #endif
 847         } capability;
 848         __le32     reserved6;
 849         __le64     size;
 850         u8      spanDepth;
 851         u8      level;
 852         u8      stripeShift;
 853         u8      rowSize;
 854         u8      rowDataSize;
 855         u8      writeMode;
 856         u8      PRL;
 857         u8      SRL;
 858         __le16     targetId;
 859         u8      ldState;
 860         u8      regTypeReqOnWrite;
 861         u8      modFactor;
 862         u8      regTypeReqOnRead;
 863         __le16     seqNum;
 864
 865         struct {
 866                 u32 ldSyncRequired:1;
 867                 u32 reserved:31;
 868         } flags;
 869
 870         u8      LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
 871         u8      fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
 872         /* Ox2D This LD accept priority boost of this type */
 873         u8 ld_accept_priority_type;
 874         u8 reserved2[2];                /* 0x2E - 0x2F */
 875         /* 0x30 - 0x33, Logical block size for the LD */
 876         u32 logical_block_length;
 877         struct {
 878 #ifndef MFI_BIG_ENDIAN
 879         /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
 880         u32 ld_pi_exp:4;
 881         /* 0x34, LOGICAL BLOCKS PER PHYSICAL
 882          *  BLOCK EXPONENT from READ CAPACITY 16
 883          */
 884         u32 ld_logical_block_exp:4;
 885         u32 reserved1:24;           /* 0x34 */
 886 #else
 887         u32 reserved1:24;           /* 0x34 */
 888         /* 0x34, LOGICAL BLOCKS PER PHYSICAL
 889          *  BLOCK EXPONENT from READ CAPACITY 16
 890          */
 891         u32 ld_logical_block_exp:4;
 892         /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
 893         u32 ld_pi_exp:4;
 894 #endif
 895         };                               /* 0x34 - 0x37 */
 896          /* 0x38 - 0x3f, This will determine which
 897           *  core will process LD IO and PD IO.
 898           */
 899         struct MR_IO_AFFINITY cpuAffinity;
 900      /* Bit definiations are specified by MR_IO_AFFINITY */
 901         u8 reserved3[0x80 - 0x40];    /* 0x40 - 0x7f */
 902 };
 903
 904 struct MR_LD_SPAN_MAP {
 905         struct MR_LD_RAID          ldRaid;
 906         u8                  dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 907         struct MR_SPAN_BLOCK_INFO  spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 908 };
 909
 910 struct MR_FW_RAID_MAP {
 911         __le32                 totalSize;
 912         union {
 913                 struct {
 914                         __le32         maxLd;
 915                         __le32         maxSpanDepth;
 916                         __le32         maxRowSize;
 917                         __le32         maxPdCount;
 918                         __le32         maxArrays;
 919                 } validationInfo;
 920                 __le32             version[5];
 921         };
 922
 923         __le32                 ldCount;
 924         __le32                 Reserved1;
 925         u8                  ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
 926                                         MAX_RAIDMAP_VIEWS];
 927         u8                  fpPdIoTimeoutSec;
 928         u8                  reserved2[7];
 929         struct MR_ARRAY_INFO       arMapInfo[MAX_RAIDMAP_ARRAYS];
 930         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 931         struct MR_LD_SPAN_MAP      ldSpanMap[1];
 932 };
 933
 934 struct IO_REQUEST_INFO {
 935         u64 ldStartBlock;
 936         u32 numBlocks;
 937         u16 ldTgtId;
 938         u8 isRead;
 939         __le16 devHandle;
 940         u8 pd_interface;
 941         u64 pdBlock;
 942         u8 fpOkForIo;
 943         u8 IoforUnevenSpan;
 944         u8 start_span;
 945         u8 do_fp_rlbypass;
 946         u64 start_row;
 947         u8  span_arm;   /* span[7:5], arm[4:0] */
 948         u8  pd_after_lb;
 949         u16 r1_alt_dev_handle; /* raid 1/10 only */
 950         bool ra_capable;
 951 };
 952
 953 struct MR_LD_TARGET_SYNC {
 954         u8  targetId;
 955         u8  reserved;
 956         __le16 seqNum;
 957 };
 958
 959 /*
 960  * RAID Map descriptor Types.
 961  * Each element should uniquely idetify one data structure in the RAID map
 962  */
 963 enum MR_RAID_MAP_DESC_TYPE {
 964         /* MR_DEV_HANDLE_INFO data */
 965         RAID_MAP_DESC_TYPE_DEVHDL_INFO    = 0x0,
 966         /* target to Ld num Index map */
 967         RAID_MAP_DESC_TYPE_TGTID_INFO     = 0x1,
 968         /* MR_ARRAY_INFO data */
 969         RAID_MAP_DESC_TYPE_ARRAY_INFO     = 0x2,
 970         /* MR_LD_SPAN_MAP data */
 971         RAID_MAP_DESC_TYPE_SPAN_INFO      = 0x3,
 972         RAID_MAP_DESC_TYPE_COUNT,
 973 };
 974
 975 /*
 976  * This table defines the offset, size and num elements  of each descriptor
 977  * type in the RAID Map buffer
 978  */
 979 struct MR_RAID_MAP_DESC_TABLE {
 980         /* Raid map descriptor type */
 981         u32 raid_map_desc_type;
 982         /* Offset into the RAID map buffer where
 983          *  descriptor data is saved
 984          */
 985         u32 raid_map_desc_offset;
 986         /* total size of the
 987          * descriptor buffer
 988          */
 989         u32 raid_map_desc_buffer_size;
 990         /* Number of elements contained in the
 991          *  descriptor buffer
 992          */
 993         u32 raid_map_desc_elements;
 994 };
 995
 996 /*
 997  * Dynamic Raid Map Structure.
 998  */
 999 struct MR_FW_RAID_MAP_DYNAMIC {
1000         u32 raid_map_size;   /* total size of RAID Map structure */
1001         u32 desc_table_offset;/* Offset of desc table into RAID map*/
1002         u32 desc_table_size;  /* Total Size of desc table */
1003         /* Total Number of elements in the desc table */
1004         u32 desc_table_num_elements;
1005         u64     reserved1;
1006         u32     reserved2[3];   /*future use */
1007         /* timeout value used by driver in FP IOs */
1008         u8 fp_pd_io_timeout_sec;
1009         u8 reserved3[3];
1010         /* when this seqNum increments, driver needs to
1011          *  release RMW buffers asap
1012          */
1013         u32 rmw_fp_seq_num;
1014         u16 ld_count;   /* count of lds. */
1015         u16 ar_count;   /* count of arrays */
1016         u16 span_count; /* count of spans */
1017         u16 reserved4[3];
1018 /*
1019  * The below structure of pointers is only to be used by the driver.
1020  * This is added in the ,API to reduce the amount of code changes
1021  * needed in the driver to support dynamic RAID map Firmware should
1022  * not update these pointers while preparing the raid map
1023  */
1024         union {
1025                 struct {
1026                         struct MR_DEV_HANDLE_INFO  *dev_hndl_info;
1027                         u16 *ld_tgt_id_to_ld;
1028                         struct MR_ARRAY_INFO *ar_map_info;
1029                         struct MR_LD_SPAN_MAP *ld_span_map;
1030                         };
1031                 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1032                 };
1033 /*
1034  * RAID Map descriptor table defines the layout of data in the RAID Map.
1035  * The size of the descriptor table itself could change.
1036  */
1037         /* Variable Size descriptor Table. */
1038         struct MR_RAID_MAP_DESC_TABLE
1039                         raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1040         /* Variable Size buffer containing all data */
1041         u32 raid_map_desc_data[1];
1042 }; /* Dynamicaly sized RAID MAp structure */
1043
1044 #define IEEE_SGE_FLAGS_ADDR_MASK            (0x03)
1045 #define IEEE_SGE_FLAGS_SYSTEM_ADDR          (0x00)
1046 #define IEEE_SGE_FLAGS_IOCDDR_ADDR          (0x01)
1047 #define IEEE_SGE_FLAGS_IOCPLB_ADDR          (0x02)
1048 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR       (0x03)
1049 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT        (0x80)
1050 #define IEEE_SGE_FLAGS_END_OF_LIST          (0x40)
1051
1052 #define MPI2_SGE_FLAGS_SHIFT                (0x02)
1053 #define IEEE_SGE_FLAGS_FORMAT_MASK          (0xC0)
1054 #define IEEE_SGE_FLAGS_FORMAT_IEEE          (0x00)
1055 #define IEEE_SGE_FLAGS_FORMAT_NVME          (0x02)
1056
1057 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK           (0x1C)
1058 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE       (0x00)
1059 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP       (0x08)
1060 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL       (0x10)
1061
1062 struct megasas_register_set;
1063 struct megasas_instance;
1064
1065 union desc_word {
1066         u64 word;
1067         struct {
1068                 u32 low;
1069                 u32 high;
1070         } u;
1071 };
1072
1073 struct megasas_cmd_fusion {
1074         struct MPI2_RAID_SCSI_IO_REQUEST        *io_request;
1075         dma_addr_t                      io_request_phys_addr;
1076
1077         union MPI2_SGE_IO_UNION *sg_frame;
1078         dma_addr_t              sg_frame_phys_addr;
1079
1080         u8 *sense;
1081         dma_addr_t sense_phys_addr;
1082
1083         struct list_head list;
1084         struct scsi_cmnd *scmd;
1085         struct megasas_instance *instance;
1086
1087         u8 retry_for_fw_reset;
1088         union MEGASAS_REQUEST_DESCRIPTOR_UNION  *request_desc;
1089
1090         /*
1091          * Context for a MFI frame.
1092          * Used to get the mfi cmd from list when a MFI cmd is completed
1093          */
1094         u32 sync_cmd_idx;
1095         u32 index;
1096         u8 pd_r1_lb;
1097         struct completion done;
1098         u8 pd_interface;
1099         u16 r1_alt_dev_handle; /* raid 1/10 only*/
1100         bool cmd_completed;  /* raid 1/10 fp writes status holder */
1101
1102 };
1103
1104 struct LD_LOAD_BALANCE_INFO {
1105         u8      loadBalanceFlag;
1106         u8      reserved1;
1107         atomic_t     scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1108         u64     last_accessed_block[MAX_PHYSICAL_DEVICES];
1109 };
1110
1111 /* SPAN_SET is info caclulated from span info from Raid map per LD */
1112 typedef struct _LD_SPAN_SET {
1113         u64  log_start_lba;
1114         u64  log_end_lba;
1115         u64  span_row_start;
1116         u64  span_row_end;
1117         u64  data_strip_start;
1118         u64  data_strip_end;
1119         u64  data_row_start;
1120         u64  data_row_end;
1121         u8   strip_offset[MAX_SPAN_DEPTH];
1122         u32    span_row_data_width;
1123         u32    diff;
1124         u32    reserved[2];
1125 } LD_SPAN_SET, *PLD_SPAN_SET;
1126
1127 typedef struct LOG_BLOCK_SPAN_INFO {
1128         LD_SPAN_SET  span_set[MAX_SPAN_DEPTH];
1129 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1130
1131 struct MR_FW_RAID_MAP_ALL {
1132         struct MR_FW_RAID_MAP raidMap;
1133         struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1134 } __attribute__ ((packed));
1135
1136 struct MR_DRV_RAID_MAP {
1137         /* total size of this structure, including this field.
1138          * This feild will be manupulated by driver for ext raid map,
1139          * else pick the value from firmware raid map.
1140          */
1141         __le32                 totalSize;
1142
1143         union {
1144         struct {
1145                 __le32         maxLd;
1146                 __le32         maxSpanDepth;
1147                 __le32         maxRowSize;
1148                 __le32         maxPdCount;
1149                 __le32         maxArrays;
1150         } validationInfo;
1151         __le32             version[5];
1152         };
1153
1154         /* timeout value used by driver in FP IOs*/
1155         u8                  fpPdIoTimeoutSec;
1156         u8                  reserved2[7];
1157
1158         __le16                 ldCount;
1159         __le16                 arCount;
1160         __le16                 spanCount;
1161         __le16                 reserve3;
1162
1163         struct MR_DEV_HANDLE_INFO
1164                 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1165         u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1166         struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1167         struct MR_LD_SPAN_MAP      ldSpanMap[1];
1168
1169 };
1170
1171 /* Driver raid map size is same as raid map ext
1172  * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1173  * And it is mainly for code re-use purpose.
1174  */
1175 struct MR_DRV_RAID_MAP_ALL {
1176
1177         struct MR_DRV_RAID_MAP raidMap;
1178         struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1179 } __packed;
1180
1181
1182
1183 struct MR_FW_RAID_MAP_EXT {
1184         /* Not usred in new map */
1185         u32                 reserved;
1186
1187         union {
1188         struct {
1189                 u32         maxLd;
1190                 u32         maxSpanDepth;
1191                 u32         maxRowSize;
1192                 u32         maxPdCount;
1193                 u32         maxArrays;
1194         } validationInfo;
1195         u32             version[5];
1196         };
1197
1198         u8                  fpPdIoTimeoutSec;
1199         u8                  reserved2[7];
1200
1201         __le16                 ldCount;
1202         __le16                 arCount;
1203         __le16                 spanCount;
1204         __le16                 reserve3;
1205
1206         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1207         u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1208         struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
1209         struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1210 };
1211
1212 /*
1213  *  * define MR_PD_CFG_SEQ structure for system PDs
1214  *   */
1215 struct MR_PD_CFG_SEQ {
1216         u16 seqNum;
1217         u16 devHandle;
1218         struct {
1219 #if   defined(__BIG_ENDIAN_BITFIELD)
1220                 u8     reserved:7;
1221                 u8     tmCapable:1;
1222 #else
1223                 u8     tmCapable:1;
1224                 u8     reserved:7;
1225 #endif
1226         } capability;
1227         u8  reserved;
1228         u16 pd_target_id;
1229 } __packed;
1230
1231 struct MR_PD_CFG_SEQ_NUM_SYNC {
1232         __le32 size;
1233         __le32 count;
1234         struct MR_PD_CFG_SEQ seq[1];
1235 } __packed;
1236
1237 /* stream detection */
1238 struct STREAM_DETECT {
1239         u64 next_seq_lba; /* next LBA to match sequential access */
1240         struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1241         struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1242         u32 count_cmds_in_stream; /* count of host commands in this stream */
1243         u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1244         u8 is_read; /* SCSI OpCode for this stream */
1245         u8 group_depth; /* total number of host commands in group */
1246         /* TRUE if cannot add any more commands to this group */
1247         bool group_flush;
1248         u8 reserved[7]; /* pad to 64-bit alignment */
1249 };
1250
1251 struct LD_STREAM_DETECT {
1252         bool write_back; /* TRUE if WB, FALSE if WT */
1253         bool fp_write_enabled;
1254         bool members_ssds;
1255         bool fp_cache_bypass_capable;
1256         u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1257         /* this is the array of stream detect structures (one per stream) */
1258         struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1259 };
1260
1261 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1262         u64 RDPQBaseAddress;
1263         u32 Reserved1;
1264         u32 Reserved2;
1265 };
1266
1267 struct fusion_context {
1268         struct megasas_cmd_fusion **cmd_list;
1269         dma_addr_t req_frames_desc_phys;
1270         u8 *req_frames_desc;
1271
1272         struct dma_pool *io_request_frames_pool;
1273         dma_addr_t io_request_frames_phys;
1274         u8 *io_request_frames;
1275
1276         struct dma_pool *sg_dma_pool;
1277         struct dma_pool *sense_dma_pool;
1278
1279         dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1280         union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1281         struct dma_pool *reply_frames_desc_pool;
1282
1283         u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1284
1285         u32 reply_q_depth;
1286         u32 request_alloc_sz;
1287         u32 reply_alloc_sz;
1288         u32 io_frames_alloc_sz;
1289
1290         struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1291         dma_addr_t rdpq_phys;
1292         u16     max_sge_in_main_msg;
1293         u16     max_sge_in_chain;
1294
1295         u8      chain_offset_io_request;
1296         u8      chain_offset_mfi_pthru;
1297
1298         struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1299         dma_addr_t ld_map_phys[2];
1300
1301         /*Non dma-able memory. Driver local copy.*/
1302         struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1303
1304         u32 max_map_sz;
1305         u32 current_map_sz;
1306         u32 old_map_sz;
1307         u32 new_map_sz;
1308         u32 drv_map_sz;
1309         u32 drv_map_pages;
1310         struct MR_PD_CFG_SEQ_NUM_SYNC   *pd_seq_sync[JBOD_MAPS_COUNT];
1311         dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1312         u8 fast_path_io;
1313         struct LD_LOAD_BALANCE_INFO *load_balance_info;
1314         u32 load_balance_info_pages;
1315         LD_SPAN_INFO *log_to_span;
1316         u32 log_to_span_pages;
1317         struct LD_STREAM_DETECT **stream_detect_by_ld;
1318         dma_addr_t ioc_init_request_phys;
1319         struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
1320
1321 };
1322
1323 union desc_value {
1324         __le64 word;
1325         struct {
1326                 __le32 low;
1327                 __le32 high;
1328         } u;
1329 };
1330
1331 void megasas_free_cmds_fusion(struct megasas_instance *instance);
1332 int megasas_ioc_init_fusion(struct megasas_instance *instance);
1333 u8 megasas_get_map_info(struct megasas_instance *instance);
1334 int megasas_sync_map_info(struct megasas_instance *instance);
1335 void megasas_release_fusion(struct megasas_instance *instance);
1336 void megasas_reset_reply_desc(struct megasas_instance *instance);
1337 int megasas_check_mpio_paths(struct megasas_instance *instance,
1338                               struct scsi_cmnd *scmd);
1339 void megasas_fusion_ocr_wq(struct work_struct *work);
1340
1341 #endif /* _MEGARAID_SAS_FUSION_H_ */