2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/acpi.h>
15 #include <linux/bcd.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/rtc/ds1307.h>
21 #include <linux/rtc.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/hwmon.h>
25 #include <linux/hwmon-sysfs.h>
26 #include <linux/clk-provider.h>
27 #include <linux/regmap.h>
30 * We can't determine type by probing, but if we expect pre-Linux code
31 * to have set the chip up as a clock (turning on the oscillator and
32 * setting the date and time), Linux can ignore the non-clock features.
33 * That's a natural job for a factory or repair bench.
50 last_ds_type /* always last */
51 /* rs5c372 too? different address... */
54 /* RTC registers don't differ much, except for the century flag */
55 #define DS1307_REG_SECS 0x00 /* 00-59 */
56 # define DS1307_BIT_CH 0x80
57 # define DS1340_BIT_nEOSC 0x80
58 # define MCP794XX_BIT_ST 0x80
59 #define DS1307_REG_MIN 0x01 /* 00-59 */
60 # define M41T0_BIT_OF 0x80
61 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66 #define DS1307_REG_WDAY 0x03 /* 01-07 */
67 # define MCP794XX_BIT_VBATEN 0x08
68 #define DS1307_REG_MDAY 0x04 /* 01-31 */
69 #define DS1307_REG_MONTH 0x05 /* 01-12 */
70 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71 #define DS1307_REG_YEAR 0x06 /* 00-99 */
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
78 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
79 # define DS1307_BIT_OUT 0x80
80 # define DS1338_BIT_OSF 0x20
81 # define DS1307_BIT_SQWE 0x10
82 # define DS1307_BIT_RS1 0x02
83 # define DS1307_BIT_RS0 0x01
84 #define DS1337_REG_CONTROL 0x0e
85 # define DS1337_BIT_nEOSC 0x80
86 # define DS1339_BIT_BBSQI 0x20
87 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
88 # define DS1337_BIT_RS2 0x10
89 # define DS1337_BIT_RS1 0x08
90 # define DS1337_BIT_INTCN 0x04
91 # define DS1337_BIT_A2IE 0x02
92 # define DS1337_BIT_A1IE 0x01
93 #define DS1340_REG_CONTROL 0x07
94 # define DS1340_BIT_OUT 0x80
95 # define DS1340_BIT_FT 0x40
96 # define DS1340_BIT_CALIB_SIGN 0x20
97 # define DS1340_M_CALIBRATION 0x1f
98 #define DS1340_REG_FLAG 0x09
99 # define DS1340_BIT_OSF 0x80
100 #define DS1337_REG_STATUS 0x0f
101 # define DS1337_BIT_OSF 0x80
102 # define DS3231_BIT_EN32KHZ 0x08
103 # define DS1337_BIT_A2I 0x02
104 # define DS1337_BIT_A1I 0x01
105 #define DS1339_REG_ALARM1_SECS 0x07
107 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
109 #define RX8025_REG_CTRL1 0x0e
110 # define RX8025_BIT_2412 0x20
111 #define RX8025_REG_CTRL2 0x0f
112 # define RX8025_BIT_PON 0x10
113 # define RX8025_BIT_VDET 0x40
114 # define RX8025_BIT_XST 0x20
117 struct nvmem_config nvmem_cfg;
120 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
121 #define HAS_ALARM 1 /* bit 1 == irq claimed */
123 struct regmap *regmap;
125 struct rtc_device *rtc;
126 #ifdef CONFIG_COMMON_CLK
127 struct clk_hw clks[2];
135 u8 offset; /* register's offset */
137 u8 century_enable_bit;
140 irq_handler_t irq_handler;
141 const struct rtc_class_ops *rtc_ops;
142 u16 trickle_charger_reg;
143 u8 (*do_trickle_setup)(struct ds1307 *, u32,
147 static int ds1307_get_time(struct device *dev, struct rtc_time *t);
148 static int ds1307_set_time(struct device *dev, struct rtc_time *t);
149 static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
150 static irqreturn_t rx8130_irq(int irq, void *dev_id);
151 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
152 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
153 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
154 static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
155 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
156 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
157 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
159 static const struct rtc_class_ops rx8130_rtc_ops = {
160 .read_time = ds1307_get_time,
161 .set_time = ds1307_set_time,
162 .read_alarm = rx8130_read_alarm,
163 .set_alarm = rx8130_set_alarm,
164 .alarm_irq_enable = rx8130_alarm_irq_enable,
167 static const struct rtc_class_ops mcp794xx_rtc_ops = {
168 .read_time = ds1307_get_time,
169 .set_time = ds1307_set_time,
170 .read_alarm = mcp794xx_read_alarm,
171 .set_alarm = mcp794xx_set_alarm,
172 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
175 static const struct chip_desc chips[last_ds_type] = {
186 .century_reg = DS1307_REG_MONTH,
187 .century_bit = DS1337_BIT_CENTURY,
195 .century_reg = DS1307_REG_MONTH,
196 .century_bit = DS1337_BIT_CENTURY,
197 .bbsqi_bit = DS1339_BIT_BBSQI,
198 .trickle_charger_reg = 0x10,
199 .do_trickle_setup = &do_trickle_setup_ds1339,
202 .century_reg = DS1307_REG_HOUR,
203 .century_enable_bit = DS1340_BIT_CENTURY_EN,
204 .century_bit = DS1340_BIT_CENTURY,
205 .trickle_charger_reg = 0x08,
208 .century_reg = DS1307_REG_MONTH,
209 .century_bit = DS1337_BIT_CENTURY,
213 .trickle_charger_reg = 0x0a,
217 .century_reg = DS1307_REG_MONTH,
218 .century_bit = DS1337_BIT_CENTURY,
219 .bbsqi_bit = DS3231_BIT_BBSQW,
223 /* this is battery backed SRAM */
224 .nvram_offset = 0x20,
225 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
227 .irq_handler = rx8130_irq,
228 .rtc_ops = &rx8130_rtc_ops,
232 /* this is battery backed SRAM */
233 .nvram_offset = 0x20,
235 .irq_handler = mcp794xx_irq,
236 .rtc_ops = &mcp794xx_rtc_ops,
240 static const struct i2c_device_id ds1307_id[] = {
241 { "ds1307", ds_1307 },
242 { "ds1308", ds_1308 },
243 { "ds1337", ds_1337 },
244 { "ds1338", ds_1338 },
245 { "ds1339", ds_1339 },
246 { "ds1388", ds_1388 },
247 { "ds1340", ds_1340 },
248 { "ds1341", ds_1341 },
249 { "ds3231", ds_3231 },
251 { "m41t00", m41t00 },
252 { "mcp7940x", mcp794xx },
253 { "mcp7941x", mcp794xx },
254 { "pt7c4338", ds_1307 },
255 { "rx8025", rx_8025 },
256 { "isl12057", ds_1337 },
257 { "rx8130", rx_8130 },
260 MODULE_DEVICE_TABLE(i2c, ds1307_id);
263 static const struct of_device_id ds1307_of_match[] = {
265 .compatible = "dallas,ds1307",
266 .data = (void *)ds_1307
269 .compatible = "dallas,ds1308",
270 .data = (void *)ds_1308
273 .compatible = "dallas,ds1337",
274 .data = (void *)ds_1337
277 .compatible = "dallas,ds1338",
278 .data = (void *)ds_1338
281 .compatible = "dallas,ds1339",
282 .data = (void *)ds_1339
285 .compatible = "dallas,ds1388",
286 .data = (void *)ds_1388
289 .compatible = "dallas,ds1340",
290 .data = (void *)ds_1340
293 .compatible = "dallas,ds1341",
294 .data = (void *)ds_1341
297 .compatible = "maxim,ds3231",
298 .data = (void *)ds_3231
301 .compatible = "st,m41t0",
302 .data = (void *)m41t00
305 .compatible = "st,m41t00",
306 .data = (void *)m41t00
309 .compatible = "microchip,mcp7940x",
310 .data = (void *)mcp794xx
313 .compatible = "microchip,mcp7941x",
314 .data = (void *)mcp794xx
317 .compatible = "pericom,pt7c4338",
318 .data = (void *)ds_1307
321 .compatible = "epson,rx8025",
322 .data = (void *)rx_8025
325 .compatible = "isil,isl12057",
326 .data = (void *)ds_1337
330 MODULE_DEVICE_TABLE(of, ds1307_of_match);
334 static const struct acpi_device_id ds1307_acpi_ids[] = {
335 { .id = "DS1307", .driver_data = ds_1307 },
336 { .id = "DS1308", .driver_data = ds_1308 },
337 { .id = "DS1337", .driver_data = ds_1337 },
338 { .id = "DS1338", .driver_data = ds_1338 },
339 { .id = "DS1339", .driver_data = ds_1339 },
340 { .id = "DS1388", .driver_data = ds_1388 },
341 { .id = "DS1340", .driver_data = ds_1340 },
342 { .id = "DS1341", .driver_data = ds_1341 },
343 { .id = "DS3231", .driver_data = ds_3231 },
344 { .id = "M41T0", .driver_data = m41t0 },
345 { .id = "M41T00", .driver_data = m41t00 },
346 { .id = "MCP7940X", .driver_data = mcp794xx },
347 { .id = "MCP7941X", .driver_data = mcp794xx },
348 { .id = "PT7C4338", .driver_data = ds_1307 },
349 { .id = "RX8025", .driver_data = rx_8025 },
350 { .id = "ISL12057", .driver_data = ds_1337 },
353 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
357 * The ds1337 and ds1339 both have two alarms, but we only use the first
358 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
359 * signal; ds1339 chips have only one alarm signal.
361 static irqreturn_t ds1307_irq(int irq, void *dev_id)
363 struct ds1307 *ds1307 = dev_id;
364 struct mutex *lock = &ds1307->rtc->ops_lock;
368 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
372 if (stat & DS1337_BIT_A1I) {
373 stat &= ~DS1337_BIT_A1I;
374 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
376 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
381 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
390 /*----------------------------------------------------------------------*/
392 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
394 struct ds1307 *ds1307 = dev_get_drvdata(dev);
396 const struct chip_desc *chip = &chips[ds1307->type];
399 /* read the RTC date and time registers all at once */
400 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
403 dev_err(dev, "%s error %d\n", "read", ret);
407 dev_dbg(dev, "%s: %7ph\n", "read", regs);
409 /* if oscillator fail bit is set, no data can be trusted */
410 if (ds1307->type == m41t0 &&
411 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
412 dev_warn_once(dev, "oscillator failed, set time!\n");
416 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
417 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
418 tmp = regs[DS1307_REG_HOUR] & 0x3f;
419 t->tm_hour = bcd2bin(tmp);
420 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
421 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
422 tmp = regs[DS1307_REG_MONTH] & 0x1f;
423 t->tm_mon = bcd2bin(tmp) - 1;
424 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
426 if (regs[chip->century_reg] & chip->century_bit &&
427 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
430 dev_dbg(dev, "%s secs=%d, mins=%d, "
431 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
432 "read", t->tm_sec, t->tm_min,
433 t->tm_hour, t->tm_mday,
434 t->tm_mon, t->tm_year, t->tm_wday);
436 /* initial clock setting can be undefined */
437 return rtc_valid_tm(t);
440 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
442 struct ds1307 *ds1307 = dev_get_drvdata(dev);
443 const struct chip_desc *chip = &chips[ds1307->type];
448 dev_dbg(dev, "%s secs=%d, mins=%d, "
449 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
450 "write", t->tm_sec, t->tm_min,
451 t->tm_hour, t->tm_mday,
452 t->tm_mon, t->tm_year, t->tm_wday);
454 if (t->tm_year < 100)
457 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
458 if (t->tm_year > (chip->century_bit ? 299 : 199))
461 if (t->tm_year > 199)
465 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
466 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
467 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
468 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
469 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
470 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
472 /* assume 20YY not 19YY */
473 tmp = t->tm_year - 100;
474 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
476 if (chip->century_enable_bit)
477 regs[chip->century_reg] |= chip->century_enable_bit;
478 if (t->tm_year > 199 && chip->century_bit)
479 regs[chip->century_reg] |= chip->century_bit;
481 if (ds1307->type == mcp794xx) {
483 * these bits were cleared when preparing the date/time
484 * values and need to be set again before writing the
485 * regsfer out to the device.
487 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
488 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
491 dev_dbg(dev, "%s: %7ph\n", "write", regs);
493 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
496 dev_err(dev, "%s error %d\n", "write", result);
502 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
504 struct ds1307 *ds1307 = dev_get_drvdata(dev);
508 if (!test_bit(HAS_ALARM, &ds1307->flags))
511 /* read all ALARM1, ALARM2, and status registers at once */
512 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
515 dev_err(dev, "%s error %d\n", "alarm read", ret);
519 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
520 ®s[0], ®s[4], ®s[7]);
523 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
524 * and that all four fields are checked matches
526 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
527 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
528 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
529 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
532 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
533 t->pending = !!(regs[8] & DS1337_BIT_A1I);
535 dev_dbg(dev, "%s secs=%d, mins=%d, "
536 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
537 "alarm read", t->time.tm_sec, t->time.tm_min,
538 t->time.tm_hour, t->time.tm_mday,
539 t->enabled, t->pending);
544 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
546 struct ds1307 *ds1307 = dev_get_drvdata(dev);
547 unsigned char regs[9];
551 if (!test_bit(HAS_ALARM, &ds1307->flags))
554 dev_dbg(dev, "%s secs=%d, mins=%d, "
555 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
556 "alarm set", t->time.tm_sec, t->time.tm_min,
557 t->time.tm_hour, t->time.tm_mday,
558 t->enabled, t->pending);
560 /* read current status of both alarms and the chip */
561 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
564 dev_err(dev, "%s error %d\n", "alarm write", ret);
570 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
571 ®s[0], ®s[4], control, status);
573 /* set ALARM1, using 24 hour and day-of-month modes */
574 regs[0] = bin2bcd(t->time.tm_sec);
575 regs[1] = bin2bcd(t->time.tm_min);
576 regs[2] = bin2bcd(t->time.tm_hour);
577 regs[3] = bin2bcd(t->time.tm_mday);
579 /* set ALARM2 to non-garbage */
585 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
586 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
588 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
591 dev_err(dev, "can't set alarm time\n");
595 /* optionally enable ALARM1 */
597 dev_dbg(dev, "alarm IRQ armed\n");
598 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
599 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
605 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
607 struct ds1307 *ds1307 = dev_get_drvdata(dev);
609 if (!test_bit(HAS_ALARM, &ds1307->flags))
612 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
614 enabled ? DS1337_BIT_A1IE : 0);
617 static const struct rtc_class_ops ds13xx_rtc_ops = {
618 .read_time = ds1307_get_time,
619 .set_time = ds1307_set_time,
620 .read_alarm = ds1337_read_alarm,
621 .set_alarm = ds1337_set_alarm,
622 .alarm_irq_enable = ds1307_alarm_irq_enable,
625 /*----------------------------------------------------------------------*/
628 * Alarm support for rx8130 devices.
631 #define RX8130_REG_ALARM_MIN 0x07
632 #define RX8130_REG_ALARM_HOUR 0x08
633 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
634 #define RX8130_REG_EXTENSION 0x0c
635 #define RX8130_REG_EXTENSION_WADA BIT(3)
636 #define RX8130_REG_FLAG 0x0d
637 #define RX8130_REG_FLAG_AF BIT(3)
638 #define RX8130_REG_CONTROL0 0x0e
639 #define RX8130_REG_CONTROL0_AIE BIT(3)
641 static irqreturn_t rx8130_irq(int irq, void *dev_id)
643 struct ds1307 *ds1307 = dev_id;
644 struct mutex *lock = &ds1307->rtc->ops_lock;
650 /* Read control registers. */
651 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
655 if (!(ctl[1] & RX8130_REG_FLAG_AF))
657 ctl[1] &= ~RX8130_REG_FLAG_AF;
658 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
660 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
665 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
673 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
675 struct ds1307 *ds1307 = dev_get_drvdata(dev);
679 if (!test_bit(HAS_ALARM, &ds1307->flags))
682 /* Read alarm registers. */
683 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
688 /* Read control registers. */
689 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
694 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
695 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
697 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
699 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
700 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
701 t->time.tm_wday = -1;
702 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
704 t->time.tm_year = -1;
705 t->time.tm_yday = -1;
706 t->time.tm_isdst = -1;
708 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
709 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
710 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
715 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
717 struct ds1307 *ds1307 = dev_get_drvdata(dev);
721 if (!test_bit(HAS_ALARM, &ds1307->flags))
724 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
725 "enabled=%d pending=%d\n", __func__,
726 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
727 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
728 t->enabled, t->pending);
730 /* Read control registers. */
731 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
736 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
737 ctl[1] |= RX8130_REG_FLAG_AF;
738 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
740 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
745 /* Hardware alarm precision is 1 minute! */
746 ald[0] = bin2bcd(t->time.tm_min);
747 ald[1] = bin2bcd(t->time.tm_hour);
748 ald[2] = bin2bcd(t->time.tm_mday);
750 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
758 ctl[2] |= RX8130_REG_CONTROL0_AIE;
760 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
764 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
766 struct ds1307 *ds1307 = dev_get_drvdata(dev);
769 if (!test_bit(HAS_ALARM, &ds1307->flags))
772 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
777 reg |= RX8130_REG_CONTROL0_AIE;
779 reg &= ~RX8130_REG_CONTROL0_AIE;
781 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
784 /*----------------------------------------------------------------------*/
787 * Alarm support for mcp794xx devices.
790 #define MCP794XX_REG_WEEKDAY 0x3
791 #define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
792 #define MCP794XX_REG_CONTROL 0x07
793 # define MCP794XX_BIT_ALM0_EN 0x10
794 # define MCP794XX_BIT_ALM1_EN 0x20
795 #define MCP794XX_REG_ALARM0_BASE 0x0a
796 #define MCP794XX_REG_ALARM0_CTRL 0x0d
797 #define MCP794XX_REG_ALARM1_BASE 0x11
798 #define MCP794XX_REG_ALARM1_CTRL 0x14
799 # define MCP794XX_BIT_ALMX_IF BIT(3)
800 # define MCP794XX_BIT_ALMX_C0 BIT(4)
801 # define MCP794XX_BIT_ALMX_C1 BIT(5)
802 # define MCP794XX_BIT_ALMX_C2 BIT(6)
803 # define MCP794XX_BIT_ALMX_POL BIT(7)
804 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
805 MCP794XX_BIT_ALMX_C1 | \
806 MCP794XX_BIT_ALMX_C2)
808 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
810 struct ds1307 *ds1307 = dev_id;
811 struct mutex *lock = &ds1307->rtc->ops_lock;
816 /* Check and clear alarm 0 interrupt flag. */
817 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
820 if (!(reg & MCP794XX_BIT_ALMX_IF))
822 reg &= ~MCP794XX_BIT_ALMX_IF;
823 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
827 /* Disable alarm 0. */
828 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
829 MCP794XX_BIT_ALM0_EN, 0);
833 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
841 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
843 struct ds1307 *ds1307 = dev_get_drvdata(dev);
847 if (!test_bit(HAS_ALARM, &ds1307->flags))
850 /* Read control and alarm 0 registers. */
851 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
856 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
858 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
859 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
860 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
861 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
862 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
863 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
864 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
865 t->time.tm_year = -1;
866 t->time.tm_yday = -1;
867 t->time.tm_isdst = -1;
869 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
870 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
871 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
872 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
873 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
874 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
875 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
880 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
882 struct ds1307 *ds1307 = dev_get_drvdata(dev);
883 unsigned char regs[10];
886 if (!test_bit(HAS_ALARM, &ds1307->flags))
889 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
890 "enabled=%d pending=%d\n", __func__,
891 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
892 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
893 t->enabled, t->pending);
895 /* Read control and alarm 0 registers. */
896 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
901 /* Set alarm 0, using 24-hour and day-of-month modes. */
902 regs[3] = bin2bcd(t->time.tm_sec);
903 regs[4] = bin2bcd(t->time.tm_min);
904 regs[5] = bin2bcd(t->time.tm_hour);
905 regs[6] = bin2bcd(t->time.tm_wday + 1);
906 regs[7] = bin2bcd(t->time.tm_mday);
907 regs[8] = bin2bcd(t->time.tm_mon + 1);
909 /* Clear the alarm 0 interrupt flag. */
910 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
911 /* Set alarm match: second, minute, hour, day, date, month. */
912 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
913 /* Disable interrupt. We will not enable until completely programmed */
914 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
916 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
923 regs[0] |= MCP794XX_BIT_ALM0_EN;
924 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
927 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
929 struct ds1307 *ds1307 = dev_get_drvdata(dev);
931 if (!test_bit(HAS_ALARM, &ds1307->flags))
934 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
935 MCP794XX_BIT_ALM0_EN,
936 enabled ? MCP794XX_BIT_ALM0_EN : 0);
939 /*----------------------------------------------------------------------*/
941 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
944 struct ds1307 *ds1307 = priv;
945 const struct chip_desc *chip = &chips[ds1307->type];
947 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
951 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
954 struct ds1307 *ds1307 = priv;
955 const struct chip_desc *chip = &chips[ds1307->type];
957 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
961 /*----------------------------------------------------------------------*/
963 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
964 u32 ohms, bool diode)
966 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
967 DS1307_TRICKLE_CHARGER_NO_DIODE;
971 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
974 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
977 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
980 dev_warn(ds1307->dev,
981 "Unsupported ohm value %u in dt\n", ohms);
987 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
988 const struct chip_desc *chip)
993 if (!chip->do_trickle_setup)
996 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1000 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1003 return chip->do_trickle_setup(ds1307, ohms, diode);
1006 /*----------------------------------------------------------------------*/
1008 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
1011 * Temperature sensor support for ds3231 devices.
1014 #define DS3231_REG_TEMPERATURE 0x11
1017 * A user-initiated temperature conversion is not started by this function,
1018 * so the temperature is updated once every 64 seconds.
1020 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1022 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1027 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1028 temp_buf, sizeof(temp_buf));
1032 * Temperature is represented as a 10-bit code with a resolution of
1033 * 0.25 degree celsius and encoded in two's complement format.
1035 temp = (temp_buf[0] << 8) | temp_buf[1];
1042 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1043 struct device_attribute *attr, char *buf)
1048 ret = ds3231_hwmon_read_temp(dev, &temp);
1052 return sprintf(buf, "%d\n", temp);
1054 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1057 static struct attribute *ds3231_hwmon_attrs[] = {
1058 &sensor_dev_attr_temp1_input.dev_attr.attr,
1061 ATTRIBUTE_GROUPS(ds3231_hwmon);
1063 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1067 if (ds1307->type != ds_3231)
1070 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1072 ds3231_hwmon_groups);
1074 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1081 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1085 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1087 /*----------------------------------------------------------------------*/
1090 * Square-wave output support for DS3231
1091 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1093 #ifdef CONFIG_COMMON_CLK
1100 #define clk_sqw_to_ds1307(clk) \
1101 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1102 #define clk_32khz_to_ds1307(clk) \
1103 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1105 static int ds3231_clk_sqw_rates[] = {
1112 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1114 struct mutex *lock = &ds1307->rtc->ops_lock;
1118 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1125 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1126 unsigned long parent_rate)
1128 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1132 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1135 if (control & DS1337_BIT_RS1)
1137 if (control & DS1337_BIT_RS2)
1140 return ds3231_clk_sqw_rates[rate_sel];
1143 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1144 unsigned long *prate)
1148 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1149 if (ds3231_clk_sqw_rates[i] <= rate)
1150 return ds3231_clk_sqw_rates[i];
1156 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1157 unsigned long parent_rate)
1159 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1163 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1165 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1169 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1173 control |= DS1337_BIT_RS1;
1175 control |= DS1337_BIT_RS2;
1177 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1181 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1183 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1185 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1188 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1190 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1192 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1195 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1197 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1200 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1204 return !(control & DS1337_BIT_INTCN);
1207 static const struct clk_ops ds3231_clk_sqw_ops = {
1208 .prepare = ds3231_clk_sqw_prepare,
1209 .unprepare = ds3231_clk_sqw_unprepare,
1210 .is_prepared = ds3231_clk_sqw_is_prepared,
1211 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1212 .round_rate = ds3231_clk_sqw_round_rate,
1213 .set_rate = ds3231_clk_sqw_set_rate,
1216 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1217 unsigned long parent_rate)
1222 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1224 struct mutex *lock = &ds1307->rtc->ops_lock;
1228 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1230 enable ? DS3231_BIT_EN32KHZ : 0);
1236 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1238 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1240 return ds3231_clk_32khz_control(ds1307, true);
1243 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1245 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1247 ds3231_clk_32khz_control(ds1307, false);
1250 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1252 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1255 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1259 return !!(status & DS3231_BIT_EN32KHZ);
1262 static const struct clk_ops ds3231_clk_32khz_ops = {
1263 .prepare = ds3231_clk_32khz_prepare,
1264 .unprepare = ds3231_clk_32khz_unprepare,
1265 .is_prepared = ds3231_clk_32khz_is_prepared,
1266 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1269 static struct clk_init_data ds3231_clks_init[] = {
1270 [DS3231_CLK_SQW] = {
1271 .name = "ds3231_clk_sqw",
1272 .ops = &ds3231_clk_sqw_ops,
1274 [DS3231_CLK_32KHZ] = {
1275 .name = "ds3231_clk_32khz",
1276 .ops = &ds3231_clk_32khz_ops,
1280 static int ds3231_clks_register(struct ds1307 *ds1307)
1282 struct device_node *node = ds1307->dev->of_node;
1283 struct clk_onecell_data *onecell;
1286 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1290 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1291 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1292 sizeof(onecell->clks[0]), GFP_KERNEL);
1296 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1297 struct clk_init_data init = ds3231_clks_init[i];
1300 * Interrupt signal due to alarm conditions and square-wave
1301 * output share same pin, so don't initialize both.
1303 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1306 /* optional override of the clockname */
1307 of_property_read_string_index(node, "clock-output-names", i,
1309 ds1307->clks[i].init = &init;
1311 onecell->clks[i] = devm_clk_register(ds1307->dev,
1313 if (IS_ERR(onecell->clks[i]))
1314 return PTR_ERR(onecell->clks[i]);
1320 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1325 static void ds1307_clks_register(struct ds1307 *ds1307)
1329 if (ds1307->type != ds_3231)
1332 ret = ds3231_clks_register(ds1307);
1334 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1341 static void ds1307_clks_register(struct ds1307 *ds1307)
1345 #endif /* CONFIG_COMMON_CLK */
1347 static const struct regmap_config regmap_config = {
1352 static int ds1307_probe(struct i2c_client *client,
1353 const struct i2c_device_id *id)
1355 struct ds1307 *ds1307;
1358 const struct chip_desc *chip;
1360 bool ds1307_can_wakeup_device = false;
1361 unsigned char regs[8];
1362 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1364 unsigned long timestamp;
1365 u8 trickle_charger_setup = 0;
1367 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1371 dev_set_drvdata(&client->dev, ds1307);
1372 ds1307->dev = &client->dev;
1373 ds1307->name = client->name;
1375 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1376 if (IS_ERR(ds1307->regmap)) {
1377 dev_err(ds1307->dev, "regmap allocation failed\n");
1378 return PTR_ERR(ds1307->regmap);
1381 i2c_set_clientdata(client, ds1307);
1383 if (client->dev.of_node) {
1384 ds1307->type = (enum ds_type)
1385 of_device_get_match_data(&client->dev);
1386 chip = &chips[ds1307->type];
1388 chip = &chips[id->driver_data];
1389 ds1307->type = id->driver_data;
1391 const struct acpi_device_id *acpi_id;
1393 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1397 chip = &chips[acpi_id->driver_data];
1398 ds1307->type = acpi_id->driver_data;
1401 want_irq = client->irq > 0 && chip->alarm;
1404 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1405 else if (pdata->trickle_charger_setup)
1406 trickle_charger_setup = pdata->trickle_charger_setup;
1408 if (trickle_charger_setup && chip->trickle_charger_reg) {
1409 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1410 dev_dbg(ds1307->dev,
1411 "writing trickle charger info 0x%x to 0x%x\n",
1412 trickle_charger_setup, chip->trickle_charger_reg);
1413 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1414 trickle_charger_setup);
1419 * For devices with no IRQ directly connected to the SoC, the RTC chip
1420 * can be forced as a wakeup source by stating that explicitly in
1421 * the device's .dts file using the "wakeup-source" boolean property.
1422 * If the "wakeup-source" property is set, don't request an IRQ.
1423 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1424 * if supported by the RTC.
1426 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1428 ds1307_can_wakeup_device = true;
1431 switch (ds1307->type) {
1436 /* get registers that the "rtc" read below won't read... */
1437 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1440 dev_dbg(ds1307->dev, "read error %d\n", err);
1444 /* oscillator off? turn it on, so clock can tick. */
1445 if (regs[0] & DS1337_BIT_nEOSC)
1446 regs[0] &= ~DS1337_BIT_nEOSC;
1449 * Using IRQ or defined as wakeup-source?
1450 * Disable the square wave and both alarms.
1451 * For some variants, be sure alarms can trigger when we're
1452 * running on Vbackup (BBSQI/BBSQW)
1454 if (want_irq || ds1307_can_wakeup_device) {
1455 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1456 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1459 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1462 /* oscillator fault? clear flag, and warn */
1463 if (regs[1] & DS1337_BIT_OSF) {
1464 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1465 regs[1] & ~DS1337_BIT_OSF);
1466 dev_warn(ds1307->dev, "SET TIME!\n");
1471 err = regmap_bulk_read(ds1307->regmap,
1472 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1474 dev_dbg(ds1307->dev, "read error %d\n", err);
1478 /* oscillator off? turn it on, so clock can tick. */
1479 if (!(regs[1] & RX8025_BIT_XST)) {
1480 regs[1] |= RX8025_BIT_XST;
1481 regmap_write(ds1307->regmap,
1482 RX8025_REG_CTRL2 << 4 | 0x08,
1484 dev_warn(ds1307->dev,
1485 "oscillator stop detected - SET TIME!\n");
1488 if (regs[1] & RX8025_BIT_PON) {
1489 regs[1] &= ~RX8025_BIT_PON;
1490 regmap_write(ds1307->regmap,
1491 RX8025_REG_CTRL2 << 4 | 0x08,
1493 dev_warn(ds1307->dev, "power-on detected\n");
1496 if (regs[1] & RX8025_BIT_VDET) {
1497 regs[1] &= ~RX8025_BIT_VDET;
1498 regmap_write(ds1307->regmap,
1499 RX8025_REG_CTRL2 << 4 | 0x08,
1501 dev_warn(ds1307->dev, "voltage drop detected\n");
1504 /* make sure we are running in 24hour mode */
1505 if (!(regs[0] & RX8025_BIT_2412)) {
1508 /* switch to 24 hour mode */
1509 regmap_write(ds1307->regmap,
1510 RX8025_REG_CTRL1 << 4 | 0x08,
1511 regs[0] | RX8025_BIT_2412);
1513 err = regmap_bulk_read(ds1307->regmap,
1514 RX8025_REG_CTRL1 << 4 | 0x08,
1517 dev_dbg(ds1307->dev, "read error %d\n", err);
1522 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1525 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1528 regmap_write(ds1307->regmap,
1529 DS1307_REG_HOUR << 4 | 0x08, hour);
1537 /* read RTC registers */
1538 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1541 dev_dbg(ds1307->dev, "read error %d\n", err);
1546 * minimal sanity checking; some chips (like DS1340) don't
1547 * specify the extra bits as must-be-zero, but there are
1548 * still a few values that are clearly out-of-range.
1550 tmp = regs[DS1307_REG_SECS];
1551 switch (ds1307->type) {
1555 /* clock halted? turn it on, so clock can tick. */
1556 if (tmp & DS1307_BIT_CH) {
1557 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1558 dev_warn(ds1307->dev, "SET TIME!\n");
1564 /* clock halted? turn it on, so clock can tick. */
1565 if (tmp & DS1307_BIT_CH)
1566 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1568 /* oscillator fault? clear flag, and warn */
1569 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1570 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1571 regs[DS1307_REG_CONTROL] &
1573 dev_warn(ds1307->dev, "SET TIME!\n");
1578 /* clock halted? turn it on, so clock can tick. */
1579 if (tmp & DS1340_BIT_nEOSC)
1580 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1582 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1584 dev_dbg(ds1307->dev, "read error %d\n", err);
1588 /* oscillator fault? clear flag, and warn */
1589 if (tmp & DS1340_BIT_OSF) {
1590 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1591 dev_warn(ds1307->dev, "SET TIME!\n");
1595 /* make sure that the backup battery is enabled */
1596 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1597 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1598 regs[DS1307_REG_WDAY] |
1599 MCP794XX_BIT_VBATEN);
1602 /* clock halted? turn it on, so clock can tick. */
1603 if (!(tmp & MCP794XX_BIT_ST)) {
1604 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1606 dev_warn(ds1307->dev, "SET TIME!\n");
1615 tmp = regs[DS1307_REG_HOUR];
1616 switch (ds1307->type) {
1621 * NOTE: ignores century bits; fix before deploying
1622 * systems that will run through year 2100.
1628 if (!(tmp & DS1307_BIT_12HR))
1632 * Be sure we're in 24 hour mode. Multi-master systems
1635 tmp = bcd2bin(tmp & 0x1f);
1638 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1640 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1645 * Some IPs have weekday reset value = 0x1 which might not correct
1646 * hence compute the wday using the current date/month/year values
1648 ds1307_get_time(ds1307->dev, &tm);
1650 timestamp = rtc_tm_to_time64(&tm);
1651 rtc_time64_to_tm(timestamp, &tm);
1654 * Check if reset wday is different from the computed wday
1655 * If different then set the wday which we computed using
1658 if (wday != tm.tm_wday)
1659 regmap_update_bits(ds1307->regmap, MCP794XX_REG_WEEKDAY,
1660 MCP794XX_REG_WEEKDAY_WDAY_MASK,
1663 if (want_irq || ds1307_can_wakeup_device) {
1664 device_set_wakeup_capable(ds1307->dev, true);
1665 set_bit(HAS_ALARM, &ds1307->flags);
1668 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1669 if (IS_ERR(ds1307->rtc))
1670 return PTR_ERR(ds1307->rtc);
1672 if (ds1307_can_wakeup_device && !want_irq) {
1673 dev_info(ds1307->dev,
1674 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1675 /* We cannot support UIE mode if we do not have an IRQ line */
1676 ds1307->rtc->uie_unsupported = 1;
1680 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1681 chip->irq_handler ?: ds1307_irq,
1682 IRQF_SHARED | IRQF_ONESHOT,
1683 ds1307->name, ds1307);
1686 device_set_wakeup_capable(ds1307->dev, false);
1687 clear_bit(HAS_ALARM, &ds1307->flags);
1688 dev_err(ds1307->dev, "unable to request IRQ!\n");
1690 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1694 if (chip->nvram_size) {
1695 ds1307->nvmem_cfg.name = "ds1307_nvram";
1696 ds1307->nvmem_cfg.word_size = 1;
1697 ds1307->nvmem_cfg.stride = 1;
1698 ds1307->nvmem_cfg.size = chip->nvram_size;
1699 ds1307->nvmem_cfg.reg_read = ds1307_nvram_read;
1700 ds1307->nvmem_cfg.reg_write = ds1307_nvram_write;
1701 ds1307->nvmem_cfg.priv = ds1307;
1703 ds1307->rtc->nvmem_config = &ds1307->nvmem_cfg;
1704 ds1307->rtc->nvram_old_abi = true;
1707 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1708 err = rtc_register_device(ds1307->rtc);
1712 ds1307_hwmon_register(ds1307);
1713 ds1307_clks_register(ds1307);
1721 static struct i2c_driver ds1307_driver = {
1723 .name = "rtc-ds1307",
1724 .of_match_table = of_match_ptr(ds1307_of_match),
1725 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1727 .probe = ds1307_probe,
1728 .id_table = ds1307_id,
1731 module_i2c_driver(ds1307_driver);
1733 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1734 MODULE_LICENSE("GPL");