4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
24 #include <linux/err.h>
25 #include <linux/clk.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pwm.h>
28 #include <linux/of_device.h>
30 /* ECAP registers and bits definitions */
36 #define ECCTL2_APWM_POL_LOW BIT(10)
37 #define ECCTL2_APWM_MODE BIT(9)
38 #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
39 #define ECCTL2_TSCTR_FREERUN BIT(4)
47 struct ecap_pwm_chip {
49 unsigned int clk_rate;
50 void __iomem *mmio_base;
51 struct ecap_context ctx;
54 static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
56 return container_of(chip, struct ecap_pwm_chip, chip);
60 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
61 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
63 static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
64 int duty_ns, int period_ns)
66 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
67 u32 period_cycles, duty_cycles;
71 if (period_ns > NSEC_PER_SEC)
76 do_div(c, NSEC_PER_SEC);
77 period_cycles = (u32)c;
79 if (period_cycles < 1) {
85 do_div(c, NSEC_PER_SEC);
89 pm_runtime_get_sync(pc->chip.dev);
91 value = readw(pc->mmio_base + ECCTL2);
93 /* Configure APWM mode & disable sync option */
94 value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
96 writew(value, pc->mmio_base + ECCTL2);
98 if (!pwm_is_enabled(pwm)) {
99 /* Update active registers if not running */
100 writel(duty_cycles, pc->mmio_base + CAP2);
101 writel(period_cycles, pc->mmio_base + CAP1);
104 * Update shadow registers to configure period and
105 * compare values. This helps current PWM period to
106 * complete on reconfiguring
108 writel(duty_cycles, pc->mmio_base + CAP4);
109 writel(period_cycles, pc->mmio_base + CAP3);
112 if (!pwm_is_enabled(pwm)) {
113 value = readw(pc->mmio_base + ECCTL2);
114 /* Disable APWM mode to put APWM output Low */
115 value &= ~ECCTL2_APWM_MODE;
116 writew(value, pc->mmio_base + ECCTL2);
119 pm_runtime_put_sync(pc->chip.dev);
124 static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
125 enum pwm_polarity polarity)
127 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
130 pm_runtime_get_sync(pc->chip.dev);
132 value = readw(pc->mmio_base + ECCTL2);
134 if (polarity == PWM_POLARITY_INVERSED)
135 /* Duty cycle defines LOW period of PWM */
136 value |= ECCTL2_APWM_POL_LOW;
138 /* Duty cycle defines HIGH period of PWM */
139 value &= ~ECCTL2_APWM_POL_LOW;
141 writew(value, pc->mmio_base + ECCTL2);
143 pm_runtime_put_sync(pc->chip.dev);
148 static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
150 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
153 /* Leave clock enabled on enabling PWM */
154 pm_runtime_get_sync(pc->chip.dev);
157 * Enable 'Free run Time stamp counter mode' to start counter
158 * and 'APWM mode' to enable APWM output
160 value = readw(pc->mmio_base + ECCTL2);
161 value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
162 writew(value, pc->mmio_base + ECCTL2);
167 static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
169 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
173 * Disable 'Free run Time stamp counter mode' to stop counter
174 * and 'APWM mode' to put APWM output to low
176 value = readw(pc->mmio_base + ECCTL2);
177 value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
178 writew(value, pc->mmio_base + ECCTL2);
180 /* Disable clock on PWM disable */
181 pm_runtime_put_sync(pc->chip.dev);
184 static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
186 if (pwm_is_enabled(pwm)) {
187 dev_warn(chip->dev, "Removing PWM device without disabling\n");
188 pm_runtime_put_sync(chip->dev);
192 static const struct pwm_ops ecap_pwm_ops = {
193 .free = ecap_pwm_free,
194 .config = ecap_pwm_config,
195 .set_polarity = ecap_pwm_set_polarity,
196 .enable = ecap_pwm_enable,
197 .disable = ecap_pwm_disable,
198 .owner = THIS_MODULE,
201 static const struct of_device_id ecap_of_match[] = {
202 { .compatible = "ti,am3352-ecap" },
203 { .compatible = "ti,am33xx-ecap" },
206 MODULE_DEVICE_TABLE(of, ecap_of_match);
208 static int ecap_pwm_probe(struct platform_device *pdev)
210 struct device_node *np = pdev->dev.of_node;
211 struct ecap_pwm_chip *pc;
216 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
220 clk = devm_clk_get(&pdev->dev, "fck");
222 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
223 dev_warn(&pdev->dev, "Binding is obsolete.\n");
224 clk = devm_clk_get(pdev->dev.parent, "fck");
229 dev_err(&pdev->dev, "failed to get clock\n");
233 pc->clk_rate = clk_get_rate(clk);
235 dev_err(&pdev->dev, "failed to get clock rate\n");
239 pc->chip.dev = &pdev->dev;
240 pc->chip.ops = &ecap_pwm_ops;
241 pc->chip.of_xlate = of_pwm_xlate_with_flags;
242 pc->chip.of_pwm_n_cells = 3;
246 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
247 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
248 if (IS_ERR(pc->mmio_base))
249 return PTR_ERR(pc->mmio_base);
251 ret = pwmchip_add(&pc->chip);
253 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
257 platform_set_drvdata(pdev, pc);
258 pm_runtime_enable(&pdev->dev);
263 static int ecap_pwm_remove(struct platform_device *pdev)
265 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
267 pm_runtime_disable(&pdev->dev);
269 return pwmchip_remove(&pc->chip);
272 #ifdef CONFIG_PM_SLEEP
273 static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
275 pm_runtime_get_sync(pc->chip.dev);
276 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
277 pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
278 pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
279 pm_runtime_put_sync(pc->chip.dev);
282 static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
284 writel(pc->ctx.cap3, pc->mmio_base + CAP3);
285 writel(pc->ctx.cap4, pc->mmio_base + CAP4);
286 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
289 static int ecap_pwm_suspend(struct device *dev)
291 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
292 struct pwm_device *pwm = pc->chip.pwms;
294 ecap_pwm_save_context(pc);
296 /* Disable explicitly if PWM is running */
297 if (pwm_is_enabled(pwm))
298 pm_runtime_put_sync(dev);
303 static int ecap_pwm_resume(struct device *dev)
305 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
306 struct pwm_device *pwm = pc->chip.pwms;
308 /* Enable explicitly if PWM was running */
309 if (pwm_is_enabled(pwm))
310 pm_runtime_get_sync(dev);
312 ecap_pwm_restore_context(pc);
317 static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
319 static struct platform_driver ecap_pwm_driver = {
322 .of_match_table = ecap_of_match,
323 .pm = &ecap_pwm_pm_ops,
325 .probe = ecap_pwm_probe,
326 .remove = ecap_pwm_remove,
328 module_platform_driver(ecap_pwm_driver);
330 MODULE_DESCRIPTION("ECAP PWM driver");
331 MODULE_AUTHOR("Texas Instruments");
332 MODULE_LICENSE("GPL");