drivers/pinctrl/sh-pfc/pfc-r8a7796.c

   1 /*
   2  * R8A7796 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   7  *
   8  * R-Car Gen3 processor support - PFC hardware block.
   9  *
  10  * Copyright (C) 2015  Renesas Electronics Corporation
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; version 2 of the License.
  15  */
  16
  17 #include <linux/kernel.h>
  18
  19 #include "core.h"
  20 #include "sh_pfc.h"
  21
  22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  23                    SH_PFC_PIN_CFG_PULL_UP | \
  24                    SH_PFC_PIN_CFG_PULL_DOWN)
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  31         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  35         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  36         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  37         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  38         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  39 /*
  40  * F_() : just information
  41  * FM() : macro for FN_xxx / xxx_MARK
  42  */
  43
  44 /* GPSR0 */
  45 #define GPSR0_15        F_(D15,                 IP7_11_8)
  46 #define GPSR0_14        F_(D14,                 IP7_7_4)
  47 #define GPSR0_13        F_(D13,                 IP7_3_0)
  48 #define GPSR0_12        F_(D12,                 IP6_31_28)
  49 #define GPSR0_11        F_(D11,                 IP6_27_24)
  50 #define GPSR0_10        F_(D10,                 IP6_23_20)
  51 #define GPSR0_9         F_(D9,                  IP6_19_16)
  52 #define GPSR0_8         F_(D8,                  IP6_15_12)
  53 #define GPSR0_7         F_(D7,                  IP6_11_8)
  54 #define GPSR0_6         F_(D6,                  IP6_7_4)
  55 #define GPSR0_5         F_(D5,                  IP6_3_0)
  56 #define GPSR0_4         F_(D4,                  IP5_31_28)
  57 #define GPSR0_3         F_(D3,                  IP5_27_24)
  58 #define GPSR0_2         F_(D2,                  IP5_23_20)
  59 #define GPSR0_1         F_(D1,                  IP5_19_16)
  60 #define GPSR0_0         F_(D0,                  IP5_15_12)
  61
  62 /* GPSR1 */
  63 #define GPSR1_28        FM(CLKOUT)
  64 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  65 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  66 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  67 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  68 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  69 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  70 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  71 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  72 #define GPSR1_19        F_(A19,                 IP4_11_8)
  73 #define GPSR1_18        F_(A18,                 IP4_7_4)
  74 #define GPSR1_17        F_(A17,                 IP4_3_0)
  75 #define GPSR1_16        F_(A16,                 IP3_31_28)
  76 #define GPSR1_15        F_(A15,                 IP3_27_24)
  77 #define GPSR1_14        F_(A14,                 IP3_23_20)
  78 #define GPSR1_13        F_(A13,                 IP3_19_16)
  79 #define GPSR1_12        F_(A12,                 IP3_15_12)
  80 #define GPSR1_11        F_(A11,                 IP3_11_8)
  81 #define GPSR1_10        F_(A10,                 IP3_7_4)
  82 #define GPSR1_9         F_(A9,                  IP3_3_0)
  83 #define GPSR1_8         F_(A8,                  IP2_31_28)
  84 #define GPSR1_7         F_(A7,                  IP2_27_24)
  85 #define GPSR1_6         F_(A6,                  IP2_23_20)
  86 #define GPSR1_5         F_(A5,                  IP2_19_16)
  87 #define GPSR1_4         F_(A4,                  IP2_15_12)
  88 #define GPSR1_3         F_(A3,                  IP2_11_8)
  89 #define GPSR1_2         F_(A2,                  IP2_7_4)
  90 #define GPSR1_1         F_(A1,                  IP2_3_0)
  91 #define GPSR1_0         F_(A0,                  IP1_31_28)
  92
  93 /* GPSR2 */
  94 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  95 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  96 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  97 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  98 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  99 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 100 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 101 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 102 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 103 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 104 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 105 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 106 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 107 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 108 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 109
 110 /* GPSR3 */
 111 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 112 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 113 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 114 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 115 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 116 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 117 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 118 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 119 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 120 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 121 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 122 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 123 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 124 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 125 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 126 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 127
 128 /* GPSR4 */
 129 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 130 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 131 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 132 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 133 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 134 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 135 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 136 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 137 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 138 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 139 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 140 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 141 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 142 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 143 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 144 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 145 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 146 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 147
 148 /* GPSR5 */
 149 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 150 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 151 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 152 #define GPSR5_22        FM(MSIOF0_RXD)
 153 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 154 #define GPSR5_20        FM(MSIOF0_TXD)
 155 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 156 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 157 #define GPSR5_17        FM(MSIOF0_SCK)
 158 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 159 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 160 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 161 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 162 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 163 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 164 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 165 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 166 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 167 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 168 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 169 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 170 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 171 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 172 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 173 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 174 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 175
 176 /* GPSR6 */
 177 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 178 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 179 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 180 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 181 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 182 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 183 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 184 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 185 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 186 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 187 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 188 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 189 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 190 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 191 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 192 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 193 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 194 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 195 #define GPSR6_13        FM(SSI_SDATA5)
 196 #define GPSR6_12        FM(SSI_WS5)
 197 #define GPSR6_11        FM(SSI_SCK5)
 198 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 199 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 200 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 201 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 202 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 203 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 204 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 205 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 206 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 207 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 208 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 209
 210 /* GPSR7 */
 211 #define GPSR7_3         FM(GP7_03)
 212 #define GPSR7_2         FM(HDMI0_CEC)
 213 #define GPSR7_1         FM(AVS2)
 214 #define GPSR7_0         FM(AVS1)
 215
 216
 217 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 218 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245
 246 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 247 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276
 277 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 278 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312
 313 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 314 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 335 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342
 343 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 344 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 366 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 367 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 368 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 370 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 371
 372 #define PINMUX_GPSR     \
 373 \
 374                                                                                                 GPSR6_31 \
 375                                                                                                 GPSR6_30 \
 376                                                                                                 GPSR6_29 \
 377                 GPSR1_28                                                                        GPSR6_28 \
 378                 GPSR1_27                                                                        GPSR6_27 \
 379                 GPSR1_26                                                                        GPSR6_26 \
 380                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 381                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 382                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 383                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 384                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 385                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 386                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 387                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 388                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 389                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 390 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 391 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 392 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 393 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 394 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 395 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 396 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 397 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 398 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 399 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 400 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 401 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 402 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 403 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 404 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 405 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 406
 407 #define PINMUX_IPSR                             \
 408 \
 409 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 410 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 411 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 412 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 413 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 414 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 415 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 416 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 417 \
 418 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 419 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 420 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 421 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 422 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 423 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 424 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 425 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 426 \
 427 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 428 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 429 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 430 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 431 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 432 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 433 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 434 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 435 \
 436 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 437 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 438 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 439 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 440 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 441 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 442 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 443 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 444 \
 445 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 446 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 447 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 448 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 449 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 450 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 451 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 452 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 453
 454 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 455 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 456 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 457 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 458 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 459 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 460 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 461 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 462 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 463 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 464 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 465 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 466 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 467 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 468 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 469 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 470 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 471 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 472 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 473
 474 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 475 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 476 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 477 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 478 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 479 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 480 #define MOD_SEL1_20             FM(SEL_SSI_0)           FM(SEL_SSI_1)
 481 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 482 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 483 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 484 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 485 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 486 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 487 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 488 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 489 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 490 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 491 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 492 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 493 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 494 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 495 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 496 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 497
 498 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 499 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 500 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 501 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 502 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 503 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 504 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 505 #define MOD_SEL2_22             FM(SEL_NDF_0)           FM(SEL_NDF_1)
 506 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 507 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 508 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 509 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 510 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 511 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 512
 513 #define PINMUX_MOD_SELS \
 514 \
 515 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 516                                                 MOD_SEL2_30 \
 517                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 518 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 519 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 520                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 521 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 522 MOD_SEL0_22                                     MOD_SEL2_22 \
 523 MOD_SEL0_21                                     MOD_SEL2_21 \
 524 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 525 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 526 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 527                                                 MOD_SEL2_17 \
 528 MOD_SEL0_16             MOD_SEL1_16 \
 529                         MOD_SEL1_15_14 \
 530 MOD_SEL0_14_13 \
 531                         MOD_SEL1_13 \
 532 MOD_SEL0_12             MOD_SEL1_12 \
 533 MOD_SEL0_11             MOD_SEL1_11 \
 534 MOD_SEL0_10             MOD_SEL1_10 \
 535 MOD_SEL0_9_8            MOD_SEL1_9 \
 536 MOD_SEL0_7_6 \
 537                         MOD_SEL1_6 \
 538 MOD_SEL0_5              MOD_SEL1_5 \
 539 MOD_SEL0_4_3            MOD_SEL1_4 \
 540                         MOD_SEL1_3 \
 541                         MOD_SEL1_2 \
 542                         MOD_SEL1_1 \
 543                         MOD_SEL1_0              MOD_SEL2_0
 544
 545 /*
 546  * These pins are not able to be muxed but have other properties
 547  * that can be set, such as drive-strength or pull-up/pull-down enable.
 548  */
 549 #define PINMUX_STATIC \
 550         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 551         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 552         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 553         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 554         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 555         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 556         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 557         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 558         FM(PRESETOUT) \
 559         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 560         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 561
 562 enum {
 563         PINMUX_RESERVED = 0,
 564
 565         PINMUX_DATA_BEGIN,
 566         GP_ALL(DATA),
 567         PINMUX_DATA_END,
 568
 569 #define F_(x, y)
 570 #define FM(x)   FN_##x,
 571         PINMUX_FUNCTION_BEGIN,
 572         GP_ALL(FN),
 573         PINMUX_GPSR
 574         PINMUX_IPSR
 575         PINMUX_MOD_SELS
 576         PINMUX_FUNCTION_END,
 577 #undef F_
 578 #undef FM
 579
 580 #define F_(x, y)
 581 #define FM(x)   x##_MARK,
 582         PINMUX_MARK_BEGIN,
 583         PINMUX_GPSR
 584         PINMUX_IPSR
 585         PINMUX_MOD_SELS
 586         PINMUX_STATIC
 587         PINMUX_MARK_END,
 588 #undef F_
 589 #undef FM
 590 };
 591
 592 static const u16 pinmux_data[] = {
 593         PINMUX_DATA_GP_ALL(),
 594
 595         PINMUX_SINGLE(AVS1),
 596         PINMUX_SINGLE(AVS2),
 597         PINMUX_SINGLE(CLKOUT),
 598         PINMUX_SINGLE(GP7_03),
 599         PINMUX_SINGLE(HDMI0_CEC),
 600         PINMUX_SINGLE(MSIOF0_RXD),
 601         PINMUX_SINGLE(MSIOF0_SCK),
 602         PINMUX_SINGLE(MSIOF0_TXD),
 603         PINMUX_SINGLE(SSI_SCK5),
 604         PINMUX_SINGLE(SSI_SDATA5),
 605         PINMUX_SINGLE(SSI_WS5),
 606
 607         /* IPSR0 */
 608         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 609         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 610
 611         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 612         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 613         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 614
 615         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 616         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 617         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 618
 619         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 620         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 621         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 622
 623         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 624         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 625         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 626
 627         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 628         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 629         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 630
 631         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 633         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 637         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 638
 639         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 641         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 645         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 646
 647         /* IPSR1 */
 648         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 650         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 653         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 654
 655         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 657         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 658         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 660         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 661
 662         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 663         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 664         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 665         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 666         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 667         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 668
 669         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 670         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 671         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 672         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 673         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 674         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 675
 676         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 677         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 678         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 679         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 680
 681         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 682         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 683         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 684         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 685
 686         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 687         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 688         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 689
 690         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 691         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 692         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 693         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 695         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 696
 697         /* IPSR2 */
 698         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 699         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 700         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 703         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 704
 705         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 706         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 707         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 708         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 710         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 711
 712         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 713         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 714         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 715         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 717         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 718
 719         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 720         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 721         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 722         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 724         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 725
 726         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 727         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 728         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 729         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 730         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 731         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 732         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 733
 734         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 735         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 736         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 737         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 738         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 739         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 740         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 741
 742         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 743         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 744         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 745         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 746         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 747         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 748         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 749
 750         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 751         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 752         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 753         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 757
 758         /* IPSR3 */
 759         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 760         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 761         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 762         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 763
 764         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 765         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 766         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 767         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 768
 769         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 770         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 771         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 772         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 773         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 774         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 775         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 776         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 777         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 778
 779         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 780         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 781         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 782         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 783         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 784         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 785
 786         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 787         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 788         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 789         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 790         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 791         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 792
 793         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 794         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 795         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 796         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 798         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 799
 800         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 801         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 802         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 803         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 805         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 806
 807         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 808         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 809         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 810         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 811
 812         /* IPSR4 */
 813         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 814         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 815         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 816         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 817
 818         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 819         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 820         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 821         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 822
 823         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 824         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 825         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 826         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 827
 828         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 829         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 830
 831         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 832         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 833         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 834
 835         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 836         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 837         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 838         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 840         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 842         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 843
 844         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 845         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 846         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 847         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 850
 851         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 852         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 853         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 854         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 857
 858         /* IPSR5 */
 859         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 860         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 861         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 862         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 863         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 864         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 865         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 866
 867         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 868         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 869         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 870         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 871         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 872         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 875
 876         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 877         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 878         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 879         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 880
 881         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 882         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 883         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 884         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 885         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 886
 887         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 888         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 889         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 890         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 891         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 892
 893         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 894         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 895         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 896         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 897
 898         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 899         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 900         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 901         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 902
 903         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 904         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 905         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 906         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 907
 908         /* IPSR6 */
 909         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 910         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 911         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 912         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 913
 914         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 915         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 916         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 917         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 918
 919         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 920         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 921         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 922         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 923
 924         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 925         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 926         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 927         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 928         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 929         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 930
 931         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 932         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 933         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 934         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 935         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 936
 937         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 938         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 939         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 940         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 941         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 943         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 944
 945         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 946         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 947         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 948         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 949         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 951         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 952
 953         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 954         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 955         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 956         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 957         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 958         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 959
 960         /* IPSR7 */
 961         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 962         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 963         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 964         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 965         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 967
 968         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 969         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 970         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 971         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 972         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 973         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 974         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 975
 976         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 977         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 978         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 979         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 980         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 982         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 983
 984         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 985         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 986         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 987
 988         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 989         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 990         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 991
 992         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 993         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 995         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 996
 997         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 998         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 999         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1000         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1001
1002         /* IPSR8 */
1003         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1004         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1005         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1006         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1007
1008         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1009         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1010         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1011         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1012
1013         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1014         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1015         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1016
1017         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1018         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1019         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDF_1),
1020         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1022
1023         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1024         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1025         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1026         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDF_1),
1027         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1029
1030         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1031         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1032         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1033         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDF_1),
1034         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1036
1037         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1038         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1039         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1040         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDF_1),
1041         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1043
1044         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1045         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1046         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1047         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDF_1),
1048         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1050
1051         /* IPSR9 */
1052         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1053         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1054
1055         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1056         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1057
1058         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1059         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1060
1061         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1062         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1063
1064         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1065         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1066
1067         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1068         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1069
1070         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1071         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1072
1073         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1074         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1075
1076         /* IPSR10 */
1077         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1078         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1079
1080         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1081         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1082
1083         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1084         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1085
1086         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1087         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1088
1089         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1090         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1091
1092         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1093         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1094         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1095
1096         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1097         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1098         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1099
1100         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1101         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1102         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1103
1104         /* IPSR11 */
1105         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1106         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1107         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1108
1109         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1110         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1111
1112         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1113         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1115
1116         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1117         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1118
1119         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1120         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1121
1122         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1123         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1124
1125         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1126         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1127         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1128         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1129         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1130         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1131         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1133         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1135
1136         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1137         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1138         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1139         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1140         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1141
1142         /* IPSR12 */
1143         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1144         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1145         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1146         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1147         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1148
1149         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1150         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1151         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1152         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1153         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1154         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1155         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1156         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1157
1158         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1159         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1160         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1161         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1162         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1163         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1164         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1165         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1166
1167         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1168         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1169         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1170         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1171         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1172
1173         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1174         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1175         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1176         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1177         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1178
1179         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1180         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1181         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1182         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1183         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1184         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1185         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1186
1187         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1188         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1189         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1190         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1191         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1192         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1193         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1194
1195         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1196         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1197         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1198         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1199         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1200         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1201         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1202
1203         /* IPSR13 */
1204         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1205         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1206         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1207         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1208         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1209         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1210
1211         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1212         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1213         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1214         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1215         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1216         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1217
1218         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1219         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1220         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1221         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
1222         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1223         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1224         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1226
1227         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1228         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1229         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
1230         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1231         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1232         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1233
1234         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1235         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1236         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
1237         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1238         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1239         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1240
1241         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1242         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1243         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1244         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI_0),
1245         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1246         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1247         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1248         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1249
1250         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1251         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1252         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1253         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI_0),
1254         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1255         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1256         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1257
1258         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1259         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1260         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1261         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1262
1263         /* IPSR14 */
1264         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1265         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1266         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDF_0),
1267         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1268         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI_0),
1269         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1270         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1272
1273         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1274         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1275         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1276         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1277         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI_0),
1278         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1279         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1281
1282         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1283         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1284         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1285
1286         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1287         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1288         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1289         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1290
1291         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1292         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1293         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1294
1295         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1296         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1297
1298         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1299         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1300
1301         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1302         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1303
1304         /* IPSR15 */
1305         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
1306
1307         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
1308         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI_1),
1309
1310         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1311         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1312         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1313
1314         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1315         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1316         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1317         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1318
1319         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1320         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1321         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1322         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1323         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1324         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1325         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1326
1327         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1328         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1329         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1330         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1331         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1332         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1334
1335         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1336         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1337         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1338         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1340         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1342
1343         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1344         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1345         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1346         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1348         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1350
1351         /* IPSR16 */
1352         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1353         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1354
1355         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1356         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1357
1358         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1359         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1360
1361         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1362         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1363         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1364         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1365         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1366         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1367         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1368
1369         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1370         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1371         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1372         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1373         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1374         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1375         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1376
1377         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1378         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1379         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1380         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1382         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1383         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1384         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1385
1386         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1387         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1388         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1389         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1390         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1391         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1392         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1393
1394         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
1395         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1396         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1397         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1398         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI_1),
1399         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1400         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1401         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1402
1403         /* IPSR17 */
1404         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1405         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1406
1407         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1408         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1409         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1410         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1411         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1412
1413         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1414         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1415         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1416         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1417         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1418         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1419         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1420
1421         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1422         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1423         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1424         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1425         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1426         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1427
1428         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1429         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1430         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI_0),
1431         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1432         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1433         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1434         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1437
1438         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1439         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1440         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI_0),
1441         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1442         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1443         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1444         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1447
1448         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1449         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1450         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI_1),
1451         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1452         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1453         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1454         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1455         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1456         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1459
1460         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1461         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1462         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI_1),
1463         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1464         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1465         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1466         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1467         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1468         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1469
1470         /* IPSR18 */
1471         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1472         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1473         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI_1),
1474         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1475         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1476         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1477         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1478         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1480
1481         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1482         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1483         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI_1),
1484         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1485         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1486         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1487         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1488         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1490
1491         /* I2C */
1492         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1493         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1494         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1495
1496 /*
1497  * Static pins can not be muxed between different functions but
1498  * still needs a mark entry in the pinmux list. Add each static
1499  * pin to the list without an associated function. The sh-pfc
1500  * core will do the right thing and skip trying to mux then pin
1501  * while still applying configuration to it
1502  */
1503 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1504         PINMUX_STATIC
1505 #undef FM
1506 };
1507
1508 /*
1509  * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1510  * Physical layout rows: A - AW, cols: 1 - 39.
1511  */
1512 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1513 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1514 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1515 #define PIN_NONE U16_MAX
1516
1517 static const struct sh_pfc_pin pinmux_pins[] = {
1518         PINMUX_GPIO_GP_ALL(),
1519
1520         /*
1521          * Pins not associated with a GPIO port.
1522          *
1523          * The pin positions are different between different r8a7796
1524          * packages, all that is needed for the pfc driver is a unique
1525          * number for each pin. To this end use the pin layout from
1526          * R-Car M3SiP to calculate a unique number for each pin.
1527          */
1528         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1529         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1530         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1531         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1532         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1533         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1534         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1570 };
1571
1572 /* - AUDIO CLOCK ------------------------------------------------------------ */
1573 static const unsigned int audio_clk_a_a_pins[] = {
1574         /* CLK A */
1575         RCAR_GP_PIN(6, 22),
1576 };
1577 static const unsigned int audio_clk_a_a_mux[] = {
1578         AUDIO_CLKA_A_MARK,
1579 };
1580 static const unsigned int audio_clk_a_b_pins[] = {
1581         /* CLK A */
1582         RCAR_GP_PIN(5, 4),
1583 };
1584 static const unsigned int audio_clk_a_b_mux[] = {
1585         AUDIO_CLKA_B_MARK,
1586 };
1587 static const unsigned int audio_clk_a_c_pins[] = {
1588         /* CLK A */
1589         RCAR_GP_PIN(5, 19),
1590 };
1591 static const unsigned int audio_clk_a_c_mux[] = {
1592         AUDIO_CLKA_C_MARK,
1593 };
1594 static const unsigned int audio_clk_b_a_pins[] = {
1595         /* CLK B */
1596         RCAR_GP_PIN(5, 12),
1597 };
1598 static const unsigned int audio_clk_b_a_mux[] = {
1599         AUDIO_CLKB_A_MARK,
1600 };
1601 static const unsigned int audio_clk_b_b_pins[] = {
1602         /* CLK B */
1603         RCAR_GP_PIN(6, 23),
1604 };
1605 static const unsigned int audio_clk_b_b_mux[] = {
1606         AUDIO_CLKB_B_MARK,
1607 };
1608 static const unsigned int audio_clk_c_a_pins[] = {
1609         /* CLK C */
1610         RCAR_GP_PIN(5, 21),
1611 };
1612 static const unsigned int audio_clk_c_a_mux[] = {
1613         AUDIO_CLKC_A_MARK,
1614 };
1615 static const unsigned int audio_clk_c_b_pins[] = {
1616         /* CLK C */
1617         RCAR_GP_PIN(5, 0),
1618 };
1619 static const unsigned int audio_clk_c_b_mux[] = {
1620         AUDIO_CLKC_B_MARK,
1621 };
1622 static const unsigned int audio_clkout_a_pins[] = {
1623         /* CLKOUT */
1624         RCAR_GP_PIN(5, 18),
1625 };
1626 static const unsigned int audio_clkout_a_mux[] = {
1627         AUDIO_CLKOUT_A_MARK,
1628 };
1629 static const unsigned int audio_clkout_b_pins[] = {
1630         /* CLKOUT */
1631         RCAR_GP_PIN(6, 28),
1632 };
1633 static const unsigned int audio_clkout_b_mux[] = {
1634         AUDIO_CLKOUT_B_MARK,
1635 };
1636 static const unsigned int audio_clkout_c_pins[] = {
1637         /* CLKOUT */
1638         RCAR_GP_PIN(5, 3),
1639 };
1640 static const unsigned int audio_clkout_c_mux[] = {
1641         AUDIO_CLKOUT_C_MARK,
1642 };
1643 static const unsigned int audio_clkout_d_pins[] = {
1644         /* CLKOUT */
1645         RCAR_GP_PIN(5, 21),
1646 };
1647 static const unsigned int audio_clkout_d_mux[] = {
1648         AUDIO_CLKOUT_D_MARK,
1649 };
1650 static const unsigned int audio_clkout1_a_pins[] = {
1651         /* CLKOUT1 */
1652         RCAR_GP_PIN(5, 15),
1653 };
1654 static const unsigned int audio_clkout1_a_mux[] = {
1655         AUDIO_CLKOUT1_A_MARK,
1656 };
1657 static const unsigned int audio_clkout1_b_pins[] = {
1658         /* CLKOUT1 */
1659         RCAR_GP_PIN(6, 29),
1660 };
1661 static const unsigned int audio_clkout1_b_mux[] = {
1662         AUDIO_CLKOUT1_B_MARK,
1663 };
1664 static const unsigned int audio_clkout2_a_pins[] = {
1665         /* CLKOUT2 */
1666         RCAR_GP_PIN(5, 16),
1667 };
1668 static const unsigned int audio_clkout2_a_mux[] = {
1669         AUDIO_CLKOUT2_A_MARK,
1670 };
1671 static const unsigned int audio_clkout2_b_pins[] = {
1672         /* CLKOUT2 */
1673         RCAR_GP_PIN(6, 30),
1674 };
1675 static const unsigned int audio_clkout2_b_mux[] = {
1676         AUDIO_CLKOUT2_B_MARK,
1677 };
1678
1679 static const unsigned int audio_clkout3_a_pins[] = {
1680         /* CLKOUT3 */
1681         RCAR_GP_PIN(5, 19),
1682 };
1683 static const unsigned int audio_clkout3_a_mux[] = {
1684         AUDIO_CLKOUT3_A_MARK,
1685 };
1686 static const unsigned int audio_clkout3_b_pins[] = {
1687         /* CLKOUT3 */
1688         RCAR_GP_PIN(6, 31),
1689 };
1690 static const unsigned int audio_clkout3_b_mux[] = {
1691         AUDIO_CLKOUT3_B_MARK,
1692 };
1693
1694 /* - EtherAVB --------------------------------------------------------------- */
1695 static const unsigned int avb_link_pins[] = {
1696         /* AVB_LINK */
1697         RCAR_GP_PIN(2, 12),
1698 };
1699 static const unsigned int avb_link_mux[] = {
1700         AVB_LINK_MARK,
1701 };
1702 static const unsigned int avb_magic_pins[] = {
1703         /* AVB_MAGIC_ */
1704         RCAR_GP_PIN(2, 10),
1705 };
1706 static const unsigned int avb_magic_mux[] = {
1707         AVB_MAGIC_MARK,
1708 };
1709 static const unsigned int avb_phy_int_pins[] = {
1710         /* AVB_PHY_INT */
1711         RCAR_GP_PIN(2, 11),
1712 };
1713 static const unsigned int avb_phy_int_mux[] = {
1714         AVB_PHY_INT_MARK,
1715 };
1716 static const unsigned int avb_mdc_pins[] = {
1717         /* AVB_MDC, AVB_MDIO */
1718         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1719 };
1720 static const unsigned int avb_mdc_mux[] = {
1721         AVB_MDC_MARK, AVB_MDIO_MARK,
1722 };
1723 static const unsigned int avb_mii_pins[] = {
1724         /*
1725          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1726          * AVB_TD1, AVB_TD2, AVB_TD3,
1727          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1728          * AVB_RD1, AVB_RD2, AVB_RD3,
1729          * AVB_TXCREFCLK
1730          */
1731         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1732         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1733         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1734         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1735         PIN_NUMBER('A', 12),
1736
1737 };
1738 static const unsigned int avb_mii_mux[] = {
1739         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1740         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1741         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1742         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1743         AVB_TXCREFCLK_MARK,
1744 };
1745 static const unsigned int avb_avtp_pps_pins[] = {
1746         /* AVB_AVTP_PPS */
1747         RCAR_GP_PIN(2, 6),
1748 };
1749 static const unsigned int avb_avtp_pps_mux[] = {
1750         AVB_AVTP_PPS_MARK,
1751 };
1752 static const unsigned int avb_avtp_match_a_pins[] = {
1753         /* AVB_AVTP_MATCH_A */
1754         RCAR_GP_PIN(2, 13),
1755 };
1756 static const unsigned int avb_avtp_match_a_mux[] = {
1757         AVB_AVTP_MATCH_A_MARK,
1758 };
1759 static const unsigned int avb_avtp_capture_a_pins[] = {
1760         /* AVB_AVTP_CAPTURE_A */
1761         RCAR_GP_PIN(2, 14),
1762 };
1763 static const unsigned int avb_avtp_capture_a_mux[] = {
1764         AVB_AVTP_CAPTURE_A_MARK,
1765 };
1766 static const unsigned int avb_avtp_match_b_pins[] = {
1767         /*  AVB_AVTP_MATCH_B */
1768         RCAR_GP_PIN(1, 8),
1769 };
1770 static const unsigned int avb_avtp_match_b_mux[] = {
1771         AVB_AVTP_MATCH_B_MARK,
1772 };
1773 static const unsigned int avb_avtp_capture_b_pins[] = {
1774         /* AVB_AVTP_CAPTURE_B */
1775         RCAR_GP_PIN(1, 11),
1776 };
1777 static const unsigned int avb_avtp_capture_b_mux[] = {
1778         AVB_AVTP_CAPTURE_B_MARK,
1779 };
1780
1781 /* - CAN ------------------------------------------------------------------ */
1782 static const unsigned int can0_data_a_pins[] = {
1783         /* TX, RX */
1784         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1785 };
1786 static const unsigned int can0_data_a_mux[] = {
1787         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1788 };
1789 static const unsigned int can0_data_b_pins[] = {
1790         /* TX, RX */
1791         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1792 };
1793 static const unsigned int can0_data_b_mux[] = {
1794         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1795 };
1796 static const unsigned int can1_data_pins[] = {
1797         /* TX, RX */
1798         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1799 };
1800 static const unsigned int can1_data_mux[] = {
1801         CAN1_TX_MARK,           CAN1_RX_MARK,
1802 };
1803
1804 /* - CAN Clock -------------------------------------------------------------- */
1805 static const unsigned int can_clk_pins[] = {
1806         /* CLK */
1807         RCAR_GP_PIN(1, 25),
1808 };
1809 static const unsigned int can_clk_mux[] = {
1810         CAN_CLK_MARK,
1811 };
1812
1813 /* - CAN FD --------------------------------------------------------------- */
1814 static const unsigned int canfd0_data_a_pins[] = {
1815         /* TX, RX */
1816         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1817 };
1818 static const unsigned int canfd0_data_a_mux[] = {
1819         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1820 };
1821 static const unsigned int canfd0_data_b_pins[] = {
1822         /* TX, RX */
1823         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1824 };
1825 static const unsigned int canfd0_data_b_mux[] = {
1826         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1827 };
1828 static const unsigned int canfd1_data_pins[] = {
1829         /* TX, RX */
1830         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1831 };
1832 static const unsigned int canfd1_data_mux[] = {
1833         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1834 };
1835
1836 /* - DRIF0 --------------------------------------------------------------- */
1837 static const unsigned int drif0_ctrl_a_pins[] = {
1838         /* CLK, SYNC */
1839         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1840 };
1841 static const unsigned int drif0_ctrl_a_mux[] = {
1842         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1843 };
1844 static const unsigned int drif0_data0_a_pins[] = {
1845         /* D0 */
1846         RCAR_GP_PIN(6, 10),
1847 };
1848 static const unsigned int drif0_data0_a_mux[] = {
1849         RIF0_D0_A_MARK,
1850 };
1851 static const unsigned int drif0_data1_a_pins[] = {
1852         /* D1 */
1853         RCAR_GP_PIN(6, 7),
1854 };
1855 static const unsigned int drif0_data1_a_mux[] = {
1856         RIF0_D1_A_MARK,
1857 };
1858 static const unsigned int drif0_ctrl_b_pins[] = {
1859         /* CLK, SYNC */
1860         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1861 };
1862 static const unsigned int drif0_ctrl_b_mux[] = {
1863         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1864 };
1865 static const unsigned int drif0_data0_b_pins[] = {
1866         /* D0 */
1867         RCAR_GP_PIN(5, 1),
1868 };
1869 static const unsigned int drif0_data0_b_mux[] = {
1870         RIF0_D0_B_MARK,
1871 };
1872 static const unsigned int drif0_data1_b_pins[] = {
1873         /* D1 */
1874         RCAR_GP_PIN(5, 2),
1875 };
1876 static const unsigned int drif0_data1_b_mux[] = {
1877         RIF0_D1_B_MARK,
1878 };
1879 static const unsigned int drif0_ctrl_c_pins[] = {
1880         /* CLK, SYNC */
1881         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1882 };
1883 static const unsigned int drif0_ctrl_c_mux[] = {
1884         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1885 };
1886 static const unsigned int drif0_data0_c_pins[] = {
1887         /* D0 */
1888         RCAR_GP_PIN(5, 13),
1889 };
1890 static const unsigned int drif0_data0_c_mux[] = {
1891         RIF0_D0_C_MARK,
1892 };
1893 static const unsigned int drif0_data1_c_pins[] = {
1894         /* D1 */
1895         RCAR_GP_PIN(5, 14),
1896 };
1897 static const unsigned int drif0_data1_c_mux[] = {
1898         RIF0_D1_C_MARK,
1899 };
1900 /* - DRIF1 --------------------------------------------------------------- */
1901 static const unsigned int drif1_ctrl_a_pins[] = {
1902         /* CLK, SYNC */
1903         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1904 };
1905 static const unsigned int drif1_ctrl_a_mux[] = {
1906         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1907 };
1908 static const unsigned int drif1_data0_a_pins[] = {
1909         /* D0 */
1910         RCAR_GP_PIN(6, 19),
1911 };
1912 static const unsigned int drif1_data0_a_mux[] = {
1913         RIF1_D0_A_MARK,
1914 };
1915 static const unsigned int drif1_data1_a_pins[] = {
1916         /* D1 */
1917         RCAR_GP_PIN(6, 20),
1918 };
1919 static const unsigned int drif1_data1_a_mux[] = {
1920         RIF1_D1_A_MARK,
1921 };
1922 static const unsigned int drif1_ctrl_b_pins[] = {
1923         /* CLK, SYNC */
1924         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1925 };
1926 static const unsigned int drif1_ctrl_b_mux[] = {
1927         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1928 };
1929 static const unsigned int drif1_data0_b_pins[] = {
1930         /* D0 */
1931         RCAR_GP_PIN(5, 7),
1932 };
1933 static const unsigned int drif1_data0_b_mux[] = {
1934         RIF1_D0_B_MARK,
1935 };
1936 static const unsigned int drif1_data1_b_pins[] = {
1937         /* D1 */
1938         RCAR_GP_PIN(5, 8),
1939 };
1940 static const unsigned int drif1_data1_b_mux[] = {
1941         RIF1_D1_B_MARK,
1942 };
1943 static const unsigned int drif1_ctrl_c_pins[] = {
1944         /* CLK, SYNC */
1945         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1946 };
1947 static const unsigned int drif1_ctrl_c_mux[] = {
1948         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1949 };
1950 static const unsigned int drif1_data0_c_pins[] = {
1951         /* D0 */
1952         RCAR_GP_PIN(5, 6),
1953 };
1954 static const unsigned int drif1_data0_c_mux[] = {
1955         RIF1_D0_C_MARK,
1956 };
1957 static const unsigned int drif1_data1_c_pins[] = {
1958         /* D1 */
1959         RCAR_GP_PIN(5, 10),
1960 };
1961 static const unsigned int drif1_data1_c_mux[] = {
1962         RIF1_D1_C_MARK,
1963 };
1964 /* - DRIF2 --------------------------------------------------------------- */
1965 static const unsigned int drif2_ctrl_a_pins[] = {
1966         /* CLK, SYNC */
1967         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1968 };
1969 static const unsigned int drif2_ctrl_a_mux[] = {
1970         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1971 };
1972 static const unsigned int drif2_data0_a_pins[] = {
1973         /* D0 */
1974         RCAR_GP_PIN(6, 7),
1975 };
1976 static const unsigned int drif2_data0_a_mux[] = {
1977         RIF2_D0_A_MARK,
1978 };
1979 static const unsigned int drif2_data1_a_pins[] = {
1980         /* D1 */
1981         RCAR_GP_PIN(6, 10),
1982 };
1983 static const unsigned int drif2_data1_a_mux[] = {
1984         RIF2_D1_A_MARK,
1985 };
1986 static const unsigned int drif2_ctrl_b_pins[] = {
1987         /* CLK, SYNC */
1988         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1989 };
1990 static const unsigned int drif2_ctrl_b_mux[] = {
1991         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1992 };
1993 static const unsigned int drif2_data0_b_pins[] = {
1994         /* D0 */
1995         RCAR_GP_PIN(6, 30),
1996 };
1997 static const unsigned int drif2_data0_b_mux[] = {
1998         RIF2_D0_B_MARK,
1999 };
2000 static const unsigned int drif2_data1_b_pins[] = {
2001         /* D1 */
2002         RCAR_GP_PIN(6, 31),
2003 };
2004 static const unsigned int drif2_data1_b_mux[] = {
2005         RIF2_D1_B_MARK,
2006 };
2007 /* - DRIF3 --------------------------------------------------------------- */
2008 static const unsigned int drif3_ctrl_a_pins[] = {
2009         /* CLK, SYNC */
2010         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2011 };
2012 static const unsigned int drif3_ctrl_a_mux[] = {
2013         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2014 };
2015 static const unsigned int drif3_data0_a_pins[] = {
2016         /* D0 */
2017         RCAR_GP_PIN(6, 19),
2018 };
2019 static const unsigned int drif3_data0_a_mux[] = {
2020         RIF3_D0_A_MARK,
2021 };
2022 static const unsigned int drif3_data1_a_pins[] = {
2023         /* D1 */
2024         RCAR_GP_PIN(6, 20),
2025 };
2026 static const unsigned int drif3_data1_a_mux[] = {
2027         RIF3_D1_A_MARK,
2028 };
2029 static const unsigned int drif3_ctrl_b_pins[] = {
2030         /* CLK, SYNC */
2031         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2032 };
2033 static const unsigned int drif3_ctrl_b_mux[] = {
2034         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2035 };
2036 static const unsigned int drif3_data0_b_pins[] = {
2037         /* D0 */
2038         RCAR_GP_PIN(6, 28),
2039 };
2040 static const unsigned int drif3_data0_b_mux[] = {
2041         RIF3_D0_B_MARK,
2042 };
2043 static const unsigned int drif3_data1_b_pins[] = {
2044         /* D1 */
2045         RCAR_GP_PIN(6, 29),
2046 };
2047 static const unsigned int drif3_data1_b_mux[] = {
2048         RIF3_D1_B_MARK,
2049 };
2050
2051 /* - DU --------------------------------------------------------------------- */
2052 static const unsigned int du_rgb666_pins[] = {
2053         /* R[7:2], G[7:2], B[7:2] */
2054         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2055         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2056         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2057         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2058         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2059         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2060 };
2061 static const unsigned int du_rgb666_mux[] = {
2062         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2063         DU_DR3_MARK, DU_DR2_MARK,
2064         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2065         DU_DG3_MARK, DU_DG2_MARK,
2066         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2067         DU_DB3_MARK, DU_DB2_MARK,
2068 };
2069 static const unsigned int du_rgb888_pins[] = {
2070         /* R[7:0], G[7:0], B[7:0] */
2071         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2072         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2073         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2074         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2075         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2076         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2077         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2078         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2079         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2080 };
2081 static const unsigned int du_rgb888_mux[] = {
2082         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2083         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2084         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2085         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2086         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2087         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2088 };
2089 static const unsigned int du_clk_out_0_pins[] = {
2090         /* CLKOUT */
2091         RCAR_GP_PIN(1, 27),
2092 };
2093 static const unsigned int du_clk_out_0_mux[] = {
2094         DU_DOTCLKOUT0_MARK
2095 };
2096 static const unsigned int du_clk_out_1_pins[] = {
2097         /* CLKOUT */
2098         RCAR_GP_PIN(2, 3),
2099 };
2100 static const unsigned int du_clk_out_1_mux[] = {
2101         DU_DOTCLKOUT1_MARK
2102 };
2103 static const unsigned int du_sync_pins[] = {
2104         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2105         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2106 };
2107 static const unsigned int du_sync_mux[] = {
2108         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2109 };
2110 static const unsigned int du_oddf_pins[] = {
2111         /* EXDISP/EXODDF/EXCDE */
2112         RCAR_GP_PIN(2, 2),
2113 };
2114 static const unsigned int du_oddf_mux[] = {
2115         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2116 };
2117 static const unsigned int du_cde_pins[] = {
2118         /* CDE */
2119         RCAR_GP_PIN(2, 0),
2120 };
2121 static const unsigned int du_cde_mux[] = {
2122         DU_CDE_MARK,
2123 };
2124 static const unsigned int du_disp_pins[] = {
2125         /* DISP */
2126         RCAR_GP_PIN(2, 1),
2127 };
2128 static const unsigned int du_disp_mux[] = {
2129         DU_DISP_MARK,
2130 };
2131
2132 /* - HSCIF0 ----------------------------------------------------------------- */
2133 static const unsigned int hscif0_data_pins[] = {
2134         /* RX, TX */
2135         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2136 };
2137 static const unsigned int hscif0_data_mux[] = {
2138         HRX0_MARK, HTX0_MARK,
2139 };
2140 static const unsigned int hscif0_clk_pins[] = {
2141         /* SCK */
2142         RCAR_GP_PIN(5, 12),
2143 };
2144 static const unsigned int hscif0_clk_mux[] = {
2145         HSCK0_MARK,
2146 };
2147 static const unsigned int hscif0_ctrl_pins[] = {
2148         /* RTS, CTS */
2149         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2150 };
2151 static const unsigned int hscif0_ctrl_mux[] = {
2152         HRTS0_N_MARK, HCTS0_N_MARK,
2153 };
2154 /* - HSCIF1 ----------------------------------------------------------------- */
2155 static const unsigned int hscif1_data_a_pins[] = {
2156         /* RX, TX */
2157         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2158 };
2159 static const unsigned int hscif1_data_a_mux[] = {
2160         HRX1_A_MARK, HTX1_A_MARK,
2161 };
2162 static const unsigned int hscif1_clk_a_pins[] = {
2163         /* SCK */
2164         RCAR_GP_PIN(6, 21),
2165 };
2166 static const unsigned int hscif1_clk_a_mux[] = {
2167         HSCK1_A_MARK,
2168 };
2169 static const unsigned int hscif1_ctrl_a_pins[] = {
2170         /* RTS, CTS */
2171         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2172 };
2173 static const unsigned int hscif1_ctrl_a_mux[] = {
2174         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2175 };
2176
2177 static const unsigned int hscif1_data_b_pins[] = {
2178         /* RX, TX */
2179         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2180 };
2181 static const unsigned int hscif1_data_b_mux[] = {
2182         HRX1_B_MARK, HTX1_B_MARK,
2183 };
2184 static const unsigned int hscif1_clk_b_pins[] = {
2185         /* SCK */
2186         RCAR_GP_PIN(5, 0),
2187 };
2188 static const unsigned int hscif1_clk_b_mux[] = {
2189         HSCK1_B_MARK,
2190 };
2191 static const unsigned int hscif1_ctrl_b_pins[] = {
2192         /* RTS, CTS */
2193         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2194 };
2195 static const unsigned int hscif1_ctrl_b_mux[] = {
2196         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2197 };
2198 /* - HSCIF2 ----------------------------------------------------------------- */
2199 static const unsigned int hscif2_data_a_pins[] = {
2200         /* RX, TX */
2201         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2202 };
2203 static const unsigned int hscif2_data_a_mux[] = {
2204         HRX2_A_MARK, HTX2_A_MARK,
2205 };
2206 static const unsigned int hscif2_clk_a_pins[] = {
2207         /* SCK */
2208         RCAR_GP_PIN(6, 10),
2209 };
2210 static const unsigned int hscif2_clk_a_mux[] = {
2211         HSCK2_A_MARK,
2212 };
2213 static const unsigned int hscif2_ctrl_a_pins[] = {
2214         /* RTS, CTS */
2215         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2216 };
2217 static const unsigned int hscif2_ctrl_a_mux[] = {
2218         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2219 };
2220
2221 static const unsigned int hscif2_data_b_pins[] = {
2222         /* RX, TX */
2223         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2224 };
2225 static const unsigned int hscif2_data_b_mux[] = {
2226         HRX2_B_MARK, HTX2_B_MARK,
2227 };
2228 static const unsigned int hscif2_clk_b_pins[] = {
2229         /* SCK */
2230         RCAR_GP_PIN(6, 21),
2231 };
2232 static const unsigned int hscif2_clk_b_mux[] = {
2233         HSCK2_B_MARK,
2234 };
2235 static const unsigned int hscif2_ctrl_b_pins[] = {
2236         /* RTS, CTS */
2237         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2238 };
2239 static const unsigned int hscif2_ctrl_b_mux[] = {
2240         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2241 };
2242
2243 static const unsigned int hscif2_data_c_pins[] = {
2244         /* RX, TX */
2245         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2246 };
2247 static const unsigned int hscif2_data_c_mux[] = {
2248         HRX2_C_MARK, HTX2_C_MARK,
2249 };
2250 static const unsigned int hscif2_clk_c_pins[] = {
2251         /* SCK */
2252         RCAR_GP_PIN(6, 24),
2253 };
2254 static const unsigned int hscif2_clk_c_mux[] = {
2255         HSCK2_C_MARK,
2256 };
2257 static const unsigned int hscif2_ctrl_c_pins[] = {
2258         /* RTS, CTS */
2259         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2260 };
2261 static const unsigned int hscif2_ctrl_c_mux[] = {
2262         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2263 };
2264 /* - HSCIF3 ----------------------------------------------------------------- */
2265 static const unsigned int hscif3_data_a_pins[] = {
2266         /* RX, TX */
2267         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2268 };
2269 static const unsigned int hscif3_data_a_mux[] = {
2270         HRX3_A_MARK, HTX3_A_MARK,
2271 };
2272 static const unsigned int hscif3_clk_pins[] = {
2273         /* SCK */
2274         RCAR_GP_PIN(1, 22),
2275 };
2276 static const unsigned int hscif3_clk_mux[] = {
2277         HSCK3_MARK,
2278 };
2279 static const unsigned int hscif3_ctrl_pins[] = {
2280         /* RTS, CTS */
2281         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2282 };
2283 static const unsigned int hscif3_ctrl_mux[] = {
2284         HRTS3_N_MARK, HCTS3_N_MARK,
2285 };
2286
2287 static const unsigned int hscif3_data_b_pins[] = {
2288         /* RX, TX */
2289         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2290 };
2291 static const unsigned int hscif3_data_b_mux[] = {
2292         HRX3_B_MARK, HTX3_B_MARK,
2293 };
2294 static const unsigned int hscif3_data_c_pins[] = {
2295         /* RX, TX */
2296         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2297 };
2298 static const unsigned int hscif3_data_c_mux[] = {
2299         HRX3_C_MARK, HTX3_C_MARK,
2300 };
2301 static const unsigned int hscif3_data_d_pins[] = {
2302         /* RX, TX */
2303         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2304 };
2305 static const unsigned int hscif3_data_d_mux[] = {
2306         HRX3_D_MARK, HTX3_D_MARK,
2307 };
2308 /* - HSCIF4 ----------------------------------------------------------------- */
2309 static const unsigned int hscif4_data_a_pins[] = {
2310         /* RX, TX */
2311         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2312 };
2313 static const unsigned int hscif4_data_a_mux[] = {
2314         HRX4_A_MARK, HTX4_A_MARK,
2315 };
2316 static const unsigned int hscif4_clk_pins[] = {
2317         /* SCK */
2318         RCAR_GP_PIN(1, 11),
2319 };
2320 static const unsigned int hscif4_clk_mux[] = {
2321         HSCK4_MARK,
2322 };
2323 static const unsigned int hscif4_ctrl_pins[] = {
2324         /* RTS, CTS */
2325         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2326 };
2327 static const unsigned int hscif4_ctrl_mux[] = {
2328         HRTS4_N_MARK, HCTS4_N_MARK,
2329 };
2330
2331 static const unsigned int hscif4_data_b_pins[] = {
2332         /* RX, TX */
2333         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2334 };
2335 static const unsigned int hscif4_data_b_mux[] = {
2336         HRX4_B_MARK, HTX4_B_MARK,
2337 };
2338
2339 /* - I2C -------------------------------------------------------------------- */
2340 static const unsigned int i2c1_a_pins[] = {
2341         /* SDA, SCL */
2342         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2343 };
2344 static const unsigned int i2c1_a_mux[] = {
2345         SDA1_A_MARK, SCL1_A_MARK,
2346 };
2347 static const unsigned int i2c1_b_pins[] = {
2348         /* SDA, SCL */
2349         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2350 };
2351 static const unsigned int i2c1_b_mux[] = {
2352         SDA1_B_MARK, SCL1_B_MARK,
2353 };
2354 static const unsigned int i2c2_a_pins[] = {
2355         /* SDA, SCL */
2356         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2357 };
2358 static const unsigned int i2c2_a_mux[] = {
2359         SDA2_A_MARK, SCL2_A_MARK,
2360 };
2361 static const unsigned int i2c2_b_pins[] = {
2362         /* SDA, SCL */
2363         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2364 };
2365 static const unsigned int i2c2_b_mux[] = {
2366         SDA2_B_MARK, SCL2_B_MARK,
2367 };
2368 static const unsigned int i2c6_a_pins[] = {
2369         /* SDA, SCL */
2370         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2371 };
2372 static const unsigned int i2c6_a_mux[] = {
2373         SDA6_A_MARK, SCL6_A_MARK,
2374 };
2375 static const unsigned int i2c6_b_pins[] = {
2376         /* SDA, SCL */
2377         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2378 };
2379 static const unsigned int i2c6_b_mux[] = {
2380         SDA6_B_MARK, SCL6_B_MARK,
2381 };
2382 static const unsigned int i2c6_c_pins[] = {
2383         /* SDA, SCL */
2384         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2385 };
2386 static const unsigned int i2c6_c_mux[] = {
2387         SDA6_C_MARK, SCL6_C_MARK,
2388 };
2389
2390 /* - INTC-EX ---------------------------------------------------------------- */
2391 static const unsigned int intc_ex_irq0_pins[] = {
2392         /* IRQ0 */
2393         RCAR_GP_PIN(2, 0),
2394 };
2395 static const unsigned int intc_ex_irq0_mux[] = {
2396         IRQ0_MARK,
2397 };
2398 static const unsigned int intc_ex_irq1_pins[] = {
2399         /* IRQ1 */
2400         RCAR_GP_PIN(2, 1),
2401 };
2402 static const unsigned int intc_ex_irq1_mux[] = {
2403         IRQ1_MARK,
2404 };
2405 static const unsigned int intc_ex_irq2_pins[] = {
2406         /* IRQ2 */
2407         RCAR_GP_PIN(2, 2),
2408 };
2409 static const unsigned int intc_ex_irq2_mux[] = {
2410         IRQ2_MARK,
2411 };
2412 static const unsigned int intc_ex_irq3_pins[] = {
2413         /* IRQ3 */
2414         RCAR_GP_PIN(2, 3),
2415 };
2416 static const unsigned int intc_ex_irq3_mux[] = {
2417         IRQ3_MARK,
2418 };
2419 static const unsigned int intc_ex_irq4_pins[] = {
2420         /* IRQ4 */
2421         RCAR_GP_PIN(2, 4),
2422 };
2423 static const unsigned int intc_ex_irq4_mux[] = {
2424         IRQ4_MARK,
2425 };
2426 static const unsigned int intc_ex_irq5_pins[] = {
2427         /* IRQ5 */
2428         RCAR_GP_PIN(2, 5),
2429 };
2430 static const unsigned int intc_ex_irq5_mux[] = {
2431         IRQ5_MARK,
2432 };
2433
2434 /* - MSIOF0 ----------------------------------------------------------------- */
2435 static const unsigned int msiof0_clk_pins[] = {
2436         /* SCK */
2437         RCAR_GP_PIN(5, 17),
2438 };
2439 static const unsigned int msiof0_clk_mux[] = {
2440         MSIOF0_SCK_MARK,
2441 };
2442 static const unsigned int msiof0_sync_pins[] = {
2443         /* SYNC */
2444         RCAR_GP_PIN(5, 18),
2445 };
2446 static const unsigned int msiof0_sync_mux[] = {
2447         MSIOF0_SYNC_MARK,
2448 };
2449 static const unsigned int msiof0_ss1_pins[] = {
2450         /* SS1 */
2451         RCAR_GP_PIN(5, 19),
2452 };
2453 static const unsigned int msiof0_ss1_mux[] = {
2454         MSIOF0_SS1_MARK,
2455 };
2456 static const unsigned int msiof0_ss2_pins[] = {
2457         /* SS2 */
2458         RCAR_GP_PIN(5, 21),
2459 };
2460 static const unsigned int msiof0_ss2_mux[] = {
2461         MSIOF0_SS2_MARK,
2462 };
2463 static const unsigned int msiof0_txd_pins[] = {
2464         /* TXD */
2465         RCAR_GP_PIN(5, 20),
2466 };
2467 static const unsigned int msiof0_txd_mux[] = {
2468         MSIOF0_TXD_MARK,
2469 };
2470 static const unsigned int msiof0_rxd_pins[] = {
2471         /* RXD */
2472         RCAR_GP_PIN(5, 22),
2473 };
2474 static const unsigned int msiof0_rxd_mux[] = {
2475         MSIOF0_RXD_MARK,
2476 };
2477 /* - MSIOF1 ----------------------------------------------------------------- */
2478 static const unsigned int msiof1_clk_a_pins[] = {
2479         /* SCK */
2480         RCAR_GP_PIN(6, 8),
2481 };
2482 static const unsigned int msiof1_clk_a_mux[] = {
2483         MSIOF1_SCK_A_MARK,
2484 };
2485 static const unsigned int msiof1_sync_a_pins[] = {
2486         /* SYNC */
2487         RCAR_GP_PIN(6, 9),
2488 };
2489 static const unsigned int msiof1_sync_a_mux[] = {
2490         MSIOF1_SYNC_A_MARK,
2491 };
2492 static const unsigned int msiof1_ss1_a_pins[] = {
2493         /* SS1 */
2494         RCAR_GP_PIN(6, 5),
2495 };
2496 static const unsigned int msiof1_ss1_a_mux[] = {
2497         MSIOF1_SS1_A_MARK,
2498 };
2499 static const unsigned int msiof1_ss2_a_pins[] = {
2500         /* SS2 */
2501         RCAR_GP_PIN(6, 6),
2502 };
2503 static const unsigned int msiof1_ss2_a_mux[] = {
2504         MSIOF1_SS2_A_MARK,
2505 };
2506 static const unsigned int msiof1_txd_a_pins[] = {
2507         /* TXD */
2508         RCAR_GP_PIN(6, 7),
2509 };
2510 static const unsigned int msiof1_txd_a_mux[] = {
2511         MSIOF1_TXD_A_MARK,
2512 };
2513 static const unsigned int msiof1_rxd_a_pins[] = {
2514         /* RXD */
2515         RCAR_GP_PIN(6, 10),
2516 };
2517 static const unsigned int msiof1_rxd_a_mux[] = {
2518         MSIOF1_RXD_A_MARK,
2519 };
2520 static const unsigned int msiof1_clk_b_pins[] = {
2521         /* SCK */
2522         RCAR_GP_PIN(5, 9),
2523 };
2524 static const unsigned int msiof1_clk_b_mux[] = {
2525         MSIOF1_SCK_B_MARK,
2526 };
2527 static const unsigned int msiof1_sync_b_pins[] = {
2528         /* SYNC */
2529         RCAR_GP_PIN(5, 3),
2530 };
2531 static const unsigned int msiof1_sync_b_mux[] = {
2532         MSIOF1_SYNC_B_MARK,
2533 };
2534 static const unsigned int msiof1_ss1_b_pins[] = {
2535         /* SS1 */
2536         RCAR_GP_PIN(5, 4),
2537 };
2538 static const unsigned int msiof1_ss1_b_mux[] = {
2539         MSIOF1_SS1_B_MARK,
2540 };
2541 static const unsigned int msiof1_ss2_b_pins[] = {
2542         /* SS2 */
2543         RCAR_GP_PIN(5, 0),
2544 };
2545 static const unsigned int msiof1_ss2_b_mux[] = {
2546         MSIOF1_SS2_B_MARK,
2547 };
2548 static const unsigned int msiof1_txd_b_pins[] = {
2549         /* TXD */
2550         RCAR_GP_PIN(5, 8),
2551 };
2552 static const unsigned int msiof1_txd_b_mux[] = {
2553         MSIOF1_TXD_B_MARK,
2554 };
2555 static const unsigned int msiof1_rxd_b_pins[] = {
2556         /* RXD */
2557         RCAR_GP_PIN(5, 7),
2558 };
2559 static const unsigned int msiof1_rxd_b_mux[] = {
2560         MSIOF1_RXD_B_MARK,
2561 };
2562 static const unsigned int msiof1_clk_c_pins[] = {
2563         /* SCK */
2564         RCAR_GP_PIN(6, 17),
2565 };
2566 static const unsigned int msiof1_clk_c_mux[] = {
2567         MSIOF1_SCK_C_MARK,
2568 };
2569 static const unsigned int msiof1_sync_c_pins[] = {
2570         /* SYNC */
2571         RCAR_GP_PIN(6, 18),
2572 };
2573 static const unsigned int msiof1_sync_c_mux[] = {
2574         MSIOF1_SYNC_C_MARK,
2575 };
2576 static const unsigned int msiof1_ss1_c_pins[] = {
2577         /* SS1 */
2578         RCAR_GP_PIN(6, 21),
2579 };
2580 static const unsigned int msiof1_ss1_c_mux[] = {
2581         MSIOF1_SS1_C_MARK,
2582 };
2583 static const unsigned int msiof1_ss2_c_pins[] = {
2584         /* SS2 */
2585         RCAR_GP_PIN(6, 27),
2586 };
2587 static const unsigned int msiof1_ss2_c_mux[] = {
2588         MSIOF1_SS2_C_MARK,
2589 };
2590 static const unsigned int msiof1_txd_c_pins[] = {
2591         /* TXD */
2592         RCAR_GP_PIN(6, 20),
2593 };
2594 static const unsigned int msiof1_txd_c_mux[] = {
2595         MSIOF1_TXD_C_MARK,
2596 };
2597 static const unsigned int msiof1_rxd_c_pins[] = {
2598         /* RXD */
2599         RCAR_GP_PIN(6, 19),
2600 };
2601 static const unsigned int msiof1_rxd_c_mux[] = {
2602         MSIOF1_RXD_C_MARK,
2603 };
2604 static const unsigned int msiof1_clk_d_pins[] = {
2605         /* SCK */
2606         RCAR_GP_PIN(5, 12),
2607 };
2608 static const unsigned int msiof1_clk_d_mux[] = {
2609         MSIOF1_SCK_D_MARK,
2610 };
2611 static const unsigned int msiof1_sync_d_pins[] = {
2612         /* SYNC */
2613         RCAR_GP_PIN(5, 15),
2614 };
2615 static const unsigned int msiof1_sync_d_mux[] = {
2616         MSIOF1_SYNC_D_MARK,
2617 };
2618 static const unsigned int msiof1_ss1_d_pins[] = {
2619         /* SS1 */
2620         RCAR_GP_PIN(5, 16),
2621 };
2622 static const unsigned int msiof1_ss1_d_mux[] = {
2623         MSIOF1_SS1_D_MARK,
2624 };
2625 static const unsigned int msiof1_ss2_d_pins[] = {
2626         /* SS2 */
2627         RCAR_GP_PIN(5, 21),
2628 };
2629 static const unsigned int msiof1_ss2_d_mux[] = {
2630         MSIOF1_SS2_D_MARK,
2631 };
2632 static const unsigned int msiof1_txd_d_pins[] = {
2633         /* TXD */
2634         RCAR_GP_PIN(5, 14),
2635 };
2636 static const unsigned int msiof1_txd_d_mux[] = {
2637         MSIOF1_TXD_D_MARK,
2638 };
2639 static const unsigned int msiof1_rxd_d_pins[] = {
2640         /* RXD */
2641         RCAR_GP_PIN(5, 13),
2642 };
2643 static const unsigned int msiof1_rxd_d_mux[] = {
2644         MSIOF1_RXD_D_MARK,
2645 };
2646 static const unsigned int msiof1_clk_e_pins[] = {
2647         /* SCK */
2648         RCAR_GP_PIN(3, 0),
2649 };
2650 static const unsigned int msiof1_clk_e_mux[] = {
2651         MSIOF1_SCK_E_MARK,
2652 };
2653 static const unsigned int msiof1_sync_e_pins[] = {
2654         /* SYNC */
2655         RCAR_GP_PIN(3, 1),
2656 };
2657 static const unsigned int msiof1_sync_e_mux[] = {
2658         MSIOF1_SYNC_E_MARK,
2659 };
2660 static const unsigned int msiof1_ss1_e_pins[] = {
2661         /* SS1 */
2662         RCAR_GP_PIN(3, 4),
2663 };
2664 static const unsigned int msiof1_ss1_e_mux[] = {
2665         MSIOF1_SS1_E_MARK,
2666 };
2667 static const unsigned int msiof1_ss2_e_pins[] = {
2668         /* SS2 */
2669         RCAR_GP_PIN(3, 5),
2670 };
2671 static const unsigned int msiof1_ss2_e_mux[] = {
2672         MSIOF1_SS2_E_MARK,
2673 };
2674 static const unsigned int msiof1_txd_e_pins[] = {
2675         /* TXD */
2676         RCAR_GP_PIN(3, 3),
2677 };
2678 static const unsigned int msiof1_txd_e_mux[] = {
2679         MSIOF1_TXD_E_MARK,
2680 };
2681 static const unsigned int msiof1_rxd_e_pins[] = {
2682         /* RXD */
2683         RCAR_GP_PIN(3, 2),
2684 };
2685 static const unsigned int msiof1_rxd_e_mux[] = {
2686         MSIOF1_RXD_E_MARK,
2687 };
2688 static const unsigned int msiof1_clk_f_pins[] = {
2689         /* SCK */
2690         RCAR_GP_PIN(5, 23),
2691 };
2692 static const unsigned int msiof1_clk_f_mux[] = {
2693         MSIOF1_SCK_F_MARK,
2694 };
2695 static const unsigned int msiof1_sync_f_pins[] = {
2696         /* SYNC */
2697         RCAR_GP_PIN(5, 24),
2698 };
2699 static const unsigned int msiof1_sync_f_mux[] = {
2700         MSIOF1_SYNC_F_MARK,
2701 };
2702 static const unsigned int msiof1_ss1_f_pins[] = {
2703         /* SS1 */
2704         RCAR_GP_PIN(6, 1),
2705 };
2706 static const unsigned int msiof1_ss1_f_mux[] = {
2707         MSIOF1_SS1_F_MARK,
2708 };
2709 static const unsigned int msiof1_ss2_f_pins[] = {
2710         /* SS2 */
2711         RCAR_GP_PIN(6, 2),
2712 };
2713 static const unsigned int msiof1_ss2_f_mux[] = {
2714         MSIOF1_SS2_F_MARK,
2715 };
2716 static const unsigned int msiof1_txd_f_pins[] = {
2717         /* TXD */
2718         RCAR_GP_PIN(6, 0),
2719 };
2720 static const unsigned int msiof1_txd_f_mux[] = {
2721         MSIOF1_TXD_F_MARK,
2722 };
2723 static const unsigned int msiof1_rxd_f_pins[] = {
2724         /* RXD */
2725         RCAR_GP_PIN(5, 25),
2726 };
2727 static const unsigned int msiof1_rxd_f_mux[] = {
2728         MSIOF1_RXD_F_MARK,
2729 };
2730 static const unsigned int msiof1_clk_g_pins[] = {
2731         /* SCK */
2732         RCAR_GP_PIN(3, 6),
2733 };
2734 static const unsigned int msiof1_clk_g_mux[] = {
2735         MSIOF1_SCK_G_MARK,
2736 };
2737 static const unsigned int msiof1_sync_g_pins[] = {
2738         /* SYNC */
2739         RCAR_GP_PIN(3, 7),
2740 };
2741 static const unsigned int msiof1_sync_g_mux[] = {
2742         MSIOF1_SYNC_G_MARK,
2743 };
2744 static const unsigned int msiof1_ss1_g_pins[] = {
2745         /* SS1 */
2746         RCAR_GP_PIN(3, 10),
2747 };
2748 static const unsigned int msiof1_ss1_g_mux[] = {
2749         MSIOF1_SS1_G_MARK,
2750 };
2751 static const unsigned int msiof1_ss2_g_pins[] = {
2752         /* SS2 */
2753         RCAR_GP_PIN(3, 11),
2754 };
2755 static const unsigned int msiof1_ss2_g_mux[] = {
2756         MSIOF1_SS2_G_MARK,
2757 };
2758 static const unsigned int msiof1_txd_g_pins[] = {
2759         /* TXD */
2760         RCAR_GP_PIN(3, 9),
2761 };
2762 static const unsigned int msiof1_txd_g_mux[] = {
2763         MSIOF1_TXD_G_MARK,
2764 };
2765 static const unsigned int msiof1_rxd_g_pins[] = {
2766         /* RXD */
2767         RCAR_GP_PIN(3, 8),
2768 };
2769 static const unsigned int msiof1_rxd_g_mux[] = {
2770         MSIOF1_RXD_G_MARK,
2771 };
2772 /* - MSIOF2 ----------------------------------------------------------------- */
2773 static const unsigned int msiof2_clk_a_pins[] = {
2774         /* SCK */
2775         RCAR_GP_PIN(1, 9),
2776 };
2777 static const unsigned int msiof2_clk_a_mux[] = {
2778         MSIOF2_SCK_A_MARK,
2779 };
2780 static const unsigned int msiof2_sync_a_pins[] = {
2781         /* SYNC */
2782         RCAR_GP_PIN(1, 8),
2783 };
2784 static const unsigned int msiof2_sync_a_mux[] = {
2785         MSIOF2_SYNC_A_MARK,
2786 };
2787 static const unsigned int msiof2_ss1_a_pins[] = {
2788         /* SS1 */
2789         RCAR_GP_PIN(1, 6),
2790 };
2791 static const unsigned int msiof2_ss1_a_mux[] = {
2792         MSIOF2_SS1_A_MARK,
2793 };
2794 static const unsigned int msiof2_ss2_a_pins[] = {
2795         /* SS2 */
2796         RCAR_GP_PIN(1, 7),
2797 };
2798 static const unsigned int msiof2_ss2_a_mux[] = {
2799         MSIOF2_SS2_A_MARK,
2800 };
2801 static const unsigned int msiof2_txd_a_pins[] = {
2802         /* TXD */
2803         RCAR_GP_PIN(1, 11),
2804 };
2805 static const unsigned int msiof2_txd_a_mux[] = {
2806         MSIOF2_TXD_A_MARK,
2807 };
2808 static const unsigned int msiof2_rxd_a_pins[] = {
2809         /* RXD */
2810         RCAR_GP_PIN(1, 10),
2811 };
2812 static const unsigned int msiof2_rxd_a_mux[] = {
2813         MSIOF2_RXD_A_MARK,
2814 };
2815 static const unsigned int msiof2_clk_b_pins[] = {
2816         /* SCK */
2817         RCAR_GP_PIN(0, 4),
2818 };
2819 static const unsigned int msiof2_clk_b_mux[] = {
2820         MSIOF2_SCK_B_MARK,
2821 };
2822 static const unsigned int msiof2_sync_b_pins[] = {
2823         /* SYNC */
2824         RCAR_GP_PIN(0, 5),
2825 };
2826 static const unsigned int msiof2_sync_b_mux[] = {
2827         MSIOF2_SYNC_B_MARK,
2828 };
2829 static const unsigned int msiof2_ss1_b_pins[] = {
2830         /* SS1 */
2831         RCAR_GP_PIN(0, 0),
2832 };
2833 static const unsigned int msiof2_ss1_b_mux[] = {
2834         MSIOF2_SS1_B_MARK,
2835 };
2836 static const unsigned int msiof2_ss2_b_pins[] = {
2837         /* SS2 */
2838         RCAR_GP_PIN(0, 1),
2839 };
2840 static const unsigned int msiof2_ss2_b_mux[] = {
2841         MSIOF2_SS2_B_MARK,
2842 };
2843 static const unsigned int msiof2_txd_b_pins[] = {
2844         /* TXD */
2845         RCAR_GP_PIN(0, 7),
2846 };
2847 static const unsigned int msiof2_txd_b_mux[] = {
2848         MSIOF2_TXD_B_MARK,
2849 };
2850 static const unsigned int msiof2_rxd_b_pins[] = {
2851         /* RXD */
2852         RCAR_GP_PIN(0, 6),
2853 };
2854 static const unsigned int msiof2_rxd_b_mux[] = {
2855         MSIOF2_RXD_B_MARK,
2856 };
2857 static const unsigned int msiof2_clk_c_pins[] = {
2858         /* SCK */
2859         RCAR_GP_PIN(2, 12),
2860 };
2861 static const unsigned int msiof2_clk_c_mux[] = {
2862         MSIOF2_SCK_C_MARK,
2863 };
2864 static const unsigned int msiof2_sync_c_pins[] = {
2865         /* SYNC */
2866         RCAR_GP_PIN(2, 11),
2867 };
2868 static const unsigned int msiof2_sync_c_mux[] = {
2869         MSIOF2_SYNC_C_MARK,
2870 };
2871 static const unsigned int msiof2_ss1_c_pins[] = {
2872         /* SS1 */
2873         RCAR_GP_PIN(2, 10),
2874 };
2875 static const unsigned int msiof2_ss1_c_mux[] = {
2876         MSIOF2_SS1_C_MARK,
2877 };
2878 static const unsigned int msiof2_ss2_c_pins[] = {
2879         /* SS2 */
2880         RCAR_GP_PIN(2, 9),
2881 };
2882 static const unsigned int msiof2_ss2_c_mux[] = {
2883         MSIOF2_SS2_C_MARK,
2884 };
2885 static const unsigned int msiof2_txd_c_pins[] = {
2886         /* TXD */
2887         RCAR_GP_PIN(2, 14),
2888 };
2889 static const unsigned int msiof2_txd_c_mux[] = {
2890         MSIOF2_TXD_C_MARK,
2891 };
2892 static const unsigned int msiof2_rxd_c_pins[] = {
2893         /* RXD */
2894         RCAR_GP_PIN(2, 13),
2895 };
2896 static const unsigned int msiof2_rxd_c_mux[] = {
2897         MSIOF2_RXD_C_MARK,
2898 };
2899 static const unsigned int msiof2_clk_d_pins[] = {
2900         /* SCK */
2901         RCAR_GP_PIN(0, 8),
2902 };
2903 static const unsigned int msiof2_clk_d_mux[] = {
2904         MSIOF2_SCK_D_MARK,
2905 };
2906 static const unsigned int msiof2_sync_d_pins[] = {
2907         /* SYNC */
2908         RCAR_GP_PIN(0, 9),
2909 };
2910 static const unsigned int msiof2_sync_d_mux[] = {
2911         MSIOF2_SYNC_D_MARK,
2912 };
2913 static const unsigned int msiof2_ss1_d_pins[] = {
2914         /* SS1 */
2915         RCAR_GP_PIN(0, 12),
2916 };
2917 static const unsigned int msiof2_ss1_d_mux[] = {
2918         MSIOF2_SS1_D_MARK,
2919 };
2920 static const unsigned int msiof2_ss2_d_pins[] = {
2921         /* SS2 */
2922         RCAR_GP_PIN(0, 13),
2923 };
2924 static const unsigned int msiof2_ss2_d_mux[] = {
2925         MSIOF2_SS2_D_MARK,
2926 };
2927 static const unsigned int msiof2_txd_d_pins[] = {
2928         /* TXD */
2929         RCAR_GP_PIN(0, 11),
2930 };
2931 static const unsigned int msiof2_txd_d_mux[] = {
2932         MSIOF2_TXD_D_MARK,
2933 };
2934 static const unsigned int msiof2_rxd_d_pins[] = {
2935         /* RXD */
2936         RCAR_GP_PIN(0, 10),
2937 };
2938 static const unsigned int msiof2_rxd_d_mux[] = {
2939         MSIOF2_RXD_D_MARK,
2940 };
2941 /* - MSIOF3 ----------------------------------------------------------------- */
2942 static const unsigned int msiof3_clk_a_pins[] = {
2943         /* SCK */
2944         RCAR_GP_PIN(0, 0),
2945 };
2946 static const unsigned int msiof3_clk_a_mux[] = {
2947         MSIOF3_SCK_A_MARK,
2948 };
2949 static const unsigned int msiof3_sync_a_pins[] = {
2950         /* SYNC */
2951         RCAR_GP_PIN(0, 1),
2952 };
2953 static const unsigned int msiof3_sync_a_mux[] = {
2954         MSIOF3_SYNC_A_MARK,
2955 };
2956 static const unsigned int msiof3_ss1_a_pins[] = {
2957         /* SS1 */
2958         RCAR_GP_PIN(0, 14),
2959 };
2960 static const unsigned int msiof3_ss1_a_mux[] = {
2961         MSIOF3_SS1_A_MARK,
2962 };
2963 static const unsigned int msiof3_ss2_a_pins[] = {
2964         /* SS2 */
2965         RCAR_GP_PIN(0, 15),
2966 };
2967 static const unsigned int msiof3_ss2_a_mux[] = {
2968         MSIOF3_SS2_A_MARK,
2969 };
2970 static const unsigned int msiof3_txd_a_pins[] = {
2971         /* TXD */
2972         RCAR_GP_PIN(0, 3),
2973 };
2974 static const unsigned int msiof3_txd_a_mux[] = {
2975         MSIOF3_TXD_A_MARK,
2976 };
2977 static const unsigned int msiof3_rxd_a_pins[] = {
2978         /* RXD */
2979         RCAR_GP_PIN(0, 2),
2980 };
2981 static const unsigned int msiof3_rxd_a_mux[] = {
2982         MSIOF3_RXD_A_MARK,
2983 };
2984 static const unsigned int msiof3_clk_b_pins[] = {
2985         /* SCK */
2986         RCAR_GP_PIN(1, 2),
2987 };
2988 static const unsigned int msiof3_clk_b_mux[] = {
2989         MSIOF3_SCK_B_MARK,
2990 };
2991 static const unsigned int msiof3_sync_b_pins[] = {
2992         /* SYNC */
2993         RCAR_GP_PIN(1, 0),
2994 };
2995 static const unsigned int msiof3_sync_b_mux[] = {
2996         MSIOF3_SYNC_B_MARK,
2997 };
2998 static const unsigned int msiof3_ss1_b_pins[] = {
2999         /* SS1 */
3000         RCAR_GP_PIN(1, 4),
3001 };
3002 static const unsigned int msiof3_ss1_b_mux[] = {
3003         MSIOF3_SS1_B_MARK,
3004 };
3005 static const unsigned int msiof3_ss2_b_pins[] = {
3006         /* SS2 */
3007         RCAR_GP_PIN(1, 5),
3008 };
3009 static const unsigned int msiof3_ss2_b_mux[] = {
3010         MSIOF3_SS2_B_MARK,
3011 };
3012 static const unsigned int msiof3_txd_b_pins[] = {
3013         /* TXD */
3014         RCAR_GP_PIN(1, 1),
3015 };
3016 static const unsigned int msiof3_txd_b_mux[] = {
3017         MSIOF3_TXD_B_MARK,
3018 };
3019 static const unsigned int msiof3_rxd_b_pins[] = {
3020         /* RXD */
3021         RCAR_GP_PIN(1, 3),
3022 };
3023 static const unsigned int msiof3_rxd_b_mux[] = {
3024         MSIOF3_RXD_B_MARK,
3025 };
3026 static const unsigned int msiof3_clk_c_pins[] = {
3027         /* SCK */
3028         RCAR_GP_PIN(1, 12),
3029 };
3030 static const unsigned int msiof3_clk_c_mux[] = {
3031         MSIOF3_SCK_C_MARK,
3032 };
3033 static const unsigned int msiof3_sync_c_pins[] = {
3034         /* SYNC */
3035         RCAR_GP_PIN(1, 13),
3036 };
3037 static const unsigned int msiof3_sync_c_mux[] = {
3038         MSIOF3_SYNC_C_MARK,
3039 };
3040 static const unsigned int msiof3_txd_c_pins[] = {
3041         /* TXD */
3042         RCAR_GP_PIN(1, 15),
3043 };
3044 static const unsigned int msiof3_txd_c_mux[] = {
3045         MSIOF3_TXD_C_MARK,
3046 };
3047 static const unsigned int msiof3_rxd_c_pins[] = {
3048         /* RXD */
3049         RCAR_GP_PIN(1, 14),
3050 };
3051 static const unsigned int msiof3_rxd_c_mux[] = {
3052         MSIOF3_RXD_C_MARK,
3053 };
3054 static const unsigned int msiof3_clk_d_pins[] = {
3055         /* SCK */
3056         RCAR_GP_PIN(1, 22),
3057 };
3058 static const unsigned int msiof3_clk_d_mux[] = {
3059         MSIOF3_SCK_D_MARK,
3060 };
3061 static const unsigned int msiof3_sync_d_pins[] = {
3062         /* SYNC */
3063         RCAR_GP_PIN(1, 23),
3064 };
3065 static const unsigned int msiof3_sync_d_mux[] = {
3066         MSIOF3_SYNC_D_MARK,
3067 };
3068 static const unsigned int msiof3_ss1_d_pins[] = {
3069         /* SS1 */
3070         RCAR_GP_PIN(1, 26),
3071 };
3072 static const unsigned int msiof3_ss1_d_mux[] = {
3073         MSIOF3_SS1_D_MARK,
3074 };
3075 static const unsigned int msiof3_txd_d_pins[] = {
3076         /* TXD */
3077         RCAR_GP_PIN(1, 25),
3078 };
3079 static const unsigned int msiof3_txd_d_mux[] = {
3080         MSIOF3_TXD_D_MARK,
3081 };
3082 static const unsigned int msiof3_rxd_d_pins[] = {
3083         /* RXD */
3084         RCAR_GP_PIN(1, 24),
3085 };
3086 static const unsigned int msiof3_rxd_d_mux[] = {
3087         MSIOF3_RXD_D_MARK,
3088 };
3089
3090 static const unsigned int msiof3_clk_e_pins[] = {
3091         /* SCK */
3092         RCAR_GP_PIN(2, 3),
3093 };
3094 static const unsigned int msiof3_clk_e_mux[] = {
3095         MSIOF3_SCK_E_MARK,
3096 };
3097 static const unsigned int msiof3_sync_e_pins[] = {
3098         /* SYNC */
3099         RCAR_GP_PIN(2, 2),
3100 };
3101 static const unsigned int msiof3_sync_e_mux[] = {
3102         MSIOF3_SYNC_E_MARK,
3103 };
3104 static const unsigned int msiof3_ss1_e_pins[] = {
3105         /* SS1 */
3106         RCAR_GP_PIN(2, 1),
3107 };
3108 static const unsigned int msiof3_ss1_e_mux[] = {
3109         MSIOF3_SS1_E_MARK,
3110 };
3111 static const unsigned int msiof3_ss2_e_pins[] = {
3112         /* SS1 */
3113         RCAR_GP_PIN(2, 0),
3114 };
3115 static const unsigned int msiof3_ss2_e_mux[] = {
3116         MSIOF3_SS2_E_MARK,
3117 };
3118 static const unsigned int msiof3_txd_e_pins[] = {
3119         /* TXD */
3120         RCAR_GP_PIN(2, 5),
3121 };
3122 static const unsigned int msiof3_txd_e_mux[] = {
3123         MSIOF3_TXD_E_MARK,
3124 };
3125 static const unsigned int msiof3_rxd_e_pins[] = {
3126         /* RXD */
3127         RCAR_GP_PIN(2, 4),
3128 };
3129 static const unsigned int msiof3_rxd_e_mux[] = {
3130         MSIOF3_RXD_E_MARK,
3131 };
3132
3133 /* - PWM0 --------------------------------------------------------------------*/
3134 static const unsigned int pwm0_pins[] = {
3135         /* PWM */
3136         RCAR_GP_PIN(2, 6),
3137 };
3138 static const unsigned int pwm0_mux[] = {
3139         PWM0_MARK,
3140 };
3141 /* - PWM1 --------------------------------------------------------------------*/
3142 static const unsigned int pwm1_a_pins[] = {
3143         /* PWM */
3144         RCAR_GP_PIN(2, 7),
3145 };
3146 static const unsigned int pwm1_a_mux[] = {
3147         PWM1_A_MARK,
3148 };
3149 static const unsigned int pwm1_b_pins[] = {
3150         /* PWM */
3151         RCAR_GP_PIN(1, 8),
3152 };
3153 static const unsigned int pwm1_b_mux[] = {
3154         PWM1_B_MARK,
3155 };
3156 /* - PWM2 --------------------------------------------------------------------*/
3157 static const unsigned int pwm2_a_pins[] = {
3158         /* PWM */
3159         RCAR_GP_PIN(2, 8),
3160 };
3161 static const unsigned int pwm2_a_mux[] = {
3162         PWM2_A_MARK,
3163 };
3164 static const unsigned int pwm2_b_pins[] = {
3165         /* PWM */
3166         RCAR_GP_PIN(1, 11),
3167 };
3168 static const unsigned int pwm2_b_mux[] = {
3169         PWM2_B_MARK,
3170 };
3171 /* - PWM3 --------------------------------------------------------------------*/
3172 static const unsigned int pwm3_a_pins[] = {
3173         /* PWM */
3174         RCAR_GP_PIN(1, 0),
3175 };
3176 static const unsigned int pwm3_a_mux[] = {
3177         PWM3_A_MARK,
3178 };
3179 static const unsigned int pwm3_b_pins[] = {
3180         /* PWM */
3181         RCAR_GP_PIN(2, 2),
3182 };
3183 static const unsigned int pwm3_b_mux[] = {
3184         PWM3_B_MARK,
3185 };
3186 /* - PWM4 --------------------------------------------------------------------*/
3187 static const unsigned int pwm4_a_pins[] = {
3188         /* PWM */
3189         RCAR_GP_PIN(1, 1),
3190 };
3191 static const unsigned int pwm4_a_mux[] = {
3192         PWM4_A_MARK,
3193 };
3194 static const unsigned int pwm4_b_pins[] = {
3195         /* PWM */
3196         RCAR_GP_PIN(2, 3),
3197 };
3198 static const unsigned int pwm4_b_mux[] = {
3199         PWM4_B_MARK,
3200 };
3201 /* - PWM5 --------------------------------------------------------------------*/
3202 static const unsigned int pwm5_a_pins[] = {
3203         /* PWM */
3204         RCAR_GP_PIN(1, 2),
3205 };
3206 static const unsigned int pwm5_a_mux[] = {
3207         PWM5_A_MARK,
3208 };
3209 static const unsigned int pwm5_b_pins[] = {
3210         /* PWM */
3211         RCAR_GP_PIN(2, 4),
3212 };
3213 static const unsigned int pwm5_b_mux[] = {
3214         PWM5_B_MARK,
3215 };
3216 /* - PWM6 --------------------------------------------------------------------*/
3217 static const unsigned int pwm6_a_pins[] = {
3218         /* PWM */
3219         RCAR_GP_PIN(1, 3),
3220 };
3221 static const unsigned int pwm6_a_mux[] = {
3222         PWM6_A_MARK,
3223 };
3224 static const unsigned int pwm6_b_pins[] = {
3225         /* PWM */
3226         RCAR_GP_PIN(2, 5),
3227 };
3228 static const unsigned int pwm6_b_mux[] = {
3229         PWM6_B_MARK,
3230 };
3231
3232 /* - SCIF0 ------------------------------------------------------------------ */
3233 static const unsigned int scif0_data_pins[] = {
3234         /* RX, TX */
3235         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3236 };
3237 static const unsigned int scif0_data_mux[] = {
3238         RX0_MARK, TX0_MARK,
3239 };
3240 static const unsigned int scif0_clk_pins[] = {
3241         /* SCK */
3242         RCAR_GP_PIN(5, 0),
3243 };
3244 static const unsigned int scif0_clk_mux[] = {
3245         SCK0_MARK,
3246 };
3247 static const unsigned int scif0_ctrl_pins[] = {
3248         /* RTS, CTS */
3249         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3250 };
3251 static const unsigned int scif0_ctrl_mux[] = {
3252         RTS0_N_MARK, CTS0_N_MARK,
3253 };
3254 /* - SCIF1 ------------------------------------------------------------------ */
3255 static const unsigned int scif1_data_a_pins[] = {
3256         /* RX, TX */
3257         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3258 };
3259 static const unsigned int scif1_data_a_mux[] = {
3260         RX1_A_MARK, TX1_A_MARK,
3261 };
3262 static const unsigned int scif1_clk_pins[] = {
3263         /* SCK */
3264         RCAR_GP_PIN(6, 21),
3265 };
3266 static const unsigned int scif1_clk_mux[] = {
3267         SCK1_MARK,
3268 };
3269 static const unsigned int scif1_ctrl_pins[] = {
3270         /* RTS, CTS */
3271         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3272 };
3273 static const unsigned int scif1_ctrl_mux[] = {
3274         RTS1_N_MARK, CTS1_N_MARK,
3275 };
3276
3277 static const unsigned int scif1_data_b_pins[] = {
3278         /* RX, TX */
3279         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3280 };
3281 static const unsigned int scif1_data_b_mux[] = {
3282         RX1_B_MARK, TX1_B_MARK,
3283 };
3284 /* - SCIF2 ------------------------------------------------------------------ */
3285 static const unsigned int scif2_data_a_pins[] = {
3286         /* RX, TX */
3287         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3288 };
3289 static const unsigned int scif2_data_a_mux[] = {
3290         RX2_A_MARK, TX2_A_MARK,
3291 };
3292 static const unsigned int scif2_clk_pins[] = {
3293         /* SCK */
3294         RCAR_GP_PIN(5, 9),
3295 };
3296 static const unsigned int scif2_clk_mux[] = {
3297         SCK2_MARK,
3298 };
3299 static const unsigned int scif2_data_b_pins[] = {
3300         /* RX, TX */
3301         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3302 };
3303 static const unsigned int scif2_data_b_mux[] = {
3304         RX2_B_MARK, TX2_B_MARK,
3305 };
3306 /* - SCIF3 ------------------------------------------------------------------ */
3307 static const unsigned int scif3_data_a_pins[] = {
3308         /* RX, TX */
3309         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3310 };
3311 static const unsigned int scif3_data_a_mux[] = {
3312         RX3_A_MARK, TX3_A_MARK,
3313 };
3314 static const unsigned int scif3_clk_pins[] = {
3315         /* SCK */
3316         RCAR_GP_PIN(1, 22),
3317 };
3318 static const unsigned int scif3_clk_mux[] = {
3319         SCK3_MARK,
3320 };
3321 static const unsigned int scif3_ctrl_pins[] = {
3322         /* RTS, CTS */
3323         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3324 };
3325 static const unsigned int scif3_ctrl_mux[] = {
3326         RTS3_N_MARK, CTS3_N_MARK,
3327 };
3328 static const unsigned int scif3_data_b_pins[] = {
3329         /* RX, TX */
3330         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3331 };
3332 static const unsigned int scif3_data_b_mux[] = {
3333         RX3_B_MARK, TX3_B_MARK,
3334 };
3335 /* - SCIF4 ------------------------------------------------------------------ */
3336 static const unsigned int scif4_data_a_pins[] = {
3337         /* RX, TX */
3338         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3339 };
3340 static const unsigned int scif4_data_a_mux[] = {
3341         RX4_A_MARK, TX4_A_MARK,
3342 };
3343 static const unsigned int scif4_clk_a_pins[] = {
3344         /* SCK */
3345         RCAR_GP_PIN(2, 10),
3346 };
3347 static const unsigned int scif4_clk_a_mux[] = {
3348         SCK4_A_MARK,
3349 };
3350 static const unsigned int scif4_ctrl_a_pins[] = {
3351         /* RTS, CTS */
3352         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3353 };
3354 static const unsigned int scif4_ctrl_a_mux[] = {
3355         RTS4_N_A_MARK, CTS4_N_A_MARK,
3356 };
3357 static const unsigned int scif4_data_b_pins[] = {
3358         /* RX, TX */
3359         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3360 };
3361 static const unsigned int scif4_data_b_mux[] = {
3362         RX4_B_MARK, TX4_B_MARK,
3363 };
3364 static const unsigned int scif4_clk_b_pins[] = {
3365         /* SCK */
3366         RCAR_GP_PIN(1, 5),
3367 };
3368 static const unsigned int scif4_clk_b_mux[] = {
3369         SCK4_B_MARK,
3370 };
3371 static const unsigned int scif4_ctrl_b_pins[] = {
3372         /* RTS, CTS */
3373         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3374 };
3375 static const unsigned int scif4_ctrl_b_mux[] = {
3376         RTS4_N_B_MARK, CTS4_N_B_MARK,
3377 };
3378 static const unsigned int scif4_data_c_pins[] = {
3379         /* RX, TX */
3380         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3381 };
3382 static const unsigned int scif4_data_c_mux[] = {
3383         RX4_C_MARK, TX4_C_MARK,
3384 };
3385 static const unsigned int scif4_clk_c_pins[] = {
3386         /* SCK */
3387         RCAR_GP_PIN(0, 8),
3388 };
3389 static const unsigned int scif4_clk_c_mux[] = {
3390         SCK4_C_MARK,
3391 };
3392 static const unsigned int scif4_ctrl_c_pins[] = {
3393         /* RTS, CTS */
3394         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3395 };
3396 static const unsigned int scif4_ctrl_c_mux[] = {
3397         RTS4_N_C_MARK, CTS4_N_C_MARK,
3398 };
3399 /* - SCIF5 ------------------------------------------------------------------ */
3400 static const unsigned int scif5_data_a_pins[] = {
3401         /* RX, TX */
3402         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3403 };
3404 static const unsigned int scif5_data_a_mux[] = {
3405         RX5_A_MARK, TX5_A_MARK,
3406 };
3407 static const unsigned int scif5_clk_a_pins[] = {
3408         /* SCK */
3409         RCAR_GP_PIN(6, 21),
3410 };
3411 static const unsigned int scif5_clk_a_mux[] = {
3412         SCK5_A_MARK,
3413 };
3414
3415 static const unsigned int scif5_data_b_pins[] = {
3416         /* RX, TX */
3417         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3418 };
3419 static const unsigned int scif5_data_b_mux[] = {
3420         RX5_B_MARK, TX5_B_MARK,
3421 };
3422 static const unsigned int scif5_clk_b_pins[] = {
3423         /* SCK */
3424         RCAR_GP_PIN(5, 0),
3425 };
3426 static const unsigned int scif5_clk_b_mux[] = {
3427         SCK5_B_MARK,
3428 };
3429
3430 /* - SCIF Clock ------------------------------------------------------------- */
3431 static const unsigned int scif_clk_a_pins[] = {
3432         /* SCIF_CLK */
3433         RCAR_GP_PIN(6, 23),
3434 };
3435 static const unsigned int scif_clk_a_mux[] = {
3436         SCIF_CLK_A_MARK,
3437 };
3438 static const unsigned int scif_clk_b_pins[] = {
3439         /* SCIF_CLK */
3440         RCAR_GP_PIN(5, 9),
3441 };
3442 static const unsigned int scif_clk_b_mux[] = {
3443         SCIF_CLK_B_MARK,
3444 };
3445
3446 /* - SDHI0 ------------------------------------------------------------------ */
3447 static const unsigned int sdhi0_data1_pins[] = {
3448         /* D0 */
3449         RCAR_GP_PIN(3, 2),
3450 };
3451 static const unsigned int sdhi0_data1_mux[] = {
3452         SD0_DAT0_MARK,
3453 };
3454 static const unsigned int sdhi0_data4_pins[] = {
3455         /* D[0:3] */
3456         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3457         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3458 };
3459 static const unsigned int sdhi0_data4_mux[] = {
3460         SD0_DAT0_MARK, SD0_DAT1_MARK,
3461         SD0_DAT2_MARK, SD0_DAT3_MARK,
3462 };
3463 static const unsigned int sdhi0_ctrl_pins[] = {
3464         /* CLK, CMD */
3465         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3466 };
3467 static const unsigned int sdhi0_ctrl_mux[] = {
3468         SD0_CLK_MARK, SD0_CMD_MARK,
3469 };
3470 static const unsigned int sdhi0_cd_pins[] = {
3471         /* CD */
3472         RCAR_GP_PIN(3, 12),
3473 };
3474 static const unsigned int sdhi0_cd_mux[] = {
3475         SD0_CD_MARK,
3476 };
3477 static const unsigned int sdhi0_wp_pins[] = {
3478         /* WP */
3479         RCAR_GP_PIN(3, 13),
3480 };
3481 static const unsigned int sdhi0_wp_mux[] = {
3482         SD0_WP_MARK,
3483 };
3484 /* - SDHI1 ------------------------------------------------------------------ */
3485 static const unsigned int sdhi1_data1_pins[] = {
3486         /* D0 */
3487         RCAR_GP_PIN(3, 8),
3488 };
3489 static const unsigned int sdhi1_data1_mux[] = {
3490         SD1_DAT0_MARK,
3491 };
3492 static const unsigned int sdhi1_data4_pins[] = {
3493         /* D[0:3] */
3494         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3495         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3496 };
3497 static const unsigned int sdhi1_data4_mux[] = {
3498         SD1_DAT0_MARK, SD1_DAT1_MARK,
3499         SD1_DAT2_MARK, SD1_DAT3_MARK,
3500 };
3501 static const unsigned int sdhi1_ctrl_pins[] = {
3502         /* CLK, CMD */
3503         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3504 };
3505 static const unsigned int sdhi1_ctrl_mux[] = {
3506         SD1_CLK_MARK, SD1_CMD_MARK,
3507 };
3508 static const unsigned int sdhi1_cd_pins[] = {
3509         /* CD */
3510         RCAR_GP_PIN(3, 14),
3511 };
3512 static const unsigned int sdhi1_cd_mux[] = {
3513         SD1_CD_MARK,
3514 };
3515 static const unsigned int sdhi1_wp_pins[] = {
3516         /* WP */
3517         RCAR_GP_PIN(3, 15),
3518 };
3519 static const unsigned int sdhi1_wp_mux[] = {
3520         SD1_WP_MARK,
3521 };
3522 /* - SDHI2 ------------------------------------------------------------------ */
3523 static const unsigned int sdhi2_data1_pins[] = {
3524         /* D0 */
3525         RCAR_GP_PIN(4, 2),
3526 };
3527 static const unsigned int sdhi2_data1_mux[] = {
3528         SD2_DAT0_MARK,
3529 };
3530 static const unsigned int sdhi2_data4_pins[] = {
3531         /* D[0:3] */
3532         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3533         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3534 };
3535 static const unsigned int sdhi2_data4_mux[] = {
3536         SD2_DAT0_MARK, SD2_DAT1_MARK,
3537         SD2_DAT2_MARK, SD2_DAT3_MARK,
3538 };
3539 static const unsigned int sdhi2_data8_pins[] = {
3540         /* D[0:7] */
3541         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3542         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3543         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3544         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3545 };
3546 static const unsigned int sdhi2_data8_mux[] = {
3547         SD2_DAT0_MARK, SD2_DAT1_MARK,
3548         SD2_DAT2_MARK, SD2_DAT3_MARK,
3549         SD2_DAT4_MARK, SD2_DAT5_MARK,
3550         SD2_DAT6_MARK, SD2_DAT7_MARK,
3551 };
3552 static const unsigned int sdhi2_ctrl_pins[] = {
3553         /* CLK, CMD */
3554         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3555 };
3556 static const unsigned int sdhi2_ctrl_mux[] = {
3557         SD2_CLK_MARK, SD2_CMD_MARK,
3558 };
3559 static const unsigned int sdhi2_cd_a_pins[] = {
3560         /* CD */
3561         RCAR_GP_PIN(4, 13),
3562 };
3563 static const unsigned int sdhi2_cd_a_mux[] = {
3564         SD2_CD_A_MARK,
3565 };
3566 static const unsigned int sdhi2_cd_b_pins[] = {
3567         /* CD */
3568         RCAR_GP_PIN(5, 10),
3569 };
3570 static const unsigned int sdhi2_cd_b_mux[] = {
3571         SD2_CD_B_MARK,
3572 };
3573 static const unsigned int sdhi2_wp_a_pins[] = {
3574         /* WP */
3575         RCAR_GP_PIN(4, 14),
3576 };
3577 static const unsigned int sdhi2_wp_a_mux[] = {
3578         SD2_WP_A_MARK,
3579 };
3580 static const unsigned int sdhi2_wp_b_pins[] = {
3581         /* WP */
3582         RCAR_GP_PIN(5, 11),
3583 };
3584 static const unsigned int sdhi2_wp_b_mux[] = {
3585         SD2_WP_B_MARK,
3586 };
3587 static const unsigned int sdhi2_ds_pins[] = {
3588         /* DS */
3589         RCAR_GP_PIN(4, 6),
3590 };
3591 static const unsigned int sdhi2_ds_mux[] = {
3592         SD2_DS_MARK,
3593 };
3594 /* - SDHI3 ------------------------------------------------------------------ */
3595 static const unsigned int sdhi3_data1_pins[] = {
3596         /* D0 */
3597         RCAR_GP_PIN(4, 9),
3598 };
3599 static const unsigned int sdhi3_data1_mux[] = {
3600         SD3_DAT0_MARK,
3601 };
3602 static const unsigned int sdhi3_data4_pins[] = {
3603         /* D[0:3] */
3604         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3605         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3606 };
3607 static const unsigned int sdhi3_data4_mux[] = {
3608         SD3_DAT0_MARK, SD3_DAT1_MARK,
3609         SD3_DAT2_MARK, SD3_DAT3_MARK,
3610 };
3611 static const unsigned int sdhi3_data8_pins[] = {
3612         /* D[0:7] */
3613         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3614         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3615         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3616         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3617 };
3618 static const unsigned int sdhi3_data8_mux[] = {
3619         SD3_DAT0_MARK, SD3_DAT1_MARK,
3620         SD3_DAT2_MARK, SD3_DAT3_MARK,
3621         SD3_DAT4_MARK, SD3_DAT5_MARK,
3622         SD3_DAT6_MARK, SD3_DAT7_MARK,
3623 };
3624 static const unsigned int sdhi3_ctrl_pins[] = {
3625         /* CLK, CMD */
3626         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3627 };
3628 static const unsigned int sdhi3_ctrl_mux[] = {
3629         SD3_CLK_MARK, SD3_CMD_MARK,
3630 };
3631 static const unsigned int sdhi3_cd_pins[] = {
3632         /* CD */
3633         RCAR_GP_PIN(4, 15),
3634 };
3635 static const unsigned int sdhi3_cd_mux[] = {
3636         SD3_CD_MARK,
3637 };
3638 static const unsigned int sdhi3_wp_pins[] = {
3639         /* WP */
3640         RCAR_GP_PIN(4, 16),
3641 };
3642 static const unsigned int sdhi3_wp_mux[] = {
3643         SD3_WP_MARK,
3644 };
3645 static const unsigned int sdhi3_ds_pins[] = {
3646         /* DS */
3647         RCAR_GP_PIN(4, 17),
3648 };
3649 static const unsigned int sdhi3_ds_mux[] = {
3650         SD3_DS_MARK,
3651 };
3652
3653 /* - SSI -------------------------------------------------------------------- */
3654 static const unsigned int ssi0_data_pins[] = {
3655         /* SDATA */
3656         RCAR_GP_PIN(6, 2),
3657 };
3658 static const unsigned int ssi0_data_mux[] = {
3659         SSI_SDATA0_MARK,
3660 };
3661 static const unsigned int ssi01239_ctrl_pins[] = {
3662         /* SCK, WS */
3663         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3664 };
3665 static const unsigned int ssi01239_ctrl_mux[] = {
3666         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3667 };
3668 static const unsigned int ssi1_data_a_pins[] = {
3669         /* SDATA */
3670         RCAR_GP_PIN(6, 3),
3671 };
3672 static const unsigned int ssi1_data_a_mux[] = {
3673         SSI_SDATA1_A_MARK,
3674 };
3675 static const unsigned int ssi1_data_b_pins[] = {
3676         /* SDATA */
3677         RCAR_GP_PIN(5, 12),
3678 };
3679 static const unsigned int ssi1_data_b_mux[] = {
3680         SSI_SDATA1_B_MARK,
3681 };
3682 static const unsigned int ssi1_ctrl_a_pins[] = {
3683         /* SCK, WS */
3684         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3685 };
3686 static const unsigned int ssi1_ctrl_a_mux[] = {
3687         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3688 };
3689 static const unsigned int ssi1_ctrl_b_pins[] = {
3690         /* SCK, WS */
3691         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3692 };
3693 static const unsigned int ssi1_ctrl_b_mux[] = {
3694         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3695 };
3696 static const unsigned int ssi2_data_a_pins[] = {
3697         /* SDATA */
3698         RCAR_GP_PIN(6, 4),
3699 };
3700 static const unsigned int ssi2_data_a_mux[] = {
3701         SSI_SDATA2_A_MARK,
3702 };
3703 static const unsigned int ssi2_data_b_pins[] = {
3704         /* SDATA */
3705         RCAR_GP_PIN(5, 13),
3706 };
3707 static const unsigned int ssi2_data_b_mux[] = {
3708         SSI_SDATA2_B_MARK,
3709 };
3710 static const unsigned int ssi2_ctrl_a_pins[] = {
3711         /* SCK, WS */
3712         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3713 };
3714 static const unsigned int ssi2_ctrl_a_mux[] = {
3715         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3716 };
3717 static const unsigned int ssi2_ctrl_b_pins[] = {
3718         /* SCK, WS */
3719         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3720 };
3721 static const unsigned int ssi2_ctrl_b_mux[] = {
3722         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3723 };
3724 static const unsigned int ssi3_data_pins[] = {
3725         /* SDATA */
3726         RCAR_GP_PIN(6, 7),
3727 };
3728 static const unsigned int ssi3_data_mux[] = {
3729         SSI_SDATA3_MARK,
3730 };
3731 static const unsigned int ssi349_ctrl_pins[] = {
3732         /* SCK, WS */
3733         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3734 };
3735 static const unsigned int ssi349_ctrl_mux[] = {
3736         SSI_SCK349_MARK, SSI_WS349_MARK,
3737 };
3738 static const unsigned int ssi4_data_pins[] = {
3739         /* SDATA */
3740         RCAR_GP_PIN(6, 10),
3741 };
3742 static const unsigned int ssi4_data_mux[] = {
3743         SSI_SDATA4_MARK,
3744 };
3745 static const unsigned int ssi4_ctrl_pins[] = {
3746         /* SCK, WS */
3747         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3748 };
3749 static const unsigned int ssi4_ctrl_mux[] = {
3750         SSI_SCK4_MARK, SSI_WS4_MARK,
3751 };
3752 static const unsigned int ssi5_data_pins[] = {
3753         /* SDATA */
3754         RCAR_GP_PIN(6, 13),
3755 };
3756 static const unsigned int ssi5_data_mux[] = {
3757         SSI_SDATA5_MARK,
3758 };
3759 static const unsigned int ssi5_ctrl_pins[] = {
3760         /* SCK, WS */
3761         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3762 };
3763 static const unsigned int ssi5_ctrl_mux[] = {
3764         SSI_SCK5_MARK, SSI_WS5_MARK,
3765 };
3766 static const unsigned int ssi6_data_pins[] = {
3767         /* SDATA */
3768         RCAR_GP_PIN(6, 16),
3769 };
3770 static const unsigned int ssi6_data_mux[] = {
3771         SSI_SDATA6_MARK,
3772 };
3773 static const unsigned int ssi6_ctrl_pins[] = {
3774         /* SCK, WS */
3775         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3776 };
3777 static const unsigned int ssi6_ctrl_mux[] = {
3778         SSI_SCK6_MARK, SSI_WS6_MARK,
3779 };
3780 static const unsigned int ssi7_data_pins[] = {
3781         /* SDATA */
3782         RCAR_GP_PIN(6, 19),
3783 };
3784 static const unsigned int ssi7_data_mux[] = {
3785         SSI_SDATA7_MARK,
3786 };
3787 static const unsigned int ssi78_ctrl_pins[] = {
3788         /* SCK, WS */
3789         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3790 };
3791 static const unsigned int ssi78_ctrl_mux[] = {
3792         SSI_SCK78_MARK, SSI_WS78_MARK,
3793 };
3794 static const unsigned int ssi8_data_pins[] = {
3795         /* SDATA */
3796         RCAR_GP_PIN(6, 20),
3797 };
3798 static const unsigned int ssi8_data_mux[] = {
3799         SSI_SDATA8_MARK,
3800 };
3801 static const unsigned int ssi9_data_a_pins[] = {
3802         /* SDATA */
3803         RCAR_GP_PIN(6, 21),
3804 };
3805 static const unsigned int ssi9_data_a_mux[] = {
3806         SSI_SDATA9_A_MARK,
3807 };
3808 static const unsigned int ssi9_data_b_pins[] = {
3809         /* SDATA */
3810         RCAR_GP_PIN(5, 14),
3811 };
3812 static const unsigned int ssi9_data_b_mux[] = {
3813         SSI_SDATA9_B_MARK,
3814 };
3815 static const unsigned int ssi9_ctrl_a_pins[] = {
3816         /* SCK, WS */
3817         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3818 };
3819 static const unsigned int ssi9_ctrl_a_mux[] = {
3820         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3821 };
3822 static const unsigned int ssi9_ctrl_b_pins[] = {
3823         /* SCK, WS */
3824         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3825 };
3826 static const unsigned int ssi9_ctrl_b_mux[] = {
3827         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3828 };
3829
3830 /* - USB0 ------------------------------------------------------------------- */
3831 static const unsigned int usb0_pins[] = {
3832         /* PWEN, OVC */
3833         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3834 };
3835 static const unsigned int usb0_mux[] = {
3836         USB0_PWEN_MARK, USB0_OVC_MARK,
3837 };
3838 /* - USB1 ------------------------------------------------------------------- */
3839 static const unsigned int usb1_pins[] = {
3840         /* PWEN, OVC */
3841         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3842 };
3843 static const unsigned int usb1_mux[] = {
3844         USB1_PWEN_MARK, USB1_OVC_MARK,
3845 };
3846
3847 /* - USB30 ------------------------------------------------------------------ */
3848 static const unsigned int usb30_pins[] = {
3849         /* PWEN, OVC */
3850         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3851 };
3852 static const unsigned int usb30_mux[] = {
3853         USB30_PWEN_MARK, USB30_OVC_MARK,
3854 };
3855
3856 static const struct sh_pfc_pin_group pinmux_groups[] = {
3857         SH_PFC_PIN_GROUP(audio_clk_a_a),
3858         SH_PFC_PIN_GROUP(audio_clk_a_b),
3859         SH_PFC_PIN_GROUP(audio_clk_a_c),
3860         SH_PFC_PIN_GROUP(audio_clk_b_a),
3861         SH_PFC_PIN_GROUP(audio_clk_b_b),
3862         SH_PFC_PIN_GROUP(audio_clk_c_a),
3863         SH_PFC_PIN_GROUP(audio_clk_c_b),
3864         SH_PFC_PIN_GROUP(audio_clkout_a),
3865         SH_PFC_PIN_GROUP(audio_clkout_b),
3866         SH_PFC_PIN_GROUP(audio_clkout_c),
3867         SH_PFC_PIN_GROUP(audio_clkout_d),
3868         SH_PFC_PIN_GROUP(audio_clkout1_a),
3869         SH_PFC_PIN_GROUP(audio_clkout1_b),
3870         SH_PFC_PIN_GROUP(audio_clkout2_a),
3871         SH_PFC_PIN_GROUP(audio_clkout2_b),
3872         SH_PFC_PIN_GROUP(audio_clkout3_a),
3873         SH_PFC_PIN_GROUP(audio_clkout3_b),
3874         SH_PFC_PIN_GROUP(avb_link),
3875         SH_PFC_PIN_GROUP(avb_magic),
3876         SH_PFC_PIN_GROUP(avb_phy_int),
3877         SH_PFC_PIN_GROUP(avb_mdc),
3878         SH_PFC_PIN_GROUP(avb_mii),
3879         SH_PFC_PIN_GROUP(avb_avtp_pps),
3880         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3881         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3882         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3883         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3884         SH_PFC_PIN_GROUP(can0_data_a),
3885         SH_PFC_PIN_GROUP(can0_data_b),
3886         SH_PFC_PIN_GROUP(can1_data),
3887         SH_PFC_PIN_GROUP(can_clk),
3888         SH_PFC_PIN_GROUP(canfd0_data_a),
3889         SH_PFC_PIN_GROUP(canfd0_data_b),
3890         SH_PFC_PIN_GROUP(canfd1_data),
3891         SH_PFC_PIN_GROUP(drif0_ctrl_a),
3892         SH_PFC_PIN_GROUP(drif0_data0_a),
3893         SH_PFC_PIN_GROUP(drif0_data1_a),
3894         SH_PFC_PIN_GROUP(drif0_ctrl_b),
3895         SH_PFC_PIN_GROUP(drif0_data0_b),
3896         SH_PFC_PIN_GROUP(drif0_data1_b),
3897         SH_PFC_PIN_GROUP(drif0_ctrl_c),
3898         SH_PFC_PIN_GROUP(drif0_data0_c),
3899         SH_PFC_PIN_GROUP(drif0_data1_c),
3900         SH_PFC_PIN_GROUP(drif1_ctrl_a),
3901         SH_PFC_PIN_GROUP(drif1_data0_a),
3902         SH_PFC_PIN_GROUP(drif1_data1_a),
3903         SH_PFC_PIN_GROUP(drif1_ctrl_b),
3904         SH_PFC_PIN_GROUP(drif1_data0_b),
3905         SH_PFC_PIN_GROUP(drif1_data1_b),
3906         SH_PFC_PIN_GROUP(drif1_ctrl_c),
3907         SH_PFC_PIN_GROUP(drif1_data0_c),
3908         SH_PFC_PIN_GROUP(drif1_data1_c),
3909         SH_PFC_PIN_GROUP(drif2_ctrl_a),
3910         SH_PFC_PIN_GROUP(drif2_data0_a),
3911         SH_PFC_PIN_GROUP(drif2_data1_a),
3912         SH_PFC_PIN_GROUP(drif2_ctrl_b),
3913         SH_PFC_PIN_GROUP(drif2_data0_b),
3914         SH_PFC_PIN_GROUP(drif2_data1_b),
3915         SH_PFC_PIN_GROUP(drif3_ctrl_a),
3916         SH_PFC_PIN_GROUP(drif3_data0_a),
3917         SH_PFC_PIN_GROUP(drif3_data1_a),
3918         SH_PFC_PIN_GROUP(drif3_ctrl_b),
3919         SH_PFC_PIN_GROUP(drif3_data0_b),
3920         SH_PFC_PIN_GROUP(drif3_data1_b),
3921         SH_PFC_PIN_GROUP(du_rgb666),
3922         SH_PFC_PIN_GROUP(du_rgb888),
3923         SH_PFC_PIN_GROUP(du_clk_out_0),
3924         SH_PFC_PIN_GROUP(du_clk_out_1),
3925         SH_PFC_PIN_GROUP(du_sync),
3926         SH_PFC_PIN_GROUP(du_oddf),
3927         SH_PFC_PIN_GROUP(du_cde),
3928         SH_PFC_PIN_GROUP(du_disp),
3929         SH_PFC_PIN_GROUP(hscif0_data),
3930         SH_PFC_PIN_GROUP(hscif0_clk),
3931         SH_PFC_PIN_GROUP(hscif0_ctrl),
3932         SH_PFC_PIN_GROUP(hscif1_data_a),
3933         SH_PFC_PIN_GROUP(hscif1_clk_a),
3934         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3935         SH_PFC_PIN_GROUP(hscif1_data_b),
3936         SH_PFC_PIN_GROUP(hscif1_clk_b),
3937         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3938         SH_PFC_PIN_GROUP(hscif2_data_a),
3939         SH_PFC_PIN_GROUP(hscif2_clk_a),
3940         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3941         SH_PFC_PIN_GROUP(hscif2_data_b),
3942         SH_PFC_PIN_GROUP(hscif2_clk_b),
3943         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3944         SH_PFC_PIN_GROUP(hscif2_data_c),
3945         SH_PFC_PIN_GROUP(hscif2_clk_c),
3946         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3947         SH_PFC_PIN_GROUP(hscif3_data_a),
3948         SH_PFC_PIN_GROUP(hscif3_clk),
3949         SH_PFC_PIN_GROUP(hscif3_ctrl),
3950         SH_PFC_PIN_GROUP(hscif3_data_b),
3951         SH_PFC_PIN_GROUP(hscif3_data_c),
3952         SH_PFC_PIN_GROUP(hscif3_data_d),
3953         SH_PFC_PIN_GROUP(hscif4_data_a),
3954         SH_PFC_PIN_GROUP(hscif4_clk),
3955         SH_PFC_PIN_GROUP(hscif4_ctrl),
3956         SH_PFC_PIN_GROUP(hscif4_data_b),
3957         SH_PFC_PIN_GROUP(i2c1_a),
3958         SH_PFC_PIN_GROUP(i2c1_b),
3959         SH_PFC_PIN_GROUP(i2c2_a),
3960         SH_PFC_PIN_GROUP(i2c2_b),
3961         SH_PFC_PIN_GROUP(i2c6_a),
3962         SH_PFC_PIN_GROUP(i2c6_b),
3963         SH_PFC_PIN_GROUP(i2c6_c),
3964         SH_PFC_PIN_GROUP(intc_ex_irq0),
3965         SH_PFC_PIN_GROUP(intc_ex_irq1),
3966         SH_PFC_PIN_GROUP(intc_ex_irq2),
3967         SH_PFC_PIN_GROUP(intc_ex_irq3),
3968         SH_PFC_PIN_GROUP(intc_ex_irq4),
3969         SH_PFC_PIN_GROUP(intc_ex_irq5),
3970         SH_PFC_PIN_GROUP(msiof0_clk),
3971         SH_PFC_PIN_GROUP(msiof0_sync),
3972         SH_PFC_PIN_GROUP(msiof0_ss1),
3973         SH_PFC_PIN_GROUP(msiof0_ss2),
3974         SH_PFC_PIN_GROUP(msiof0_txd),
3975         SH_PFC_PIN_GROUP(msiof0_rxd),
3976         SH_PFC_PIN_GROUP(msiof1_clk_a),
3977         SH_PFC_PIN_GROUP(msiof1_sync_a),
3978         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3979         SH_PFC_PIN_GROUP(msiof1_ss2_a),
3980         SH_PFC_PIN_GROUP(msiof1_txd_a),
3981         SH_PFC_PIN_GROUP(msiof1_rxd_a),
3982         SH_PFC_PIN_GROUP(msiof1_clk_b),
3983         SH_PFC_PIN_GROUP(msiof1_sync_b),
3984         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3985         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3986         SH_PFC_PIN_GROUP(msiof1_txd_b),
3987         SH_PFC_PIN_GROUP(msiof1_rxd_b),
3988         SH_PFC_PIN_GROUP(msiof1_clk_c),
3989         SH_PFC_PIN_GROUP(msiof1_sync_c),
3990         SH_PFC_PIN_GROUP(msiof1_ss1_c),
3991         SH_PFC_PIN_GROUP(msiof1_ss2_c),
3992         SH_PFC_PIN_GROUP(msiof1_txd_c),
3993         SH_PFC_PIN_GROUP(msiof1_rxd_c),
3994         SH_PFC_PIN_GROUP(msiof1_clk_d),
3995         SH_PFC_PIN_GROUP(msiof1_sync_d),
3996         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3997         SH_PFC_PIN_GROUP(msiof1_ss2_d),
3998         SH_PFC_PIN_GROUP(msiof1_txd_d),
3999         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4000         SH_PFC_PIN_GROUP(msiof1_clk_e),
4001         SH_PFC_PIN_GROUP(msiof1_sync_e),
4002         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4003         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4004         SH_PFC_PIN_GROUP(msiof1_txd_e),
4005         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4006         SH_PFC_PIN_GROUP(msiof1_clk_f),
4007         SH_PFC_PIN_GROUP(msiof1_sync_f),
4008         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4009         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4010         SH_PFC_PIN_GROUP(msiof1_txd_f),
4011         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4012         SH_PFC_PIN_GROUP(msiof1_clk_g),
4013         SH_PFC_PIN_GROUP(msiof1_sync_g),
4014         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4015         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4016         SH_PFC_PIN_GROUP(msiof1_txd_g),
4017         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4018         SH_PFC_PIN_GROUP(msiof2_clk_a),
4019         SH_PFC_PIN_GROUP(msiof2_sync_a),
4020         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4021         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4022         SH_PFC_PIN_GROUP(msiof2_txd_a),
4023         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4024         SH_PFC_PIN_GROUP(msiof2_clk_b),
4025         SH_PFC_PIN_GROUP(msiof2_sync_b),
4026         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4027         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4028         SH_PFC_PIN_GROUP(msiof2_txd_b),
4029         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4030         SH_PFC_PIN_GROUP(msiof2_clk_c),
4031         SH_PFC_PIN_GROUP(msiof2_sync_c),
4032         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4033         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4034         SH_PFC_PIN_GROUP(msiof2_txd_c),
4035         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4036         SH_PFC_PIN_GROUP(msiof2_clk_d),
4037         SH_PFC_PIN_GROUP(msiof2_sync_d),
4038         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4039         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4040         SH_PFC_PIN_GROUP(msiof2_txd_d),
4041         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4042         SH_PFC_PIN_GROUP(msiof3_clk_a),
4043         SH_PFC_PIN_GROUP(msiof3_sync_a),
4044         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4045         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4046         SH_PFC_PIN_GROUP(msiof3_txd_a),
4047         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4048         SH_PFC_PIN_GROUP(msiof3_clk_b),
4049         SH_PFC_PIN_GROUP(msiof3_sync_b),
4050         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4051         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4052         SH_PFC_PIN_GROUP(msiof3_txd_b),
4053         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4054         SH_PFC_PIN_GROUP(msiof3_clk_c),
4055         SH_PFC_PIN_GROUP(msiof3_sync_c),
4056         SH_PFC_PIN_GROUP(msiof3_txd_c),
4057         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4058         SH_PFC_PIN_GROUP(msiof3_clk_d),
4059         SH_PFC_PIN_GROUP(msiof3_sync_d),
4060         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4061         SH_PFC_PIN_GROUP(msiof3_txd_d),
4062         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4063         SH_PFC_PIN_GROUP(msiof3_clk_e),
4064         SH_PFC_PIN_GROUP(msiof3_sync_e),
4065         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4066         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4067         SH_PFC_PIN_GROUP(msiof3_txd_e),
4068         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4069         SH_PFC_PIN_GROUP(pwm0),
4070         SH_PFC_PIN_GROUP(pwm1_a),
4071         SH_PFC_PIN_GROUP(pwm1_b),
4072         SH_PFC_PIN_GROUP(pwm2_a),
4073         SH_PFC_PIN_GROUP(pwm2_b),
4074         SH_PFC_PIN_GROUP(pwm3_a),
4075         SH_PFC_PIN_GROUP(pwm3_b),
4076         SH_PFC_PIN_GROUP(pwm4_a),
4077         SH_PFC_PIN_GROUP(pwm4_b),
4078         SH_PFC_PIN_GROUP(pwm5_a),
4079         SH_PFC_PIN_GROUP(pwm5_b),
4080         SH_PFC_PIN_GROUP(pwm6_a),
4081         SH_PFC_PIN_GROUP(pwm6_b),
4082         SH_PFC_PIN_GROUP(scif0_data),
4083         SH_PFC_PIN_GROUP(scif0_clk),
4084         SH_PFC_PIN_GROUP(scif0_ctrl),
4085         SH_PFC_PIN_GROUP(scif1_data_a),
4086         SH_PFC_PIN_GROUP(scif1_clk),
4087         SH_PFC_PIN_GROUP(scif1_ctrl),
4088         SH_PFC_PIN_GROUP(scif1_data_b),
4089         SH_PFC_PIN_GROUP(scif2_data_a),
4090         SH_PFC_PIN_GROUP(scif2_clk),
4091         SH_PFC_PIN_GROUP(scif2_data_b),
4092         SH_PFC_PIN_GROUP(scif3_data_a),
4093         SH_PFC_PIN_GROUP(scif3_clk),
4094         SH_PFC_PIN_GROUP(scif3_ctrl),
4095         SH_PFC_PIN_GROUP(scif3_data_b),
4096         SH_PFC_PIN_GROUP(scif4_data_a),
4097         SH_PFC_PIN_GROUP(scif4_clk_a),
4098         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4099         SH_PFC_PIN_GROUP(scif4_data_b),
4100         SH_PFC_PIN_GROUP(scif4_clk_b),
4101         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4102         SH_PFC_PIN_GROUP(scif4_data_c),
4103         SH_PFC_PIN_GROUP(scif4_clk_c),
4104         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4105         SH_PFC_PIN_GROUP(scif5_data_a),
4106         SH_PFC_PIN_GROUP(scif5_clk_a),
4107         SH_PFC_PIN_GROUP(scif5_data_b),
4108         SH_PFC_PIN_GROUP(scif5_clk_b),
4109         SH_PFC_PIN_GROUP(scif_clk_a),
4110         SH_PFC_PIN_GROUP(scif_clk_b),
4111         SH_PFC_PIN_GROUP(sdhi0_data1),
4112         SH_PFC_PIN_GROUP(sdhi0_data4),
4113         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4114         SH_PFC_PIN_GROUP(sdhi0_cd),
4115         SH_PFC_PIN_GROUP(sdhi0_wp),
4116         SH_PFC_PIN_GROUP(sdhi1_data1),
4117         SH_PFC_PIN_GROUP(sdhi1_data4),
4118         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4119         SH_PFC_PIN_GROUP(sdhi1_cd),
4120         SH_PFC_PIN_GROUP(sdhi1_wp),
4121         SH_PFC_PIN_GROUP(sdhi2_data1),
4122         SH_PFC_PIN_GROUP(sdhi2_data4),
4123         SH_PFC_PIN_GROUP(sdhi2_data8),
4124         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4125         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4126         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4127         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4128         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4129         SH_PFC_PIN_GROUP(sdhi2_ds),
4130         SH_PFC_PIN_GROUP(sdhi3_data1),
4131         SH_PFC_PIN_GROUP(sdhi3_data4),
4132         SH_PFC_PIN_GROUP(sdhi3_data8),
4133         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4134         SH_PFC_PIN_GROUP(sdhi3_cd),
4135         SH_PFC_PIN_GROUP(sdhi3_wp),
4136         SH_PFC_PIN_GROUP(sdhi3_ds),
4137         SH_PFC_PIN_GROUP(ssi0_data),
4138         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4139         SH_PFC_PIN_GROUP(ssi1_data_a),
4140         SH_PFC_PIN_GROUP(ssi1_data_b),
4141         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4142         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4143         SH_PFC_PIN_GROUP(ssi2_data_a),
4144         SH_PFC_PIN_GROUP(ssi2_data_b),
4145         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4146         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4147         SH_PFC_PIN_GROUP(ssi3_data),
4148         SH_PFC_PIN_GROUP(ssi349_ctrl),
4149         SH_PFC_PIN_GROUP(ssi4_data),
4150         SH_PFC_PIN_GROUP(ssi4_ctrl),
4151         SH_PFC_PIN_GROUP(ssi5_data),
4152         SH_PFC_PIN_GROUP(ssi5_ctrl),
4153         SH_PFC_PIN_GROUP(ssi6_data),
4154         SH_PFC_PIN_GROUP(ssi6_ctrl),
4155         SH_PFC_PIN_GROUP(ssi7_data),
4156         SH_PFC_PIN_GROUP(ssi78_ctrl),
4157         SH_PFC_PIN_GROUP(ssi8_data),
4158         SH_PFC_PIN_GROUP(ssi9_data_a),
4159         SH_PFC_PIN_GROUP(ssi9_data_b),
4160         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4161         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4162         SH_PFC_PIN_GROUP(usb0),
4163         SH_PFC_PIN_GROUP(usb1),
4164         SH_PFC_PIN_GROUP(usb30),
4165 };
4166
4167 static const char * const audio_clk_groups[] = {
4168         "audio_clk_a_a",
4169         "audio_clk_a_b",
4170         "audio_clk_a_c",
4171         "audio_clk_b_a",
4172         "audio_clk_b_b",
4173         "audio_clk_c_a",
4174         "audio_clk_c_b",
4175         "audio_clkout_a",
4176         "audio_clkout_b",
4177         "audio_clkout_c",
4178         "audio_clkout_d",
4179         "audio_clkout1_a",
4180         "audio_clkout1_b",
4181         "audio_clkout2_a",
4182         "audio_clkout2_b",
4183         "audio_clkout3_a",
4184         "audio_clkout3_b",
4185 };
4186
4187 static const char * const avb_groups[] = {
4188         "avb_link",
4189         "avb_magic",
4190         "avb_phy_int",
4191         "avb_mdc",
4192         "avb_mii",
4193         "avb_avtp_pps",
4194         "avb_avtp_match_a",
4195         "avb_avtp_capture_a",
4196         "avb_avtp_match_b",
4197         "avb_avtp_capture_b",
4198 };
4199
4200 static const char * const can0_groups[] = {
4201         "can0_data_a",
4202         "can0_data_b",
4203 };
4204
4205 static const char * const can1_groups[] = {
4206         "can1_data",
4207 };
4208
4209 static const char * const can_clk_groups[] = {
4210         "can_clk",
4211 };
4212
4213 static const char * const canfd0_groups[] = {
4214         "canfd0_data_a",
4215         "canfd0_data_b",
4216 };
4217
4218 static const char * const canfd1_groups[] = {
4219         "canfd1_data",
4220 };
4221
4222 static const char * const drif0_groups[] = {
4223         "drif0_ctrl_a",
4224         "drif0_data0_a",
4225         "drif0_data1_a",
4226         "drif0_ctrl_b",
4227         "drif0_data0_b",
4228         "drif0_data1_b",
4229         "drif0_ctrl_c",
4230         "drif0_data0_c",
4231         "drif0_data1_c",
4232 };
4233
4234 static const char * const drif1_groups[] = {
4235         "drif1_ctrl_a",
4236         "drif1_data0_a",
4237         "drif1_data1_a",
4238         "drif1_ctrl_b",
4239         "drif1_data0_b",
4240         "drif1_data1_b",
4241         "drif1_ctrl_c",
4242         "drif1_data0_c",
4243         "drif1_data1_c",
4244 };
4245
4246 static const char * const drif2_groups[] = {
4247         "drif2_ctrl_a",
4248         "drif2_data0_a",
4249         "drif2_data1_a",
4250         "drif2_ctrl_b",
4251         "drif2_data0_b",
4252         "drif2_data1_b",
4253 };
4254
4255 static const char * const drif3_groups[] = {
4256         "drif3_ctrl_a",
4257         "drif3_data0_a",
4258         "drif3_data1_a",
4259         "drif3_ctrl_b",
4260         "drif3_data0_b",
4261         "drif3_data1_b",
4262 };
4263
4264 static const char * const du_groups[] = {
4265         "du_rgb666",
4266         "du_rgb888",
4267         "du_clk_out_0",
4268         "du_clk_out_1",
4269         "du_sync",
4270         "du_oddf",
4271         "du_cde",
4272         "du_disp",
4273 };
4274
4275 static const char * const hscif0_groups[] = {
4276         "hscif0_data",
4277         "hscif0_clk",
4278         "hscif0_ctrl",
4279 };
4280
4281 static const char * const hscif1_groups[] = {
4282         "hscif1_data_a",
4283         "hscif1_clk_a",
4284         "hscif1_ctrl_a",
4285         "hscif1_data_b",
4286         "hscif1_clk_b",
4287         "hscif1_ctrl_b",
4288 };
4289
4290 static const char * const hscif2_groups[] = {
4291         "hscif2_data_a",
4292         "hscif2_clk_a",
4293         "hscif2_ctrl_a",
4294         "hscif2_data_b",
4295         "hscif2_clk_b",
4296         "hscif2_ctrl_b",
4297         "hscif2_data_c",
4298         "hscif2_clk_c",
4299         "hscif2_ctrl_c",
4300 };
4301
4302 static const char * const hscif3_groups[] = {
4303         "hscif3_data_a",
4304         "hscif3_clk",
4305         "hscif3_ctrl",
4306         "hscif3_data_b",
4307         "hscif3_data_c",
4308         "hscif3_data_d",
4309 };
4310
4311 static const char * const hscif4_groups[] = {
4312         "hscif4_data_a",
4313         "hscif4_clk",
4314         "hscif4_ctrl",
4315         "hscif4_data_b",
4316 };
4317
4318 static const char * const i2c1_groups[] = {
4319         "i2c1_a",
4320         "i2c1_b",
4321 };
4322
4323 static const char * const i2c2_groups[] = {
4324         "i2c2_a",
4325         "i2c2_b",
4326 };
4327
4328 static const char * const i2c6_groups[] = {
4329         "i2c6_a",
4330         "i2c6_b",
4331         "i2c6_c",
4332 };
4333
4334 static const char * const intc_ex_groups[] = {
4335         "intc_ex_irq0",
4336         "intc_ex_irq1",
4337         "intc_ex_irq2",
4338         "intc_ex_irq3",
4339         "intc_ex_irq4",
4340         "intc_ex_irq5",
4341 };
4342
4343 static const char * const msiof0_groups[] = {
4344         "msiof0_clk",
4345         "msiof0_sync",
4346         "msiof0_ss1",
4347         "msiof0_ss2",
4348         "msiof0_txd",
4349         "msiof0_rxd",
4350 };
4351
4352 static const char * const msiof1_groups[] = {
4353         "msiof1_clk_a",
4354         "msiof1_sync_a",
4355         "msiof1_ss1_a",
4356         "msiof1_ss2_a",
4357         "msiof1_txd_a",
4358         "msiof1_rxd_a",
4359         "msiof1_clk_b",
4360         "msiof1_sync_b",
4361         "msiof1_ss1_b",
4362         "msiof1_ss2_b",
4363         "msiof1_txd_b",
4364         "msiof1_rxd_b",
4365         "msiof1_clk_c",
4366         "msiof1_sync_c",
4367         "msiof1_ss1_c",
4368         "msiof1_ss2_c",
4369         "msiof1_txd_c",
4370         "msiof1_rxd_c",
4371         "msiof1_clk_d",
4372         "msiof1_sync_d",
4373         "msiof1_ss1_d",
4374         "msiof1_ss2_d",
4375         "msiof1_txd_d",
4376         "msiof1_rxd_d",
4377         "msiof1_clk_e",
4378         "msiof1_sync_e",
4379         "msiof1_ss1_e",
4380         "msiof1_ss2_e",
4381         "msiof1_txd_e",
4382         "msiof1_rxd_e",
4383         "msiof1_clk_f",
4384         "msiof1_sync_f",
4385         "msiof1_ss1_f",
4386         "msiof1_ss2_f",
4387         "msiof1_txd_f",
4388         "msiof1_rxd_f",
4389         "msiof1_clk_g",
4390         "msiof1_sync_g",
4391         "msiof1_ss1_g",
4392         "msiof1_ss2_g",
4393         "msiof1_txd_g",
4394         "msiof1_rxd_g",
4395 };
4396
4397 static const char * const msiof2_groups[] = {
4398         "msiof2_clk_a",
4399         "msiof2_sync_a",
4400         "msiof2_ss1_a",
4401         "msiof2_ss2_a",
4402         "msiof2_txd_a",
4403         "msiof2_rxd_a",
4404         "msiof2_clk_b",
4405         "msiof2_sync_b",
4406         "msiof2_ss1_b",
4407         "msiof2_ss2_b",
4408         "msiof2_txd_b",
4409         "msiof2_rxd_b",
4410         "msiof2_clk_c",
4411         "msiof2_sync_c",
4412         "msiof2_ss1_c",
4413         "msiof2_ss2_c",
4414         "msiof2_txd_c",
4415         "msiof2_rxd_c",
4416         "msiof2_clk_d",
4417         "msiof2_sync_d",
4418         "msiof2_ss1_d",
4419         "msiof2_ss2_d",
4420         "msiof2_txd_d",
4421         "msiof2_rxd_d",
4422 };
4423
4424 static const char * const msiof3_groups[] = {
4425         "msiof3_clk_a",
4426         "msiof3_sync_a",
4427         "msiof3_ss1_a",
4428         "msiof3_ss2_a",
4429         "msiof3_txd_a",
4430         "msiof3_rxd_a",
4431         "msiof3_clk_b",
4432         "msiof3_sync_b",
4433         "msiof3_ss1_b",
4434         "msiof3_ss2_b",
4435         "msiof3_txd_b",
4436         "msiof3_rxd_b",
4437         "msiof3_clk_c",
4438         "msiof3_sync_c",
4439         "msiof3_txd_c",
4440         "msiof3_rxd_c",
4441         "msiof3_clk_d",
4442         "msiof3_sync_d",
4443         "msiof3_ss1_d",
4444         "msiof3_txd_d",
4445         "msiof3_rxd_d",
4446         "msiof3_clk_e",
4447         "msiof3_sync_e",
4448         "msiof3_ss1_e",
4449         "msiof3_ss2_e",
4450         "msiof3_txd_e",
4451         "msiof3_rxd_e",
4452 };
4453
4454 static const char * const pwm0_groups[] = {
4455         "pwm0",
4456 };
4457
4458 static const char * const pwm1_groups[] = {
4459         "pwm1_a",
4460         "pwm1_b",
4461 };
4462
4463 static const char * const pwm2_groups[] = {
4464         "pwm2_a",
4465         "pwm2_b",
4466 };
4467
4468 static const char * const pwm3_groups[] = {
4469         "pwm3_a",
4470         "pwm3_b",
4471 };
4472
4473 static const char * const pwm4_groups[] = {
4474         "pwm4_a",
4475         "pwm4_b",
4476 };
4477
4478 static const char * const pwm5_groups[] = {
4479         "pwm5_a",
4480         "pwm5_b",
4481 };
4482
4483 static const char * const pwm6_groups[] = {
4484         "pwm6_a",
4485         "pwm6_b",
4486 };
4487
4488 static const char * const scif0_groups[] = {
4489         "scif0_data",
4490         "scif0_clk",
4491         "scif0_ctrl",
4492 };
4493
4494 static const char * const scif1_groups[] = {
4495         "scif1_data_a",
4496         "scif1_clk",
4497         "scif1_ctrl",
4498         "scif1_data_b",
4499 };
4500
4501 static const char * const scif2_groups[] = {
4502         "scif2_data_a",
4503         "scif2_clk",
4504         "scif2_data_b",
4505 };
4506
4507 static const char * const scif3_groups[] = {
4508         "scif3_data_a",
4509         "scif3_clk",
4510         "scif3_ctrl",
4511         "scif3_data_b",
4512 };
4513
4514 static const char * const scif4_groups[] = {
4515         "scif4_data_a",
4516         "scif4_clk_a",
4517         "scif4_ctrl_a",
4518         "scif4_data_b",
4519         "scif4_clk_b",
4520         "scif4_ctrl_b",
4521         "scif4_data_c",
4522         "scif4_clk_c",
4523         "scif4_ctrl_c",
4524 };
4525
4526 static const char * const scif5_groups[] = {
4527         "scif5_data_a",
4528         "scif5_clk_a",
4529         "scif5_data_b",
4530         "scif5_clk_b",
4531 };
4532
4533 static const char * const scif_clk_groups[] = {
4534         "scif_clk_a",
4535         "scif_clk_b",
4536 };
4537
4538 static const char * const sdhi0_groups[] = {
4539         "sdhi0_data1",
4540         "sdhi0_data4",
4541         "sdhi0_ctrl",
4542         "sdhi0_cd",
4543         "sdhi0_wp",
4544 };
4545
4546 static const char * const sdhi1_groups[] = {
4547         "sdhi1_data1",
4548         "sdhi1_data4",
4549         "sdhi1_ctrl",
4550         "sdhi1_cd",
4551         "sdhi1_wp",
4552 };
4553
4554 static const char * const sdhi2_groups[] = {
4555         "sdhi2_data1",
4556         "sdhi2_data4",
4557         "sdhi2_data8",
4558         "sdhi2_ctrl",
4559         "sdhi2_cd_a",
4560         "sdhi2_wp_a",
4561         "sdhi2_cd_b",
4562         "sdhi2_wp_b",
4563         "sdhi2_ds",
4564 };
4565
4566 static const char * const sdhi3_groups[] = {
4567         "sdhi3_data1",
4568         "sdhi3_data4",
4569         "sdhi3_data8",
4570         "sdhi3_ctrl",
4571         "sdhi3_cd",
4572         "sdhi3_wp",
4573         "sdhi3_ds",
4574 };
4575
4576 static const char * const ssi_groups[] = {
4577         "ssi0_data",
4578         "ssi01239_ctrl",
4579         "ssi1_data_a",
4580         "ssi1_data_b",
4581         "ssi1_ctrl_a",
4582         "ssi1_ctrl_b",
4583         "ssi2_data_a",
4584         "ssi2_data_b",
4585         "ssi2_ctrl_a",
4586         "ssi2_ctrl_b",
4587         "ssi3_data",
4588         "ssi349_ctrl",
4589         "ssi4_data",
4590         "ssi4_ctrl",
4591         "ssi5_data",
4592         "ssi5_ctrl",
4593         "ssi6_data",
4594         "ssi6_ctrl",
4595         "ssi7_data",
4596         "ssi78_ctrl",
4597         "ssi8_data",
4598         "ssi9_data_a",
4599         "ssi9_data_b",
4600         "ssi9_ctrl_a",
4601         "ssi9_ctrl_b",
4602 };
4603
4604 static const char * const usb0_groups[] = {
4605         "usb0",
4606 };
4607
4608 static const char * const usb1_groups[] = {
4609         "usb1",
4610 };
4611
4612 static const char * const usb30_groups[] = {
4613         "usb30",
4614 };
4615
4616 static const struct sh_pfc_function pinmux_functions[] = {
4617         SH_PFC_FUNCTION(audio_clk),
4618         SH_PFC_FUNCTION(avb),
4619         SH_PFC_FUNCTION(can0),
4620         SH_PFC_FUNCTION(can1),
4621         SH_PFC_FUNCTION(can_clk),
4622         SH_PFC_FUNCTION(canfd0),
4623         SH_PFC_FUNCTION(canfd1),
4624         SH_PFC_FUNCTION(drif0),
4625         SH_PFC_FUNCTION(drif1),
4626         SH_PFC_FUNCTION(drif2),
4627         SH_PFC_FUNCTION(drif3),
4628         SH_PFC_FUNCTION(du),
4629         SH_PFC_FUNCTION(hscif0),
4630         SH_PFC_FUNCTION(hscif1),
4631         SH_PFC_FUNCTION(hscif2),
4632         SH_PFC_FUNCTION(hscif3),
4633         SH_PFC_FUNCTION(hscif4),
4634         SH_PFC_FUNCTION(i2c1),
4635         SH_PFC_FUNCTION(i2c2),
4636         SH_PFC_FUNCTION(i2c6),
4637         SH_PFC_FUNCTION(intc_ex),
4638         SH_PFC_FUNCTION(msiof0),
4639         SH_PFC_FUNCTION(msiof1),
4640         SH_PFC_FUNCTION(msiof2),
4641         SH_PFC_FUNCTION(msiof3),
4642         SH_PFC_FUNCTION(pwm0),
4643         SH_PFC_FUNCTION(pwm1),
4644         SH_PFC_FUNCTION(pwm2),
4645         SH_PFC_FUNCTION(pwm3),
4646         SH_PFC_FUNCTION(pwm4),
4647         SH_PFC_FUNCTION(pwm5),
4648         SH_PFC_FUNCTION(pwm6),
4649         SH_PFC_FUNCTION(scif0),
4650         SH_PFC_FUNCTION(scif1),
4651         SH_PFC_FUNCTION(scif2),
4652         SH_PFC_FUNCTION(scif3),
4653         SH_PFC_FUNCTION(scif4),
4654         SH_PFC_FUNCTION(scif5),
4655         SH_PFC_FUNCTION(scif_clk),
4656         SH_PFC_FUNCTION(sdhi0),
4657         SH_PFC_FUNCTION(sdhi1),
4658         SH_PFC_FUNCTION(sdhi2),
4659         SH_PFC_FUNCTION(sdhi3),
4660         SH_PFC_FUNCTION(ssi),
4661         SH_PFC_FUNCTION(usb0),
4662         SH_PFC_FUNCTION(usb1),
4663         SH_PFC_FUNCTION(usb30),
4664 };
4665
4666 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4667 #define F_(x, y)        FN_##y
4668 #define FM(x)           FN_##x
4669         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4670                 0, 0,
4671                 0, 0,
4672                 0, 0,
4673                 0, 0,
4674                 0, 0,
4675                 0, 0,
4676                 0, 0,
4677                 0, 0,
4678                 0, 0,
4679                 0, 0,
4680                 0, 0,
4681                 0, 0,
4682                 0, 0,
4683                 0, 0,
4684                 0, 0,
4685                 0, 0,
4686                 GP_0_15_FN,     GPSR0_15,
4687                 GP_0_14_FN,     GPSR0_14,
4688                 GP_0_13_FN,     GPSR0_13,
4689                 GP_0_12_FN,     GPSR0_12,
4690                 GP_0_11_FN,     GPSR0_11,
4691                 GP_0_10_FN,     GPSR0_10,
4692                 GP_0_9_FN,      GPSR0_9,
4693                 GP_0_8_FN,      GPSR0_8,
4694                 GP_0_7_FN,      GPSR0_7,
4695                 GP_0_6_FN,      GPSR0_6,
4696                 GP_0_5_FN,      GPSR0_5,
4697                 GP_0_4_FN,      GPSR0_4,
4698                 GP_0_3_FN,      GPSR0_3,
4699                 GP_0_2_FN,      GPSR0_2,
4700                 GP_0_1_FN,      GPSR0_1,
4701                 GP_0_0_FN,      GPSR0_0, }
4702         },
4703         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4704                 0, 0,
4705                 0, 0,
4706                 0, 0,
4707                 GP_1_28_FN,     GPSR1_28,
4708                 GP_1_27_FN,     GPSR1_27,
4709                 GP_1_26_FN,     GPSR1_26,
4710                 GP_1_25_FN,     GPSR1_25,
4711                 GP_1_24_FN,     GPSR1_24,
4712                 GP_1_23_FN,     GPSR1_23,
4713                 GP_1_22_FN,     GPSR1_22,
4714                 GP_1_21_FN,     GPSR1_21,
4715                 GP_1_20_FN,     GPSR1_20,
4716                 GP_1_19_FN,     GPSR1_19,
4717                 GP_1_18_FN,     GPSR1_18,
4718                 GP_1_17_FN,     GPSR1_17,
4719                 GP_1_16_FN,     GPSR1_16,
4720                 GP_1_15_FN,     GPSR1_15,
4721                 GP_1_14_FN,     GPSR1_14,
4722                 GP_1_13_FN,     GPSR1_13,
4723                 GP_1_12_FN,     GPSR1_12,
4724                 GP_1_11_FN,     GPSR1_11,
4725                 GP_1_10_FN,     GPSR1_10,
4726                 GP_1_9_FN,      GPSR1_9,
4727                 GP_1_8_FN,      GPSR1_8,
4728                 GP_1_7_FN,      GPSR1_7,
4729                 GP_1_6_FN,      GPSR1_6,
4730                 GP_1_5_FN,      GPSR1_5,
4731                 GP_1_4_FN,      GPSR1_4,
4732                 GP_1_3_FN,      GPSR1_3,
4733                 GP_1_2_FN,      GPSR1_2,
4734                 GP_1_1_FN,      GPSR1_1,
4735                 GP_1_0_FN,      GPSR1_0, }
4736         },
4737         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4738                 0, 0,
4739                 0, 0,
4740                 0, 0,
4741                 0, 0,
4742                 0, 0,
4743                 0, 0,
4744                 0, 0,
4745                 0, 0,
4746                 0, 0,
4747                 0, 0,
4748                 0, 0,
4749                 0, 0,
4750                 0, 0,
4751                 0, 0,
4752                 0, 0,
4753                 0, 0,
4754                 0, 0,
4755                 GP_2_14_FN,     GPSR2_14,
4756                 GP_2_13_FN,     GPSR2_13,
4757                 GP_2_12_FN,     GPSR2_12,
4758                 GP_2_11_FN,     GPSR2_11,
4759                 GP_2_10_FN,     GPSR2_10,
4760                 GP_2_9_FN,      GPSR2_9,
4761                 GP_2_8_FN,      GPSR2_8,
4762                 GP_2_7_FN,      GPSR2_7,
4763                 GP_2_6_FN,      GPSR2_6,
4764                 GP_2_5_FN,      GPSR2_5,
4765                 GP_2_4_FN,      GPSR2_4,
4766                 GP_2_3_FN,      GPSR2_3,
4767                 GP_2_2_FN,      GPSR2_2,
4768                 GP_2_1_FN,      GPSR2_1,
4769                 GP_2_0_FN,      GPSR2_0, }
4770         },
4771         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4772                 0, 0,
4773                 0, 0,
4774                 0, 0,
4775                 0, 0,
4776                 0, 0,
4777                 0, 0,
4778                 0, 0,
4779                 0, 0,
4780                 0, 0,
4781                 0, 0,
4782                 0, 0,
4783                 0, 0,
4784                 0, 0,
4785                 0, 0,
4786                 0, 0,
4787                 0, 0,
4788                 GP_3_15_FN,     GPSR3_15,
4789                 GP_3_14_FN,     GPSR3_14,
4790                 GP_3_13_FN,     GPSR3_13,
4791                 GP_3_12_FN,     GPSR3_12,
4792                 GP_3_11_FN,     GPSR3_11,
4793                 GP_3_10_FN,     GPSR3_10,
4794                 GP_3_9_FN,      GPSR3_9,
4795                 GP_3_8_FN,      GPSR3_8,
4796                 GP_3_7_FN,      GPSR3_7,
4797                 GP_3_6_FN,      GPSR3_6,
4798                 GP_3_5_FN,      GPSR3_5,
4799                 GP_3_4_FN,      GPSR3_4,
4800                 GP_3_3_FN,      GPSR3_3,
4801                 GP_3_2_FN,      GPSR3_2,
4802                 GP_3_1_FN,      GPSR3_1,
4803                 GP_3_0_FN,      GPSR3_0, }
4804         },
4805         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4806                 0, 0,
4807                 0, 0,
4808                 0, 0,
4809                 0, 0,
4810                 0, 0,
4811                 0, 0,
4812                 0, 0,
4813                 0, 0,
4814                 0, 0,
4815                 0, 0,
4816                 0, 0,
4817                 0, 0,
4818                 0, 0,
4819                 0, 0,
4820                 GP_4_17_FN,     GPSR4_17,
4821                 GP_4_16_FN,     GPSR4_16,
4822                 GP_4_15_FN,     GPSR4_15,
4823                 GP_4_14_FN,     GPSR4_14,
4824                 GP_4_13_FN,     GPSR4_13,
4825                 GP_4_12_FN,     GPSR4_12,
4826                 GP_4_11_FN,     GPSR4_11,
4827                 GP_4_10_FN,     GPSR4_10,
4828                 GP_4_9_FN,      GPSR4_9,
4829                 GP_4_8_FN,      GPSR4_8,
4830                 GP_4_7_FN,      GPSR4_7,
4831                 GP_4_6_FN,      GPSR4_6,
4832                 GP_4_5_FN,      GPSR4_5,
4833                 GP_4_4_FN,      GPSR4_4,
4834                 GP_4_3_FN,      GPSR4_3,
4835                 GP_4_2_FN,      GPSR4_2,
4836                 GP_4_1_FN,      GPSR4_1,
4837                 GP_4_0_FN,      GPSR4_0, }
4838         },
4839         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4840                 0, 0,
4841                 0, 0,
4842                 0, 0,
4843                 0, 0,
4844                 0, 0,
4845                 0, 0,
4846                 GP_5_25_FN,     GPSR5_25,
4847                 GP_5_24_FN,     GPSR5_24,
4848                 GP_5_23_FN,     GPSR5_23,
4849                 GP_5_22_FN,     GPSR5_22,
4850                 GP_5_21_FN,     GPSR5_21,
4851                 GP_5_20_FN,     GPSR5_20,
4852                 GP_5_19_FN,     GPSR5_19,
4853                 GP_5_18_FN,     GPSR5_18,
4854                 GP_5_17_FN,     GPSR5_17,
4855                 GP_5_16_FN,     GPSR5_16,
4856                 GP_5_15_FN,     GPSR5_15,
4857                 GP_5_14_FN,     GPSR5_14,
4858                 GP_5_13_FN,     GPSR5_13,
4859                 GP_5_12_FN,     GPSR5_12,
4860                 GP_5_11_FN,     GPSR5_11,
4861                 GP_5_10_FN,     GPSR5_10,
4862                 GP_5_9_FN,      GPSR5_9,
4863                 GP_5_8_FN,      GPSR5_8,
4864                 GP_5_7_FN,      GPSR5_7,
4865                 GP_5_6_FN,      GPSR5_6,
4866                 GP_5_5_FN,      GPSR5_5,
4867                 GP_5_4_FN,      GPSR5_4,
4868                 GP_5_3_FN,      GPSR5_3,
4869                 GP_5_2_FN,      GPSR5_2,
4870                 GP_5_1_FN,      GPSR5_1,
4871                 GP_5_0_FN,      GPSR5_0, }
4872         },
4873         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4874                 GP_6_31_FN,     GPSR6_31,
4875                 GP_6_30_FN,     GPSR6_30,
4876                 GP_6_29_FN,     GPSR6_29,
4877                 GP_6_28_FN,     GPSR6_28,
4878                 GP_6_27_FN,     GPSR6_27,
4879                 GP_6_26_FN,     GPSR6_26,
4880                 GP_6_25_FN,     GPSR6_25,
4881                 GP_6_24_FN,     GPSR6_24,
4882                 GP_6_23_FN,     GPSR6_23,
4883                 GP_6_22_FN,     GPSR6_22,
4884                 GP_6_21_FN,     GPSR6_21,
4885                 GP_6_20_FN,     GPSR6_20,
4886                 GP_6_19_FN,     GPSR6_19,
4887                 GP_6_18_FN,     GPSR6_18,
4888                 GP_6_17_FN,     GPSR6_17,
4889                 GP_6_16_FN,     GPSR6_16,
4890                 GP_6_15_FN,     GPSR6_15,
4891                 GP_6_14_FN,     GPSR6_14,
4892                 GP_6_13_FN,     GPSR6_13,
4893                 GP_6_12_FN,     GPSR6_12,
4894                 GP_6_11_FN,     GPSR6_11,
4895                 GP_6_10_FN,     GPSR6_10,
4896                 GP_6_9_FN,      GPSR6_9,
4897                 GP_6_8_FN,      GPSR6_8,
4898                 GP_6_7_FN,      GPSR6_7,
4899                 GP_6_6_FN,      GPSR6_6,
4900                 GP_6_5_FN,      GPSR6_5,
4901                 GP_6_4_FN,      GPSR6_4,
4902                 GP_6_3_FN,      GPSR6_3,
4903                 GP_6_2_FN,      GPSR6_2,
4904                 GP_6_1_FN,      GPSR6_1,
4905                 GP_6_0_FN,      GPSR6_0, }
4906         },
4907         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4908                 0, 0,
4909                 0, 0,
4910                 0, 0,
4911                 0, 0,
4912                 0, 0,
4913                 0, 0,
4914                 0, 0,
4915                 0, 0,
4916                 0, 0,
4917                 0, 0,
4918                 0, 0,
4919                 0, 0,
4920                 0, 0,
4921                 0, 0,
4922                 0, 0,
4923                 0, 0,
4924                 0, 0,
4925                 0, 0,
4926                 0, 0,
4927                 0, 0,
4928                 0, 0,
4929                 0, 0,
4930                 0, 0,
4931                 0, 0,
4932                 0, 0,
4933                 0, 0,
4934                 0, 0,
4935                 0, 0,
4936                 GP_7_3_FN, GPSR7_3,
4937                 GP_7_2_FN, GPSR7_2,
4938                 GP_7_1_FN, GPSR7_1,
4939                 GP_7_0_FN, GPSR7_0, }
4940         },
4941 #undef F_
4942 #undef FM
4943
4944 #define F_(x, y)        x,
4945 #define FM(x)           FN_##x,
4946         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4947                 IP0_31_28
4948                 IP0_27_24
4949                 IP0_23_20
4950                 IP0_19_16
4951                 IP0_15_12
4952                 IP0_11_8
4953                 IP0_7_4
4954                 IP0_3_0 }
4955         },
4956         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4957                 IP1_31_28
4958                 IP1_27_24
4959                 IP1_23_20
4960                 IP1_19_16
4961                 IP1_15_12
4962                 IP1_11_8
4963                 IP1_7_4
4964                 IP1_3_0 }
4965         },
4966         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4967                 IP2_31_28
4968                 IP2_27_24
4969                 IP2_23_20
4970                 IP2_19_16
4971                 IP2_15_12
4972                 IP2_11_8
4973                 IP2_7_4
4974                 IP2_3_0 }
4975         },
4976         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4977                 IP3_31_28
4978                 IP3_27_24
4979                 IP3_23_20
4980                 IP3_19_16
4981                 IP3_15_12
4982                 IP3_11_8
4983                 IP3_7_4
4984                 IP3_3_0 }
4985         },
4986         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4987                 IP4_31_28
4988                 IP4_27_24
4989                 IP4_23_20
4990                 IP4_19_16
4991                 IP4_15_12
4992                 IP4_11_8
4993                 IP4_7_4
4994                 IP4_3_0 }
4995         },
4996         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4997                 IP5_31_28
4998                 IP5_27_24
4999                 IP5_23_20
5000                 IP5_19_16
5001                 IP5_15_12
5002                 IP5_11_8
5003                 IP5_7_4
5004                 IP5_3_0 }
5005         },
5006         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5007                 IP6_31_28
5008                 IP6_27_24
5009                 IP6_23_20
5010                 IP6_19_16
5011                 IP6_15_12
5012                 IP6_11_8
5013                 IP6_7_4
5014                 IP6_3_0 }
5015         },
5016         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5017                 IP7_31_28
5018                 IP7_27_24
5019                 IP7_23_20
5020                 IP7_19_16
5021                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5022                 IP7_11_8
5023                 IP7_7_4
5024                 IP7_3_0 }
5025         },
5026         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5027                 IP8_31_28
5028                 IP8_27_24
5029                 IP8_23_20
5030                 IP8_19_16
5031                 IP8_15_12
5032                 IP8_11_8
5033                 IP8_7_4
5034                 IP8_3_0 }
5035         },
5036         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5037                 IP9_31_28
5038                 IP9_27_24
5039                 IP9_23_20
5040                 IP9_19_16
5041                 IP9_15_12
5042                 IP9_11_8
5043                 IP9_7_4
5044                 IP9_3_0 }
5045         },
5046         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5047                 IP10_31_28
5048                 IP10_27_24
5049                 IP10_23_20
5050                 IP10_19_16
5051                 IP10_15_12
5052                 IP10_11_8
5053                 IP10_7_4
5054                 IP10_3_0 }
5055         },
5056         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5057                 IP11_31_28
5058                 IP11_27_24
5059                 IP11_23_20
5060                 IP11_19_16
5061                 IP11_15_12
5062                 IP11_11_8
5063                 IP11_7_4
5064                 IP11_3_0 }
5065         },
5066         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5067                 IP12_31_28
5068                 IP12_27_24
5069                 IP12_23_20
5070                 IP12_19_16
5071                 IP12_15_12
5072                 IP12_11_8
5073                 IP12_7_4
5074                 IP12_3_0 }
5075         },
5076         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5077                 IP13_31_28
5078                 IP13_27_24
5079                 IP13_23_20
5080                 IP13_19_16
5081                 IP13_15_12
5082                 IP13_11_8
5083                 IP13_7_4
5084                 IP13_3_0 }
5085         },
5086         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5087                 IP14_31_28
5088                 IP14_27_24
5089                 IP14_23_20
5090                 IP14_19_16
5091                 IP14_15_12
5092                 IP14_11_8
5093                 IP14_7_4
5094                 IP14_3_0 }
5095         },
5096         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5097                 IP15_31_28
5098                 IP15_27_24
5099                 IP15_23_20
5100                 IP15_19_16
5101                 IP15_15_12
5102                 IP15_11_8
5103                 IP15_7_4
5104                 IP15_3_0 }
5105         },
5106         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5107                 IP16_31_28
5108                 IP16_27_24
5109                 IP16_23_20
5110                 IP16_19_16
5111                 IP16_15_12
5112                 IP16_11_8
5113                 IP16_7_4
5114                 IP16_3_0 }
5115         },
5116         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5117                 IP17_31_28
5118                 IP17_27_24
5119                 IP17_23_20
5120                 IP17_19_16
5121                 IP17_15_12
5122                 IP17_11_8
5123                 IP17_7_4
5124                 IP17_3_0 }
5125         },
5126         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5127                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5128                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5129                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5130                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5131                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5132                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5133                 IP18_7_4
5134                 IP18_3_0 }
5135         },
5136 #undef F_
5137 #undef FM
5138
5139 #define F_(x, y)        x,
5140 #define FM(x)           FN_##x,
5141         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5142                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5143                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5144                 MOD_SEL0_31_30_29
5145                 MOD_SEL0_28_27
5146                 MOD_SEL0_26_25_24
5147                 MOD_SEL0_23
5148                 MOD_SEL0_22
5149                 MOD_SEL0_21
5150                 MOD_SEL0_20
5151                 MOD_SEL0_19
5152                 MOD_SEL0_18_17
5153                 MOD_SEL0_16
5154                 0, 0, /* RESERVED 15 */
5155                 MOD_SEL0_14_13
5156                 MOD_SEL0_12
5157                 MOD_SEL0_11
5158                 MOD_SEL0_10
5159                 MOD_SEL0_9_8
5160                 MOD_SEL0_7_6
5161                 MOD_SEL0_5
5162                 MOD_SEL0_4_3
5163                 /* RESERVED 2, 1, 0 */
5164                 0, 0, 0, 0, 0, 0, 0, 0 }
5165         },
5166         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5167                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5168                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5169                 MOD_SEL1_31_30
5170                 MOD_SEL1_29_28_27
5171                 MOD_SEL1_26
5172                 MOD_SEL1_25_24
5173                 MOD_SEL1_23_22_21
5174                 MOD_SEL1_20
5175                 MOD_SEL1_19
5176                 MOD_SEL1_18_17
5177                 MOD_SEL1_16
5178                 MOD_SEL1_15_14
5179                 MOD_SEL1_13
5180                 MOD_SEL1_12
5181                 MOD_SEL1_11
5182                 MOD_SEL1_10
5183                 MOD_SEL1_9
5184                 0, 0, 0, 0, /* RESERVED 8, 7 */
5185                 MOD_SEL1_6
5186                 MOD_SEL1_5
5187                 MOD_SEL1_4
5188                 MOD_SEL1_3
5189                 MOD_SEL1_2
5190                 MOD_SEL1_1
5191                 MOD_SEL1_0 }
5192         },
5193         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5194                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5195                              4, 4, 4, 3, 1) {
5196                 MOD_SEL2_31
5197                 MOD_SEL2_30
5198                 MOD_SEL2_29
5199                 MOD_SEL2_28_27
5200                 MOD_SEL2_26
5201                 MOD_SEL2_25_24_23
5202                 MOD_SEL2_22
5203                 MOD_SEL2_21
5204                 MOD_SEL2_20
5205                 MOD_SEL2_19
5206                 MOD_SEL2_18
5207                 MOD_SEL2_17
5208                 /* RESERVED 16 */
5209                 0, 0,
5210                 /* RESERVED 15, 14, 13, 12 */
5211                 0, 0, 0, 0, 0, 0, 0, 0,
5212                 0, 0, 0, 0, 0, 0, 0, 0,
5213                 /* RESERVED 11, 10, 9, 8 */
5214                 0, 0, 0, 0, 0, 0, 0, 0,
5215                 0, 0, 0, 0, 0, 0, 0, 0,
5216                 /* RESERVED 7, 6, 5, 4 */
5217                 0, 0, 0, 0, 0, 0, 0, 0,
5218                 0, 0, 0, 0, 0, 0, 0, 0,
5219                 /* RESERVED 3, 2, 1 */
5220                 0, 0, 0, 0, 0, 0, 0, 0,
5221                 MOD_SEL2_0 }
5222         },
5223         { },
5224 };
5225
5226 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5227         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5228                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5229                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5230                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5231                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5232                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5233                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5234                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5235                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5236         } },
5237         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5238                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5239                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5240                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5241                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5242                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5243                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5244                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5245                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5246         } },
5247         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5248                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5249                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5250                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5251                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5252                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5253                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5254                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5255                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5256         } },
5257         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5258                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5259                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5260                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5261                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5262                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5263                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5264                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5265                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5266         } },
5267         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5268                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5269                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5270                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5271                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5272                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5273                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5274                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5275                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5276         } },
5277         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5278                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5279                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5280                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5281                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5282                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5283                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5284                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5285                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5286         } },
5287         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5288                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5289                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5290                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5291                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5292                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5293                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5294                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5295                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5296         } },
5297         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5298                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5299                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5300                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5301                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5302                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5303                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5304                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5305                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5306         } },
5307         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5308                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5309                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5310                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5311                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5312                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5313                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5314                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5315                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5316         } },
5317         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5318                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5319                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5320                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5321                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5322                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5323                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5324                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5325                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5326         } },
5327         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5328                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5329                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5330                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5331                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5332                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5333                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5334                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5335                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5336         } },
5337         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5338                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5339                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5340                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5341                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5342                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5343                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5344                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5345                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5346         } },
5347         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5348                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN2 */
5349                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5350                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5351         } },
5352         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5353                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5354                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5355                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5356                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5357                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5358                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5359                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5360                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5361         } },
5362         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5363                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5364                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5365                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5366                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5367                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5368                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5369                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5370                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5371         } },
5372         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5373                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5374                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5375                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5376                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5377                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5378                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5379                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5380                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5381         } },
5382         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5383                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5384                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5385                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5386                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5387                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5388                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5389                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5390                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5391         } },
5392         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5393                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5394                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5395                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5396                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5397                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5398                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5399                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5400                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5401         } },
5402         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5403                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5404                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5405                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5406                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5407                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5408                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5409                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5410                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5411         } },
5412         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5413                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5414                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5415                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5416                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5417                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5418                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5419                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5420                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5421         } },
5422         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5423                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5424                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5425                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5426                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5427                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5428                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5429                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5430                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5431         } },
5432         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5433                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5434                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5435                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5436                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5437                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5438                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5439                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5440                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5441         } },
5442         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5443                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5444                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5445                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5446                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5447                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5448                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5449                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5450                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5451         } },
5452         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5453                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5454                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5455                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5456                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5457                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5458                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5459                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5460                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5461         } },
5462         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5463                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5464                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5465                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5466                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5467                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5468                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5469                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5470         } },
5471         { },
5472 };
5473
5474 enum ioctrl_regs {
5475         POCCTRL,
5476 };
5477
5478 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5479         [POCCTRL] = { 0xe6060380, },
5480         { /* sentinel */ },
5481 };
5482
5483 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5484 {
5485         int bit = -EINVAL;
5486
5487         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5488
5489         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5490                 bit = pin & 0x1f;
5491
5492         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5493                 bit = (pin & 0x1f) + 12;
5494
5495         return bit;
5496 }
5497
5498 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5499         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5500                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5501                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5502                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5503                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5504                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5505                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5506                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5507                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5508                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5509                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5510                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5511                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5512                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5513                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5514                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5515                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5516                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5517                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5518                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5519                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5520                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5521                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5522                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5523                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5524                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5525                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5526                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5527                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5528                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5529                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5530                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5531                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5532         } },
5533         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5534                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5535                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5536                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5537                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5538                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5539                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5540                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5541                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5542                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5543                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5544                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5545                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5546                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5547                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5548                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5549                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5550                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5551                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5552                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5553                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5554                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5555                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5556                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5557                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5558                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5559                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5560                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5561                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5562                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5563                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5564                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5565                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5566         } },
5567         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5568                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5569                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5570                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5571                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5572                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5573                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5574                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5575                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5576                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5577                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5578                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5579                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5580                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5581                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5582                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5583                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5584                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5585                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5586                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5587                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5588                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5589                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5590                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5591                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5592                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5593                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5594                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5595                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5596                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5597                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5598                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5599                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5600         } },
5601         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5602                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5603                 [ 1] = PIN_NONE,
5604                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5605                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5606                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5607                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5608                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5609                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5610                 [ 8] = PIN_NONE,
5611                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5612                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5613                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5614                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5615                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5616                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5617                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5618                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5619                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5620                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5621                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5622                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5623                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5624                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5625                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5626                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5627                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5628                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5629                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5630                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5631                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5632                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5633                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5634         } },
5635         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5636                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5637                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5638                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5639                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5640                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5641                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5642                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5643                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5644                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5645                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5646                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5647                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5648                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5649                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5650                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5651                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5652                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
5653                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5654                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5655                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5656                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
5657                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5658                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5659                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5660                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5661                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5662                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5663                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5664                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5665                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5666                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5667                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5668         } },
5669         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5670                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5671                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5672                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5673                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5674                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5675                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5676                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5677                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5678                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5679                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5680                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5681                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5682                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5683                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5684                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5685                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5686                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5687                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5688                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5689                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5690                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5691                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5692                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5693                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5694                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5695                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5696                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5697                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5698                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5699                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5700                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5701                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5702         } },
5703         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5704                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5705                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5706                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5707                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5708                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5709                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
5710                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
5711                 [ 7] = PIN_NONE,
5712                 [ 8] = PIN_NONE,
5713                 [ 9] = PIN_NONE,
5714                 [10] = PIN_NONE,
5715                 [11] = PIN_NONE,
5716                 [12] = PIN_NONE,
5717                 [13] = PIN_NONE,
5718                 [14] = PIN_NONE,
5719                 [15] = PIN_NONE,
5720                 [16] = PIN_NONE,
5721                 [17] = PIN_NONE,
5722                 [18] = PIN_NONE,
5723                 [19] = PIN_NONE,
5724                 [20] = PIN_NONE,
5725                 [21] = PIN_NONE,
5726                 [22] = PIN_NONE,
5727                 [23] = PIN_NONE,
5728                 [24] = PIN_NONE,
5729                 [25] = PIN_NONE,
5730                 [26] = PIN_NONE,
5731                 [27] = PIN_NONE,
5732                 [28] = PIN_NONE,
5733                 [29] = PIN_NONE,
5734                 [30] = PIN_NONE,
5735                 [31] = PIN_NONE,
5736         } },
5737         { /* sentinel */ },
5738 };
5739
5740 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5741                                             unsigned int pin)
5742 {
5743         const struct pinmux_bias_reg *reg;
5744         unsigned int bit;
5745
5746         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5747         if (!reg)
5748                 return PIN_CONFIG_BIAS_DISABLE;
5749
5750         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5751                 return PIN_CONFIG_BIAS_DISABLE;
5752         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5753                 return PIN_CONFIG_BIAS_PULL_UP;
5754         else
5755                 return PIN_CONFIG_BIAS_PULL_DOWN;
5756 }
5757
5758 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5759                                    unsigned int bias)
5760 {
5761         const struct pinmux_bias_reg *reg;
5762         u32 enable, updown;
5763         unsigned int bit;
5764
5765         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5766         if (!reg)
5767                 return;
5768
5769         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5770         if (bias != PIN_CONFIG_BIAS_DISABLE)
5771                 enable |= BIT(bit);
5772
5773         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5774         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5775                 updown |= BIT(bit);
5776
5777         sh_pfc_write(pfc, reg->pud, updown);
5778         sh_pfc_write(pfc, reg->puen, enable);
5779 }
5780
5781 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
5782         .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
5783         .get_bias = r8a7796_pinmux_get_bias,
5784         .set_bias = r8a7796_pinmux_set_bias,
5785 };
5786
5787 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5788         .name = "r8a77960_pfc",
5789         .ops = &r8a7796_pinmux_ops,
5790         .unlock_reg = 0xe6060000, /* PMMR */
5791
5792         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5793
5794         .pins = pinmux_pins,
5795         .nr_pins = ARRAY_SIZE(pinmux_pins),
5796         .groups = pinmux_groups,
5797         .nr_groups = ARRAY_SIZE(pinmux_groups),
5798         .functions = pinmux_functions,
5799         .nr_functions = ARRAY_SIZE(pinmux_functions),
5800
5801         .cfg_regs = pinmux_config_regs,
5802         .drive_regs = pinmux_drive_regs,
5803         .bias_regs = pinmux_bias_regs,
5804         .ioctrl_regs = pinmux_ioctrl_regs,
5805
5806         .pinmux_data = pinmux_data,
5807         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5808 };