1 /* SPDX-License-Identifier: GPL-2.0
3 * SuperH Pin Function Controller Support
5 * Copyright (c) 2008 Magnus Damm
11 #include <linux/bug.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/spinlock.h>
14 #include <linux/stringify.h>
24 #define SH_PFC_PIN_NONE U16_MAX
26 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
27 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
28 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
29 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
30 #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
31 SH_PFC_PIN_CFG_PULL_DOWN)
32 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
33 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
35 #define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
36 #define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
38 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
39 SH_PFC_PIN_VOLTAGE_18_33)
40 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
41 SH_PFC_PIN_VOLTAGE_25_33)
43 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
52 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) { \
56 .nr_pins = ARRAY_SIZE(n##_pins) + \
57 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
59 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
61 struct sh_pfc_pin_group {
63 const unsigned int *pins;
64 const unsigned int *mux;
69 * Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
70 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
71 * in this case. It accepts an optional 'version' argument used when the
72 * same group can appear on a different set of pins.
74 #define VIN_DATA_PIN_GROUP(n, s, ...) { \
75 .name = #n#s#__VA_ARGS__, \
76 .pins = n##__VA_ARGS__##_pins.data##s, \
77 .mux = n##__VA_ARGS__##_mux.data##s, \
78 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
82 unsigned int data12[12];
83 unsigned int data10[10];
84 unsigned int data8[8];
88 unsigned int data16[16];
89 unsigned int data12[12];
90 unsigned int data10[10];
91 unsigned int data8[8];
95 unsigned int data24[24];
96 unsigned int data20[20];
97 unsigned int data16[16];
98 unsigned int data12[12];
99 unsigned int data10[10];
100 unsigned int data8[8];
101 unsigned int data4[4];
104 #define SH_PFC_FUNCTION(n) { \
106 .groups = n##_groups, \
107 .nr_groups = ARRAY_SIZE(n##_groups), \
110 struct sh_pfc_function {
112 const char * const *groups;
113 unsigned int nr_groups;
121 struct pinmux_cfg_reg {
123 u8 reg_width, field_width;
125 u16 nr_enum_ids; /* for variable width regs only */
126 #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
128 #define SET_NR_ENUM_IDS(n)
131 const u8 *var_field_width;
134 #define GROUP(...) __VA_ARGS__
137 * Describe a config register consisting of several fields of the same width
138 * - name: Register name (unused, for documentation purposes only)
139 * - r: Physical register address
140 * - r_width: Width of the register (in bits)
141 * - f_width: Width of the fixed-width register fields (in bits)
142 * - ids: For each register field (from left to right, i.e. MSB to LSB),
143 * 2^f_width enum IDs must be specified, one for each possible
144 * combination of the register field bit values, all wrapped using
147 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
148 .reg = r, .reg_width = r_width, \
149 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
150 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
151 (r_width / f_width) * (1 << f_width)), \
152 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
156 * Describe a config register consisting of several fields of different widths
157 * - name: Register name (unused, for documentation purposes only)
158 * - r: Physical register address
159 * - r_width: Width of the register (in bits)
160 * - f_widths: List of widths of the register fields (in bits), from left
161 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
162 * - ids: For each register field (from left to right, i.e. MSB to LSB),
163 * 2^f_widths[i] enum IDs must be specified, one for each possible
164 * combination of the register field bit values, all wrapped using
167 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
168 .reg = r, .reg_width = r_width, \
169 .var_field_width = (const u8 []) { f_widths, 0 }, \
170 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
171 .enum_ids = (const u16 []) { ids }
173 struct pinmux_drive_reg_field {
179 struct pinmux_drive_reg {
181 const struct pinmux_drive_reg_field fields[8];
184 #define PINMUX_DRIVE_REG(name, r) \
188 struct pinmux_bias_reg { /* At least one of puen/pud must exist */
189 u32 puen; /* Pull-enable or pull-up control register */
190 u32 pud; /* Pull-up/down or pull-down control register */
194 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
199 struct pinmux_ioctrl_reg {
203 struct pinmux_data_reg {
210 * Describe a data register
211 * - name: Register name (unused, for documentation purposes only)
212 * - r: Physical register address
213 * - r_width: Width of the register (in bits)
214 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
215 * enum ID must be specified, all wrapped using the GROUP() macro.
217 #define PINMUX_DATA_REG(name, r, r_width, ids) \
218 .reg = r, .reg_width = r_width + \
219 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
221 .enum_ids = (const u16 [r_width]) { ids }
228 * Describe the mapping from GPIOs to a single IRQ
229 * - ids...: List of GPIOs that are mapped to the same IRQ
231 #define PINMUX_IRQ(ids...) { \
232 .gpios = (const short []) { ids, -1 } \
235 struct pinmux_range {
241 struct sh_pfc_window {
247 struct sh_pfc_pin_range;
251 const struct sh_pfc_soc_info *info;
254 unsigned int num_windows;
255 struct sh_pfc_window *windows;
256 unsigned int num_irqs;
259 struct sh_pfc_pin_range *ranges;
260 unsigned int nr_ranges;
262 unsigned int nr_gpio_pins;
264 struct sh_pfc_chip *gpio;
268 struct sh_pfc_soc_operations {
269 int (*init)(struct sh_pfc *pfc);
270 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
271 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
273 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
274 void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin);
277 struct sh_pfc_soc_info {
279 const struct sh_pfc_soc_operations *ops;
281 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
282 struct pinmux_range input;
283 struct pinmux_range output;
284 const struct pinmux_irq *gpio_irq;
285 unsigned int gpio_irq_size;
288 struct pinmux_range function;
290 const struct sh_pfc_pin *pins;
291 unsigned int nr_pins;
292 const struct sh_pfc_pin_group *groups;
293 unsigned int nr_groups;
294 const struct sh_pfc_function *functions;
295 unsigned int nr_functions;
297 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
298 const struct pinmux_func *func_gpios;
299 unsigned int nr_func_gpios;
302 const struct pinmux_cfg_reg *cfg_regs;
303 const struct pinmux_drive_reg *drive_regs;
304 const struct pinmux_bias_reg *bias_regs;
305 const struct pinmux_ioctrl_reg *ioctrl_regs;
306 const struct pinmux_data_reg *data_regs;
308 const u16 *pinmux_data;
309 unsigned int pinmux_data_size;
311 u32 unlock_reg; /* can be literal address or mask */
314 extern const struct sh_pfc_soc_info emev2_pinmux_info;
315 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
316 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
317 extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
318 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
319 extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
320 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
321 extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
322 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
323 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
324 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
325 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
326 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
327 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
328 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
329 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
330 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
331 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
332 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
333 extern const struct sh_pfc_soc_info r8a77950_pinmux_info;
334 extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
335 extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
336 extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
337 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
338 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
339 extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
340 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
341 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
342 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
343 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
344 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
345 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
346 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
347 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
348 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
349 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
350 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
351 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
352 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
353 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
354 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
355 extern const struct sh_pfc_soc_info shx3_pinmux_info;
357 /* -----------------------------------------------------------------------------
358 * Helper macros to create pin and port lists
362 * sh_pfc_soc_info pinmux_data array macros
366 * Describe generic pinmux data
367 * - data_or_mark: *_DATA or *_MARK enum ID
368 * - ids...: List of enum IDs to associate with data_or_mark
370 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
373 * Describe a pinmux configuration without GPIO function that needs
374 * configuration in a Peripheral Function Select Register (IPSR)
375 * - ipsr: IPSR field (unused, for documentation purposes only)
376 * - fn: Function name, referring to a field in the IPSR
378 #define PINMUX_IPSR_NOGP(ipsr, fn) \
379 PINMUX_DATA(fn##_MARK, FN_##fn)
382 * Describe a pinmux configuration with GPIO function that needs configuration
383 * in both a Peripheral Function Select Register (IPSR) and in a
384 * GPIO/Peripheral Function Select Register (GPSR)
386 * - fn: Function name, also referring to the IPSR field
388 #define PINMUX_IPSR_GPSR(ipsr, fn) \
389 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
392 * Describe a pinmux configuration without GPIO function that needs
393 * configuration in a Peripheral Function Select Register (IPSR), and where the
394 * pinmux function has a representation in a Module Select Register (MOD_SEL).
395 * - ipsr: IPSR field (unused, for documentation purposes only)
396 * - fn: Function name, also referring to the IPSR field
397 * - msel: Module selector
399 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
400 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
403 * Describe a pinmux configuration with GPIO function where the pinmux function
404 * has no representation in a Peripheral Function Select Register (IPSR), but
405 * instead solely depends on a group selection.
407 * - fn: Function name, also referring to the GPSR field
408 * - gsel: Group selector
410 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
411 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
414 * Describe a pinmux configuration with GPIO function that needs configuration
415 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
416 * Function Select Register (GPSR), and where the pinmux function has a
417 * representation in a Module Select Register (MOD_SEL).
419 * - fn: Function name, also referring to the IPSR field
420 * - msel: Module selector
422 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
423 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
426 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
427 * an additional select register that controls physical multiplexing
430 * - fn: Function name, also referring to the IPSR field
431 * - psel: Physical multiplexing selector
432 * - msel: Module selector
434 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
435 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
438 * Describe a pinmux configuration in which a pin is physically multiplexed
441 * - fn: Function name
442 * - psel: Physical multiplexing selector
444 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
445 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
448 * Describe a pinmux configuration for a single-function pin with GPIO
450 * - fn: Function name
452 #define PINMUX_SINGLE(fn) \
453 PINMUX_DATA(fn##_MARK, FN_##fn)
456 * GP port style (32 ports banks)
459 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
460 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
461 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
463 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
464 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
465 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
466 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
468 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
469 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
470 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
471 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
472 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
474 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
475 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
476 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
477 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
478 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
480 #define PORT_GP_CFG_7(bank, fn, sfx, cfg) \
481 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
482 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)
483 #define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)
485 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
486 PORT_GP_CFG_7(bank, fn, sfx, cfg), \
487 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
488 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
490 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
491 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
492 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
493 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
495 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
496 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
497 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
498 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
500 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
501 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
502 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
503 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
505 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
506 PORT_GP_CFG_11(bank, fn, sfx, cfg), \
507 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
508 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
510 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
511 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
512 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
513 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
514 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
516 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
517 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
518 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
519 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
521 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
522 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
523 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
524 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
526 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
527 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
528 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
529 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
531 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
532 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
533 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
534 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
536 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
537 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
538 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
539 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
540 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
542 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
543 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
544 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
545 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
547 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
548 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
549 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
550 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
552 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
553 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
554 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
555 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
557 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
558 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
559 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
560 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
562 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
563 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
564 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
565 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
567 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
568 PORT_GP_CFG_25(bank, fn, sfx, cfg), \
569 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
570 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
572 #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
573 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
574 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
575 #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
577 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
578 PORT_GP_CFG_27(bank, fn, sfx, cfg), \
579 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
580 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
582 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
583 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
584 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
585 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
587 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
588 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
589 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
590 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
592 #define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
593 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
594 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
595 #define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
597 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
598 PORT_GP_CFG_31(bank, fn, sfx, cfg), \
599 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
600 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
602 #define PORT_GP_32_REV(bank, fn, sfx) \
603 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
604 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
605 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
606 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
607 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
608 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
609 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
610 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
611 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
612 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
613 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
614 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
615 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
616 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
617 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
618 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
620 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
621 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
622 #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
624 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
625 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \
626 .pin = (bank * 32) + _pin, \
627 .name = __stringify(_name), \
628 .enum_id = _name##_DATA, \
631 #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
633 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
634 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
635 #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
638 * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
640 * The largest GP pin index is obtained by taking the size of a union,
641 * containing one array per GP pin, sized by the corresponding pin index.
642 * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
643 * while the members of a union must be terminated by semicolons, the commas
644 * are absorbed by wrapping them inside dummy attributes.
646 #define _GP_ENTRY(bank, pin, name, sfx, cfg) \
647 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
648 #define GP_ASSIGN_LAST() \
649 GP_LAST = sizeof(union { \
650 char dummy[0] __attribute__((deprecated, \
651 CPU_ALL_GP(_GP_ENTRY, unused), \
656 * PORT style (linear pin space)
659 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
661 #define PORT_10(pn, fn, pfx, sfx) \
662 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
663 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
664 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
665 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
666 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
668 #define PORT_90(pn, fn, pfx, sfx) \
669 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
670 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
671 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
672 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
673 PORT_10(pn+90, fn, pfx##9, sfx)
675 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
676 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
677 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
679 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
680 #define PINMUX_GPIO(_pin) \
683 .name = __stringify(GPIO_##_pin), \
684 .enum_id = _pin##_DATA, \
687 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
688 #define SH_PFC_PIN_CFG(_pin, cfgs) { \
690 .name = __stringify(PORT##_pin), \
691 .enum_id = PORT##_pin##_DATA, \
695 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
696 * PORT_name_OUT, PORT_name_IN marks
698 #define _PORT_DATA(pn, pfx, sfx) \
699 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
700 PORT##pfx##_OUT, PORT##pfx##_IN)
701 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
704 * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
706 * The largest PORT pin index is obtained by taking the size of a union,
707 * containing one array per PORT pin, sized by the corresponding pin index.
708 * As the fields in the CPU_ALL_PORT() macro definition are separated by
709 * commas, while the members of a union must be terminated by semicolons, the
710 * commas are absorbed by wrapping them inside dummy attributes.
712 #define _PORT_ENTRY(pn, pfx, sfx) \
713 deprecated)); char pfx[pn] __attribute__((deprecated
714 #define PORT_ASSIGN_LAST() \
715 PORT_LAST = sizeof(union { \
716 char dummy[0] __attribute__((deprecated, \
717 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
721 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
722 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
723 [gpio - (base)] = { \
724 .name = __stringify(gpio), \
725 .enum_id = data_or_mark, \
727 #define GPIO_FN(str) \
728 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
731 * Pins not associated with a GPIO port
734 #define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
735 #define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
737 /* NOGP_ALL - Expand to a list of PIN_id */
738 #define _NOGP_ALL(pin, name, cfg) PIN_##pin
739 #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
741 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
742 #define _NOGP_PINMUX(_pin, _name, cfg) { \
744 .name = "PIN_" _name, \
745 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
747 #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
750 * PORTnCR helper macro for SH-Mobile/R-Mobile
752 #define PORTCR(nr, reg) { \
753 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(2, 2, 1, 3), \
755 /* PULMD[1:0], handled by .set_bias() */ \
758 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
759 /* SEC, not supported */ \
762 PORT##nr##_FN0, PORT##nr##_FN1, \
763 PORT##nr##_FN2, PORT##nr##_FN3, \
764 PORT##nr##_FN4, PORT##nr##_FN5, \
765 PORT##nr##_FN6, PORT##nr##_FN7 \
770 * GPIO number helper macro for R-Car
772 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
777 const struct pinmux_bias_reg *
778 rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
780 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
781 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
784 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
785 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
788 #endif /* __SH_PFC_H */