drivers/pinctrl/renesas/pinctrl-rzg2l.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RZ/G2L Pin Control and GPIO driver core
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corporation.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/gpio/driver.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/mutex.h>
  15 #include <linux/of.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/spinlock.h>
  20
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinmux.h>
  26
  27 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  28
  29 #include "../core.h"
  30 #include "../pinconf.h"
  31 #include "../pinmux.h"
  32
  33 #define DRV_NAME        "pinctrl-rzg2l"
  34
  35 /*
  36  * Use 16 lower bits [15:0] for pin identifier
  37  * Use 16 higher bits [31:16] for pin mux function
  38  */
  39 #define MUX_PIN_ID_MASK         GENMASK(15, 0)
  40 #define MUX_FUNC_MASK           GENMASK(31, 16)
  41 #define MUX_FUNC_OFFS           16
  42 #define MUX_FUNC(pinconf)       (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  43
  44 /* PIN capabilities */
  45 #define PIN_CFG_IOLH_A                  BIT(0)
  46 #define PIN_CFG_IOLH_B                  BIT(1)
  47 #define PIN_CFG_SR                      BIT(2)
  48 #define PIN_CFG_IEN                     BIT(3)
  49 #define PIN_CFG_PUPD                    BIT(4)
  50 #define PIN_CFG_IO_VMC_SD0              BIT(5)
  51 #define PIN_CFG_IO_VMC_SD1              BIT(6)
  52 #define PIN_CFG_IO_VMC_QSPI             BIT(7)
  53 #define PIN_CFG_IO_VMC_ETH0             BIT(8)
  54 #define PIN_CFG_IO_VMC_ETH1             BIT(9)
  55 #define PIN_CFG_FILONOFF                BIT(10)
  56 #define PIN_CFG_FILNUM                  BIT(11)
  57 #define PIN_CFG_FILCLKSEL               BIT(12)
  58 #define PIN_CFG_IOLH_C                  BIT(13)
  59 #define PIN_CFG_SOFT_PS                 BIT(14)
  60 #define PIN_CFG_OEN                     BIT(15)
  61
  62 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
  63                                         (PIN_CFG_IOLH_##group | \
  64                                          PIN_CFG_PUPD | \
  65                                          PIN_CFG_FILONOFF | \
  66                                          PIN_CFG_FILNUM | \
  67                                          PIN_CFG_FILCLKSEL)
  68
  69 #define RZG2L_MPXED_PIN_FUNCS           (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
  70                                          PIN_CFG_SR)
  71
  72 #define RZG3S_MPXED_PIN_FUNCS(group)    (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
  73                                          PIN_CFG_SOFT_PS)
  74
  75 #define RZG2L_MPXED_ETH_PIN_FUNCS(x)    ((x) | \
  76                                          PIN_CFG_FILONOFF | \
  77                                          PIN_CFG_FILNUM | \
  78                                          PIN_CFG_FILCLKSEL)
  79
  80 /*
  81  * n indicates number of pins in the port, a is the register index
  82  * and f is pin configuration capabilities supported.
  83  */
  84 #define RZG2L_GPIO_PORT_PACK(n, a, f)   (((n) << 28) | ((a) << 20) | (f))
  85 #define RZG2L_GPIO_PORT_GET_PINCNT(x)   (((x) & GENMASK(30, 28)) >> 28)
  86
  87 /*
  88  * BIT(31) indicates dedicated pin, p is the register index while
  89  * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
  90  * (b * 8) and f is the pin configuration capabilities supported.
  91  */
  92 #define RZG2L_SINGLE_PIN                BIT(31)
  93 #define RZG2L_SINGLE_PIN_PACK(p, b, f)  (RZG2L_SINGLE_PIN | \
  94                                          ((p) << 24) | ((b) << 20) | (f))
  95 #define RZG2L_SINGLE_PIN_GET_BIT(x)     (((x) & GENMASK(22, 20)) >> 20)
  96
  97 #define RZG2L_PIN_CFG_TO_CAPS(cfg)              ((cfg) & GENMASK(19, 0))
  98 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg)       ((cfg) & RZG2L_SINGLE_PIN ? \
  99                                                 (((cfg) & GENMASK(30, 24)) >> 24) : \
 100                                                 (((cfg) & GENMASK(26, 20)) >> 20))
 101
 102 #define P(off)                  (0x0000 + (off))
 103 #define PM(off)                 (0x0100 + (off) * 2)
 104 #define PMC(off)                (0x0200 + (off))
 105 #define PFC(off)                (0x0400 + (off) * 4)
 106 #define PIN(off)                (0x0800 + (off))
 107 #define IOLH(off)               (0x1000 + (off) * 8)
 108 #define IEN(off)                (0x1800 + (off) * 8)
 109 #define ISEL(off)               (0x2C00 + (off) * 8)
 110 #define SD_CH(off, ch)          ((off) + (ch) * 4)
 111 #define ETH_POC(off, ch)        ((off) + (ch) * 4)
 112 #define QSPI                    (0x3008)
 113 #define ETH_MODE                (0x3018)
 114
 115 #define PVDD_2500               2       /* I/O domain voltage 2.5V */
 116 #define PVDD_1800               1       /* I/O domain voltage <= 1.8V */
 117 #define PVDD_3300               0       /* I/O domain voltage >= 3.3V */
 118
 119 #define PWPR_B0WI               BIT(7)  /* Bit Write Disable */
 120 #define PWPR_PFCWE              BIT(6)  /* PFC Register Write Enable */
 121
 122 #define PM_MASK                 0x03
 123 #define PFC_MASK                0x07
 124 #define IEN_MASK                0x01
 125 #define IOLH_MASK               0x03
 126
 127 #define PM_INPUT                0x1
 128 #define PM_OUTPUT               0x2
 129
 130 #define RZG2L_PIN_ID_TO_PORT(id)        ((id) / RZG2L_PINS_PER_PORT)
 131 #define RZG2L_PIN_ID_TO_PIN(id)         ((id) % RZG2L_PINS_PER_PORT)
 132
 133 #define RZG2L_TINT_MAX_INTERRUPT        32
 134 #define RZG2L_TINT_IRQ_START_INDEX      9
 135 #define RZG2L_PACK_HWIRQ(t, i)          (((t) << 16) | (i))
 136
 137 /**
 138  * struct rzg2l_register_offsets - specific register offsets
 139  * @pwpr: PWPR register offset
 140  * @sd_ch: SD_CH register offset
 141  * @eth_poc: ETH_POC register offset
 142  */
 143 struct rzg2l_register_offsets {
 144         u16 pwpr;
 145         u16 sd_ch;
 146         u16 eth_poc;
 147 };
 148
 149 /**
 150  * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
 151  * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
 152  * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
 153  * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
 154  * @RZG2L_IOLH_IDX_MAX: maximum index
 155  */
 156 enum rzg2l_iolh_index {
 157         RZG2L_IOLH_IDX_1V8 = 0,
 158         RZG2L_IOLH_IDX_2V5 = 4,
 159         RZG2L_IOLH_IDX_3V3 = 8,
 160         RZG2L_IOLH_IDX_MAX = 12,
 161 };
 162
 163 /* Maximum number of driver strength entries per power source. */
 164 #define RZG2L_IOLH_MAX_DS_ENTRIES       (4)
 165
 166 /**
 167  * struct rzg2l_hwcfg - hardware configuration data structure
 168  * @regs: hardware specific register offsets
 169  * @iolh_groupa_ua: IOLH group A uA specific values
 170  * @iolh_groupb_ua: IOLH group B uA specific values
 171  * @iolh_groupc_ua: IOLH group C uA specific values
 172  * @iolh_groupb_oi: IOLH group B output impedance specific values
 173  * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
 174  * @func_base: base number for port function (see register PFC)
 175  * @oen_max_pin: the maximum pin number supporting output enable
 176  * @oen_max_port: the maximum port number supporting output enable
 177  */
 178 struct rzg2l_hwcfg {
 179         const struct rzg2l_register_offsets regs;
 180         u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
 181         u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
 182         u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
 183         u16 iolh_groupb_oi[4];
 184         bool drive_strength_ua;
 185         u8 func_base;
 186         u8 oen_max_pin;
 187         u8 oen_max_port;
 188 };
 189
 190 struct rzg2l_dedicated_configs {
 191         const char *name;
 192         u32 config;
 193 };
 194
 195 struct rzg2l_pinctrl_data {
 196         const char * const *port_pins;
 197         const u32 *port_pin_configs;
 198         unsigned int n_ports;
 199         const struct rzg2l_dedicated_configs *dedicated_pins;
 200         unsigned int n_port_pins;
 201         unsigned int n_dedicated_pins;
 202         const struct rzg2l_hwcfg *hwcfg;
 203 };
 204
 205 /**
 206  * struct rzg2l_pinctrl_pin_settings - pin data
 207  * @power_source: power source
 208  * @drive_strength_ua: drive strength (in micro amps)
 209  */
 210 struct rzg2l_pinctrl_pin_settings {
 211         u16 power_source;
 212         u16 drive_strength_ua;
 213 };
 214
 215 struct rzg2l_pinctrl {
 216         struct pinctrl_dev              *pctl;
 217         struct pinctrl_desc             desc;
 218         struct pinctrl_pin_desc         *pins;
 219
 220         const struct rzg2l_pinctrl_data *data;
 221         void __iomem                    *base;
 222         struct device                   *dev;
 223
 224         struct gpio_chip                gpio_chip;
 225         struct pinctrl_gpio_range       gpio_range;
 226         DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
 227         spinlock_t                      bitmap_lock; /* protect tint_slot bitmap */
 228         unsigned int                    hwirq[RZG2L_TINT_MAX_INTERRUPT];
 229
 230         spinlock_t                      lock; /* lock read/write registers */
 231         struct mutex                    mutex; /* serialize adding groups and functions */
 232
 233         struct rzg2l_pinctrl_pin_settings *settings;
 234 };
 235
 236 static const u16 available_ps[] = { 1800, 2500, 3300 };
 237
 238 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
 239                                        u8 pin, u8 off, u8 func)
 240 {
 241         const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
 242         unsigned long flags;
 243         u32 reg;
 244
 245         spin_lock_irqsave(&pctrl->lock, flags);
 246
 247         /* Set pin to 'Non-use (Hi-Z input protection)'  */
 248         reg = readw(pctrl->base + PM(off));
 249         reg &= ~(PM_MASK << (pin * 2));
 250         writew(reg, pctrl->base + PM(off));
 251
 252         /* Temporarily switch to GPIO mode with PMC register */
 253         reg = readb(pctrl->base + PMC(off));
 254         writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
 255
 256         /* Set the PWPR register to allow PFC register to write */
 257         writel(0x0, pctrl->base + regs->pwpr);          /* B0WI=0, PFCWE=0 */
 258         writel(PWPR_PFCWE, pctrl->base + regs->pwpr);   /* B0WI=0, PFCWE=1 */
 259
 260         /* Select Pin function mode with PFC register */
 261         reg = readl(pctrl->base + PFC(off));
 262         reg &= ~(PFC_MASK << (pin * 4));
 263         writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
 264
 265         /* Set the PWPR register to be write-protected */
 266         writel(0x0, pctrl->base + regs->pwpr);          /* B0WI=0, PFCWE=0 */
 267         writel(PWPR_B0WI, pctrl->base + regs->pwpr);    /* B0WI=1, PFCWE=0 */
 268
 269         /* Switch to Peripheral pin function with PMC register */
 270         reg = readb(pctrl->base + PMC(off));
 271         writeb(reg | BIT(pin), pctrl->base + PMC(off));
 272
 273         spin_unlock_irqrestore(&pctrl->lock, flags);
 274 };
 275
 276 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 277                                  unsigned int func_selector,
 278                                  unsigned int group_selector)
 279 {
 280         struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 281         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 282         struct function_desc *func;
 283         unsigned int i, *psel_val;
 284         struct group_desc *group;
 285         const unsigned int *pins;
 286
 287         func = pinmux_generic_get_function(pctldev, func_selector);
 288         if (!func)
 289                 return -EINVAL;
 290         group = pinctrl_generic_get_group(pctldev, group_selector);
 291         if (!group)
 292                 return -EINVAL;
 293
 294         psel_val = func->data;
 295         pins = group->grp.pins;
 296
 297         for (i = 0; i < group->grp.npins; i++) {
 298                 unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;
 299                 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
 300                 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
 301
 302                 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
 303                         RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
 304
 305                 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);
 306         }
 307
 308         return 0;
 309 };
 310
 311 static int rzg2l_map_add_config(struct pinctrl_map *map,
 312                                 const char *group_or_pin,
 313                                 enum pinctrl_map_type type,
 314                                 unsigned long *configs,
 315                                 unsigned int num_configs)
 316 {
 317         unsigned long *cfgs;
 318
 319         cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
 320                        GFP_KERNEL);
 321         if (!cfgs)
 322                 return -ENOMEM;
 323
 324         map->type = type;
 325         map->data.configs.group_or_pin = group_or_pin;
 326         map->data.configs.configs = cfgs;
 327         map->data.configs.num_configs = num_configs;
 328
 329         return 0;
 330 }
 331
 332 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 333                                    struct device_node *np,
 334                                    struct device_node *parent,
 335                                    struct pinctrl_map **map,
 336                                    unsigned int *num_maps,
 337                                    unsigned int *index)
 338 {
 339         struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 340         struct pinctrl_map *maps = *map;
 341         unsigned int nmaps = *num_maps;
 342         unsigned long *configs = NULL;
 343         unsigned int *pins, *psel_val;
 344         unsigned int num_pinmux = 0;
 345         unsigned int idx = *index;
 346         unsigned int num_pins, i;
 347         unsigned int num_configs;
 348         struct property *pinmux;
 349         struct property *prop;
 350         int ret, gsel, fsel;
 351         const char **pin_fn;
 352         const char *name;
 353         const char *pin;
 354
 355         pinmux = of_find_property(np, "pinmux", NULL);
 356         if (pinmux)
 357                 num_pinmux = pinmux->length / sizeof(u32);
 358
 359         ret = of_property_count_strings(np, "pins");
 360         if (ret == -EINVAL) {
 361                 num_pins = 0;
 362         } else if (ret < 0) {
 363                 dev_err(pctrl->dev, "Invalid pins list in DT\n");
 364                 return ret;
 365         } else {
 366                 num_pins = ret;
 367         }
 368
 369         if (!num_pinmux && !num_pins)
 370                 return 0;
 371
 372         if (num_pinmux && num_pins) {
 373                 dev_err(pctrl->dev,
 374                         "DT node must contain either a pinmux or pins and not both\n");
 375                 return -EINVAL;
 376         }
 377
 378         ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
 379         if (ret < 0)
 380                 return ret;
 381
 382         if (num_pins && !num_configs) {
 383                 dev_err(pctrl->dev, "DT node must contain a config\n");
 384                 ret = -ENODEV;
 385                 goto done;
 386         }
 387
 388         if (num_pinmux) {
 389                 nmaps += 1;
 390                 if (num_configs)
 391                         nmaps += 1;
 392         }
 393
 394         if (num_pins)
 395                 nmaps += num_pins;
 396
 397         maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
 398         if (!maps) {
 399                 ret = -ENOMEM;
 400                 goto done;
 401         }
 402
 403         *map = maps;
 404         *num_maps = nmaps;
 405         if (num_pins) {
 406                 of_property_for_each_string(np, "pins", prop, pin) {
 407                         ret = rzg2l_map_add_config(&maps[idx], pin,
 408                                                    PIN_MAP_TYPE_CONFIGS_PIN,
 409                                                    configs, num_configs);
 410                         if (ret < 0)
 411                                 goto done;
 412
 413                         idx++;
 414                 }
 415                 ret = 0;
 416                 goto done;
 417         }
 418
 419         pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
 420         psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
 421                                 GFP_KERNEL);
 422         pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
 423         if (!pins || !psel_val || !pin_fn) {
 424                 ret = -ENOMEM;
 425                 goto done;
 426         }
 427
 428         /* Collect pin locations and mux settings from DT properties */
 429         for (i = 0; i < num_pinmux; ++i) {
 430                 u32 value;
 431
 432                 ret = of_property_read_u32_index(np, "pinmux", i, &value);
 433                 if (ret)
 434                         goto done;
 435                 pins[i] = value & MUX_PIN_ID_MASK;
 436                 psel_val[i] = MUX_FUNC(value);
 437         }
 438
 439         if (parent) {
 440                 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
 441                                       parent, np);
 442                 if (!name) {
 443                         ret = -ENOMEM;
 444                         goto done;
 445                 }
 446         } else {
 447                 name = np->name;
 448         }
 449
 450         mutex_lock(&pctrl->mutex);
 451
 452         /* Register a single pin group listing all the pins we read from DT */
 453         gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
 454         if (gsel < 0) {
 455                 ret = gsel;
 456                 goto unlock;
 457         }
 458
 459         /*
 460          * Register a single group function where the 'data' is an array PSEL
 461          * register values read from DT.
 462          */
 463         pin_fn[0] = name;
 464         fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
 465         if (fsel < 0) {
 466                 ret = fsel;
 467                 goto remove_group;
 468         }
 469
 470         mutex_unlock(&pctrl->mutex);
 471
 472         maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
 473         maps[idx].data.mux.group = name;
 474         maps[idx].data.mux.function = name;
 475         idx++;
 476
 477         if (num_configs) {
 478                 ret = rzg2l_map_add_config(&maps[idx], name,
 479                                            PIN_MAP_TYPE_CONFIGS_GROUP,
 480                                            configs, num_configs);
 481                 if (ret < 0)
 482                         goto remove_group;
 483
 484                 idx++;
 485         }
 486
 487         dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
 488         ret = 0;
 489         goto done;
 490
 491 remove_group:
 492         pinctrl_generic_remove_group(pctldev, gsel);
 493 unlock:
 494         mutex_unlock(&pctrl->mutex);
 495 done:
 496         *index = idx;
 497         kfree(configs);
 498         return ret;
 499 }
 500
 501 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
 502                               struct pinctrl_map *map,
 503                               unsigned int num_maps)
 504 {
 505         unsigned int i;
 506
 507         if (!map)
 508                 return;
 509
 510         for (i = 0; i < num_maps; ++i) {
 511                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
 512                     map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
 513                         kfree(map[i].data.configs.configs);
 514         }
 515         kfree(map);
 516 }
 517
 518 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
 519                                 struct device_node *np,
 520                                 struct pinctrl_map **map,
 521                                 unsigned int *num_maps)
 522 {
 523         struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 524         struct device_node *child;
 525         unsigned int index;
 526         int ret;
 527
 528         *map = NULL;
 529         *num_maps = 0;
 530         index = 0;
 531
 532         for_each_child_of_node(np, child) {
 533                 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
 534                                               num_maps, &index);
 535                 if (ret < 0) {
 536                         of_node_put(child);
 537                         goto done;
 538                 }
 539         }
 540
 541         if (*num_maps == 0) {
 542                 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
 543                                               num_maps, &index);
 544                 if (ret < 0)
 545                         goto done;
 546         }
 547
 548         if (*num_maps)
 549                 return 0;
 550
 551         dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
 552         ret = -EINVAL;
 553
 554 done:
 555         rzg2l_dt_free_map(pctldev, *map, *num_maps);
 556
 557         return ret;
 558 }
 559
 560 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
 561                                    u32 cfg, u32 port, u8 bit)
 562 {
 563         u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
 564         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
 565         u32 data;
 566
 567         if (bit >= pincount || port >= pctrl->data->n_port_pins)
 568                 return -EINVAL;
 569
 570         data = pctrl->data->port_pin_configs[port];
 571         if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
 572                 return -EINVAL;
 573
 574         return 0;
 575 }
 576
 577 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
 578                                  u8 bit, u32 mask)
 579 {
 580         void __iomem *addr = pctrl->base + offset;
 581
 582         /* handle _L/_H for 32-bit register read/write */
 583         if (bit >= 4) {
 584                 bit -= 4;
 585                 addr += 4;
 586         }
 587
 588         return (readl(addr) >> (bit * 8)) & mask;
 589 }
 590
 591 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
 592                                  u8 bit, u32 mask, u32 val)
 593 {
 594         void __iomem *addr = pctrl->base + offset;
 595         unsigned long flags;
 596         u32 reg;
 597
 598         /* handle _L/_H for 32-bit register read/write */
 599         if (bit >= 4) {
 600                 bit -= 4;
 601                 addr += 4;
 602         }
 603
 604         spin_lock_irqsave(&pctrl->lock, flags);
 605         reg = readl(addr) & ~(mask << (bit * 8));
 606         writel(reg | (val << (bit * 8)), addr);
 607         spin_unlock_irqrestore(&pctrl->lock, flags);
 608 }
 609
 610 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)
 611 {
 612         if (caps & PIN_CFG_IO_VMC_SD0)
 613                 return SD_CH(regs->sd_ch, 0);
 614         if (caps & PIN_CFG_IO_VMC_SD1)
 615                 return SD_CH(regs->sd_ch, 1);
 616         if (caps & PIN_CFG_IO_VMC_ETH0)
 617                 return ETH_POC(regs->eth_poc, 0);
 618         if (caps & PIN_CFG_IO_VMC_ETH1)
 619                 return ETH_POC(regs->eth_poc, 1);
 620         if (caps & PIN_CFG_IO_VMC_QSPI)
 621                 return QSPI;
 622
 623         return -EINVAL;
 624 }
 625
 626 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
 627 {
 628         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 629         const struct rzg2l_register_offsets *regs = &hwcfg->regs;
 630         int pwr_reg;
 631         u8 val;
 632
 633         if (caps & PIN_CFG_SOFT_PS)
 634                 return pctrl->settings[pin].power_source;
 635
 636         pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
 637         if (pwr_reg < 0)
 638                 return pwr_reg;
 639
 640         val = readb(pctrl->base + pwr_reg);
 641         switch (val) {
 642         case PVDD_1800:
 643                 return 1800;
 644         case PVDD_2500:
 645                 return 2500;
 646         case PVDD_3300:
 647                 return 3300;
 648         default:
 649                 /* Should not happen. */
 650                 return -EINVAL;
 651         }
 652 }
 653
 654 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
 655 {
 656         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 657         const struct rzg2l_register_offsets *regs = &hwcfg->regs;
 658         int pwr_reg;
 659         u8 val;
 660
 661         if (caps & PIN_CFG_SOFT_PS) {
 662                 pctrl->settings[pin].power_source = ps;
 663                 return 0;
 664         }
 665
 666         switch (ps) {
 667         case 1800:
 668                 val = PVDD_1800;
 669                 break;
 670         case 2500:
 671                 val = PVDD_2500;
 672                 break;
 673         case 3300:
 674                 val = PVDD_3300;
 675                 break;
 676         default:
 677                 return -EINVAL;
 678         }
 679
 680         pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
 681         if (pwr_reg < 0)
 682                 return pwr_reg;
 683
 684         writeb(val, pctrl->base + pwr_reg);
 685         pctrl->settings[pin].power_source = ps;
 686
 687         return 0;
 688 }
 689
 690 static bool rzg2l_ps_is_supported(u16 ps)
 691 {
 692         unsigned int i;
 693
 694         for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
 695                 if (available_ps[i] == ps)
 696                         return true;
 697         }
 698
 699         return false;
 700 }
 701
 702 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
 703 {
 704         unsigned int i;
 705
 706         for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
 707                 if (available_ps[i] == ps)
 708                         break;
 709         }
 710
 711         /*
 712          * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
 713          * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
 714          */
 715         return i * RZG2L_IOLH_MAX_DS_ENTRIES;
 716 }
 717
 718 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
 719 {
 720         if (caps & PIN_CFG_IOLH_A)
 721                 return hwcfg->iolh_groupa_ua[val];
 722
 723         if (caps & PIN_CFG_IOLH_B)
 724                 return hwcfg->iolh_groupb_ua[val];
 725
 726         if (caps & PIN_CFG_IOLH_C)
 727                 return hwcfg->iolh_groupc_ua[val];
 728
 729         /* Should not happen. */
 730         return 0;
 731 }
 732
 733 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,
 734                                 enum rzg2l_iolh_index ps_index, u16 ua)
 735 {
 736         const u16 *array = NULL;
 737         unsigned int i;
 738
 739         if (caps & PIN_CFG_IOLH_A)
 740                 array = &hwcfg->iolh_groupa_ua[ps_index];
 741
 742         if (caps & PIN_CFG_IOLH_B)
 743                 array = &hwcfg->iolh_groupb_ua[ps_index];
 744
 745         if (caps & PIN_CFG_IOLH_C)
 746                 array = &hwcfg->iolh_groupc_ua[ps_index];
 747
 748         if (!array)
 749                 return -EINVAL;
 750
 751         for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
 752                 if (array[i] == ua)
 753                         return i;
 754         }
 755
 756         return -EINVAL;
 757 }
 758
 759 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
 760                                   enum rzg2l_iolh_index iolh_idx,
 761                                   u16 ds)
 762 {
 763         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 764         const u16 *array = NULL;
 765         unsigned int i;
 766
 767         if (caps & PIN_CFG_IOLH_A)
 768                 array = hwcfg->iolh_groupa_ua;
 769
 770         if (caps & PIN_CFG_IOLH_B)
 771                 array = hwcfg->iolh_groupb_ua;
 772
 773         if (caps & PIN_CFG_IOLH_C)
 774                 array = hwcfg->iolh_groupc_ua;
 775
 776         /* Should not happen. */
 777         if (!array)
 778                 return false;
 779
 780         if (!array[iolh_idx])
 781                 return false;
 782
 783         for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
 784                 if (array[iolh_idx + i] == ds)
 785                         return true;
 786         }
 787
 788         return false;
 789 }
 790
 791 static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
 792 {
 793         if (!(caps & PIN_CFG_OEN))
 794                 return false;
 795
 796         if (pin > max_pin)
 797                 return false;
 798
 799         return true;
 800 }
 801
 802 static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
 803 {
 804         if (pin)
 805                 pin *= 2;
 806
 807         if (offset / RZG2L_PINS_PER_PORT == max_port)
 808                 pin += 1;
 809
 810         return pin;
 811 }
 812
 813 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
 814 {
 815         u8 max_port = pctrl->data->hwcfg->oen_max_port;
 816         u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
 817         u8 bit;
 818
 819         if (!rzg2l_oen_is_supported(caps, pin, max_pin))
 820                 return 0;
 821
 822         bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
 823
 824         return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
 825 }
 826
 827 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
 828 {
 829         u8 max_port = pctrl->data->hwcfg->oen_max_port;
 830         u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
 831         unsigned long flags;
 832         u8 val, bit;
 833
 834         if (!rzg2l_oen_is_supported(caps, pin, max_pin))
 835                 return -EINVAL;
 836
 837         bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
 838
 839         spin_lock_irqsave(&pctrl->lock, flags);
 840         val = readb(pctrl->base + ETH_MODE);
 841         if (oen)
 842                 val &= ~BIT(bit);
 843         else
 844                 val |= BIT(bit);
 845         writeb(val, pctrl->base + ETH_MODE);
 846         spin_unlock_irqrestore(&pctrl->lock, flags);
 847
 848         return 0;
 849 }
 850
 851 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
 852                                      unsigned int _pin,
 853                                      unsigned long *config)
 854 {
 855         struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 856         enum pin_config_param param = pinconf_to_config_param(*config);
 857         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 858         const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
 859         unsigned int *pin_data = pin->drv_data;
 860         unsigned int arg = 0;
 861         u32 off, cfg;
 862         int ret;
 863         u8 bit;
 864
 865         if (!pin_data)
 866                 return -EINVAL;
 867
 868         off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
 869         cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);
 870         if (*pin_data & RZG2L_SINGLE_PIN) {
 871                 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
 872         } else {
 873                 bit = RZG2L_PIN_ID_TO_PIN(_pin);
 874
 875                 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
 876                         return -EINVAL;
 877         }
 878
 879         switch (param) {
 880         case PIN_CONFIG_INPUT_ENABLE:
 881                 if (!(cfg & PIN_CFG_IEN))
 882                         return -EINVAL;
 883                 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
 884                 if (!arg)
 885                         return -EINVAL;
 886                 break;
 887
 888         case PIN_CONFIG_OUTPUT_ENABLE:
 889                 arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
 890                 if (!arg)
 891                         return -EINVAL;
 892                 break;
 893
 894         case PIN_CONFIG_POWER_SOURCE:
 895                 ret = rzg2l_get_power_source(pctrl, _pin, cfg);
 896                 if (ret < 0)
 897                         return ret;
 898                 arg = ret;
 899                 break;
 900
 901         case PIN_CONFIG_DRIVE_STRENGTH: {
 902                 unsigned int index;
 903
 904                 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
 905                         return -EINVAL;
 906
 907                 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
 908                 /*
 909                  * Drive strenght mA is supported only by group A and only
 910                  * for 3V3 port source.
 911                  */
 912                 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
 913                 break;
 914         }
 915
 916         case PIN_CONFIG_DRIVE_STRENGTH_UA: {
 917                 enum rzg2l_iolh_index iolh_idx;
 918                 u8 val;
 919
 920                 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
 921                     !hwcfg->drive_strength_ua)
 922                         return -EINVAL;
 923
 924                 ret = rzg2l_get_power_source(pctrl, _pin, cfg);
 925                 if (ret < 0)
 926                         return ret;
 927                 iolh_idx = rzg2l_ps_to_iolh_idx(ret);
 928                 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
 929                 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val);
 930                 break;
 931         }
 932
 933         case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
 934                 unsigned int index;
 935
 936                 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
 937                         return -EINVAL;
 938
 939                 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
 940                 arg = hwcfg->iolh_groupb_oi[index];
 941                 break;
 942         }
 943
 944         default:
 945                 return -ENOTSUPP;
 946         }
 947
 948         *config = pinconf_to_config_packed(param, arg);
 949
 950         return 0;
 951 };
 952
 953 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
 954                                      unsigned int _pin,
 955                                      unsigned long *_configs,
 956                                      unsigned int num_configs)
 957 {
 958         struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 959         const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
 960         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 961         struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
 962         unsigned int *pin_data = pin->drv_data;
 963         enum pin_config_param param;
 964         unsigned int i, arg, index;
 965         u32 cfg, off;
 966         int ret;
 967         u8 bit;
 968
 969         if (!pin_data)
 970                 return -EINVAL;
 971
 972         off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
 973         cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);
 974         if (*pin_data & RZG2L_SINGLE_PIN) {
 975                 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
 976         } else {
 977                 bit = RZG2L_PIN_ID_TO_PIN(_pin);
 978
 979                 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
 980                         return -EINVAL;
 981         }
 982
 983         for (i = 0; i < num_configs; i++) {
 984                 param = pinconf_to_config_param(_configs[i]);
 985                 switch (param) {
 986                 case PIN_CONFIG_INPUT_ENABLE:
 987                         arg = pinconf_to_config_argument(_configs[i]);
 988
 989                         if (!(cfg & PIN_CFG_IEN))
 990                                 return -EINVAL;
 991
 992                         rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);
 993                         break;
 994
 995                 case PIN_CONFIG_OUTPUT_ENABLE:
 996                         arg = pinconf_to_config_argument(_configs[i]);
 997                         ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
 998                         if (ret)
 999                                 return ret;
1000                         break;
1001
1002                 case PIN_CONFIG_POWER_SOURCE:
1003                         settings.power_source = pinconf_to_config_argument(_configs[i]);
1004                         break;
1005
1006                 case PIN_CONFIG_DRIVE_STRENGTH:
1007                         arg = pinconf_to_config_argument(_configs[i]);
1008
1009                         if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1010                                 return -EINVAL;
1011
1012                         for (index = RZG2L_IOLH_IDX_3V3;
1013                              index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
1014                                 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
1015                                         break;
1016                         }
1017                         if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
1018                                 return -EINVAL;
1019
1020                         rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1021                         break;
1022
1023                 case PIN_CONFIG_DRIVE_STRENGTH_UA:
1024                         if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1025                             !hwcfg->drive_strength_ua)
1026                                 return -EINVAL;
1027
1028                         settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]);
1029                         break;
1030
1031                 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
1032                         arg = pinconf_to_config_argument(_configs[i]);
1033
1034                         if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1035                                 return -EINVAL;
1036
1037                         for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
1038                                 if (arg == hwcfg->iolh_groupb_oi[index])
1039                                         break;
1040                         }
1041                         if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
1042                                 return -EINVAL;
1043
1044                         rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1045                         break;
1046
1047                 default:
1048                         return -EOPNOTSUPP;
1049                 }
1050         }
1051
1052         /* Apply power source. */
1053         if (settings.power_source != pctrl->settings[_pin].power_source) {
1054                 ret = rzg2l_ps_is_supported(settings.power_source);
1055                 if (!ret)
1056                         return -EINVAL;
1057
1058                 /* Apply power source. */
1059                 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source);
1060                 if (ret)
1061                         return ret;
1062         }
1063
1064         /* Apply drive strength. */
1065         if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {
1066                 enum rzg2l_iolh_index iolh_idx;
1067                 int val;
1068
1069                 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source);
1070                 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,
1071                                             settings.drive_strength_ua);
1072                 if (!ret)
1073                         return -EINVAL;
1074
1075                 /* Get register value for this PS/DS tuple. */
1076                 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua);
1077                 if (val < 0)
1078                         return val;
1079
1080                 /* Apply drive strength. */
1081                 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);
1082                 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;
1083         }
1084
1085         return 0;
1086 }
1087
1088 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
1089                                            unsigned int group,
1090                                            unsigned long *configs,
1091                                            unsigned int num_configs)
1092 {
1093         const unsigned int *pins;
1094         unsigned int i, npins;
1095         int ret;
1096
1097         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1098         if (ret)
1099                 return ret;
1100
1101         for (i = 0; i < npins; i++) {
1102                 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,
1103                                                 num_configs);
1104                 if (ret)
1105                         return ret;
1106         }
1107
1108         return 0;
1109 };
1110
1111 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
1112                                            unsigned int group,
1113                                            unsigned long *config)
1114 {
1115         const unsigned int *pins;
1116         unsigned int i, npins, prev_config = 0;
1117         int ret;
1118
1119         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1120         if (ret)
1121                 return ret;
1122
1123         for (i = 0; i < npins; i++) {
1124                 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);
1125                 if (ret)
1126                         return ret;
1127
1128                 /* Check config matching between to pin  */
1129                 if (i && prev_config != *config)
1130                         return -EOPNOTSUPP;
1131
1132                 prev_config = *config;
1133         }
1134
1135         return 0;
1136 };
1137
1138 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
1139         .get_groups_count = pinctrl_generic_get_group_count,
1140         .get_group_name = pinctrl_generic_get_group_name,
1141         .get_group_pins = pinctrl_generic_get_group_pins,
1142         .dt_node_to_map = rzg2l_dt_node_to_map,
1143         .dt_free_map = rzg2l_dt_free_map,
1144 };
1145
1146 static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
1147         .get_functions_count = pinmux_generic_get_function_count,
1148         .get_function_name = pinmux_generic_get_function_name,
1149         .get_function_groups = pinmux_generic_get_function_groups,
1150         .set_mux = rzg2l_pinctrl_set_mux,
1151         .strict = true,
1152 };
1153
1154 static const struct pinconf_ops rzg2l_pinctrl_confops = {
1155         .is_generic = true,
1156         .pin_config_get = rzg2l_pinctrl_pinconf_get,
1157         .pin_config_set = rzg2l_pinctrl_pinconf_set,
1158         .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
1159         .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
1160         .pin_config_config_dbg_show = pinconf_generic_dump_config,
1161 };
1162
1163 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
1164 {
1165         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1166         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1167         u32 *pin_data = pin_desc->drv_data;
1168         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1169         u32 port = RZG2L_PIN_ID_TO_PORT(offset);
1170         u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1171         unsigned long flags;
1172         u8 reg8;
1173         int ret;
1174
1175         ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
1176         if (ret)
1177                 return ret;
1178
1179         ret = pinctrl_gpio_request(chip, offset);
1180         if (ret)
1181                 return ret;
1182
1183         spin_lock_irqsave(&pctrl->lock, flags);
1184
1185         /* Select GPIO mode in PMC Register */
1186         reg8 = readb(pctrl->base + PMC(off));
1187         reg8 &= ~BIT(bit);
1188         writeb(reg8, pctrl->base + PMC(off));
1189
1190         spin_unlock_irqrestore(&pctrl->lock, flags);
1191
1192         return 0;
1193 }
1194
1195 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
1196                                      bool output)
1197 {
1198         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1199         unsigned int *pin_data = pin_desc->drv_data;
1200         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1201         u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1202         unsigned long flags;
1203         u16 reg16;
1204
1205         spin_lock_irqsave(&pctrl->lock, flags);
1206
1207         reg16 = readw(pctrl->base + PM(off));
1208         reg16 &= ~(PM_MASK << (bit * 2));
1209
1210         reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
1211         writew(reg16, pctrl->base + PM(off));
1212
1213         spin_unlock_irqrestore(&pctrl->lock, flags);
1214 }
1215
1216 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1217 {
1218         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1219         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1220         unsigned int *pin_data = pin_desc->drv_data;
1221         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1222         u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1223
1224         if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {
1225                 u16 reg16;
1226
1227                 reg16 = readw(pctrl->base + PM(off));
1228                 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1229                 if (reg16 == PM_OUTPUT)
1230                         return GPIO_LINE_DIRECTION_OUT;
1231         }
1232
1233         return GPIO_LINE_DIRECTION_IN;
1234 }
1235
1236 static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
1237                                       unsigned int offset)
1238 {
1239         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1240
1241         rzg2l_gpio_set_direction(pctrl, offset, false);
1242
1243         return 0;
1244 }
1245
1246 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1247                            int value)
1248 {
1249         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1250         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1251         unsigned int *pin_data = pin_desc->drv_data;
1252         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1253         u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1254         unsigned long flags;
1255         u8 reg8;
1256
1257         spin_lock_irqsave(&pctrl->lock, flags);
1258
1259         reg8 = readb(pctrl->base + P(off));
1260
1261         if (value)
1262                 writeb(reg8 | BIT(bit), pctrl->base + P(off));
1263         else
1264                 writeb(reg8 & ~BIT(bit), pctrl->base + P(off));
1265
1266         spin_unlock_irqrestore(&pctrl->lock, flags);
1267 }
1268
1269 static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
1270                                        unsigned int offset, int value)
1271 {
1272         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1273
1274         rzg2l_gpio_set(chip, offset, value);
1275         rzg2l_gpio_set_direction(pctrl, offset, true);
1276
1277         return 0;
1278 }
1279
1280 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
1281 {
1282         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1283         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1284         unsigned int *pin_data = pin_desc->drv_data;
1285         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1286         u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1287         u16 reg16;
1288
1289         reg16 = readw(pctrl->base + PM(off));
1290         reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1291
1292         if (reg16 == PM_INPUT)
1293                 return !!(readb(pctrl->base + PIN(off)) & BIT(bit));
1294         else if (reg16 == PM_OUTPUT)
1295                 return !!(readb(pctrl->base + P(off)) & BIT(bit));
1296         else
1297                 return -EINVAL;
1298 }
1299
1300 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
1301 {
1302         unsigned int virq;
1303
1304         pinctrl_gpio_free(chip, offset);
1305
1306         virq = irq_find_mapping(chip->irq.domain, offset);
1307         if (virq)
1308                 irq_dispose_mapping(virq);
1309
1310         /*
1311          * Set the GPIO as an input to ensure that the next GPIO request won't
1312          * drive the GPIO pin as an output.
1313          */
1314         rzg2l_gpio_direction_input(chip, offset);
1315 }
1316
1317 static const char * const rzg2l_gpio_names[] = {
1318         "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
1319         "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
1320         "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
1321         "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
1322         "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
1323         "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
1324         "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
1325         "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
1326         "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
1327         "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
1328         "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
1329         "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
1330         "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
1331         "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
1332         "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
1333         "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
1334         "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
1335         "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
1336         "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
1337         "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
1338         "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
1339         "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
1340         "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
1341         "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
1342         "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
1343         "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
1344         "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
1345         "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
1346         "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
1347         "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
1348         "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
1349         "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
1350         "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
1351         "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
1352         "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
1353         "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
1354         "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
1355         "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
1356         "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
1357         "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
1358         "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
1359         "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
1360         "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
1361         "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
1362         "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
1363         "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
1364         "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
1365         "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
1366         "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
1367 };
1368
1369 static const u32 r9a07g044_gpio_configs[] = {
1370         RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
1371         RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
1372         RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
1373         RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
1374         RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
1375         RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
1376         RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
1377         RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
1378         RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
1379         RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
1380         RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
1381         RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1382         RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1383         RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1384         RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1385         RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1386         RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1387         RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1388         RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1389         RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1390         RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1391         RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1392         RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1393         RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1394         RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1395         RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1396         RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1397         RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1398         RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1399         RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1400         RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1401         RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1402         RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1403         RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1404         RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1405         RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1406         RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1407         RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1408         RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
1409         RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
1410         RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
1411         RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
1412         RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
1413         RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
1414         RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
1415         RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
1416         RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
1417         RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
1418         RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
1419 };
1420
1421 static const u32 r9a07g043_gpio_configs[] = {
1422         RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1423         RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1424         RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1425         RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1426         RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1427         RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1428         RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1429         RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1430         RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1431         RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1432         RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1433         RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1434         RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1435         RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1436         RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1437         RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1438         RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1439         RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1440         RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1441 };
1442
1443 static const u32 r9a08g045_gpio_configs[] = {
1444         RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P0  */
1445         RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1446                                                                 PIN_CFG_IO_VMC_ETH0)) |
1447                                       PIN_CFG_OEN | PIN_CFG_IEN,                        /* P1 */
1448         RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1449                                                                 PIN_CFG_IO_VMC_ETH0)),  /* P2 */
1450         RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1451                                                                 PIN_CFG_IO_VMC_ETH0)),  /* P3 */
1452         RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1453                                                                 PIN_CFG_IO_VMC_ETH0)),  /* P4 */
1454         RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P5  */
1455         RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P6  */
1456         RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1457                                                                 PIN_CFG_IO_VMC_ETH1)) |
1458                                       PIN_CFG_OEN | PIN_CFG_IEN,                        /* P7 */
1459         RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1460                                                                 PIN_CFG_IO_VMC_ETH1)),  /* P8 */
1461         RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1462                                                                 PIN_CFG_IO_VMC_ETH1)),  /* P9 */
1463         RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1464                                                                 PIN_CFG_IO_VMC_ETH1)),  /* P10 */
1465         RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),          /* P11  */
1466         RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),          /* P12  */
1467         RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P13  */
1468         RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P14  */
1469         RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P15  */
1470         RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P16  */
1471         RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P17  */
1472         RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P18 */
1473 };
1474
1475 static const struct {
1476         struct rzg2l_dedicated_configs common[35];
1477         struct rzg2l_dedicated_configs rzg2l_pins[7];
1478 } rzg2l_dedicated_pins = {
1479         .common = {
1480                 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
1481                  (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
1482                 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
1483                  (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1484                 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
1485                  (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1486                 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
1487                 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
1488                 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
1489                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1490                 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
1491                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1492                 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
1493                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1494                 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
1495                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1496                 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
1497                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1498                 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
1499                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1500                 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
1501                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1502                 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
1503                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1504                 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
1505                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1506                 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
1507                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1508                 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
1509                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1510                 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
1511                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
1512                 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
1513                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1514                 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
1515                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1516                 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
1517                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1518                 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
1519                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1520                 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
1521                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1522                 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
1523                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1524                 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
1525                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1526                 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
1527                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1528                 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
1529                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1530                 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
1531                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1532                 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
1533                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1534                 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
1535                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1536                 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
1537                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1538                 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
1539                 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
1540                 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
1541                 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
1542                 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
1543         },
1544         .rzg2l_pins = {
1545                 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1546                 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
1547                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1548                 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
1549                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1550                 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
1551                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1552                 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
1553                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1554                 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
1555                  (PIN_CFG_IOLH_B | PIN_CFG_SR  | PIN_CFG_IO_VMC_QSPI)) },
1556                 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
1557                  (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1558         }
1559 };
1560
1561 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
1562         { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
1563                                                 PIN_CFG_FILCLKSEL)) },
1564         { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
1565                                                       PIN_CFG_SOFT_PS)) },
1566         { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
1567         { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
1568         { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
1569         { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1570                                                      PIN_CFG_IO_VMC_SD0)) },
1571         { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
1572         { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1573                                                        PIN_CFG_IO_VMC_SD0)) },
1574         { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1575                                                        PIN_CFG_IO_VMC_SD0)) },
1576         { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1577                                                        PIN_CFG_IO_VMC_SD0)) },
1578         { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1579                                                        PIN_CFG_IO_VMC_SD0)) },
1580         { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1581                                                        PIN_CFG_IO_VMC_SD0)) },
1582         { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1583                                                        PIN_CFG_IO_VMC_SD0)) },
1584         { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1585                                                        PIN_CFG_IO_VMC_SD0)) },
1586         { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1587                                                        PIN_CFG_IO_VMC_SD0)) },
1588         { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
1589         { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1590                                                      PIN_CFG_IO_VMC_SD1)) },
1591         { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1592                                                        PIN_CFG_IO_VMC_SD1)) },
1593         { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1594                                                        PIN_CFG_IO_VMC_SD1)) },
1595         { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1596                                                        PIN_CFG_IO_VMC_SD1)) },
1597         { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1598                                                        PIN_CFG_IO_VMC_SD1)) },
1599 };
1600
1601 static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
1602 {
1603         unsigned int gpioint;
1604         unsigned int i;
1605         u32 port, bit;
1606
1607         port = virq / 8;
1608         bit = virq % 8;
1609
1610         if (port >= data->n_ports ||
1611             bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
1612                 return -EINVAL;
1613
1614         gpioint = bit;
1615         for (i = 0; i < port; i++)
1616                 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
1617
1618         return gpioint;
1619 }
1620
1621 static void rzg2l_gpio_irq_disable(struct irq_data *d)
1622 {
1623         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1624         struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1625         unsigned int hwirq = irqd_to_hwirq(d);
1626         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
1627         unsigned int *pin_data = pin_desc->drv_data;
1628         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1629         u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
1630         unsigned long flags;
1631         void __iomem *addr;
1632
1633         irq_chip_disable_parent(d);
1634
1635         addr = pctrl->base + ISEL(off);
1636         if (bit >= 4) {
1637                 bit -= 4;
1638                 addr += 4;
1639         }
1640
1641         spin_lock_irqsave(&pctrl->lock, flags);
1642         writel(readl(addr) & ~BIT(bit * 8), addr);
1643         spin_unlock_irqrestore(&pctrl->lock, flags);
1644
1645         gpiochip_disable_irq(gc, hwirq);
1646 }
1647
1648 static void rzg2l_gpio_irq_enable(struct irq_data *d)
1649 {
1650         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1651         struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1652         unsigned int hwirq = irqd_to_hwirq(d);
1653         const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
1654         unsigned int *pin_data = pin_desc->drv_data;
1655         u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1656         u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
1657         unsigned long flags;
1658         void __iomem *addr;
1659
1660         gpiochip_enable_irq(gc, hwirq);
1661
1662         addr = pctrl->base + ISEL(off);
1663         if (bit >= 4) {
1664                 bit -= 4;
1665                 addr += 4;
1666         }
1667
1668         spin_lock_irqsave(&pctrl->lock, flags);
1669         writel(readl(addr) | BIT(bit * 8), addr);
1670         spin_unlock_irqrestore(&pctrl->lock, flags);
1671
1672         irq_chip_enable_parent(d);
1673 }
1674
1675 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1676 {
1677         return irq_chip_set_type_parent(d, type);
1678 }
1679
1680 static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
1681 {
1682         irq_chip_eoi_parent(d);
1683 }
1684
1685 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
1686 {
1687         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1688
1689         seq_printf(p, dev_name(gc->parent));
1690 }
1691
1692 static const struct irq_chip rzg2l_gpio_irqchip = {
1693         .name = "rzg2l-gpio",
1694         .irq_disable = rzg2l_gpio_irq_disable,
1695         .irq_enable = rzg2l_gpio_irq_enable,
1696         .irq_mask = irq_chip_mask_parent,
1697         .irq_unmask = irq_chip_unmask_parent,
1698         .irq_set_type = rzg2l_gpio_irq_set_type,
1699         .irq_eoi = rzg2l_gpio_irqc_eoi,
1700         .irq_print_chip = rzg2l_gpio_irq_print_chip,
1701         .irq_set_affinity = irq_chip_set_affinity_parent,
1702         .flags = IRQCHIP_IMMUTABLE,
1703         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1704 };
1705
1706 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
1707                                             unsigned int child,
1708                                             unsigned int child_type,
1709                                             unsigned int *parent,
1710                                             unsigned int *parent_type)
1711 {
1712         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
1713         unsigned long flags;
1714         int gpioint, irq;
1715
1716         gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
1717         if (gpioint < 0)
1718                 return gpioint;
1719
1720         spin_lock_irqsave(&pctrl->bitmap_lock, flags);
1721         irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));
1722         spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
1723         if (irq < 0)
1724                 return -ENOSPC;
1725         pctrl->hwirq[irq] = child;
1726         irq += RZG2L_TINT_IRQ_START_INDEX;
1727
1728         /* All these interrupts are level high in the CPU */
1729         *parent_type = IRQ_TYPE_LEVEL_HIGH;
1730         *parent = RZG2L_PACK_HWIRQ(gpioint, irq);
1731         return 0;
1732 }
1733
1734 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1735                                              union gpio_irq_fwspec *gfwspec,
1736                                              unsigned int parent_hwirq,
1737                                              unsigned int parent_type)
1738 {
1739         struct irq_fwspec *fwspec = &gfwspec->fwspec;
1740
1741         fwspec->fwnode = chip->irq.parent_domain->fwnode;
1742         fwspec->param_count = 2;
1743         fwspec->param[0] = parent_hwirq;
1744         fwspec->param[1] = parent_type;
1745
1746         return 0;
1747 }
1748
1749 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1750                                        unsigned int nr_irqs)
1751 {
1752         struct irq_data *d;
1753
1754         d = irq_domain_get_irq_data(domain, virq);
1755         if (d) {
1756                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1757                 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1758                 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1759                 unsigned long flags;
1760                 unsigned int i;
1761
1762                 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
1763                         if (pctrl->hwirq[i] == hwirq) {
1764                                 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
1765                                 bitmap_release_region(pctrl->tint_slot, i, get_order(1));
1766                                 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
1767                                 pctrl->hwirq[i] = 0;
1768                                 break;
1769                         }
1770                 }
1771         }
1772         irq_domain_free_irqs_common(domain, virq, nr_irqs);
1773 }
1774
1775 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
1776                                       unsigned long *valid_mask,
1777                                       unsigned int ngpios)
1778 {
1779         struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
1780         struct gpio_chip *chip = &pctrl->gpio_chip;
1781         unsigned int offset;
1782
1783         /* Forbid unused lines to be mapped as IRQs */
1784         for (offset = 0; offset < chip->ngpio; offset++) {
1785                 u32 port, bit;
1786
1787                 port = offset / 8;
1788                 bit = offset % 8;
1789
1790                 if (port >= pctrl->data->n_ports ||
1791                     bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
1792                         clear_bit(offset, valid_mask);
1793         }
1794 }
1795
1796 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
1797 {
1798         struct device_node *np = pctrl->dev->of_node;
1799         struct gpio_chip *chip = &pctrl->gpio_chip;
1800         const char *name = dev_name(pctrl->dev);
1801         struct irq_domain *parent_domain;
1802         struct of_phandle_args of_args;
1803         struct device_node *parent_np;
1804         struct gpio_irq_chip *girq;
1805         int ret;
1806
1807         parent_np = of_irq_find_parent(np);
1808         if (!parent_np)
1809                 return -ENXIO;
1810
1811         parent_domain = irq_find_host(parent_np);
1812         of_node_put(parent_np);
1813         if (!parent_domain)
1814                 return -EPROBE_DEFER;
1815
1816         ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
1817         if (ret) {
1818                 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
1819                 return ret;
1820         }
1821
1822         if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
1823             of_args.args[2] != pctrl->data->n_port_pins) {
1824                 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
1825                 return -EINVAL;
1826         }
1827
1828         chip->names = pctrl->data->port_pins;
1829         chip->request = rzg2l_gpio_request;
1830         chip->free = rzg2l_gpio_free;
1831         chip->get_direction = rzg2l_gpio_get_direction;
1832         chip->direction_input = rzg2l_gpio_direction_input;
1833         chip->direction_output = rzg2l_gpio_direction_output;
1834         chip->get = rzg2l_gpio_get;
1835         chip->set = rzg2l_gpio_set;
1836         chip->label = name;
1837         chip->parent = pctrl->dev;
1838         chip->owner = THIS_MODULE;
1839         chip->base = -1;
1840         chip->ngpio = of_args.args[2];
1841
1842         girq = &chip->irq;
1843         gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
1844         girq->fwnode = of_node_to_fwnode(np);
1845         girq->parent_domain = parent_domain;
1846         girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
1847         girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
1848         girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
1849         girq->init_valid_mask = rzg2l_init_irq_valid_mask;
1850
1851         pctrl->gpio_range.id = 0;
1852         pctrl->gpio_range.pin_base = 0;
1853         pctrl->gpio_range.base = 0;
1854         pctrl->gpio_range.npins = chip->ngpio;
1855         pctrl->gpio_range.name = chip->label;
1856         pctrl->gpio_range.gc = chip;
1857         ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1858         if (ret) {
1859                 dev_err(pctrl->dev, "failed to add GPIO controller\n");
1860                 return ret;
1861         }
1862
1863         dev_dbg(pctrl->dev, "Registered gpio controller\n");
1864
1865         return 0;
1866 }
1867
1868 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
1869 {
1870         const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1871         struct pinctrl_pin_desc *pins;
1872         unsigned int i, j;
1873         u32 *pin_data;
1874         int ret;
1875
1876         pctrl->desc.name = DRV_NAME;
1877         pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
1878         pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
1879         pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
1880         pctrl->desc.confops = &rzg2l_pinctrl_confops;
1881         pctrl->desc.owner = THIS_MODULE;
1882
1883         pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
1884         if (!pins)
1885                 return -ENOMEM;
1886
1887         pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
1888                                 sizeof(*pin_data), GFP_KERNEL);
1889         if (!pin_data)
1890                 return -ENOMEM;
1891
1892         pctrl->pins = pins;
1893         pctrl->desc.pins = pins;
1894
1895         for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
1896                 pins[i].number = i;
1897                 pins[i].name = pctrl->data->port_pins[i];
1898                 if (i && !(i % RZG2L_PINS_PER_PORT))
1899                         j++;
1900                 pin_data[i] = pctrl->data->port_pin_configs[j];
1901                 pins[i].drv_data = &pin_data[i];
1902         }
1903
1904         for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1905                 unsigned int index = pctrl->data->n_port_pins + i;
1906
1907                 pins[index].number = index;
1908                 pins[index].name = pctrl->data->dedicated_pins[i].name;
1909                 pin_data[index] = pctrl->data->dedicated_pins[i].config;
1910                 pins[index].drv_data = &pin_data[index];
1911         }
1912
1913         pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings),
1914                                        GFP_KERNEL);
1915         if (!pctrl->settings)
1916                 return -ENOMEM;
1917
1918         for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {
1919                 if (pin_data[i] & PIN_CFG_SOFT_PS) {
1920                         pctrl->settings[i].power_source = 3300;
1921                 } else {
1922                         ret = rzg2l_get_power_source(pctrl, i, pin_data[i]);
1923                         if (ret < 0)
1924                                 continue;
1925                         pctrl->settings[i].power_source = ret;
1926                 }
1927         }
1928
1929         ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1930                                              &pctrl->pctl);
1931         if (ret) {
1932                 dev_err(pctrl->dev, "pinctrl registration failed\n");
1933                 return ret;
1934         }
1935
1936         ret = pinctrl_enable(pctrl->pctl);
1937         if (ret) {
1938                 dev_err(pctrl->dev, "pinctrl enable failed\n");
1939                 return ret;
1940         }
1941
1942         ret = rzg2l_gpio_register(pctrl);
1943         if (ret) {
1944                 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1945                 return ret;
1946         }
1947
1948         return 0;
1949 }
1950
1951 static int rzg2l_pinctrl_probe(struct platform_device *pdev)
1952 {
1953         struct rzg2l_pinctrl *pctrl;
1954         struct clk *clk;
1955         int ret;
1956
1957         BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >
1958                      ARRAY_SIZE(rzg2l_gpio_names));
1959
1960         BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
1961                      ARRAY_SIZE(rzg2l_gpio_names));
1962
1963         BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
1964                      ARRAY_SIZE(rzg2l_gpio_names));
1965
1966         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1967         if (!pctrl)
1968                 return -ENOMEM;
1969
1970         pctrl->dev = &pdev->dev;
1971
1972         pctrl->data = of_device_get_match_data(&pdev->dev);
1973         if (!pctrl->data)
1974                 return -EINVAL;
1975
1976         pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1977         if (IS_ERR(pctrl->base))
1978                 return PTR_ERR(pctrl->base);
1979
1980         clk = devm_clk_get_enabled(pctrl->dev, NULL);
1981         if (IS_ERR(clk))
1982                 return dev_err_probe(pctrl->dev, PTR_ERR(clk),
1983                                      "failed to enable GPIO clk\n");
1984
1985         spin_lock_init(&pctrl->lock);
1986         spin_lock_init(&pctrl->bitmap_lock);
1987         mutex_init(&pctrl->mutex);
1988
1989         platform_set_drvdata(pdev, pctrl);
1990
1991         ret = rzg2l_pinctrl_register(pctrl);
1992         if (ret)
1993                 return ret;
1994
1995         dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1996         return 0;
1997 }
1998
1999 static const struct rzg2l_hwcfg rzg2l_hwcfg = {
2000         .regs = {
2001                 .pwpr = 0x3014,
2002                 .sd_ch = 0x3000,
2003                 .eth_poc = 0x300c,
2004         },
2005         .iolh_groupa_ua = {
2006                 /* 3v3 power source */
2007                 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
2008         },
2009         .iolh_groupb_oi = { 100, 66, 50, 33, },
2010 };
2011
2012 static const struct rzg2l_hwcfg rzg3s_hwcfg = {
2013         .regs = {
2014                 .pwpr = 0x3000,
2015                 .sd_ch = 0x3004,
2016                 .eth_poc = 0x3010,
2017         },
2018         .iolh_groupa_ua = {
2019                 /* 1v8 power source */
2020                 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
2021                 /* 3v3 power source */
2022                 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
2023         },
2024         .iolh_groupb_ua = {
2025                 /* 1v8 power source */
2026                 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
2027                 /* 3v3 power source */
2028                 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
2029         },
2030         .iolh_groupc_ua = {
2031                 /* 1v8 power source */
2032                 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
2033                 /* 2v5 source */
2034                 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
2035                 /* 3v3 power source */
2036                 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
2037         },
2038         .drive_strength_ua = true,
2039         .func_base = 1,
2040         .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
2041         .oen_max_port = 7, /* P7_1 is the maximum OEN port. */
2042 };
2043
2044 static struct rzg2l_pinctrl_data r9a07g043_data = {
2045         .port_pins = rzg2l_gpio_names,
2046         .port_pin_configs = r9a07g043_gpio_configs,
2047         .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
2048         .dedicated_pins = rzg2l_dedicated_pins.common,
2049         .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
2050         .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
2051         .hwcfg = &rzg2l_hwcfg,
2052 };
2053
2054 static struct rzg2l_pinctrl_data r9a07g044_data = {
2055         .port_pins = rzg2l_gpio_names,
2056         .port_pin_configs = r9a07g044_gpio_configs,
2057         .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
2058         .dedicated_pins = rzg2l_dedicated_pins.common,
2059         .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,
2060         .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
2061                 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
2062         .hwcfg = &rzg2l_hwcfg,
2063 };
2064
2065 static struct rzg2l_pinctrl_data r9a08g045_data = {
2066         .port_pins = rzg2l_gpio_names,
2067         .port_pin_configs = r9a08g045_gpio_configs,
2068         .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
2069         .dedicated_pins = rzg3s_dedicated_pins,
2070         .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
2071         .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
2072         .hwcfg = &rzg3s_hwcfg,
2073 };
2074
2075 static const struct of_device_id rzg2l_pinctrl_of_table[] = {
2076         {
2077                 .compatible = "renesas,r9a07g043-pinctrl",
2078                 .data = &r9a07g043_data,
2079         },
2080         {
2081                 .compatible = "renesas,r9a07g044-pinctrl",
2082                 .data = &r9a07g044_data,
2083         },
2084         {
2085                 .compatible = "renesas,r9a08g045-pinctrl",
2086                 .data = &r9a08g045_data,
2087         },
2088         { /* sentinel */ }
2089 };
2090
2091 static struct platform_driver rzg2l_pinctrl_driver = {
2092         .driver = {
2093                 .name = DRV_NAME,
2094                 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
2095         },
2096         .probe = rzg2l_pinctrl_probe,
2097 };
2098
2099 static int __init rzg2l_pinctrl_init(void)
2100 {
2101         return platform_driver_register(&rzg2l_pinctrl_driver);
2102 }
2103 core_initcall(rzg2l_pinctrl_init);
2104
2105 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
2106 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");