1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
24 #include <linux/log2.h>
25 #include <linux/qcom_scm.h>
27 #include <linux/soc/qcom/irq.h>
30 #include "../pinconf.h"
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
34 #define MAX_NR_GPIO 300
35 #define MAX_NR_TILES 4
36 #define PS_HOLD_OFFSET 0x820
39 * struct msm_pinctrl - state for a pinctrl-msm device
40 * @dev: device handle.
41 * @pctrl: pinctrl handle.
42 * @chip: gpiochip handle.
43 * @desc: pin controller descriptor
44 * @restart_nb: restart notifier block.
45 * @irq_chip: irq chip information
46 * @irq: parent irq for the TLMM irq_chip.
47 * @intr_target_use_scm: route irq to application cpu using scm calls
48 * @lock: Spinlock to protect register resources as well
49 * as msm_pinctrl data structures.
50 * @enabled_irqs: Bitmap of currently enabled irqs.
51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
53 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
54 * @disabled_for_mux: These IRQs were disabled because we muxed away.
55 * @soc: Reference to soc_data of platform specific data.
56 * @regs: Base addresses for the TLMM tiles.
57 * @phys_base: Physical base address
61 struct pinctrl_dev *pctrl;
62 struct gpio_chip chip;
63 struct pinctrl_desc desc;
64 struct notifier_block restart_nb;
66 struct irq_chip irq_chip;
69 bool intr_target_use_scm;
73 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
74 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
75 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
76 DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
78 const struct msm_pinctrl_soc_data *soc;
79 void __iomem *regs[MAX_NR_TILES];
80 u32 phys_base[MAX_NR_TILES];
83 #define MSM_ACCESSOR(name) \
84 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
85 const struct msm_pingroup *g) \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
90 const struct msm_pingroup *g) \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
97 MSM_ACCESSOR(intr_cfg)
98 MSM_ACCESSOR(intr_status)
99 MSM_ACCESSOR(intr_target)
101 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
102 const struct msm_pingroup *g)
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
106 msm_writel_intr_status(val, pctrl, g);
109 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
113 return pctrl->soc->ngroups;
116 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
121 return pctrl->soc->groups[group].name;
124 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
126 const unsigned **pins,
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
131 *pins = pctrl->soc->groups[group].pins;
132 *num_pins = pctrl->soc->groups[group].npins;
136 static const struct pinctrl_ops msm_pinctrl_ops = {
137 .get_groups_count = msm_get_groups_count,
138 .get_group_name = msm_get_group_name,
139 .get_group_pins = msm_get_group_pins,
140 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
141 .dt_free_map = pinctrl_utils_free_map,
144 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
146 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
147 struct gpio_chip *chip = &pctrl->chip;
149 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
152 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
156 return pctrl->soc->nfunctions;
159 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
164 return pctrl->soc->functions[function].name;
167 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
169 const char * const **groups,
170 unsigned * const num_groups)
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
174 *groups = pctrl->soc->functions[function].groups;
175 *num_groups = pctrl->soc->functions[function].ngroups;
179 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
183 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
184 struct gpio_chip *gc = &pctrl->chip;
185 unsigned int irq = irq_find_mapping(gc->irq.domain, group);
186 struct irq_data *d = irq_get_irq_data(irq);
187 unsigned int gpio_func = pctrl->soc->gpio_func;
188 unsigned int egpio_func = pctrl->soc->egpio_func;
189 const struct msm_pingroup *g;
194 g = &pctrl->soc->groups[group];
195 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
197 for (i = 0; i < g->nfuncs; i++) {
198 if (g->funcs[i] == function)
202 if (WARN_ON(i == g->nfuncs))
206 * If an GPIO interrupt is setup on this pin then we need special
207 * handling. Specifically interrupt detection logic will still see
208 * the pin twiddle even when we're muxed away.
210 * When we see a pin with an interrupt setup on it then we'll disable
211 * (mask) interrupts on it when we mux away until we mux back. Note
212 * that disable_irq() refcounts and interrupts are disabled as long as
213 * at least one disable_irq() has been called.
215 if (d && i != gpio_func &&
216 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
219 raw_spin_lock_irqsave(&pctrl->lock, flags);
221 val = msm_readl_ctl(pctrl, g);
223 if (egpio_func && i == egpio_func) {
224 if (val & BIT(g->egpio_present))
225 val &= ~BIT(g->egpio_enable);
228 val |= i << g->mux_bit;
229 /* Claim ownership of pin if egpio capable */
230 if (egpio_func && val & BIT(g->egpio_present))
231 val |= BIT(g->egpio_enable);
234 msm_writel_ctl(val, pctrl, g);
236 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
238 if (d && i == gpio_func &&
239 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
241 * Clear interrupts detected while not GPIO since we only
244 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
245 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
247 msm_ack_intr_status(pctrl, g);
255 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
256 struct pinctrl_gpio_range *range,
259 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
260 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
262 /* No funcs? Probably ACPI so can't do anything here */
266 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
269 static const struct pinmux_ops msm_pinmux_ops = {
270 .request = msm_pinmux_request,
271 .get_functions_count = msm_get_functions_count,
272 .get_function_name = msm_get_function_name,
273 .get_function_groups = msm_get_function_groups,
274 .gpio_request_enable = msm_pinmux_request_gpio,
275 .set_mux = msm_pinmux_set_mux,
278 static int msm_config_reg(struct msm_pinctrl *pctrl,
279 const struct msm_pingroup *g,
285 case PIN_CONFIG_BIAS_DISABLE:
286 case PIN_CONFIG_BIAS_PULL_DOWN:
287 case PIN_CONFIG_BIAS_BUS_HOLD:
288 case PIN_CONFIG_BIAS_PULL_UP:
292 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
296 case PIN_CONFIG_DRIVE_STRENGTH:
300 case PIN_CONFIG_OUTPUT:
301 case PIN_CONFIG_INPUT_ENABLE:
312 #define MSM_NO_PULL 0
313 #define MSM_PULL_DOWN 1
315 #define MSM_PULL_UP_NO_KEEPER 2
316 #define MSM_PULL_UP 3
318 static unsigned msm_regval_to_drive(u32 val)
320 return (val + 1) * 2;
323 static int msm_config_group_get(struct pinctrl_dev *pctldev,
325 unsigned long *config)
327 const struct msm_pingroup *g;
328 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
329 unsigned param = pinconf_to_config_param(*config);
336 g = &pctrl->soc->groups[group];
338 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
342 val = msm_readl_ctl(pctrl, g);
343 arg = (val >> bit) & mask;
345 /* Convert register value to pinconf value */
347 case PIN_CONFIG_BIAS_DISABLE:
348 if (arg != MSM_NO_PULL)
352 case PIN_CONFIG_BIAS_PULL_DOWN:
353 if (arg != MSM_PULL_DOWN)
357 case PIN_CONFIG_BIAS_BUS_HOLD:
358 if (pctrl->soc->pull_no_keeper)
361 if (arg != MSM_KEEPER)
365 case PIN_CONFIG_BIAS_PULL_UP:
366 if (pctrl->soc->pull_no_keeper)
367 arg = arg == MSM_PULL_UP_NO_KEEPER;
369 arg = arg == MSM_PULL_UP;
373 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
374 /* Pin is not open-drain */
379 case PIN_CONFIG_DRIVE_STRENGTH:
380 arg = msm_regval_to_drive(arg);
382 case PIN_CONFIG_OUTPUT:
383 /* Pin is not output */
387 val = msm_readl_io(pctrl, g);
388 arg = !!(val & BIT(g->in_bit));
390 case PIN_CONFIG_INPUT_ENABLE:
400 *config = pinconf_to_config_packed(param, arg);
405 static int msm_config_group_set(struct pinctrl_dev *pctldev,
407 unsigned long *configs,
408 unsigned num_configs)
410 const struct msm_pingroup *g;
411 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
421 g = &pctrl->soc->groups[group];
423 for (i = 0; i < num_configs; i++) {
424 param = pinconf_to_config_param(configs[i]);
425 arg = pinconf_to_config_argument(configs[i]);
427 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
431 /* Convert pinconf values to register values */
433 case PIN_CONFIG_BIAS_DISABLE:
436 case PIN_CONFIG_BIAS_PULL_DOWN:
439 case PIN_CONFIG_BIAS_BUS_HOLD:
440 if (pctrl->soc->pull_no_keeper)
445 case PIN_CONFIG_BIAS_PULL_UP:
446 if (pctrl->soc->pull_no_keeper)
447 arg = MSM_PULL_UP_NO_KEEPER;
451 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
454 case PIN_CONFIG_DRIVE_STRENGTH:
455 /* Check for invalid values */
456 if (arg > 16 || arg < 2 || (arg % 2) != 0)
461 case PIN_CONFIG_OUTPUT:
462 /* set output value */
463 raw_spin_lock_irqsave(&pctrl->lock, flags);
464 val = msm_readl_io(pctrl, g);
466 val |= BIT(g->out_bit);
468 val &= ~BIT(g->out_bit);
469 msm_writel_io(val, pctrl, g);
470 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
475 case PIN_CONFIG_INPUT_ENABLE:
480 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
485 /* Range-check user-supplied value */
487 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
491 raw_spin_lock_irqsave(&pctrl->lock, flags);
492 val = msm_readl_ctl(pctrl, g);
493 val &= ~(mask << bit);
495 msm_writel_ctl(val, pctrl, g);
496 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
502 static const struct pinconf_ops msm_pinconf_ops = {
504 .pin_config_group_get = msm_config_group_get,
505 .pin_config_group_set = msm_config_group_set,
508 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
510 const struct msm_pingroup *g;
511 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
515 g = &pctrl->soc->groups[offset];
517 raw_spin_lock_irqsave(&pctrl->lock, flags);
519 val = msm_readl_ctl(pctrl, g);
520 val &= ~BIT(g->oe_bit);
521 msm_writel_ctl(val, pctrl, g);
523 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
528 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
530 const struct msm_pingroup *g;
531 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
535 g = &pctrl->soc->groups[offset];
537 raw_spin_lock_irqsave(&pctrl->lock, flags);
539 val = msm_readl_io(pctrl, g);
541 val |= BIT(g->out_bit);
543 val &= ~BIT(g->out_bit);
544 msm_writel_io(val, pctrl, g);
546 val = msm_readl_ctl(pctrl, g);
547 val |= BIT(g->oe_bit);
548 msm_writel_ctl(val, pctrl, g);
550 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
555 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
557 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
558 const struct msm_pingroup *g;
561 g = &pctrl->soc->groups[offset];
563 val = msm_readl_ctl(pctrl, g);
565 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
566 GPIO_LINE_DIRECTION_IN;
569 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
571 const struct msm_pingroup *g;
572 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
575 g = &pctrl->soc->groups[offset];
577 val = msm_readl_io(pctrl, g);
578 return !!(val & BIT(g->in_bit));
581 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
583 const struct msm_pingroup *g;
584 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
588 g = &pctrl->soc->groups[offset];
590 raw_spin_lock_irqsave(&pctrl->lock, flags);
592 val = msm_readl_io(pctrl, g);
594 val |= BIT(g->out_bit);
596 val &= ~BIT(g->out_bit);
597 msm_writel_io(val, pctrl, g);
599 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
602 #ifdef CONFIG_DEBUG_FS
603 #include <linux/seq_file.h>
605 static void msm_gpio_dbg_show_one(struct seq_file *s,
606 struct pinctrl_dev *pctldev,
607 struct gpio_chip *chip,
611 const struct msm_pingroup *g;
612 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
620 static const char * const pulls_keeper[] = {
627 static const char * const pulls_no_keeper[] = {
633 if (!gpiochip_line_is_valid(chip, offset))
636 g = &pctrl->soc->groups[offset];
637 ctl_reg = msm_readl_ctl(pctrl, g);
638 io_reg = msm_readl_io(pctrl, g);
640 is_out = !!(ctl_reg & BIT(g->oe_bit));
641 func = (ctl_reg >> g->mux_bit) & 7;
642 drive = (ctl_reg >> g->drv_bit) & 7;
643 pull = (ctl_reg >> g->pull_bit) & 3;
646 val = !!(io_reg & BIT(g->out_bit));
648 val = !!(io_reg & BIT(g->in_bit));
650 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
651 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
652 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
653 if (pctrl->soc->pull_no_keeper)
654 seq_printf(s, " %s", pulls_no_keeper[pull]);
656 seq_printf(s, " %s", pulls_keeper[pull]);
660 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
662 unsigned gpio = chip->base;
665 for (i = 0; i < chip->ngpio; i++, gpio++)
666 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
670 #define msm_gpio_dbg_show NULL
673 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
674 unsigned long *valid_mask,
677 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
680 const int *reserved = pctrl->soc->reserved_gpios;
683 /* Driver provided reserved list overrides DT and ACPI */
685 bitmap_fill(valid_mask, ngpios);
686 for (i = 0; reserved[i] >= 0; i++) {
687 if (i >= ngpios || reserved[i] >= ngpios) {
688 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
691 clear_bit(reserved[i], valid_mask);
697 /* The number of GPIOs in the ACPI tables */
698 len = ret = device_property_count_u16(pctrl->dev, "gpios");
705 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
709 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
711 dev_err(pctrl->dev, "could not read list of GPIOs\n");
715 bitmap_zero(valid_mask, ngpios);
716 for (i = 0; i < len; i++)
717 set_bit(tmp[i], valid_mask);
724 static const struct gpio_chip msm_gpio_template = {
725 .direction_input = msm_gpio_direction_input,
726 .direction_output = msm_gpio_direction_output,
727 .get_direction = msm_gpio_get_direction,
730 .request = gpiochip_generic_request,
731 .free = gpiochip_generic_free,
732 .dbg_show = msm_gpio_dbg_show,
735 /* For dual-edge interrupts in software, since some hardware has no
738 * At appropriate moments, this function may be called to flip the polarity
739 * settings of both-edge irq lines to try and catch the next edge.
741 * The attempt is considered successful if:
742 * - the status bit goes high, indicating that an edge was caught, or
743 * - the input value of the gpio doesn't change during the attempt.
744 * If the value changes twice during the process, that would cause the first
745 * test to fail but would force the second, as two opposite
746 * transitions would cause a detection no matter the polarity setting.
748 * The do-loop tries to sledge-hammer closed the timing hole between
749 * the initial value-read and the polarity-write - if the line value changes
750 * during that window, an interrupt is lost, the new polarity setting is
751 * incorrect, and the first success test will fail, causing a retry.
753 * Algorithm comes from Google's msmgpio driver.
755 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
756 const struct msm_pingroup *g,
759 int loop_limit = 100;
760 unsigned val, val2, intstat;
764 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
766 pol = msm_readl_intr_cfg(pctrl, g);
767 pol ^= BIT(g->intr_polarity_bit);
768 msm_writel_intr_cfg(pol, pctrl, g);
770 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
771 intstat = msm_readl_intr_status(pctrl, g);
772 if (intstat || (val == val2))
774 } while (loop_limit-- > 0);
775 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
779 static void msm_gpio_irq_mask(struct irq_data *d)
781 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
782 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
783 const struct msm_pingroup *g;
788 irq_chip_mask_parent(d);
790 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
793 g = &pctrl->soc->groups[d->hwirq];
795 raw_spin_lock_irqsave(&pctrl->lock, flags);
797 val = msm_readl_intr_cfg(pctrl, g);
799 * There are two bits that control interrupt forwarding to the CPU. The
800 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
801 * latched into the interrupt status register when the hardware detects
802 * an irq that it's configured for (either edge for edge type or level
803 * for level type irq). The 'non-raw' status enable bit causes the
804 * hardware to assert the summary interrupt to the CPU if the latched
805 * status bit is set. There's a bug though, the edge detection logic
806 * seems to have a problem where toggling the RAW_STATUS_EN bit may
807 * cause the status bit to latch spuriously when there isn't any edge
808 * so we can't touch that bit for edge type irqs and we have to keep
809 * the bit set anyway so that edges are latched while the line is masked.
811 * To make matters more complicated, leaving the RAW_STATUS_EN bit
812 * enabled all the time causes level interrupts to re-latch into the
813 * status register because the level is still present on the line after
814 * we ack it. We clear the raw status enable bit during mask here and
815 * set the bit on unmask so the interrupt can't latch into the hardware
818 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
819 val &= ~BIT(g->intr_raw_status_bit);
821 val &= ~BIT(g->intr_enable_bit);
822 msm_writel_intr_cfg(val, pctrl, g);
824 clear_bit(d->hwirq, pctrl->enabled_irqs);
826 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
829 static void msm_gpio_irq_unmask(struct irq_data *d)
831 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
832 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
833 const struct msm_pingroup *g;
838 irq_chip_unmask_parent(d);
840 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
843 g = &pctrl->soc->groups[d->hwirq];
845 raw_spin_lock_irqsave(&pctrl->lock, flags);
847 val = msm_readl_intr_cfg(pctrl, g);
848 val |= BIT(g->intr_raw_status_bit);
849 val |= BIT(g->intr_enable_bit);
850 msm_writel_intr_cfg(val, pctrl, g);
852 set_bit(d->hwirq, pctrl->enabled_irqs);
854 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
857 static void msm_gpio_irq_enable(struct irq_data *d)
859 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
860 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
863 irq_chip_enable_parent(d);
865 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
866 msm_gpio_irq_unmask(d);
869 static void msm_gpio_irq_disable(struct irq_data *d)
871 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
872 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
875 irq_chip_disable_parent(d);
877 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
878 msm_gpio_irq_mask(d);
882 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
885 * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
886 * normally handled by the parent irqchip. The logic here is slightly
887 * different due to what's easy to do with our parent, but in principle it's
890 static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
892 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
893 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
894 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
895 int loop_limit = 100;
899 /* Read the value and make a guess about what edge we need to catch */
900 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
901 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
904 /* Set the parent to catch the next edge */
905 irq_chip_set_type_parent(d, type);
908 * Possibly the line changed between when we last read "val"
909 * (and decided what edge we needed) and when set the edge.
910 * If the value didn't change (or changed and then changed
911 * back) then we're done.
913 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
914 if (type == IRQ_TYPE_EDGE_RISING) {
917 type = IRQ_TYPE_EDGE_FALLING;
918 } else if (type == IRQ_TYPE_EDGE_FALLING) {
921 type = IRQ_TYPE_EDGE_RISING;
923 } while (loop_limit-- > 0);
924 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
927 static void msm_gpio_irq_ack(struct irq_data *d)
929 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
930 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
931 const struct msm_pingroup *g;
934 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
935 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
936 msm_gpio_update_dual_edge_parent(d);
940 g = &pctrl->soc->groups[d->hwirq];
942 raw_spin_lock_irqsave(&pctrl->lock, flags);
944 msm_ack_intr_status(pctrl, g);
946 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
947 msm_gpio_update_dual_edge_pos(pctrl, g, d);
949 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
952 static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
955 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
956 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
958 return type == IRQ_TYPE_EDGE_BOTH &&
959 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
960 test_bit(d->hwirq, pctrl->skip_wake_irqs);
963 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
965 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
966 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
967 const struct msm_pingroup *g;
972 if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
973 set_bit(d->hwirq, pctrl->dual_edge_irqs);
974 irq_set_handler_locked(d, handle_fasteoi_ack_irq);
975 msm_gpio_update_dual_edge_parent(d);
980 irq_chip_set_type_parent(d, type);
982 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
983 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
984 irq_set_handler_locked(d, handle_fasteoi_irq);
988 g = &pctrl->soc->groups[d->hwirq];
990 raw_spin_lock_irqsave(&pctrl->lock, flags);
993 * For hw without possibility of detecting both edges
995 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
996 set_bit(d->hwirq, pctrl->dual_edge_irqs);
998 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1000 /* Route interrupts to application cpu.
1001 * With intr_target_use_scm interrupts are routed to
1002 * application cpu using scm calls.
1004 if (pctrl->intr_target_use_scm) {
1005 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1008 qcom_scm_io_readl(addr, &val);
1010 val &= ~(7 << g->intr_target_bit);
1011 val |= g->intr_target_kpss_val << g->intr_target_bit;
1013 ret = qcom_scm_io_writel(addr, val);
1016 "Failed routing %lu interrupt to Apps proc",
1019 val = msm_readl_intr_target(pctrl, g);
1020 val &= ~(7 << g->intr_target_bit);
1021 val |= g->intr_target_kpss_val << g->intr_target_bit;
1022 msm_writel_intr_target(val, pctrl, g);
1025 /* Update configuration for gpio.
1026 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
1027 * internal circuitry of TLMM, toggling the RAW_STATUS
1028 * could cause the INTR_STATUS to be set for EDGE interrupts.
1030 val = msm_readl_intr_cfg(pctrl, g);
1031 was_enabled = val & BIT(g->intr_raw_status_bit);
1032 val |= BIT(g->intr_raw_status_bit);
1033 if (g->intr_detection_width == 2) {
1034 val &= ~(3 << g->intr_detection_bit);
1035 val &= ~(1 << g->intr_polarity_bit);
1037 case IRQ_TYPE_EDGE_RISING:
1038 val |= 1 << g->intr_detection_bit;
1039 val |= BIT(g->intr_polarity_bit);
1041 case IRQ_TYPE_EDGE_FALLING:
1042 val |= 2 << g->intr_detection_bit;
1043 val |= BIT(g->intr_polarity_bit);
1045 case IRQ_TYPE_EDGE_BOTH:
1046 val |= 3 << g->intr_detection_bit;
1047 val |= BIT(g->intr_polarity_bit);
1049 case IRQ_TYPE_LEVEL_LOW:
1051 case IRQ_TYPE_LEVEL_HIGH:
1052 val |= BIT(g->intr_polarity_bit);
1055 } else if (g->intr_detection_width == 1) {
1056 val &= ~(1 << g->intr_detection_bit);
1057 val &= ~(1 << g->intr_polarity_bit);
1059 case IRQ_TYPE_EDGE_RISING:
1060 val |= BIT(g->intr_detection_bit);
1061 val |= BIT(g->intr_polarity_bit);
1063 case IRQ_TYPE_EDGE_FALLING:
1064 val |= BIT(g->intr_detection_bit);
1066 case IRQ_TYPE_EDGE_BOTH:
1067 val |= BIT(g->intr_detection_bit);
1068 val |= BIT(g->intr_polarity_bit);
1070 case IRQ_TYPE_LEVEL_LOW:
1072 case IRQ_TYPE_LEVEL_HIGH:
1073 val |= BIT(g->intr_polarity_bit);
1079 msm_writel_intr_cfg(val, pctrl, g);
1082 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
1083 * Clear the interrupt. This is safe because we have
1084 * IRQCHIP_SET_TYPE_MASKED.
1087 msm_ack_intr_status(pctrl, g);
1089 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1090 msm_gpio_update_dual_edge_pos(pctrl, g, d);
1092 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1094 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1095 irq_set_handler_locked(d, handle_level_irq);
1096 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1097 irq_set_handler_locked(d, handle_edge_irq);
1102 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1105 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1108 * While they may not wake up when the TLMM is powered off,
1109 * some GPIOs would like to wakeup the system from suspend
1110 * when TLMM is powered on. To allow that, enable the GPIO
1111 * summary line to be wakeup capable at GIC.
1113 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1114 return irq_chip_set_wake_parent(d, on);
1116 return irq_set_irq_wake(pctrl->irq, on);
1119 static int msm_gpio_irq_reqres(struct irq_data *d)
1121 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1122 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1125 if (!try_module_get(gc->owner))
1128 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1131 msm_gpio_direction_input(gc, d->hwirq);
1133 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1135 "unable to lock HW IRQ %lu for IRQ\n",
1142 * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
1143 * only works if disable is not lazy since we only clear any bogus
1144 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
1146 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1150 module_put(gc->owner);
1154 static void msm_gpio_irq_relres(struct irq_data *d)
1156 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1158 gpiochip_unlock_as_irq(gc, d->hwirq);
1159 module_put(gc->owner);
1162 static int msm_gpio_irq_set_affinity(struct irq_data *d,
1163 const struct cpumask *dest, bool force)
1165 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1166 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1168 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1169 return irq_chip_set_affinity_parent(d, dest, force);
1174 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1177 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1179 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1180 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1185 static void msm_gpio_irq_handler(struct irq_desc *desc)
1187 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1188 const struct msm_pingroup *g;
1189 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1190 struct irq_chip *chip = irq_desc_get_chip(desc);
1195 chained_irq_enter(chip, desc);
1198 * Each pin has it's own IRQ status register, so use
1199 * enabled_irq bitmap to limit the number of reads.
1201 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1202 g = &pctrl->soc->groups[i];
1203 val = msm_readl_intr_status(pctrl, g);
1204 if (val & BIT(g->intr_status_bit)) {
1205 generic_handle_domain_irq(gc->irq.domain, i);
1210 /* No interrupts were flagged */
1212 handle_bad_irq(desc);
1214 chained_irq_exit(chip, desc);
1217 static int msm_gpio_wakeirq(struct gpio_chip *gc,
1219 unsigned int child_type,
1220 unsigned int *parent,
1221 unsigned int *parent_type)
1223 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1224 const struct msm_gpio_wakeirq_map *map;
1227 *parent = GPIO_NO_WAKE_IRQ;
1228 *parent_type = IRQ_TYPE_EDGE_RISING;
1230 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1231 map = &pctrl->soc->wakeirq_map[i];
1232 if (map->gpio == child) {
1233 *parent = map->wakeirq;
1241 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1243 if (pctrl->soc->reserved_gpios)
1246 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1249 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1251 struct gpio_chip *chip;
1252 struct gpio_irq_chip *girq;
1254 unsigned gpio, ngpio = pctrl->soc->ngpios;
1255 struct device_node *np;
1258 if (WARN_ON(ngpio > MAX_NR_GPIO))
1261 chip = &pctrl->chip;
1263 chip->ngpio = ngpio;
1264 chip->label = dev_name(pctrl->dev);
1265 chip->parent = pctrl->dev;
1266 chip->owner = THIS_MODULE;
1267 if (msm_gpio_needs_valid_mask(pctrl))
1268 chip->init_valid_mask = msm_gpio_init_valid_mask;
1270 pctrl->irq_chip.name = "msmgpio";
1271 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1272 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1273 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1274 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1275 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1276 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1277 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1278 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1279 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1280 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1281 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1282 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND |
1283 IRQCHIP_SET_TYPE_MASKED |
1284 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
1286 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1288 chip->irq.parent_domain = irq_find_matching_host(np,
1291 if (!chip->irq.parent_domain)
1292 return -EPROBE_DEFER;
1293 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1294 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1296 * Let's skip handling the GPIOs, if the parent irqchip
1297 * is handling the direct connect IRQ of the GPIO.
1299 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1300 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1301 gpio = pctrl->soc->wakeirq_map[i].gpio;
1302 set_bit(gpio, pctrl->skip_wake_irqs);
1307 girq->chip = &pctrl->irq_chip;
1308 girq->parent_handler = msm_gpio_irq_handler;
1309 girq->fwnode = pctrl->dev->fwnode;
1310 girq->num_parents = 1;
1311 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1315 girq->default_type = IRQ_TYPE_NONE;
1316 girq->handler = handle_bad_irq;
1317 girq->parents[0] = pctrl->irq;
1319 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1321 dev_err(pctrl->dev, "Failed register gpiochip\n");
1326 * For DeviceTree-supported systems, the gpio core checks the
1327 * pinctrl's device node for the "gpio-ranges" property.
1328 * If it is present, it takes care of adding the pin ranges
1329 * for the driver. In this case the driver can skip ahead.
1331 * In order to remain compatible with older, existing DeviceTree
1332 * files which don't set the "gpio-ranges" property or systems that
1333 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1335 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1336 ret = gpiochip_add_pin_range(&pctrl->chip,
1337 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1339 dev_err(pctrl->dev, "Failed to add pin range\n");
1340 gpiochip_remove(&pctrl->chip);
1348 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1351 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1353 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1358 static struct msm_pinctrl *poweroff_pctrl;
1360 static void msm_ps_hold_poweroff(void)
1362 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1365 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1368 const struct msm_function *func = pctrl->soc->functions;
1370 for (i = 0; i < pctrl->soc->nfunctions; i++)
1371 if (!strcmp(func[i].name, "ps_hold")) {
1372 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1373 pctrl->restart_nb.priority = 128;
1374 if (register_restart_handler(&pctrl->restart_nb))
1376 "failed to setup restart handler.\n");
1377 poweroff_pctrl = pctrl;
1378 pm_power_off = msm_ps_hold_poweroff;
1383 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1385 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1387 return pinctrl_force_sleep(pctrl->pctrl);
1390 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1392 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1394 return pinctrl_force_default(pctrl->pctrl);
1397 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1398 msm_pinctrl_resume);
1400 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1402 int msm_pinctrl_probe(struct platform_device *pdev,
1403 const struct msm_pinctrl_soc_data *soc_data)
1405 struct msm_pinctrl *pctrl;
1406 struct resource *res;
1410 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1414 pctrl->dev = &pdev->dev;
1415 pctrl->soc = soc_data;
1416 pctrl->chip = msm_gpio_template;
1417 pctrl->intr_target_use_scm = of_device_is_compatible(
1418 pctrl->dev->of_node,
1419 "qcom,ipq8064-pinctrl");
1421 raw_spin_lock_init(&pctrl->lock);
1423 if (soc_data->tiles) {
1424 for (i = 0; i < soc_data->ntiles; i++) {
1425 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1426 soc_data->tiles[i]);
1427 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1428 if (IS_ERR(pctrl->regs[i]))
1429 return PTR_ERR(pctrl->regs[i]);
1432 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1433 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1434 if (IS_ERR(pctrl->regs[0]))
1435 return PTR_ERR(pctrl->regs[0]);
1437 pctrl->phys_base[0] = res->start;
1440 msm_pinctrl_setup_pm_reset(pctrl);
1442 pctrl->irq = platform_get_irq(pdev, 0);
1446 pctrl->desc.owner = THIS_MODULE;
1447 pctrl->desc.pctlops = &msm_pinctrl_ops;
1448 pctrl->desc.pmxops = &msm_pinmux_ops;
1449 pctrl->desc.confops = &msm_pinconf_ops;
1450 pctrl->desc.name = dev_name(&pdev->dev);
1451 pctrl->desc.pins = pctrl->soc->pins;
1452 pctrl->desc.npins = pctrl->soc->npins;
1454 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1455 if (IS_ERR(pctrl->pctrl)) {
1456 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1457 return PTR_ERR(pctrl->pctrl);
1460 ret = msm_gpio_init(pctrl);
1464 platform_set_drvdata(pdev, pctrl);
1466 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1470 EXPORT_SYMBOL(msm_pinctrl_probe);
1472 int msm_pinctrl_remove(struct platform_device *pdev)
1474 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1476 gpiochip_remove(&pctrl->chip);
1478 unregister_restart_handler(&pctrl->restart_nb);
1482 EXPORT_SYMBOL(msm_pinctrl_remove);
1484 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
1485 MODULE_LICENSE("GPL v2");