drivers/pinctrl/pinctrl-max77620.c

   1 /*
   2  * MAX77620 pin control driver.
   3  *
   4  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author:
   7  *      Chaitanya Bandi <bandik@nvidia.com>
   8  *      Laxman Dewangan <ldewangan@nvidia.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/mfd/max77620.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinmux.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24
  25 #include "core.h"
  26 #include "pinconf.h"
  27 #include "pinctrl-utils.h"
  28
  29 #define MAX77620_PIN_NUM 8
  30
  31 enum max77620_pin_ppdrv {
  32         MAX77620_PIN_UNCONFIG_DRV,
  33         MAX77620_PIN_OD_DRV,
  34         MAX77620_PIN_PP_DRV,
  35 };
  36
  37 #define MAX77620_ACTIVE_FPS_SOURCE              (PIN_CONFIG_END + 1)
  38 #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS      (PIN_CONFIG_END + 2)
  39 #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS    (PIN_CONFIG_END + 3)
  40 #define MAX77620_SUSPEND_FPS_SOURCE             (PIN_CONFIG_END + 4)
  41 #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS     (PIN_CONFIG_END + 5)
  42 #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS   (PIN_CONFIG_END + 6)
  43
  44 struct max77620_pin_function {
  45         const char *name;
  46         const char * const *groups;
  47         unsigned int ngroups;
  48         int mux_option;
  49 };
  50
  51 static const struct pinconf_generic_params max77620_cfg_params[] = {
  52         {
  53                 .property = "maxim,active-fps-source",
  54                 .param = MAX77620_ACTIVE_FPS_SOURCE,
  55         }, {
  56                 .property = "maxim,active-fps-power-up-slot",
  57                 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
  58         }, {
  59                 .property = "maxim,active-fps-power-down-slot",
  60                 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
  61         }, {
  62                 .property = "maxim,suspend-fps-source",
  63                 .param = MAX77620_SUSPEND_FPS_SOURCE,
  64         }, {
  65                 .property = "maxim,suspend-fps-power-up-slot",
  66                 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
  67         }, {
  68                 .property = "maxim,suspend-fps-power-down-slot",
  69                 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
  70         },
  71 };
  72
  73 enum max77620_alternate_pinmux_option {
  74         MAX77620_PINMUX_GPIO                            = 0,
  75         MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN       = 1,
  76         MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT    = 2,
  77         MAX77620_PINMUX_32K_OUT1                        = 3,
  78         MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN  = 4,
  79         MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN  = 5,
  80         MAX77620_PINMUX_REFERENCE_OUT                   = 6,
  81 };
  82
  83 struct max77620_pingroup {
  84         const char *name;
  85         const unsigned int pins[1];
  86         unsigned int npins;
  87         enum max77620_alternate_pinmux_option alt_option;
  88 };
  89
  90 struct max77620_pin_info {
  91         enum max77620_pin_ppdrv drv_type;
  92         int pull_config;
  93 };
  94
  95 struct max77620_fps_config {
  96         int active_fps_src;
  97         int active_power_up_slots;
  98         int active_power_down_slots;
  99         int suspend_fps_src;
 100         int suspend_power_up_slots;
 101         int suspend_power_down_slots;
 102 };
 103
 104 struct max77620_pctrl_info {
 105         struct device *dev;
 106         struct pinctrl_dev *pctl;
 107         struct regmap *rmap;
 108         int pins_current_opt[MAX77620_GPIO_NR];
 109         const struct max77620_pin_function *functions;
 110         unsigned int num_functions;
 111         const struct max77620_pingroup *pin_groups;
 112         int num_pin_groups;
 113         const struct pinctrl_pin_desc *pins;
 114         unsigned int num_pins;
 115         struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
 116         struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
 117 };
 118
 119 static const struct pinctrl_pin_desc max77620_pins_desc[] = {
 120         PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
 121         PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
 122         PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
 123         PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
 124         PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
 125         PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
 126         PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
 127         PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
 128 };
 129
 130 static const char * const gpio_groups[] = {
 131         "gpio0",
 132         "gpio1",
 133         "gpio2",
 134         "gpio3",
 135         "gpio4",
 136         "gpio5",
 137         "gpio6",
 138         "gpio7",
 139 };
 140
 141 #define FUNCTION_GROUP(fname, mux)                      \
 142         {                                               \
 143                 .name = fname,                          \
 144                 .groups = gpio_groups,                  \
 145                 .ngroups = ARRAY_SIZE(gpio_groups),     \
 146                 .mux_option = MAX77620_PINMUX_##mux,    \
 147         }
 148
 149 static const struct max77620_pin_function max77620_pin_function[] = {
 150         FUNCTION_GROUP("gpio", GPIO),
 151         FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
 152         FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
 153         FUNCTION_GROUP("32k-out1", 32K_OUT1),
 154         FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
 155         FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
 156         FUNCTION_GROUP("reference-out", REFERENCE_OUT),
 157 };
 158
 159 #define MAX77620_PINGROUP(pg_name, pin_id, option) \
 160         {                                                               \
 161                 .name = #pg_name,                                       \
 162                 .pins = {MAX77620_##pin_id},                            \
 163                 .npins = 1,                                             \
 164                 .alt_option = MAX77620_PINMUX_##option,                 \
 165         }
 166
 167 static const struct max77620_pingroup max77620_pingroups[] = {
 168         MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
 169         MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
 170         MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
 171         MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
 172         MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
 173         MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
 174         MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
 175         MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
 176 };
 177
 178 static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 179 {
 180         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 181
 182         return mpci->num_pin_groups;
 183 }
 184
 185 static const char *max77620_pinctrl_get_group_name(
 186                 struct pinctrl_dev *pctldev, unsigned int group)
 187 {
 188         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 189
 190         return mpci->pin_groups[group].name;
 191 }
 192
 193 static int max77620_pinctrl_get_group_pins(
 194                 struct pinctrl_dev *pctldev, unsigned int group,
 195                 const unsigned int **pins, unsigned int *num_pins)
 196 {
 197         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 198
 199         *pins = mpci->pin_groups[group].pins;
 200         *num_pins = mpci->pin_groups[group].npins;
 201
 202         return 0;
 203 }
 204
 205 static const struct pinctrl_ops max77620_pinctrl_ops = {
 206         .get_groups_count = max77620_pinctrl_get_groups_count,
 207         .get_group_name = max77620_pinctrl_get_group_name,
 208         .get_group_pins = max77620_pinctrl_get_group_pins,
 209         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 210         .dt_free_map = pinctrl_utils_free_map,
 211 };
 212
 213 static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 214 {
 215         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 216
 217         return mpci->num_functions;
 218 }
 219
 220 static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 221                                                   unsigned int function)
 222 {
 223         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 224
 225         return mpci->functions[function].name;
 226 }
 227
 228 static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 229                                             unsigned int function,
 230                                             const char * const **groups,
 231                                             unsigned int * const num_groups)
 232 {
 233         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 234
 235         *groups = mpci->functions[function].groups;
 236         *num_groups = mpci->functions[function].ngroups;
 237
 238         return 0;
 239 }
 240
 241 static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
 242                                    unsigned int function, unsigned int group)
 243 {
 244         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 245         u8 val;
 246         int ret;
 247
 248         if (function == MAX77620_PINMUX_GPIO) {
 249                 val = 0;
 250         } else if (function == mpci->pin_groups[group].alt_option) {
 251                 val = 1 << group;
 252         } else {
 253                 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
 254                         group, function);
 255                 return -EINVAL;
 256         }
 257         ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
 258                                  BIT(group), val);
 259         if (ret < 0)
 260                 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
 261
 262         return ret;
 263 }
 264
 265 static const struct pinmux_ops max77620_pinmux_ops = {
 266         .get_functions_count    = max77620_pinctrl_get_funcs_count,
 267         .get_function_name      = max77620_pinctrl_get_func_name,
 268         .get_function_groups    = max77620_pinctrl_get_func_groups,
 269         .set_mux                = max77620_pinctrl_enable,
 270 };
 271
 272 static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
 273                                 unsigned int pin, unsigned long *config)
 274 {
 275         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 276         struct device *dev = mpci->dev;
 277         enum pin_config_param param = pinconf_to_config_param(*config);
 278         unsigned int val;
 279         int arg = 0;
 280         int ret;
 281
 282         switch (param) {
 283         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 284                 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
 285                         arg = 1;
 286                 break;
 287
 288         case PIN_CONFIG_DRIVE_PUSH_PULL:
 289                 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
 290                         arg = 1;
 291                 break;
 292
 293         case PIN_CONFIG_BIAS_PULL_UP:
 294                 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
 295                 if (ret < 0) {
 296                         dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
 297                         return ret;
 298                 }
 299                 if (val & BIT(pin))
 300                         arg = 1;
 301                 break;
 302
 303         case PIN_CONFIG_BIAS_PULL_DOWN:
 304                 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
 305                 if (ret < 0) {
 306                         dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
 307                         return ret;
 308                 }
 309                 if (val & BIT(pin))
 310                         arg = 1;
 311                 break;
 312
 313         default:
 314                 dev_err(dev, "Properties not supported\n");
 315                 return -ENOTSUPP;
 316         }
 317
 318         *config = pinconf_to_config_packed(param, (u16)arg);
 319
 320         return 0;
 321 }
 322
 323 static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
 324                                     int addr, int *fps)
 325 {
 326         unsigned int val;
 327         int ret;
 328
 329         ret = regmap_read(mpci->rmap, addr, &val);
 330         if (ret < 0) {
 331                 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
 332                 return ret;
 333         }
 334         *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
 335
 336         return 0;
 337 }
 338
 339 static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
 340                                   int pin, int param)
 341 {
 342         struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
 343         int addr, ret;
 344         int param_val;
 345         int mask, shift;
 346
 347         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 348                 return 0;
 349
 350         addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
 351         switch (param) {
 352         case MAX77620_ACTIVE_FPS_SOURCE:
 353         case MAX77620_SUSPEND_FPS_SOURCE:
 354                 mask = MAX77620_FPS_SRC_MASK;
 355                 shift = MAX77620_FPS_SRC_SHIFT;
 356                 param_val = fps_config->active_fps_src;
 357                 if (param == MAX77620_SUSPEND_FPS_SOURCE)
 358                         param_val = fps_config->suspend_fps_src;
 359                 break;
 360
 361         case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
 362         case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
 363                 mask = MAX77620_FPS_PU_PERIOD_MASK;
 364                 shift = MAX77620_FPS_PU_PERIOD_SHIFT;
 365                 param_val = fps_config->active_power_up_slots;
 366                 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
 367                         param_val = fps_config->suspend_power_up_slots;
 368                 break;
 369
 370         case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
 371         case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
 372                 mask = MAX77620_FPS_PD_PERIOD_MASK;
 373                 shift = MAX77620_FPS_PD_PERIOD_SHIFT;
 374                 param_val = fps_config->active_power_down_slots;
 375                 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
 376                         param_val = fps_config->suspend_power_down_slots;
 377                 break;
 378
 379         default:
 380                 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
 381                         param, pin);
 382                 return -EINVAL;
 383         }
 384
 385         if (param_val < 0)
 386                 return 0;
 387
 388         ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
 389         if (ret < 0)
 390                 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
 391
 392         return ret;
 393 }
 394
 395 static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
 396                                 unsigned int pin, unsigned long *configs,
 397                                 unsigned int num_configs)
 398 {
 399         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 400         struct device *dev = mpci->dev;
 401         struct max77620_fps_config *fps_config;
 402         int param;
 403         u32 param_val;
 404         unsigned int val;
 405         unsigned int pu_val;
 406         unsigned int pd_val;
 407         int addr, ret;
 408         int i;
 409
 410         for (i = 0; i < num_configs; i++) {
 411                 param = pinconf_to_config_param(configs[i]);
 412                 param_val = pinconf_to_config_argument(configs[i]);
 413
 414                 switch (param) {
 415                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 416                         val = param_val ? 0 : 1;
 417                         ret = regmap_update_bits(mpci->rmap,
 418                                                  MAX77620_REG_GPIO0 + pin,
 419                                                  MAX77620_CNFG_GPIO_DRV_MASK,
 420                                                  val);
 421                         if (ret)
 422                                 goto report_update_failure;
 423
 424                         mpci->pin_info[pin].drv_type = val ?
 425                                 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
 426                         break;
 427
 428                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 429                         val = param_val ? 1 : 0;
 430                         ret = regmap_update_bits(mpci->rmap,
 431                                                  MAX77620_REG_GPIO0 + pin,
 432                                                  MAX77620_CNFG_GPIO_DRV_MASK,
 433                                                  val);
 434                         if (ret)
 435                                 goto report_update_failure;
 436
 437                         mpci->pin_info[pin].drv_type = val ?
 438                                 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
 439                         break;
 440
 441                 case MAX77620_ACTIVE_FPS_SOURCE:
 442                 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
 443                 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
 444                         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 445                                 return -EINVAL;
 446
 447                         fps_config = &mpci->fps_config[pin];
 448
 449                         if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
 450                             (param_val == MAX77620_FPS_SRC_DEF)) {
 451                                 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
 452                                 ret = max77620_get_default_fps(
 453                                                 mpci, addr,
 454                                                 &fps_config->active_fps_src);
 455                                 if (ret < 0)
 456                                         return ret;
 457                                 break;
 458                         }
 459
 460                         if (param == MAX77620_ACTIVE_FPS_SOURCE)
 461                                 fps_config->active_fps_src = param_val;
 462                         else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
 463                                 fps_config->active_power_up_slots = param_val;
 464                         else
 465                                 fps_config->active_power_down_slots = param_val;
 466
 467                         ret = max77620_set_fps_param(mpci, pin, param);
 468                         if (ret < 0)
 469                                 return ret;
 470                         break;
 471
 472                 case MAX77620_SUSPEND_FPS_SOURCE:
 473                 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
 474                 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
 475                         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 476                                 return -EINVAL;
 477
 478                         fps_config = &mpci->fps_config[pin];
 479
 480                         if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
 481                             (param_val == MAX77620_FPS_SRC_DEF)) {
 482                                 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
 483                                 ret = max77620_get_default_fps(
 484                                                 mpci, addr,
 485                                                 &fps_config->suspend_fps_src);
 486                                 if (ret < 0)
 487                                         return ret;
 488                                 break;
 489                         }
 490
 491                         if (param == MAX77620_SUSPEND_FPS_SOURCE)
 492                                 fps_config->suspend_fps_src = param_val;
 493                         else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
 494                                 fps_config->suspend_power_up_slots = param_val;
 495                         else
 496                                 fps_config->suspend_power_down_slots =
 497                                                                 param_val;
 498                         break;
 499
 500                 case PIN_CONFIG_BIAS_PULL_UP:
 501                 case PIN_CONFIG_BIAS_PULL_DOWN:
 502                         pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
 503                                                         BIT(pin) : 0;
 504                         pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
 505                                                         BIT(pin) : 0;
 506
 507                         ret = regmap_update_bits(mpci->rmap,
 508                                                  MAX77620_REG_PUE_GPIO,
 509                                                  BIT(pin), pu_val);
 510                         if (ret < 0) {
 511                                 dev_err(dev, "PUE_GPIO update failed: %d\n",
 512                                         ret);
 513                                 return ret;
 514                         }
 515
 516                         ret = regmap_update_bits(mpci->rmap,
 517                                                  MAX77620_REG_PDE_GPIO,
 518                                                  BIT(pin), pd_val);
 519                         if (ret < 0) {
 520                                 dev_err(dev, "PDE_GPIO update failed: %d\n",
 521                                         ret);
 522                                 return ret;
 523                         }
 524                         break;
 525
 526                 default:
 527                         dev_err(dev, "Properties not supported\n");
 528                         return -ENOTSUPP;
 529                 }
 530         }
 531
 532         return 0;
 533
 534 report_update_failure:
 535         dev_err(dev, "Reg 0x%02x update failed %d\n",
 536                 MAX77620_REG_GPIO0 + pin, ret);
 537         return ret;
 538 }
 539
 540 static const struct pinconf_ops max77620_pinconf_ops = {
 541         .pin_config_get = max77620_pinconf_get,
 542         .pin_config_set = max77620_pinconf_set,
 543 };
 544
 545 static struct pinctrl_desc max77620_pinctrl_desc = {
 546         .pctlops = &max77620_pinctrl_ops,
 547         .pmxops = &max77620_pinmux_ops,
 548         .confops = &max77620_pinconf_ops,
 549 };
 550
 551 static int max77620_pinctrl_probe(struct platform_device *pdev)
 552 {
 553         struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
 554         struct max77620_pctrl_info *mpci;
 555         int i;
 556
 557         mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
 558         if (!mpci)
 559                 return -ENOMEM;
 560
 561         mpci->dev = &pdev->dev;
 562         mpci->dev->of_node = pdev->dev.parent->of_node;
 563         mpci->rmap = max77620->rmap;
 564
 565         mpci->pins = max77620_pins_desc;
 566         mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
 567         mpci->functions = max77620_pin_function;
 568         mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
 569         mpci->pin_groups = max77620_pingroups;
 570         mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
 571         platform_set_drvdata(pdev, mpci);
 572
 573         max77620_pinctrl_desc.name = dev_name(&pdev->dev);
 574         max77620_pinctrl_desc.pins = max77620_pins_desc;
 575         max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
 576         max77620_pinctrl_desc.num_custom_params =
 577                                 ARRAY_SIZE(max77620_cfg_params);
 578         max77620_pinctrl_desc.custom_params = max77620_cfg_params;
 579
 580         for (i = 0; i < MAX77620_PIN_NUM; ++i) {
 581                 mpci->fps_config[i].active_fps_src = -1;
 582                 mpci->fps_config[i].active_power_up_slots = -1;
 583                 mpci->fps_config[i].active_power_down_slots = -1;
 584                 mpci->fps_config[i].suspend_fps_src = -1;
 585                 mpci->fps_config[i].suspend_power_up_slots = -1;
 586                 mpci->fps_config[i].suspend_power_down_slots = -1;
 587         }
 588
 589         mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
 590                                            mpci);
 591         if (IS_ERR(mpci->pctl)) {
 592                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 593                 return PTR_ERR(mpci->pctl);
 594         }
 595
 596         return 0;
 597 }
 598
 599 #ifdef CONFIG_PM_SLEEP
 600 static int max77620_suspend_fps_param[] = {
 601         MAX77620_SUSPEND_FPS_SOURCE,
 602         MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
 603         MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
 604 };
 605
 606 static int max77620_active_fps_param[] = {
 607         MAX77620_ACTIVE_FPS_SOURCE,
 608         MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
 609         MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
 610 };
 611
 612 static int max77620_pinctrl_suspend(struct device *dev)
 613 {
 614         struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
 615         int pin, p;
 616
 617         for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
 618                 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 619                         continue;
 620                 for (p = 0; p < 3; ++p)
 621                         max77620_set_fps_param(
 622                                 mpci, pin, max77620_suspend_fps_param[p]);
 623         }
 624
 625         return 0;
 626 };
 627
 628 static int max77620_pinctrl_resume(struct device *dev)
 629 {
 630         struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
 631         int pin, p;
 632
 633         for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
 634                 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 635                         continue;
 636                 for (p = 0; p < 3; ++p)
 637                         max77620_set_fps_param(
 638                                 mpci, pin, max77620_active_fps_param[p]);
 639         }
 640
 641         return 0;
 642 }
 643 #endif
 644
 645 static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
 646         SET_SYSTEM_SLEEP_PM_OPS(
 647                 max77620_pinctrl_suspend, max77620_pinctrl_resume)
 648 };
 649
 650 static const struct platform_device_id max77620_pinctrl_devtype[] = {
 651         { .name = "max77620-pinctrl", },
 652         { .name = "max20024-pinctrl", },
 653         {},
 654 };
 655 MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
 656
 657 static struct platform_driver max77620_pinctrl_driver = {
 658         .driver = {
 659                 .name = "max77620-pinctrl",
 660                 .pm = &max77620_pinctrl_pm_ops,
 661         },
 662         .probe = max77620_pinctrl_probe,
 663         .id_table = max77620_pinctrl_devtype,
 664 };
 665
 666 module_platform_driver(max77620_pinctrl_driver);
 667
 668 MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
 669 MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
 670 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
 671 MODULE_ALIAS("platform:max77620-pinctrl");
 672 MODULE_LICENSE("GPL v2");