1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
15 #include <linux/module.h>
16 #include <linux/of_irq.h>
19 #include "pinctrl-mtk-common-v2.h"
22 * struct mtk_drive_desc - the structure that holds the information
23 * of the driving current
24 * @min: the minimum current of this group
25 * @max: the maximum current of this group
26 * @step: the step current of this group
27 * @scal: the weight factor
29 * formula: output = ((input) / step - 1) * scal
31 struct mtk_drive_desc {
38 /* The groups of drive strength */
39 static const struct mtk_drive_desc mtk_drive[] = {
40 [DRV_GRP0] = { 4, 16, 4, 1 },
41 [DRV_GRP1] = { 4, 16, 4, 2 },
42 [DRV_GRP2] = { 2, 8, 2, 1 },
43 [DRV_GRP3] = { 2, 8, 2, 2 },
44 [DRV_GRP4] = { 2, 16, 2, 1 },
47 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
49 writel_relaxed(val, pctl->base[i] + reg);
52 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
54 return readl_relaxed(pctl->base[i] + reg);
57 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
61 val = mtk_r32(pctl, i, reg);
64 mtk_w32(pctl, i, reg, val);
67 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
68 const struct mtk_pin_desc *desc,
69 int field, struct mtk_pin_field *pfd)
71 const struct mtk_pin_field_calc *c;
72 const struct mtk_pin_reg_calc *rc;
73 int start = 0, end, check;
77 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
78 rc = &hw->soc->reg_cal[field];
81 "Not support field %d for this soc\n", field);
85 end = rc->nranges - 1;
87 while (start <= end) {
88 check = (start + end) >> 1;
89 if (desc->number >= rc->range[check].s_pin
90 && desc->number <= rc->range[check].e_pin) {
93 } else if (start == end)
95 else if (desc->number < rc->range[check].s_pin)
102 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
103 field, desc->number, desc->name);
107 c = rc->range + check;
109 if (c->i_base > hw->nbase - 1) {
111 "Invalid base for field %d for pin = %d (%s)\n",
112 field, desc->number, desc->name);
116 /* Calculated bits as the overall offset the pin is located at,
117 * if c->fixed is held, that determines the all the pins in the
118 * range use the same field with the s_pin.
120 bits = c->fixed ? c->s_bit : c->s_bit +
121 (desc->number - c->s_pin) * (c->x_bits);
123 /* Fill pfd from bits. For example 32-bit register applied is assumed
124 * when c->sz_reg is equal to 32.
126 pfd->index = c->i_base;
127 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
128 pfd->bitpos = bits % c->sz_reg;
129 pfd->mask = (1 << c->x_bits) - 1;
131 /* pfd->next is used for indicating that bit wrapping-around happens
132 * which requires the manipulation for bit 0 starting in the next
133 * register to form the complete field read/write.
135 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
140 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
141 const struct mtk_pin_desc *desc,
142 int field, struct mtk_pin_field *pfd)
144 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
145 dev_err(hw->dev, "Invalid Field %d\n", field);
149 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
152 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
154 *l = 32 - pf->bitpos;
155 *h = get_count_order(pf->mask) - *l;
158 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
159 struct mtk_pin_field *pf, int value)
161 int nbits_l, nbits_h;
163 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
165 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
166 (value & pf->mask) << pf->bitpos);
168 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
169 (value & pf->mask) >> nbits_l);
172 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
173 struct mtk_pin_field *pf, int *value)
175 int nbits_l, nbits_h, h, l;
177 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
179 l = (mtk_r32(hw, pf->index, pf->offset)
180 >> pf->bitpos) & (BIT(nbits_l) - 1);
181 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
182 & (BIT(nbits_h) - 1);
184 *value = (h << nbits_l) | l;
187 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
188 int field, int value)
190 struct mtk_pin_field pf;
193 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
197 if (value < 0 || value > pf.mask)
201 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
202 (value & pf.mask) << pf.bitpos);
204 mtk_hw_write_cross_field(hw, &pf, value);
208 EXPORT_SYMBOL_GPL(mtk_hw_set_value);
210 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
211 int field, int *value)
213 struct mtk_pin_field pf;
216 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
221 *value = (mtk_r32(hw, pf.index, pf.offset)
222 >> pf.bitpos) & pf.mask;
224 mtk_hw_read_cross_field(hw, &pf, value);
228 EXPORT_SYMBOL_GPL(mtk_hw_get_value);
230 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
232 const struct mtk_pin_desc *desc;
235 desc = (const struct mtk_pin_desc *)hw->soc->pins;
237 while (i < hw->soc->npins) {
238 if (desc[i].eint.eint_n == eint_n)
239 return desc[i].number;
247 * Virtual GPIO only used inside SOC and not being exported to outside SOC.
248 * Some modules use virtual GPIO as eint (e.g. pmif or usb).
249 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
250 * and we can set GPIO as eint.
251 * But some modules use specific eint which doesn't have real GPIO pin.
252 * So we use virtual GPIO to map it.
255 bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
257 const struct mtk_pin_desc *desc;
258 bool virt_gpio = false;
260 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
262 /* if the GPIO is not supported for eint mode */
263 if (desc->eint.eint_m == NO_EINT_SUPPORT)
266 if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
271 EXPORT_SYMBOL_GPL(mtk_is_virt_gpio);
273 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
274 unsigned int *gpio_n,
275 struct gpio_chip **gpio_chip)
277 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
278 const struct mtk_pin_desc *desc;
280 desc = (const struct mtk_pin_desc *)hw->soc->pins;
281 *gpio_chip = &hw->chip;
283 /* Be greedy to guess first gpio_n is equal to eint_n */
284 if (desc[eint_n].eint.eint_n == eint_n)
287 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
289 return *gpio_n == EINT_NA ? -EINVAL : 0;
292 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
294 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
295 const struct mtk_pin_desc *desc;
296 struct gpio_chip *gpio_chip;
300 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
304 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
306 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
313 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
315 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
316 const struct mtk_pin_desc *desc;
317 struct gpio_chip *gpio_chip;
321 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
325 if (mtk_is_virt_gpio(hw, gpio_n))
328 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
330 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
335 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
339 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
340 /* SMT is supposed to be supported by every real GPIO and doesn't
341 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
342 * is just for adding EINT support to these virtual GPIOs. It should
343 * add an extra flag in the pin descriptor when more pins with
344 * distinctive characteristic come out.
346 if (err && err != -ENOTSUPP)
352 static const struct mtk_eint_xt mtk_eint_xt = {
353 .get_gpio_n = mtk_xt_get_gpio_n,
354 .get_gpio_state = mtk_xt_get_gpio_state,
355 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
358 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
360 struct device_node *np = pdev->dev.of_node;
363 if (!IS_ENABLED(CONFIG_EINT_MTK))
366 if (!of_property_read_bool(np, "interrupt-controller"))
369 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
373 hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint");
374 if (IS_ERR(hw->eint->base)) {
375 ret = PTR_ERR(hw->eint->base);
379 hw->eint->irq = irq_of_parse_and_map(np, 0);
380 if (!hw->eint->irq) {
385 if (!hw->soc->eint_hw) {
390 hw->eint->dev = &pdev->dev;
391 hw->eint->hw = hw->soc->eint_hw;
393 hw->eint->gpio_xlate = &mtk_eint_xt;
395 return mtk_eint_do_init(hw->eint);
398 devm_kfree(hw->dev, hw->eint);
402 EXPORT_SYMBOL_GPL(mtk_build_eint);
405 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
406 const struct mtk_pin_desc *desc)
410 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
415 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
422 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set);
424 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
425 const struct mtk_pin_desc *desc, int *res)
430 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
434 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
438 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
445 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get);
447 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
448 const struct mtk_pin_desc *desc, bool pullup)
452 arg = pullup ? 1 : 2;
454 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
458 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
465 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set);
467 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
468 const struct mtk_pin_desc *desc, bool pullup, int *res)
472 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
474 err = mtk_hw_get_value(hw, desc, reg, &v);
485 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
488 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
489 const struct mtk_pin_desc *desc)
491 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
494 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
496 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
497 const struct mtk_pin_desc *desc, int *res)
501 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
512 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1);
514 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
515 const struct mtk_pin_desc *desc, bool pullup)
519 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
521 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
526 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
532 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1);
534 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
535 const struct mtk_pin_desc *desc, bool pullup,
540 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
544 if (v == MTK_DISABLE)
547 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
551 if (pullup ^ (v == MTK_PULLUP))
558 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
560 /* Combo for the following pull register type:
562 * 2. PULLSEL + PULLEN
565 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
566 const struct mtk_pin_desc *desc,
571 if (arg == MTK_DISABLE) {
574 } else if ((arg == MTK_ENABLE) && pullup) {
577 } else if ((arg == MTK_ENABLE) && !pullup) {
585 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
589 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
595 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
596 const struct mtk_pin_desc *desc,
601 if (arg == MTK_DISABLE)
603 else if (arg == MTK_ENABLE)
610 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
614 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
620 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
621 const struct mtk_pin_desc *desc,
626 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
630 } else if (arg == MTK_PUPD_SET_R1R0_01) {
633 } else if (arg == MTK_PUPD_SET_R1R0_10) {
636 } else if (arg == MTK_PUPD_SET_R1R0_11) {
644 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
645 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
649 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
653 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
659 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
660 const struct mtk_pin_desc *desc,
661 u32 *pullup, u32 *enable)
665 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
669 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
673 if (pu == 0 && pd == 0) {
675 *enable = MTK_DISABLE;
676 } else if (pu == 1 && pd == 0) {
678 *enable = MTK_ENABLE;
679 } else if (pu == 0 && pd == 1) {
681 *enable = MTK_ENABLE;
689 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
690 const struct mtk_pin_desc *desc,
691 u32 *pullup, u32 *enable)
695 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
699 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
705 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
706 const struct mtk_pin_desc *desc,
707 u32 *pullup, u32 *enable)
711 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
714 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
715 *pullup = !(*pullup);
717 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
721 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
725 if ((r1 == 0) && (r0 == 0))
726 *enable = MTK_PUPD_SET_R1R0_00;
727 else if ((r1 == 0) && (r0 == 1))
728 *enable = MTK_PUPD_SET_R1R0_01;
729 else if ((r1 == 1) && (r0 == 0))
730 *enable = MTK_PUPD_SET_R1R0_10;
731 else if ((r1 == 1) && (r0 == 1))
732 *enable = MTK_PUPD_SET_R1R0_11;
740 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
741 const struct mtk_pin_desc *desc,
746 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
750 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
754 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
759 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
761 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
762 const struct mtk_pin_desc *desc,
763 u32 *pullup, u32 *enable)
767 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
771 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
775 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
780 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
783 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
784 const struct mtk_pin_desc *desc, u32 arg)
786 const struct mtk_drive_desc *tb;
789 tb = &mtk_drive[desc->drv_n];
790 /* 4mA when (e8, e4) = (0, 0)
791 * 8mA when (e8, e4) = (0, 1)
792 * 12mA when (e8, e4) = (1, 0)
793 * 16mA when (e8, e4) = (1, 1)
795 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
796 arg = (arg / tb->step - 1) * tb->scal;
797 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
802 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
810 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set);
812 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
813 const struct mtk_pin_desc *desc, int *val)
815 const struct mtk_drive_desc *tb;
818 tb = &mtk_drive[desc->drv_n];
820 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
824 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
828 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
829 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
831 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
835 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get);
838 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
839 const struct mtk_pin_desc *desc, u32 arg)
841 const struct mtk_drive_desc *tb;
844 tb = &mtk_drive[desc->drv_n];
846 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
847 arg = (arg / tb->step - 1) * tb->scal;
849 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
857 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1);
859 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
860 const struct mtk_pin_desc *desc, int *val)
862 const struct mtk_drive_desc *tb;
865 tb = &mtk_drive[desc->drv_n];
867 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
871 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
875 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1);
877 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
878 const struct mtk_pin_desc *desc, u32 arg)
880 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
882 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw);
884 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
885 const struct mtk_pin_desc *desc, int *val)
887 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
889 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw);
891 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
892 const struct mtk_pin_desc *desc, bool pullup,
897 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
898 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
899 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
900 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
902 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
906 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
911 arg = pullup ? 0 : 1;
913 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
915 /* If PUPD register is not supported for that pin, let's fallback to
916 * general bias control.
918 if (err == -ENOTSUPP) {
919 if (hw->soc->bias_set) {
920 err = hw->soc->bias_set(hw, desc, pullup);
923 } else if (hw->soc->bias_set_combo) {
924 err = hw->soc->bias_set_combo(hw, desc, pullup, arg);
934 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set);
936 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
937 const struct mtk_pin_desc *desc, bool pullup,
943 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
945 /* If PUPD register is not supported for that pin, let's fallback to
946 * general bias control.
948 if (err == -ENOTSUPP) {
949 if (hw->soc->bias_get) {
950 err = hw->soc->bias_get(hw, desc, pullup, val);
957 /* t == 0 supposes PULLUP for the customized PULL setup */
965 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
969 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
973 *val = (t | t2 << 1) & 0x7;
977 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get);
979 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
980 const struct mtk_pin_desc *desc, u32 arg)
984 int e0 = !!(arg & 2);
985 int e1 = !!(arg & 4);
987 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
994 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
998 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
1004 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set);
1006 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
1007 const struct mtk_pin_desc *desc, u32 *val)
1012 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
1016 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
1020 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
1024 *val = (en | e0 << 1 | e1 << 2) & 0x7;
1028 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
1030 MODULE_LICENSE("GPL v2");
1031 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1032 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");