1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/slab.h>
21 #define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
23 #define OPMODE_MASK GENMASK(4, 3)
24 #define OPMODE_NORMAL (0x00)
25 #define OPMODE_NONDRIVING BIT(3)
26 #define TERMSEL BIT(5)
28 #define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
29 #define XCVRSEL BIT(0)
31 #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
34 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
36 #define RETENABLEN BIT(3)
37 #define FSEL_MASK GENMASK(6, 4)
38 #define FSEL_DEFAULT (0x3 << 4)
40 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
41 #define VBUSVLDEXTSEL0 BIT(4)
42 #define PLLBTUNE BIT(5)
44 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
45 #define VREGBYPASS BIT(0)
47 #define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
48 #define VBUSVLDEXT0 BIT(0)
50 #define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
51 #define USB2_AUTO_RESUME BIT(0)
52 #define USB2_SUSPEND_N BIT(2)
53 #define USB2_SUSPEND_N_SEL BIT(3)
55 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c)
56 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70)
57 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74)
58 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78)
59 #define PARAM_OVRD_MASK 0xFF
61 #define USB2_PHY_USB_PHY_CFG0 (0x94)
62 #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
63 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
65 #define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
66 #define REFCLK_SEL_MASK GENMASK(1, 0)
67 #define REFCLK_SEL_DEFAULT (0x2 << 0)
69 #define HS_DISCONNECT_MASK GENMASK(2, 0)
70 #define SQUELCH_DETECTOR_MASK GENMASK(7, 5)
72 #define HS_AMPLITUDE_MASK GENMASK(3, 0)
73 #define PREEMPHASIS_DURATION_MASK BIT(5)
74 #define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6)
76 #define HS_RISE_FALL_MASK GENMASK(1, 0)
77 #define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2)
78 #define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4)
80 #define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0)
82 static const char * const qcom_snps_hsphy_vreg_names[] = {
83 "vdda-pll", "vdda33", "vdda18",
86 #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
88 struct override_param {
93 struct override_param_map {
94 const char *prop_name;
95 const struct override_param *param_table;
101 struct phy_override_seq {
108 #define NUM_HSPHY_TUNING_PARAMS (9)
111 * struct qcom_snps_hsphy - snps hs phy attributes
113 * @dev: device structure
116 * @base: iomapped memory space for snps hs phy
118 * @num_clks: number of clocks
119 * @clks: array of clocks
120 * @phy_reset: phy reset control
121 * @vregs: regulator supplies bulk data
122 * @phy_initialized: if PHY has been initialized correctly
123 * @mode: contains the current mode the PHY is in
124 * @update_seq_cfg: tuning parameters for phy init
126 struct qcom_snps_hsphy {
133 struct clk_bulk_data *clks;
134 struct reset_control *phy_reset;
135 struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
137 bool phy_initialized;
139 struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS];
142 static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy)
144 struct device *dev = hsphy->dev;
147 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL);
152 * TODO: Currently no device tree instantiation of the PHY is using the clock.
153 * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get().
155 hsphy->clks[0].id = "cfg_ahb";
156 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb");
157 if (IS_ERR(hsphy->clks[0].clk))
158 return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk),
159 "failed to get cfg_ahb clk\n");
161 hsphy->clks[1].id = "ref";
162 hsphy->clks[1].clk = devm_clk_get(dev, "ref");
163 if (IS_ERR(hsphy->clks[1].clk))
164 return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk),
165 "failed to get ref clk\n");
170 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
175 reg = readl_relaxed(base + offset);
178 writel_relaxed(reg, base + offset);
180 /* Ensure above write is completed */
181 readl_relaxed(base + offset);
184 static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
186 dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
188 if (hsphy->mode == PHY_MODE_USB_HOST) {
189 /* Enable auto-resume to meet remote wakeup timing */
190 qcom_snps_hsphy_write_mask(hsphy->base,
191 USB2_PHY_USB_PHY_HS_PHY_CTRL2,
194 usleep_range(500, 1000);
195 qcom_snps_hsphy_write_mask(hsphy->base,
196 USB2_PHY_USB_PHY_HS_PHY_CTRL2,
197 0, USB2_AUTO_RESUME);
203 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
205 dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
210 static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
212 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
214 if (!hsphy->phy_initialized)
217 return qcom_snps_hsphy_suspend(hsphy);
220 static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
222 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
224 if (!hsphy->phy_initialized)
227 return qcom_snps_hsphy_resume(hsphy);
230 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
233 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
239 static const struct override_param hs_disconnect_sc7280[] = {
250 static const struct override_param squelch_det_threshold_sc7280[] = {
261 static const struct override_param hs_amplitude_sc7280[] = {
280 static const struct override_param preemphasis_duration_sc7280[] = {
285 static const struct override_param preemphasis_amplitude_sc7280[] = {
292 static const struct override_param hs_rise_fall_time_sc7280[] = {
299 static const struct override_param hs_crossover_voltage_sc7280[] = {
305 static const struct override_param hs_output_impedance_sc7280[] = {
312 static const struct override_param ls_fs_output_impedance_sc7280[] = {
320 static const struct override_param_map sc7280_snps_7nm_phy[] = {
322 "qcom,hs-disconnect-bp",
323 hs_disconnect_sc7280,
324 ARRAY_SIZE(hs_disconnect_sc7280),
325 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
329 "qcom,squelch-detector-bp",
330 squelch_det_threshold_sc7280,
331 ARRAY_SIZE(squelch_det_threshold_sc7280),
332 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
333 SQUELCH_DETECTOR_MASK
336 "qcom,hs-amplitude-bp",
338 ARRAY_SIZE(hs_amplitude_sc7280),
339 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
343 "qcom,pre-emphasis-duration-bp",
344 preemphasis_duration_sc7280,
345 ARRAY_SIZE(preemphasis_duration_sc7280),
346 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
347 PREEMPHASIS_DURATION_MASK,
350 "qcom,pre-emphasis-amplitude-bp",
351 preemphasis_amplitude_sc7280,
352 ARRAY_SIZE(preemphasis_amplitude_sc7280),
353 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
354 PREEMPHASIS_AMPLITUDE_MASK,
357 "qcom,hs-rise-fall-time-bp",
358 hs_rise_fall_time_sc7280,
359 ARRAY_SIZE(hs_rise_fall_time_sc7280),
360 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
364 "qcom,hs-crossover-voltage-microvolt",
365 hs_crossover_voltage_sc7280,
366 ARRAY_SIZE(hs_crossover_voltage_sc7280),
367 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
368 HS_CROSSOVER_VOLTAGE_MASK
371 "qcom,hs-output-impedance-micro-ohms",
372 hs_output_impedance_sc7280,
373 ARRAY_SIZE(hs_output_impedance_sc7280),
374 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
375 HS_OUTPUT_IMPEDANCE_MASK,
378 "qcom,ls-fs-output-impedance-bp",
379 ls_fs_output_impedance_sc7280,
380 ARRAY_SIZE(ls_fs_output_impedance_sc7280),
381 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3,
382 LS_FS_OUTPUT_IMPEDANCE_MASK,
387 static int qcom_snps_hsphy_init(struct phy *phy)
389 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
392 dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
394 ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
398 ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks);
400 dev_err(&phy->dev, "failed to enable clocks, %d\n", ret);
404 ret = reset_control_assert(hsphy->phy_reset);
406 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
410 usleep_range(100, 150);
412 ret = reset_control_deassert(hsphy->phy_reset);
414 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
418 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
419 UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
420 UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
421 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
423 qcom_snps_hsphy_write_mask(hsphy->base,
424 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
426 qcom_snps_hsphy_write_mask(hsphy->base,
427 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
429 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
430 REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
431 qcom_snps_hsphy_write_mask(hsphy->base,
432 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
433 VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
434 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
435 VBUSVLDEXT0, VBUSVLDEXT0);
437 for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {
438 if (hsphy->update_seq_cfg[i].need_update)
439 qcom_snps_hsphy_write_mask(hsphy->base,
440 hsphy->update_seq_cfg[i].offset,
441 hsphy->update_seq_cfg[i].mask,
442 hsphy->update_seq_cfg[i].value);
445 qcom_snps_hsphy_write_mask(hsphy->base,
446 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
447 VREGBYPASS, VREGBYPASS);
449 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
450 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
451 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
453 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
456 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
459 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
462 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
463 USB2_SUSPEND_N_SEL, 0);
465 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
466 UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
468 hsphy->phy_initialized = true;
473 clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);
475 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
480 static int qcom_snps_hsphy_exit(struct phy *phy)
482 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
484 reset_control_assert(hsphy->phy_reset);
485 clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);
486 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
487 hsphy->phy_initialized = false;
492 static const struct phy_ops qcom_snps_hsphy_gen_ops = {
493 .init = qcom_snps_hsphy_init,
494 .exit = qcom_snps_hsphy_exit,
495 .set_mode = qcom_snps_hsphy_set_mode,
496 .owner = THIS_MODULE,
499 static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
500 { .compatible = "qcom,sm8150-usb-hs-phy", },
501 { .compatible = "qcom,usb-snps-hs-5nm-phy", },
503 .compatible = "qcom,usb-snps-hs-7nm-phy",
504 .data = &sc7280_snps_7nm_phy,
506 { .compatible = "qcom,usb-snps-femto-v2-phy", },
509 MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
511 static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
512 SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
513 qcom_snps_hsphy_runtime_resume, NULL)
516 static void qcom_snps_hsphy_override_param_update_val(
517 const struct override_param_map map,
518 s32 dt_val, struct phy_override_seq *seq_entry)
523 * Param table for each param is in increasing order
524 * of dt values. We need to iterate over the list to
525 * select the entry that matches the dt value and pick
526 * up the corresponding register value.
528 for (i = 0; i < map.table_size - 1; i++) {
529 if (map.param_table[i].value == dt_val)
533 seq_entry->need_update = true;
534 seq_entry->offset = map.reg_offset;
535 seq_entry->mask = map.param_mask;
536 seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask);
539 static void qcom_snps_hsphy_read_override_param_seq(struct device *dev)
541 struct device_node *node = dev->of_node;
544 struct qcom_snps_hsphy *hsphy;
545 const struct override_param_map *cfg = of_device_get_match_data(dev);
550 hsphy = dev_get_drvdata(dev);
552 for (i = 0; cfg[i].prop_name != NULL; i++) {
553 ret = of_property_read_s32(node, cfg[i].prop_name, &val);
557 qcom_snps_hsphy_override_param_update_val(cfg[i], val,
558 &hsphy->update_seq_cfg[i]);
559 dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n",
560 cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value);
565 static int qcom_snps_hsphy_probe(struct platform_device *pdev)
567 struct device *dev = &pdev->dev;
568 struct qcom_snps_hsphy *hsphy;
569 struct phy_provider *phy_provider;
570 struct phy *generic_phy;
574 hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
580 hsphy->base = devm_platform_ioremap_resource(pdev, 0);
581 if (IS_ERR(hsphy->base))
582 return PTR_ERR(hsphy->base);
584 ret = qcom_snps_hsphy_clk_init(hsphy);
586 return dev_err_probe(dev, ret, "failed to initialize clocks\n");
588 hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
589 if (IS_ERR(hsphy->phy_reset)) {
590 dev_err(dev, "failed to get phy core reset\n");
591 return PTR_ERR(hsphy->phy_reset);
594 num = ARRAY_SIZE(hsphy->vregs);
595 for (i = 0; i < num; i++)
596 hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
598 ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
600 return dev_err_probe(dev, ret,
601 "failed to get regulator supplies\n");
603 pm_runtime_set_active(dev);
604 pm_runtime_enable(dev);
606 * Prevent runtime pm from being ON by default. Users can enable
607 * it using power/control in sysfs.
609 pm_runtime_forbid(dev);
611 generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
612 if (IS_ERR(generic_phy)) {
613 ret = PTR_ERR(generic_phy);
614 dev_err(dev, "failed to create phy, %d\n", ret);
617 hsphy->phy = generic_phy;
619 dev_set_drvdata(dev, hsphy);
620 phy_set_drvdata(generic_phy, hsphy);
621 qcom_snps_hsphy_read_override_param_seq(dev);
623 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
624 if (!IS_ERR(phy_provider))
625 dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
627 pm_runtime_disable(dev);
629 return PTR_ERR_OR_ZERO(phy_provider);
632 static struct platform_driver qcom_snps_hsphy_driver = {
633 .probe = qcom_snps_hsphy_probe,
635 .name = "qcom-snps-hs-femto-v2-phy",
636 .pm = &qcom_snps_hsphy_pm_ops,
637 .of_match_table = qcom_snps_hsphy_of_match_table,
641 module_platform_driver(qcom_snps_hsphy_driver);
643 MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
644 MODULE_LICENSE("GPL v2");