1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARMv8 PMUv3 Performance Events handling code.
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
8 * This code is based heavily on the ARMv7 perf event code.
11 #include <asm/irq_regs.h>
12 #include <asm/perf_event.h>
15 #include <clocksource/arm_arch_timer.h>
17 #include <linux/acpi.h>
18 #include <linux/clocksource.h>
20 #include <linux/perf/arm_pmu.h>
21 #include <linux/perf/arm_pmuv3.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched_clock.h>
24 #include <linux/smp.h>
26 #include <asm/arm_pmuv3.h>
28 /* ARMv8 Cortex-A53 specific event types. */
29 #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
31 /* ARMv8 Cavium ThunderX specific event types. */
32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
34 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
36 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
39 * ARMv8 Architectural defined events, not all of these may
40 * be supported on any given implementation. Unsupported events will
41 * be disabled at run-time based on the PMCEID registers.
43 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
44 PERF_MAP_ALL_UNSUPPORTED,
45 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
46 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
47 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
48 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
49 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
50 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
51 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
52 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
58 PERF_CACHE_MAP_ALL_UNSUPPORTED,
60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
64 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
75 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
76 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
80 [PERF_COUNT_HW_CACHE_OP_MAX]
81 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
82 PERF_CACHE_MAP_ALL_UNSUPPORTED,
84 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
86 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
87 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
91 [PERF_COUNT_HW_CACHE_OP_MAX]
92 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
93 PERF_CACHE_MAP_ALL_UNSUPPORTED,
95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
100 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
101 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
103 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
104 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
108 [PERF_COUNT_HW_CACHE_OP_MAX]
109 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
110 PERF_CACHE_MAP_ALL_UNSUPPORTED,
112 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
113 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
117 [PERF_COUNT_HW_CACHE_OP_MAX]
118 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
119 PERF_CACHE_MAP_ALL_UNSUPPORTED,
121 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
122 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
123 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
124 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
125 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
126 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
128 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
131 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
132 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
133 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
134 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
138 [PERF_COUNT_HW_CACHE_OP_MAX]
139 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
140 PERF_CACHE_MAP_ALL_UNSUPPORTED,
142 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
143 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
144 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
145 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
147 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
148 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
149 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
150 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
152 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
153 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
157 armv8pmu_events_sysfs_show(struct device *dev,
158 struct device_attribute *attr, char *page)
160 struct perf_pmu_events_attr *pmu_attr;
162 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
164 return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
167 #define ARMV8_EVENT_ATTR(name, config) \
168 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
170 static struct attribute *armv8_pmuv3_event_attrs[] = {
171 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
172 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
173 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
174 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
175 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
176 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
177 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
178 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
179 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
180 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
181 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
182 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
183 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
184 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
185 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
186 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
187 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
188 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
189 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
190 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
191 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
192 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
193 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
194 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
195 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
196 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
197 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
198 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
199 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
200 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
201 /* Don't expose the chain event in /sys, since it's useless in isolation */
202 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
203 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
204 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
205 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
206 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
207 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
208 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
209 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
210 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
211 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
212 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
213 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
214 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
215 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
216 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
217 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
218 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
219 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
220 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
221 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
222 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
223 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
224 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
225 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
226 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
227 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
228 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
229 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
230 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
231 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
232 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
233 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
234 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
235 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
236 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
237 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
238 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
239 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
240 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
241 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
242 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
243 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
244 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
245 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),
246 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),
247 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),
248 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),
249 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),
250 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),
251 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),
252 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),
253 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),
254 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),
255 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
256 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
257 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
258 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
259 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
260 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
265 armv8pmu_event_attr_is_visible(struct kobject *kobj,
266 struct attribute *attr, int unused)
268 struct device *dev = kobj_to_dev(kobj);
269 struct pmu *pmu = dev_get_drvdata(dev);
270 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
271 struct perf_pmu_events_attr *pmu_attr;
273 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
275 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
276 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
279 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
280 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
282 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
283 test_bit(id, cpu_pmu->pmceid_ext_bitmap))
290 static const struct attribute_group armv8_pmuv3_events_attr_group = {
292 .attrs = armv8_pmuv3_event_attrs,
293 .is_visible = armv8pmu_event_attr_is_visible,
296 PMU_FORMAT_ATTR(event, "config:0-15");
297 PMU_FORMAT_ATTR(long, "config1:0");
298 PMU_FORMAT_ATTR(rdpmc, "config1:1");
300 static int sysctl_perf_user_access __read_mostly;
302 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
304 return event->attr.config1 & 0x1;
307 static inline bool armv8pmu_event_want_user_access(struct perf_event *event)
309 return event->attr.config1 & 0x2;
312 static struct attribute *armv8_pmuv3_format_attrs[] = {
313 &format_attr_event.attr,
314 &format_attr_long.attr,
315 &format_attr_rdpmc.attr,
319 static const struct attribute_group armv8_pmuv3_format_attr_group = {
321 .attrs = armv8_pmuv3_format_attrs,
324 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
327 struct pmu *pmu = dev_get_drvdata(dev);
328 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
329 u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
331 return sysfs_emit(page, "0x%08x\n", slots);
334 static DEVICE_ATTR_RO(slots);
336 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
339 struct pmu *pmu = dev_get_drvdata(dev);
340 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
341 u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
342 & ARMV8_PMU_BUS_SLOTS_MASK;
344 return sysfs_emit(page, "0x%08x\n", bus_slots);
347 static DEVICE_ATTR_RO(bus_slots);
349 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
352 struct pmu *pmu = dev_get_drvdata(dev);
353 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
354 u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
355 & ARMV8_PMU_BUS_WIDTH_MASK;
358 /* Encoded as Log2(number of bytes), plus one */
359 if (bus_width > 2 && bus_width < 13)
360 val = 1 << (bus_width - 1);
362 return sysfs_emit(page, "0x%08x\n", val);
365 static DEVICE_ATTR_RO(bus_width);
367 static struct attribute *armv8_pmuv3_caps_attrs[] = {
368 &dev_attr_slots.attr,
369 &dev_attr_bus_slots.attr,
370 &dev_attr_bus_width.attr,
374 static const struct attribute_group armv8_pmuv3_caps_attr_group = {
376 .attrs = armv8_pmuv3_caps_attrs,
380 * Perf Events' indices
382 #define ARMV8_IDX_CYCLE_COUNTER 0
383 #define ARMV8_IDX_COUNTER0 1
384 #define ARMV8_IDX_CYCLE_COUNTER_USER 32
387 * We unconditionally enable ARMv8.5-PMU long event counter support
388 * (64-bit events) where supported. Indicate if this arm_pmu has long
389 * event counter support.
391 * On AArch32, long counters make no sense (you can't access the top
392 * bits), so we only enable this on AArch64.
394 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
396 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver));
399 static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
401 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
405 * We must chain two programmable counters for 64 bit events,
406 * except when we have allocated the 64bit cycle counter (for CPU
407 * cycles event) or when user space counter access is enabled.
409 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
411 int idx = event->hw.idx;
412 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
414 return !armv8pmu_event_has_user_read(event) &&
415 armv8pmu_event_is_64bit(event) &&
416 !armv8pmu_has_long_event(cpu_pmu) &&
417 (idx != ARMV8_IDX_CYCLE_COUNTER);
421 * ARMv8 low level PMU access
425 * Perf Event to low level counters mapping
427 #define ARMV8_IDX_TO_COUNTER(x) \
428 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
430 static inline u32 armv8pmu_pmcr_read(void)
435 static inline void armv8pmu_pmcr_write(u32 val)
437 val &= ARMV8_PMU_PMCR_MASK;
442 static inline int armv8pmu_has_overflowed(u32 pmovsr)
444 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
447 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
449 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
452 static inline u64 armv8pmu_read_evcntr(int idx)
454 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
456 return read_pmevcntrn(counter);
459 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
461 int idx = event->hw.idx;
462 u64 val = armv8pmu_read_evcntr(idx);
464 if (armv8pmu_event_is_chained(event))
465 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
470 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
471 * is set the event counters also become 64-bit counters. Unless the
472 * user has requested a long counter (attr.config1) then we want to
473 * interrupt upon 32-bit overflow - we achieve this by applying a bias.
475 static bool armv8pmu_event_needs_bias(struct perf_event *event)
477 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
478 struct hw_perf_event *hwc = &event->hw;
481 if (armv8pmu_event_is_64bit(event))
484 if (armv8pmu_has_long_event(cpu_pmu) ||
485 idx == ARMV8_IDX_CYCLE_COUNTER)
491 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
493 if (armv8pmu_event_needs_bias(event))
494 value |= GENMASK_ULL(63, 32);
499 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
501 if (armv8pmu_event_needs_bias(event))
502 value &= ~GENMASK_ULL(63, 32);
507 static u64 armv8pmu_read_counter(struct perf_event *event)
509 struct hw_perf_event *hwc = &event->hw;
513 if (idx == ARMV8_IDX_CYCLE_COUNTER)
514 value = read_pmccntr();
516 value = armv8pmu_read_hw_counter(event);
518 return armv8pmu_unbias_long_counter(event, value);
521 static inline void armv8pmu_write_evcntr(int idx, u64 value)
523 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
525 write_pmevcntrn(counter, value);
528 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
531 int idx = event->hw.idx;
533 if (armv8pmu_event_is_chained(event)) {
534 armv8pmu_write_evcntr(idx, upper_32_bits(value));
535 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
537 armv8pmu_write_evcntr(idx, value);
541 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
543 struct hw_perf_event *hwc = &event->hw;
546 value = armv8pmu_bias_long_counter(event, value);
548 if (idx == ARMV8_IDX_CYCLE_COUNTER)
549 write_pmccntr(value);
551 armv8pmu_write_hw_counter(event, value);
554 static inline void armv8pmu_write_evtype(int idx, u32 val)
556 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
558 val &= ARMV8_PMU_EVTYPE_MASK;
559 write_pmevtypern(counter, val);
562 static inline void armv8pmu_write_event_type(struct perf_event *event)
564 struct hw_perf_event *hwc = &event->hw;
568 * For chained events, the low counter is programmed to count
569 * the event of interest and the high counter is programmed
570 * with CHAIN event code with filters set to count at all ELs.
572 if (armv8pmu_event_is_chained(event)) {
573 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
574 ARMV8_PMU_INCLUDE_EL2;
576 armv8pmu_write_evtype(idx - 1, hwc->config_base);
577 armv8pmu_write_evtype(idx, chain_evt);
579 if (idx == ARMV8_IDX_CYCLE_COUNTER)
580 write_pmccfiltr(hwc->config_base);
582 armv8pmu_write_evtype(idx, hwc->config_base);
586 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
588 int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
589 u32 mask = BIT(counter);
591 if (armv8pmu_event_is_chained(event))
592 mask |= BIT(counter - 1);
596 static inline void armv8pmu_enable_counter(u32 mask)
599 * Make sure event configuration register writes are visible before we
600 * enable the counter.
603 write_pmcntenset(mask);
606 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
608 struct perf_event_attr *attr = &event->attr;
609 u32 mask = armv8pmu_event_cnten_mask(event);
611 kvm_set_pmu_events(mask, attr);
613 /* We rely on the hypervisor switch code to enable guest counters */
614 if (!kvm_pmu_counter_deferred(attr))
615 armv8pmu_enable_counter(mask);
618 static inline void armv8pmu_disable_counter(u32 mask)
620 write_pmcntenclr(mask);
622 * Make sure the effects of disabling the counter are visible before we
623 * start configuring the event.
628 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
630 struct perf_event_attr *attr = &event->attr;
631 u32 mask = armv8pmu_event_cnten_mask(event);
633 kvm_clr_pmu_events(mask);
635 /* We rely on the hypervisor switch code to disable guest counters */
636 if (!kvm_pmu_counter_deferred(attr))
637 armv8pmu_disable_counter(mask);
640 static inline void armv8pmu_enable_intens(u32 mask)
642 write_pmintenset(mask);
645 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
647 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
648 armv8pmu_enable_intens(BIT(counter));
651 static inline void armv8pmu_disable_intens(u32 mask)
653 write_pmintenclr(mask);
655 /* Clear the overflow flag in case an interrupt is pending. */
656 write_pmovsclr(mask);
660 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
662 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
663 armv8pmu_disable_intens(BIT(counter));
666 static inline u32 armv8pmu_getreset_flags(void)
671 value = read_pmovsclr();
673 /* Write to clear flags */
674 value &= ARMV8_PMU_OVSR_MASK;
675 write_pmovsclr(value);
680 static void update_pmuserenr(u64 val)
682 lockdep_assert_irqs_disabled();
685 * The current PMUSERENR_EL0 value might be the value for the guest.
686 * If that's the case, have KVM keep tracking of the register value
687 * for the host EL0 so that KVM can restore it before returning to
688 * the host EL0. Otherwise, update the register now.
690 if (kvm_set_pmuserenr(val))
693 write_pmuserenr(val);
696 static void armv8pmu_disable_user_access(void)
701 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
704 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
706 /* Clear any unused counters to avoid leaking their contents */
707 for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) {
708 if (i == ARMV8_IDX_CYCLE_COUNTER)
711 armv8pmu_write_evcntr(i, 0);
714 update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR);
717 static void armv8pmu_enable_event(struct perf_event *event)
720 * Enable counter and interrupt, and set the counter to count
721 * the event that we're interested in.
727 armv8pmu_disable_event_counter(event);
732 armv8pmu_write_event_type(event);
735 * Enable interrupt for this counter
737 armv8pmu_enable_event_irq(event);
742 armv8pmu_enable_event_counter(event);
745 static void armv8pmu_disable_event(struct perf_event *event)
750 armv8pmu_disable_event_counter(event);
753 * Disable interrupt for this counter
755 armv8pmu_disable_event_irq(event);
758 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
760 struct perf_event_context *ctx;
763 ctx = perf_cpu_task_ctx();
765 nr_user = ctx->nr_user;
767 if (sysctl_perf_user_access && nr_user)
768 armv8pmu_enable_user_access(cpu_pmu);
770 armv8pmu_disable_user_access();
772 /* Enable all counters */
773 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
776 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
778 /* Disable all counters */
779 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
782 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
785 struct perf_sample_data data;
786 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
787 struct pt_regs *regs;
791 * Get and reset the IRQ flags
793 pmovsr = armv8pmu_getreset_flags();
796 * Did an overflow occur?
798 if (!armv8pmu_has_overflowed(pmovsr))
802 * Handle the counter(s) overflow(s)
804 regs = get_irq_regs();
807 * Stop the PMU while processing the counter overflows
808 * to prevent skews in group events.
810 armv8pmu_stop(cpu_pmu);
811 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
812 struct perf_event *event = cpuc->events[idx];
813 struct hw_perf_event *hwc;
815 /* Ignore if we don't have an event. */
820 * We have a single interrupt for all counters. Check that
821 * each counter has overflowed before we process it.
823 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
827 armpmu_event_update(event);
828 perf_sample_data_init(&data, 0, hwc->last_period);
829 if (!armpmu_event_set_period(event))
833 * Perf event overflow will queue the processing of the event as
834 * an irq_work which will be taken care of in the handling of
837 if (perf_event_overflow(event, &data, regs))
838 cpu_pmu->disable(event);
840 armv8pmu_start(cpu_pmu);
845 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
846 struct arm_pmu *cpu_pmu)
850 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) {
851 if (!test_and_set_bit(idx, cpuc->used_mask))
857 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
858 struct arm_pmu *cpu_pmu)
863 * Chaining requires two consecutive event counters, where
864 * the lower idx must be even.
866 for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
867 if (!test_and_set_bit(idx, cpuc->used_mask)) {
868 /* Check if the preceding even counter is available */
869 if (!test_and_set_bit(idx - 1, cpuc->used_mask))
871 /* Release the Odd counter */
872 clear_bit(idx, cpuc->used_mask);
878 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
879 struct perf_event *event)
881 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
882 struct hw_perf_event *hwc = &event->hw;
883 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
885 /* Always prefer to place a cycle counter into the cycle counter. */
886 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
887 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
888 return ARMV8_IDX_CYCLE_COUNTER;
889 else if (armv8pmu_event_is_64bit(event) &&
890 armv8pmu_event_want_user_access(event) &&
891 !armv8pmu_has_long_event(cpu_pmu))
896 * Otherwise use events counters
898 if (armv8pmu_event_is_chained(event))
899 return armv8pmu_get_chain_idx(cpuc, cpu_pmu);
901 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
904 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
905 struct perf_event *event)
907 int idx = event->hw.idx;
909 clear_bit(idx, cpuc->used_mask);
910 if (armv8pmu_event_is_chained(event))
911 clear_bit(idx - 1, cpuc->used_mask);
914 static int armv8pmu_user_event_idx(struct perf_event *event)
916 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event))
920 * We remap the cycle counter index to 32 to
921 * match the offset applied to the rest of
922 * the counter indices.
924 if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
925 return ARMV8_IDX_CYCLE_COUNTER_USER;
927 return event->hw.idx;
931 * Add an event filter to a given event.
933 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
934 struct perf_event_attr *attr)
936 unsigned long config_base = 0;
938 if (attr->exclude_idle)
942 * If we're running in hyp mode, then we *are* the hypervisor.
943 * Therefore we ignore exclude_hv in this configuration, since
944 * there's no hypervisor to sample anyway. This is consistent
945 * with other architectures (x86 and Power).
947 if (is_kernel_in_hyp_mode()) {
948 if (!attr->exclude_kernel && !attr->exclude_host)
949 config_base |= ARMV8_PMU_INCLUDE_EL2;
950 if (attr->exclude_guest)
951 config_base |= ARMV8_PMU_EXCLUDE_EL1;
952 if (attr->exclude_host)
953 config_base |= ARMV8_PMU_EXCLUDE_EL0;
955 if (!attr->exclude_hv && !attr->exclude_host)
956 config_base |= ARMV8_PMU_INCLUDE_EL2;
960 * Filter out !VHE kernels and guest kernels
962 if (attr->exclude_kernel)
963 config_base |= ARMV8_PMU_EXCLUDE_EL1;
965 if (attr->exclude_user)
966 config_base |= ARMV8_PMU_EXCLUDE_EL0;
969 * Install the filter into config_base as this is used to
970 * construct the event type.
972 event->config_base = config_base;
977 static void armv8pmu_reset(void *info)
979 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
982 /* The counter and interrupt enable registers are unknown at reset. */
983 armv8pmu_disable_counter(U32_MAX);
984 armv8pmu_disable_intens(U32_MAX);
986 /* Clear the counters we flip at guest entry/exit */
987 kvm_clr_pmu_events(U32_MAX);
990 * Initialize & Reset PMNC. Request overflow interrupt for
991 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
993 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
995 /* Enable long event counter support where available */
996 if (armv8pmu_has_long_event(cpu_pmu))
997 pmcr |= ARMV8_PMU_PMCR_LP;
999 armv8pmu_pmcr_write(pmcr);
1002 static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu,
1003 struct perf_event *event)
1005 if (event->attr.type == PERF_TYPE_HARDWARE &&
1006 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) {
1008 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
1009 armpmu->pmceid_bitmap))
1010 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED;
1012 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED,
1013 armpmu->pmceid_bitmap))
1014 return ARMV8_PMUV3_PERFCTR_BR_RETIRED;
1016 return HW_OP_UNSUPPORTED;
1019 return armpmu_map_event(event, &armv8_pmuv3_perf_map,
1020 &armv8_pmuv3_perf_cache_map,
1021 ARMV8_PMU_EVTYPE_EVENT);
1024 static int __armv8_pmuv3_map_event(struct perf_event *event,
1025 const unsigned (*extra_event_map)
1026 [PERF_COUNT_HW_MAX],
1027 const unsigned (*extra_cache_map)
1028 [PERF_COUNT_HW_CACHE_MAX]
1029 [PERF_COUNT_HW_CACHE_OP_MAX]
1030 [PERF_COUNT_HW_CACHE_RESULT_MAX])
1033 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
1035 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event);
1038 * CHAIN events only work when paired with an adjacent counter, and it
1039 * never makes sense for a user to open one in isolation, as they'll be
1040 * rotated arbitrarily.
1042 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN)
1045 if (armv8pmu_event_is_64bit(event))
1046 event->hw.flags |= ARMPMU_EVT_64BIT;
1049 * User events must be allocated into a single counter, and so
1050 * must not be chained.
1052 * Most 64-bit events require long counter support, but 64-bit
1053 * CPU_CYCLES events can be placed into the dedicated cycle
1054 * counter when this is free.
1056 if (armv8pmu_event_want_user_access(event)) {
1057 if (!(event->attach_state & PERF_ATTACH_TASK))
1059 if (armv8pmu_event_is_64bit(event) &&
1060 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
1061 !armv8pmu_has_long_event(armpmu))
1064 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1067 /* Only expose micro/arch events supported by this PMU */
1068 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1069 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1073 return armpmu_map_event(event, extra_event_map, extra_cache_map,
1074 ARMV8_PMU_EVTYPE_EVENT);
1077 static int armv8_pmuv3_map_event(struct perf_event *event)
1079 return __armv8_pmuv3_map_event(event, NULL, NULL);
1082 static int armv8_a53_map_event(struct perf_event *event)
1084 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1087 static int armv8_a57_map_event(struct perf_event *event)
1089 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1092 static int armv8_a73_map_event(struct perf_event *event)
1094 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1097 static int armv8_thunder_map_event(struct perf_event *event)
1099 return __armv8_pmuv3_map_event(event, NULL,
1100 &armv8_thunder_perf_cache_map);
1103 static int armv8_vulcan_map_event(struct perf_event *event)
1105 return __armv8_pmuv3_map_event(event, NULL,
1106 &armv8_vulcan_perf_cache_map);
1109 struct armv8pmu_probe_info {
1110 struct arm_pmu *pmu;
1114 static void __armv8pmu_probe_pmu(void *info)
1116 struct armv8pmu_probe_info *probe = info;
1117 struct arm_pmu *cpu_pmu = probe->pmu;
1122 pmuver = read_pmuver();
1123 if (!pmuv3_implemented(pmuver))
1126 cpu_pmu->pmuver = pmuver;
1127 probe->present = true;
1129 /* Read the nb of CNTx counters supported from PMNC */
1130 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1131 & ARMV8_PMU_PMCR_N_MASK;
1133 /* Add the CPU cycles counter */
1134 cpu_pmu->num_events += 1;
1136 pmceid[0] = pmceid_raw[0] = read_pmceid0();
1137 pmceid[1] = pmceid_raw[1] = read_pmceid1();
1139 bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1140 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1142 pmceid[0] = pmceid_raw[0] >> 32;
1143 pmceid[1] = pmceid_raw[1] >> 32;
1145 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1146 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1148 /* store PMMIR register for sysfs */
1149 if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31)))
1150 cpu_pmu->reg_pmmir = read_pmmir();
1152 cpu_pmu->reg_pmmir = 0;
1155 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1157 struct armv8pmu_probe_info probe = {
1163 ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1164 __armv8pmu_probe_pmu,
1169 return probe.present ? 0 : -ENODEV;
1172 static void armv8pmu_disable_user_access_ipi(void *unused)
1174 armv8pmu_disable_user_access();
1177 static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write,
1178 void *buffer, size_t *lenp, loff_t *ppos)
1180 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1181 if (ret || !write || sysctl_perf_user_access)
1184 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1);
1188 static struct ctl_table armv8_pmu_sysctl_table[] = {
1190 .procname = "perf_user_access",
1191 .data = &sysctl_perf_user_access,
1192 .maxlen = sizeof(unsigned int),
1194 .proc_handler = armv8pmu_proc_user_access_handler,
1195 .extra1 = SYSCTL_ZERO,
1196 .extra2 = SYSCTL_ONE,
1201 static void armv8_pmu_register_sysctl_table(void)
1203 static u32 tbl_registered = 0;
1205 if (!cmpxchg_relaxed(&tbl_registered, 0, 1))
1206 register_sysctl("kernel", armv8_pmu_sysctl_table);
1209 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1210 int (*map_event)(struct perf_event *event),
1211 const struct attribute_group *events,
1212 const struct attribute_group *format,
1213 const struct attribute_group *caps)
1215 int ret = armv8pmu_probe_pmu(cpu_pmu);
1219 cpu_pmu->handle_irq = armv8pmu_handle_irq;
1220 cpu_pmu->enable = armv8pmu_enable_event;
1221 cpu_pmu->disable = armv8pmu_disable_event;
1222 cpu_pmu->read_counter = armv8pmu_read_counter;
1223 cpu_pmu->write_counter = armv8pmu_write_counter;
1224 cpu_pmu->get_event_idx = armv8pmu_get_event_idx;
1225 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx;
1226 cpu_pmu->start = armv8pmu_start;
1227 cpu_pmu->stop = armv8pmu_stop;
1228 cpu_pmu->reset = armv8pmu_reset;
1229 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
1231 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx;
1233 cpu_pmu->name = name;
1234 cpu_pmu->map_event = map_event;
1235 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1236 events : &armv8_pmuv3_events_attr_group;
1237 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1238 format : &armv8_pmuv3_format_attr_group;
1239 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1240 caps : &armv8_pmuv3_caps_attr_group;
1242 armv8_pmu_register_sysctl_table();
1246 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1247 int (*map_event)(struct perf_event *event))
1249 return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1252 #define PMUV3_INIT_SIMPLE(name) \
1253 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
1255 return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
1258 PMUV3_INIT_SIMPLE(armv8_pmuv3)
1260 PMUV3_INIT_SIMPLE(armv8_cortex_a34)
1261 PMUV3_INIT_SIMPLE(armv8_cortex_a55)
1262 PMUV3_INIT_SIMPLE(armv8_cortex_a65)
1263 PMUV3_INIT_SIMPLE(armv8_cortex_a75)
1264 PMUV3_INIT_SIMPLE(armv8_cortex_a76)
1265 PMUV3_INIT_SIMPLE(armv8_cortex_a77)
1266 PMUV3_INIT_SIMPLE(armv8_cortex_a78)
1267 PMUV3_INIT_SIMPLE(armv9_cortex_a510)
1268 PMUV3_INIT_SIMPLE(armv9_cortex_a710)
1269 PMUV3_INIT_SIMPLE(armv8_cortex_x1)
1270 PMUV3_INIT_SIMPLE(armv9_cortex_x2)
1271 PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
1272 PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
1273 PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
1274 PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
1276 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
1277 PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
1279 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1281 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1282 armv8_a53_map_event);
1285 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1287 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1288 armv8_a53_map_event);
1291 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1293 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1294 armv8_a57_map_event);
1297 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1299 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1300 armv8_a57_map_event);
1303 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1305 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1306 armv8_a73_map_event);
1309 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1311 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1312 armv8_thunder_map_event);
1315 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1317 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1318 armv8_vulcan_map_event);
1321 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1322 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
1323 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init},
1324 {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
1325 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
1326 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init},
1327 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
1328 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init},
1329 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
1330 {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
1331 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init},
1332 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
1333 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
1334 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
1335 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init},
1336 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init},
1337 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init},
1338 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init},
1339 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
1340 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
1341 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init},
1342 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init},
1343 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
1344 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
1345 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
1346 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init},
1350 static int armv8_pmu_device_probe(struct platform_device *pdev)
1352 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1355 static struct platform_driver armv8_pmu_driver = {
1357 .name = ARMV8_PMU_PDEV_NAME,
1358 .of_match_table = armv8_pmu_of_device_ids,
1359 .suppress_bind_attrs = true,
1361 .probe = armv8_pmu_device_probe,
1364 static int __init armv8_pmu_driver_init(void)
1367 return platform_driver_register(&armv8_pmu_driver);
1369 return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
1371 device_initcall(armv8_pmu_driver_init)
1373 void arch_perf_update_userpage(struct perf_event *event,
1374 struct perf_event_mmap_page *userpg, u64 now)
1376 struct clock_read_data *rd;
1380 userpg->cap_user_time = 0;
1381 userpg->cap_user_time_zero = 0;
1382 userpg->cap_user_time_short = 0;
1383 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event);
1385 if (userpg->cap_user_rdpmc) {
1386 if (event->hw.flags & ARMPMU_EVT_64BIT)
1387 userpg->pmc_width = 64;
1389 userpg->pmc_width = 32;
1393 rd = sched_clock_read_begin(&seq);
1395 if (rd->read_sched_clock != arch_timer_read_counter)
1398 userpg->time_mult = rd->mult;
1399 userpg->time_shift = rd->shift;
1400 userpg->time_zero = rd->epoch_ns;
1401 userpg->time_cycles = rd->epoch_cyc;
1402 userpg->time_mask = rd->sched_clock_mask;
1405 * Subtract the cycle base, such that software that
1406 * doesn't know about cap_user_time_short still 'works'
1407 * assuming no wraps.
1409 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1410 userpg->time_zero -= ns;
1412 } while (sched_clock_read_retry(seq));
1414 userpg->time_offset = userpg->time_zero - now;
1417 * time_shift is not expected to be greater than 31 due to
1418 * the original published conversion algorithm shifting a
1419 * 32-bit value (now specifies a 64-bit value) - refer
1420 * perf_event_mmap_page documentation in perf_event.h.
1422 if (userpg->time_shift == 32) {
1423 userpg->time_shift = 31;
1424 userpg->time_mult >>= 1;
1428 * Internal timekeeping for enabled/running/stopped times
1429 * is always computed with the sched_clock.
1431 userpg->cap_user_time = 1;
1432 userpg->cap_user_time_zero = 1;
1433 userpg->cap_user_time_short = 1;