drivers/perf/arm_pmuv3.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARMv8 PMUv3 Performance Events handling code.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  * Author: Will Deacon <will.deacon@arm.com>
   7  *
   8  * This code is based heavily on the ARMv7 perf event code.
   9  */
  10
  11 #include <asm/irq_regs.h>
  12 #include <asm/perf_event.h>
  13 #include <asm/virt.h>
  14
  15 #include <clocksource/arm_arch_timer.h>
  16
  17 #include <linux/acpi.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/of.h>
  20 #include <linux/perf/arm_pmu.h>
  21 #include <linux/perf/arm_pmuv3.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sched_clock.h>
  24 #include <linux/smp.h>
  25
  26 #include <asm/arm_pmuv3.h>
  27
  28 /* ARMv8 Cortex-A53 specific event types. */
  29 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
  30
  31 /* ARMv8 Cavium ThunderX specific event types. */
  32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
  33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
  34 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
  35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
  36 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
  37
  38 /*
  39  * ARMv8 Architectural defined events, not all of these may
  40  * be supported on any given implementation. Unsupported events will
  41  * be disabled at run-time based on the PMCEID registers.
  42  */
  43 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
  44         PERF_MAP_ALL_UNSUPPORTED,
  45         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
  46         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
  47         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  48         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  49         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  50         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
  51         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
  52         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
  53 };
  54
  55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  56                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  58         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  59
  60         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  61         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  62
  63         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
  64         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
  65
  66         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
  67         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
  68
  69         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
  70         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
  71
  72         [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
  73         [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
  74
  75         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
  76         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  77 };
  78
  79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  80                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  81                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  82         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  83
  84         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
  85
  86         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  87         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  88 };
  89
  90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  91                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  92                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  93         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  94
  95         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  96         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  97         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  98         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  99
 100         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 101         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 102
 103         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 104         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 105 };
 106
 107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 108                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 109                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 110         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 111
 112         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 113         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 114 };
 115
 116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 117                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 118                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 119         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 120
 121         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 122         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 123         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 124         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 125         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 126         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 127
 128         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 129         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 130
 131         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 132         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 133         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 134         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 135 };
 136
 137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 138                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 139                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 140         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 141
 142         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 143         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 144         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 145         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 146
 147         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 148         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 149         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 150         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 151
 152         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 153         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 154 };
 155
 156 static ssize_t
 157 armv8pmu_events_sysfs_show(struct device *dev,
 158                            struct device_attribute *attr, char *page)
 159 {
 160         struct perf_pmu_events_attr *pmu_attr;
 161
 162         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 163
 164         return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
 165 }
 166
 167 #define ARMV8_EVENT_ATTR(name, config)                                          \
 168         PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
 169
 170 static struct attribute *armv8_pmuv3_event_attrs[] = {
 171         ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
 172         ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
 173         ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
 174         ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
 175         ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
 176         ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
 177         ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
 178         ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
 179         ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
 180         ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
 181         ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
 182         ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
 183         ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
 184         ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
 185         ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
 186         ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
 187         ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
 188         ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
 189         ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
 190         ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
 191         ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
 192         ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
 193         ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
 194         ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
 195         ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
 196         ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
 197         ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
 198         ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
 199         ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
 200         ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
 201         /* Don't expose the chain event in /sys, since it's useless in isolation */
 202         ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
 203         ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
 204         ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
 205         ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
 206         ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
 207         ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
 208         ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
 209         ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
 210         ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
 211         ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
 212         ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
 213         ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
 214         ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
 215         ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
 216         ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
 217         ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
 218         ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
 219         ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
 220         ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
 221         ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
 222         ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
 223         ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
 224         ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
 225         ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
 226         ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
 227         ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
 228         ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
 229         ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
 230         ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
 231         ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
 232         ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
 233         ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
 234         ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
 235         ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
 236         ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
 237         ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
 238         ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
 239         ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
 240         ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
 241         ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
 242         ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
 243         ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
 244         ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
 245         ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),
 246         ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),
 247         ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),
 248         ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),
 249         ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),
 250         ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),
 251         ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),
 252         ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),
 253         ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),
 254         ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),
 255         ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
 256         ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
 257         ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
 258         ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
 259         ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
 260         ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
 261         NULL,
 262 };
 263
 264 static umode_t
 265 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 266                                struct attribute *attr, int unused)
 267 {
 268         struct device *dev = kobj_to_dev(kobj);
 269         struct pmu *pmu = dev_get_drvdata(dev);
 270         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 271         struct perf_pmu_events_attr *pmu_attr;
 272
 273         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 274
 275         if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 276             test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 277                 return attr->mode;
 278
 279         if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
 280                 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
 281
 282                 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 283                     test_bit(id, cpu_pmu->pmceid_ext_bitmap))
 284                         return attr->mode;
 285         }
 286
 287         return 0;
 288 }
 289
 290 static const struct attribute_group armv8_pmuv3_events_attr_group = {
 291         .name = "events",
 292         .attrs = armv8_pmuv3_event_attrs,
 293         .is_visible = armv8pmu_event_attr_is_visible,
 294 };
 295
 296 PMU_FORMAT_ATTR(event, "config:0-15");
 297 PMU_FORMAT_ATTR(long, "config1:0");
 298 PMU_FORMAT_ATTR(rdpmc, "config1:1");
 299
 300 static int sysctl_perf_user_access __read_mostly;
 301
 302 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
 303 {
 304         return event->attr.config1 & 0x1;
 305 }
 306
 307 static inline bool armv8pmu_event_want_user_access(struct perf_event *event)
 308 {
 309         return event->attr.config1 & 0x2;
 310 }
 311
 312 static struct attribute *armv8_pmuv3_format_attrs[] = {
 313         &format_attr_event.attr,
 314         &format_attr_long.attr,
 315         &format_attr_rdpmc.attr,
 316         NULL,
 317 };
 318
 319 static const struct attribute_group armv8_pmuv3_format_attr_group = {
 320         .name = "format",
 321         .attrs = armv8_pmuv3_format_attrs,
 322 };
 323
 324 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
 325                           char *page)
 326 {
 327         struct pmu *pmu = dev_get_drvdata(dev);
 328         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 329         u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
 330
 331         return sysfs_emit(page, "0x%08x\n", slots);
 332 }
 333
 334 static DEVICE_ATTR_RO(slots);
 335
 336 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
 337                               char *page)
 338 {
 339         struct pmu *pmu = dev_get_drvdata(dev);
 340         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 341         u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
 342                         & ARMV8_PMU_BUS_SLOTS_MASK;
 343
 344         return sysfs_emit(page, "0x%08x\n", bus_slots);
 345 }
 346
 347 static DEVICE_ATTR_RO(bus_slots);
 348
 349 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
 350                               char *page)
 351 {
 352         struct pmu *pmu = dev_get_drvdata(dev);
 353         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 354         u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
 355                         & ARMV8_PMU_BUS_WIDTH_MASK;
 356         u32 val = 0;
 357
 358         /* Encoded as Log2(number of bytes), plus one */
 359         if (bus_width > 2 && bus_width < 13)
 360                 val = 1 << (bus_width - 1);
 361
 362         return sysfs_emit(page, "0x%08x\n", val);
 363 }
 364
 365 static DEVICE_ATTR_RO(bus_width);
 366
 367 static struct attribute *armv8_pmuv3_caps_attrs[] = {
 368         &dev_attr_slots.attr,
 369         &dev_attr_bus_slots.attr,
 370         &dev_attr_bus_width.attr,
 371         NULL,
 372 };
 373
 374 static const struct attribute_group armv8_pmuv3_caps_attr_group = {
 375         .name = "caps",
 376         .attrs = armv8_pmuv3_caps_attrs,
 377 };
 378
 379 /*
 380  * Perf Events' indices
 381  */
 382 #define ARMV8_IDX_CYCLE_COUNTER 0
 383 #define ARMV8_IDX_COUNTER0      1
 384 #define ARMV8_IDX_CYCLE_COUNTER_USER    32
 385
 386 /*
 387  * We unconditionally enable ARMv8.5-PMU long event counter support
 388  * (64-bit events) where supported. Indicate if this arm_pmu has long
 389  * event counter support.
 390  *
 391  * On AArch32, long counters make no sense (you can't access the top
 392  * bits), so we only enable this on AArch64.
 393  */
 394 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
 395 {
 396         return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver));
 397 }
 398
 399 static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
 400 {
 401         return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
 402 }
 403
 404 /*
 405  * We must chain two programmable counters for 64 bit events,
 406  * except when we have allocated the 64bit cycle counter (for CPU
 407  * cycles event) or when user space counter access is enabled.
 408  */
 409 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
 410 {
 411         int idx = event->hw.idx;
 412         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 413
 414         return !armv8pmu_event_has_user_read(event) &&
 415                armv8pmu_event_is_64bit(event) &&
 416                !armv8pmu_has_long_event(cpu_pmu) &&
 417                (idx != ARMV8_IDX_CYCLE_COUNTER);
 418 }
 419
 420 /*
 421  * ARMv8 low level PMU access
 422  */
 423
 424 /*
 425  * Perf Event to low level counters mapping
 426  */
 427 #define ARMV8_IDX_TO_COUNTER(x) \
 428         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 429
 430 static inline u32 armv8pmu_pmcr_read(void)
 431 {
 432         return read_pmcr();
 433 }
 434
 435 static inline void armv8pmu_pmcr_write(u32 val)
 436 {
 437         val &= ARMV8_PMU_PMCR_MASK;
 438         isb();
 439         write_pmcr(val);
 440 }
 441
 442 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 443 {
 444         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 445 }
 446
 447 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 448 {
 449         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 450 }
 451
 452 static inline u64 armv8pmu_read_evcntr(int idx)
 453 {
 454         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 455
 456         return read_pmevcntrn(counter);
 457 }
 458
 459 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
 460 {
 461         int idx = event->hw.idx;
 462         u64 val = armv8pmu_read_evcntr(idx);
 463
 464         if (armv8pmu_event_is_chained(event))
 465                 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
 466         return val;
 467 }
 468
 469 /*
 470  * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
 471  * is set the event counters also become 64-bit counters. Unless the
 472  * user has requested a long counter (attr.config1) then we want to
 473  * interrupt upon 32-bit overflow - we achieve this by applying a bias.
 474  */
 475 static bool armv8pmu_event_needs_bias(struct perf_event *event)
 476 {
 477         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 478         struct hw_perf_event *hwc = &event->hw;
 479         int idx = hwc->idx;
 480
 481         if (armv8pmu_event_is_64bit(event))
 482                 return false;
 483
 484         if (armv8pmu_has_long_event(cpu_pmu) ||
 485             idx == ARMV8_IDX_CYCLE_COUNTER)
 486                 return true;
 487
 488         return false;
 489 }
 490
 491 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
 492 {
 493         if (armv8pmu_event_needs_bias(event))
 494                 value |= GENMASK_ULL(63, 32);
 495
 496         return value;
 497 }
 498
 499 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
 500 {
 501         if (armv8pmu_event_needs_bias(event))
 502                 value &= ~GENMASK_ULL(63, 32);
 503
 504         return value;
 505 }
 506
 507 static u64 armv8pmu_read_counter(struct perf_event *event)
 508 {
 509         struct hw_perf_event *hwc = &event->hw;
 510         int idx = hwc->idx;
 511         u64 value;
 512
 513         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 514                 value = read_pmccntr();
 515         else
 516                 value = armv8pmu_read_hw_counter(event);
 517
 518         return  armv8pmu_unbias_long_counter(event, value);
 519 }
 520
 521 static inline void armv8pmu_write_evcntr(int idx, u64 value)
 522 {
 523         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 524
 525         write_pmevcntrn(counter, value);
 526 }
 527
 528 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
 529                                              u64 value)
 530 {
 531         int idx = event->hw.idx;
 532
 533         if (armv8pmu_event_is_chained(event)) {
 534                 armv8pmu_write_evcntr(idx, upper_32_bits(value));
 535                 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
 536         } else {
 537                 armv8pmu_write_evcntr(idx, value);
 538         }
 539 }
 540
 541 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
 542 {
 543         struct hw_perf_event *hwc = &event->hw;
 544         int idx = hwc->idx;
 545
 546         value = armv8pmu_bias_long_counter(event, value);
 547
 548         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 549                 write_pmccntr(value);
 550         else
 551                 armv8pmu_write_hw_counter(event, value);
 552 }
 553
 554 static inline void armv8pmu_write_evtype(int idx, u32 val)
 555 {
 556         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 557
 558         val &= ARMV8_PMU_EVTYPE_MASK;
 559         write_pmevtypern(counter, val);
 560 }
 561
 562 static inline void armv8pmu_write_event_type(struct perf_event *event)
 563 {
 564         struct hw_perf_event *hwc = &event->hw;
 565         int idx = hwc->idx;
 566
 567         /*
 568          * For chained events, the low counter is programmed to count
 569          * the event of interest and the high counter is programmed
 570          * with CHAIN event code with filters set to count at all ELs.
 571          */
 572         if (armv8pmu_event_is_chained(event)) {
 573                 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
 574                                 ARMV8_PMU_INCLUDE_EL2;
 575
 576                 armv8pmu_write_evtype(idx - 1, hwc->config_base);
 577                 armv8pmu_write_evtype(idx, chain_evt);
 578         } else {
 579                 if (idx == ARMV8_IDX_CYCLE_COUNTER)
 580                         write_pmccfiltr(hwc->config_base);
 581                 else
 582                         armv8pmu_write_evtype(idx, hwc->config_base);
 583         }
 584 }
 585
 586 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
 587 {
 588         int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 589         u32 mask = BIT(counter);
 590
 591         if (armv8pmu_event_is_chained(event))
 592                 mask |= BIT(counter - 1);
 593         return mask;
 594 }
 595
 596 static inline void armv8pmu_enable_counter(u32 mask)
 597 {
 598         /*
 599          * Make sure event configuration register writes are visible before we
 600          * enable the counter.
 601          * */
 602         isb();
 603         write_pmcntenset(mask);
 604 }
 605
 606 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
 607 {
 608         struct perf_event_attr *attr = &event->attr;
 609         u32 mask = armv8pmu_event_cnten_mask(event);
 610
 611         kvm_set_pmu_events(mask, attr);
 612
 613         /* We rely on the hypervisor switch code to enable guest counters */
 614         if (!kvm_pmu_counter_deferred(attr))
 615                 armv8pmu_enable_counter(mask);
 616 }
 617
 618 static inline void armv8pmu_disable_counter(u32 mask)
 619 {
 620         write_pmcntenclr(mask);
 621         /*
 622          * Make sure the effects of disabling the counter are visible before we
 623          * start configuring the event.
 624          */
 625         isb();
 626 }
 627
 628 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
 629 {
 630         struct perf_event_attr *attr = &event->attr;
 631         u32 mask = armv8pmu_event_cnten_mask(event);
 632
 633         kvm_clr_pmu_events(mask);
 634
 635         /* We rely on the hypervisor switch code to disable guest counters */
 636         if (!kvm_pmu_counter_deferred(attr))
 637                 armv8pmu_disable_counter(mask);
 638 }
 639
 640 static inline void armv8pmu_enable_intens(u32 mask)
 641 {
 642         write_pmintenset(mask);
 643 }
 644
 645 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
 646 {
 647         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 648         armv8pmu_enable_intens(BIT(counter));
 649 }
 650
 651 static inline void armv8pmu_disable_intens(u32 mask)
 652 {
 653         write_pmintenclr(mask);
 654         isb();
 655         /* Clear the overflow flag in case an interrupt is pending. */
 656         write_pmovsclr(mask);
 657         isb();
 658 }
 659
 660 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
 661 {
 662         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 663         armv8pmu_disable_intens(BIT(counter));
 664 }
 665
 666 static inline u32 armv8pmu_getreset_flags(void)
 667 {
 668         u32 value;
 669
 670         /* Read */
 671         value = read_pmovsclr();
 672
 673         /* Write to clear flags */
 674         value &= ARMV8_PMU_OVSR_MASK;
 675         write_pmovsclr(value);
 676
 677         return value;
 678 }
 679
 680 static void update_pmuserenr(u64 val)
 681 {
 682         lockdep_assert_irqs_disabled();
 683
 684         /*
 685          * The current PMUSERENR_EL0 value might be the value for the guest.
 686          * If that's the case, have KVM keep tracking of the register value
 687          * for the host EL0 so that KVM can restore it before returning to
 688          * the host EL0. Otherwise, update the register now.
 689          */
 690         if (kvm_set_pmuserenr(val))
 691                 return;
 692
 693         write_pmuserenr(val);
 694 }
 695
 696 static void armv8pmu_disable_user_access(void)
 697 {
 698         update_pmuserenr(0);
 699 }
 700
 701 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
 702 {
 703         int i;
 704         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 705
 706         /* Clear any unused counters to avoid leaking their contents */
 707         for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) {
 708                 if (i == ARMV8_IDX_CYCLE_COUNTER)
 709                         write_pmccntr(0);
 710                 else
 711                         armv8pmu_write_evcntr(i, 0);
 712         }
 713
 714         update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR);
 715 }
 716
 717 static void armv8pmu_enable_event(struct perf_event *event)
 718 {
 719         /*
 720          * Enable counter and interrupt, and set the counter to count
 721          * the event that we're interested in.
 722          */
 723
 724         /*
 725          * Disable counter
 726          */
 727         armv8pmu_disable_event_counter(event);
 728
 729         /*
 730          * Set event.
 731          */
 732         armv8pmu_write_event_type(event);
 733
 734         /*
 735          * Enable interrupt for this counter
 736          */
 737         armv8pmu_enable_event_irq(event);
 738
 739         /*
 740          * Enable counter
 741          */
 742         armv8pmu_enable_event_counter(event);
 743 }
 744
 745 static void armv8pmu_disable_event(struct perf_event *event)
 746 {
 747         /*
 748          * Disable counter
 749          */
 750         armv8pmu_disable_event_counter(event);
 751
 752         /*
 753          * Disable interrupt for this counter
 754          */
 755         armv8pmu_disable_event_irq(event);
 756 }
 757
 758 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 759 {
 760         struct perf_event_context *ctx;
 761         int nr_user = 0;
 762
 763         ctx = perf_cpu_task_ctx();
 764         if (ctx)
 765                 nr_user = ctx->nr_user;
 766
 767         if (sysctl_perf_user_access && nr_user)
 768                 armv8pmu_enable_user_access(cpu_pmu);
 769         else
 770                 armv8pmu_disable_user_access();
 771
 772         /* Enable all counters */
 773         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 774 }
 775
 776 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 777 {
 778         /* Disable all counters */
 779         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 780 }
 781
 782 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
 783 {
 784         u32 pmovsr;
 785         struct perf_sample_data data;
 786         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 787         struct pt_regs *regs;
 788         int idx;
 789
 790         /*
 791          * Get and reset the IRQ flags
 792          */
 793         pmovsr = armv8pmu_getreset_flags();
 794
 795         /*
 796          * Did an overflow occur?
 797          */
 798         if (!armv8pmu_has_overflowed(pmovsr))
 799                 return IRQ_NONE;
 800
 801         /*
 802          * Handle the counter(s) overflow(s)
 803          */
 804         regs = get_irq_regs();
 805
 806         /*
 807          * Stop the PMU while processing the counter overflows
 808          * to prevent skews in group events.
 809          */
 810         armv8pmu_stop(cpu_pmu);
 811         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 812                 struct perf_event *event = cpuc->events[idx];
 813                 struct hw_perf_event *hwc;
 814
 815                 /* Ignore if we don't have an event. */
 816                 if (!event)
 817                         continue;
 818
 819                 /*
 820                  * We have a single interrupt for all counters. Check that
 821                  * each counter has overflowed before we process it.
 822                  */
 823                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 824                         continue;
 825
 826                 hwc = &event->hw;
 827                 armpmu_event_update(event);
 828                 perf_sample_data_init(&data, 0, hwc->last_period);
 829                 if (!armpmu_event_set_period(event))
 830                         continue;
 831
 832                 /*
 833                  * Perf event overflow will queue the processing of the event as
 834                  * an irq_work which will be taken care of in the handling of
 835                  * IPI_IRQ_WORK.
 836                  */
 837                 if (perf_event_overflow(event, &data, regs))
 838                         cpu_pmu->disable(event);
 839         }
 840         armv8pmu_start(cpu_pmu);
 841
 842         return IRQ_HANDLED;
 843 }
 844
 845 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
 846                                     struct arm_pmu *cpu_pmu)
 847 {
 848         int idx;
 849
 850         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) {
 851                 if (!test_and_set_bit(idx, cpuc->used_mask))
 852                         return idx;
 853         }
 854         return -EAGAIN;
 855 }
 856
 857 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
 858                                    struct arm_pmu *cpu_pmu)
 859 {
 860         int idx;
 861
 862         /*
 863          * Chaining requires two consecutive event counters, where
 864          * the lower idx must be even.
 865          */
 866         for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
 867                 if (!test_and_set_bit(idx, cpuc->used_mask)) {
 868                         /* Check if the preceding even counter is available */
 869                         if (!test_and_set_bit(idx - 1, cpuc->used_mask))
 870                                 return idx;
 871                         /* Release the Odd counter */
 872                         clear_bit(idx, cpuc->used_mask);
 873                 }
 874         }
 875         return -EAGAIN;
 876 }
 877
 878 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 879                                   struct perf_event *event)
 880 {
 881         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 882         struct hw_perf_event *hwc = &event->hw;
 883         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 884
 885         /* Always prefer to place a cycle counter into the cycle counter. */
 886         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 887                 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 888                         return ARMV8_IDX_CYCLE_COUNTER;
 889                 else if (armv8pmu_event_is_64bit(event) &&
 890                            armv8pmu_event_want_user_access(event) &&
 891                            !armv8pmu_has_long_event(cpu_pmu))
 892                                 return -EAGAIN;
 893         }
 894
 895         /*
 896          * Otherwise use events counters
 897          */
 898         if (armv8pmu_event_is_chained(event))
 899                 return  armv8pmu_get_chain_idx(cpuc, cpu_pmu);
 900         else
 901                 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
 902 }
 903
 904 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
 905                                      struct perf_event *event)
 906 {
 907         int idx = event->hw.idx;
 908
 909         clear_bit(idx, cpuc->used_mask);
 910         if (armv8pmu_event_is_chained(event))
 911                 clear_bit(idx - 1, cpuc->used_mask);
 912 }
 913
 914 static int armv8pmu_user_event_idx(struct perf_event *event)
 915 {
 916         if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event))
 917                 return 0;
 918
 919         /*
 920          * We remap the cycle counter index to 32 to
 921          * match the offset applied to the rest of
 922          * the counter indices.
 923          */
 924         if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
 925                 return ARMV8_IDX_CYCLE_COUNTER_USER;
 926
 927         return event->hw.idx;
 928 }
 929
 930 /*
 931  * Add an event filter to a given event.
 932  */
 933 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 934                                      struct perf_event_attr *attr)
 935 {
 936         unsigned long config_base = 0;
 937
 938         if (attr->exclude_idle)
 939                 return -EPERM;
 940
 941         /*
 942          * If we're running in hyp mode, then we *are* the hypervisor.
 943          * Therefore we ignore exclude_hv in this configuration, since
 944          * there's no hypervisor to sample anyway. This is consistent
 945          * with other architectures (x86 and Power).
 946          */
 947         if (is_kernel_in_hyp_mode()) {
 948                 if (!attr->exclude_kernel && !attr->exclude_host)
 949                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 950                 if (attr->exclude_guest)
 951                         config_base |= ARMV8_PMU_EXCLUDE_EL1;
 952                 if (attr->exclude_host)
 953                         config_base |= ARMV8_PMU_EXCLUDE_EL0;
 954         } else {
 955                 if (!attr->exclude_hv && !attr->exclude_host)
 956                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 957         }
 958
 959         /*
 960          * Filter out !VHE kernels and guest kernels
 961          */
 962         if (attr->exclude_kernel)
 963                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 964
 965         if (attr->exclude_user)
 966                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 967
 968         /*
 969          * Install the filter into config_base as this is used to
 970          * construct the event type.
 971          */
 972         event->config_base = config_base;
 973
 974         return 0;
 975 }
 976
 977 static void armv8pmu_reset(void *info)
 978 {
 979         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 980         u32 pmcr;
 981
 982         /* The counter and interrupt enable registers are unknown at reset. */
 983         armv8pmu_disable_counter(U32_MAX);
 984         armv8pmu_disable_intens(U32_MAX);
 985
 986         /* Clear the counters we flip at guest entry/exit */
 987         kvm_clr_pmu_events(U32_MAX);
 988
 989         /*
 990          * Initialize & Reset PMNC. Request overflow interrupt for
 991          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 992          */
 993         pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
 994
 995         /* Enable long event counter support where available */
 996         if (armv8pmu_has_long_event(cpu_pmu))
 997                 pmcr |= ARMV8_PMU_PMCR_LP;
 998
 999         armv8pmu_pmcr_write(pmcr);
1000 }
1001
1002 static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu,
1003                                       struct perf_event *event)
1004 {
1005         if (event->attr.type == PERF_TYPE_HARDWARE &&
1006             event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) {
1007
1008                 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
1009                              armpmu->pmceid_bitmap))
1010                         return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED;
1011
1012                 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED,
1013                              armpmu->pmceid_bitmap))
1014                         return ARMV8_PMUV3_PERFCTR_BR_RETIRED;
1015
1016                 return HW_OP_UNSUPPORTED;
1017         }
1018
1019         return armpmu_map_event(event, &armv8_pmuv3_perf_map,
1020                                 &armv8_pmuv3_perf_cache_map,
1021                                 ARMV8_PMU_EVTYPE_EVENT);
1022 }
1023
1024 static int __armv8_pmuv3_map_event(struct perf_event *event,
1025                                    const unsigned (*extra_event_map)
1026                                                   [PERF_COUNT_HW_MAX],
1027                                    const unsigned (*extra_cache_map)
1028                                                   [PERF_COUNT_HW_CACHE_MAX]
1029                                                   [PERF_COUNT_HW_CACHE_OP_MAX]
1030                                                   [PERF_COUNT_HW_CACHE_RESULT_MAX])
1031 {
1032         int hw_event_id;
1033         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
1034
1035         hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event);
1036
1037         /*
1038          * CHAIN events only work when paired with an adjacent counter, and it
1039          * never makes sense for a user to open one in isolation, as they'll be
1040          * rotated arbitrarily.
1041          */
1042         if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN)
1043                 return -EINVAL;
1044
1045         if (armv8pmu_event_is_64bit(event))
1046                 event->hw.flags |= ARMPMU_EVT_64BIT;
1047
1048         /*
1049          * User events must be allocated into a single counter, and so
1050          * must not be chained.
1051          *
1052          * Most 64-bit events require long counter support, but 64-bit
1053          * CPU_CYCLES events can be placed into the dedicated cycle
1054          * counter when this is free.
1055          */
1056         if (armv8pmu_event_want_user_access(event)) {
1057                 if (!(event->attach_state & PERF_ATTACH_TASK))
1058                         return -EINVAL;
1059                 if (armv8pmu_event_is_64bit(event) &&
1060                     (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
1061                     !armv8pmu_has_long_event(armpmu))
1062                         return -EOPNOTSUPP;
1063
1064                 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1065         }
1066
1067         /* Only expose micro/arch events supported by this PMU */
1068         if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1069             && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1070                 return hw_event_id;
1071         }
1072
1073         return armpmu_map_event(event, extra_event_map, extra_cache_map,
1074                                 ARMV8_PMU_EVTYPE_EVENT);
1075 }
1076
1077 static int armv8_pmuv3_map_event(struct perf_event *event)
1078 {
1079         return __armv8_pmuv3_map_event(event, NULL, NULL);
1080 }
1081
1082 static int armv8_a53_map_event(struct perf_event *event)
1083 {
1084         return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1085 }
1086
1087 static int armv8_a57_map_event(struct perf_event *event)
1088 {
1089         return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1090 }
1091
1092 static int armv8_a73_map_event(struct perf_event *event)
1093 {
1094         return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1095 }
1096
1097 static int armv8_thunder_map_event(struct perf_event *event)
1098 {
1099         return __armv8_pmuv3_map_event(event, NULL,
1100                                        &armv8_thunder_perf_cache_map);
1101 }
1102
1103 static int armv8_vulcan_map_event(struct perf_event *event)
1104 {
1105         return __armv8_pmuv3_map_event(event, NULL,
1106                                        &armv8_vulcan_perf_cache_map);
1107 }
1108
1109 struct armv8pmu_probe_info {
1110         struct arm_pmu *pmu;
1111         bool present;
1112 };
1113
1114 static void __armv8pmu_probe_pmu(void *info)
1115 {
1116         struct armv8pmu_probe_info *probe = info;
1117         struct arm_pmu *cpu_pmu = probe->pmu;
1118         u64 pmceid_raw[2];
1119         u32 pmceid[2];
1120         int pmuver;
1121
1122         pmuver = read_pmuver();
1123         if (!pmuv3_implemented(pmuver))
1124                 return;
1125
1126         cpu_pmu->pmuver = pmuver;
1127         probe->present = true;
1128
1129         /* Read the nb of CNTx counters supported from PMNC */
1130         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1131                 & ARMV8_PMU_PMCR_N_MASK;
1132
1133         /* Add the CPU cycles counter */
1134         cpu_pmu->num_events += 1;
1135
1136         pmceid[0] = pmceid_raw[0] = read_pmceid0();
1137         pmceid[1] = pmceid_raw[1] = read_pmceid1();
1138
1139         bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1140                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1141
1142         pmceid[0] = pmceid_raw[0] >> 32;
1143         pmceid[1] = pmceid_raw[1] >> 32;
1144
1145         bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1146                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1147
1148         /* store PMMIR register for sysfs */
1149         if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31)))
1150                 cpu_pmu->reg_pmmir = read_pmmir();
1151         else
1152                 cpu_pmu->reg_pmmir = 0;
1153 }
1154
1155 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1156 {
1157         struct armv8pmu_probe_info probe = {
1158                 .pmu = cpu_pmu,
1159                 .present = false,
1160         };
1161         int ret;
1162
1163         ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1164                                     __armv8pmu_probe_pmu,
1165                                     &probe, 1);
1166         if (ret)
1167                 return ret;
1168
1169         return probe.present ? 0 : -ENODEV;
1170 }
1171
1172 static void armv8pmu_disable_user_access_ipi(void *unused)
1173 {
1174         armv8pmu_disable_user_access();
1175 }
1176
1177 static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write,
1178                 void *buffer, size_t *lenp, loff_t *ppos)
1179 {
1180         int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1181         if (ret || !write || sysctl_perf_user_access)
1182                 return ret;
1183
1184         on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1);
1185         return 0;
1186 }
1187
1188 static struct ctl_table armv8_pmu_sysctl_table[] = {
1189         {
1190                 .procname       = "perf_user_access",
1191                 .data           = &sysctl_perf_user_access,
1192                 .maxlen         = sizeof(unsigned int),
1193                 .mode           = 0644,
1194                 .proc_handler   = armv8pmu_proc_user_access_handler,
1195                 .extra1         = SYSCTL_ZERO,
1196                 .extra2         = SYSCTL_ONE,
1197         },
1198         { }
1199 };
1200
1201 static void armv8_pmu_register_sysctl_table(void)
1202 {
1203         static u32 tbl_registered = 0;
1204
1205         if (!cmpxchg_relaxed(&tbl_registered, 0, 1))
1206                 register_sysctl("kernel", armv8_pmu_sysctl_table);
1207 }
1208
1209 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1210                           int (*map_event)(struct perf_event *event),
1211                           const struct attribute_group *events,
1212                           const struct attribute_group *format,
1213                           const struct attribute_group *caps)
1214 {
1215         int ret = armv8pmu_probe_pmu(cpu_pmu);
1216         if (ret)
1217                 return ret;
1218
1219         cpu_pmu->handle_irq             = armv8pmu_handle_irq;
1220         cpu_pmu->enable                 = armv8pmu_enable_event;
1221         cpu_pmu->disable                = armv8pmu_disable_event;
1222         cpu_pmu->read_counter           = armv8pmu_read_counter;
1223         cpu_pmu->write_counter          = armv8pmu_write_counter;
1224         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx;
1225         cpu_pmu->clear_event_idx        = armv8pmu_clear_event_idx;
1226         cpu_pmu->start                  = armv8pmu_start;
1227         cpu_pmu->stop                   = armv8pmu_stop;
1228         cpu_pmu->reset                  = armv8pmu_reset;
1229         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1230
1231         cpu_pmu->pmu.event_idx          = armv8pmu_user_event_idx;
1232
1233         cpu_pmu->name                   = name;
1234         cpu_pmu->map_event              = map_event;
1235         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1236                         events : &armv8_pmuv3_events_attr_group;
1237         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1238                         format : &armv8_pmuv3_format_attr_group;
1239         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1240                         caps : &armv8_pmuv3_caps_attr_group;
1241
1242         armv8_pmu_register_sysctl_table();
1243         return 0;
1244 }
1245
1246 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1247                                    int (*map_event)(struct perf_event *event))
1248 {
1249         return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1250 }
1251
1252 #define PMUV3_INIT_SIMPLE(name)                                         \
1253 static int name##_pmu_init(struct arm_pmu *cpu_pmu)                     \
1254 {                                                                       \
1255         return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
1256 }
1257
1258 PMUV3_INIT_SIMPLE(armv8_pmuv3)
1259
1260 PMUV3_INIT_SIMPLE(armv8_cortex_a34)
1261 PMUV3_INIT_SIMPLE(armv8_cortex_a55)
1262 PMUV3_INIT_SIMPLE(armv8_cortex_a65)
1263 PMUV3_INIT_SIMPLE(armv8_cortex_a75)
1264 PMUV3_INIT_SIMPLE(armv8_cortex_a76)
1265 PMUV3_INIT_SIMPLE(armv8_cortex_a77)
1266 PMUV3_INIT_SIMPLE(armv8_cortex_a78)
1267 PMUV3_INIT_SIMPLE(armv9_cortex_a510)
1268 PMUV3_INIT_SIMPLE(armv9_cortex_a710)
1269 PMUV3_INIT_SIMPLE(armv8_cortex_x1)
1270 PMUV3_INIT_SIMPLE(armv9_cortex_x2)
1271 PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
1272 PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
1273 PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
1274 PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
1275
1276 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
1277 PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
1278
1279 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1280 {
1281         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1282                                        armv8_a53_map_event);
1283 }
1284
1285 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1286 {
1287         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1288                                        armv8_a53_map_event);
1289 }
1290
1291 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1292 {
1293         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1294                                        armv8_a57_map_event);
1295 }
1296
1297 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1298 {
1299         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1300                                        armv8_a57_map_event);
1301 }
1302
1303 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1304 {
1305         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1306                                        armv8_a73_map_event);
1307 }
1308
1309 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1310 {
1311         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1312                                        armv8_thunder_map_event);
1313 }
1314
1315 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1316 {
1317         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1318                                        armv8_vulcan_map_event);
1319 }
1320
1321 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1322         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_pmu_init},
1323         {.compatible = "arm,cortex-a34-pmu",    .data = armv8_cortex_a34_pmu_init},
1324         {.compatible = "arm,cortex-a35-pmu",    .data = armv8_a35_pmu_init},
1325         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1326         {.compatible = "arm,cortex-a55-pmu",    .data = armv8_cortex_a55_pmu_init},
1327         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1328         {.compatible = "arm,cortex-a65-pmu",    .data = armv8_cortex_a65_pmu_init},
1329         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1330         {.compatible = "arm,cortex-a73-pmu",    .data = armv8_a73_pmu_init},
1331         {.compatible = "arm,cortex-a75-pmu",    .data = armv8_cortex_a75_pmu_init},
1332         {.compatible = "arm,cortex-a76-pmu",    .data = armv8_cortex_a76_pmu_init},
1333         {.compatible = "arm,cortex-a77-pmu",    .data = armv8_cortex_a77_pmu_init},
1334         {.compatible = "arm,cortex-a78-pmu",    .data = armv8_cortex_a78_pmu_init},
1335         {.compatible = "arm,cortex-a510-pmu",   .data = armv9_cortex_a510_pmu_init},
1336         {.compatible = "arm,cortex-a710-pmu",   .data = armv9_cortex_a710_pmu_init},
1337         {.compatible = "arm,cortex-x1-pmu",     .data = armv8_cortex_x1_pmu_init},
1338         {.compatible = "arm,cortex-x2-pmu",     .data = armv9_cortex_x2_pmu_init},
1339         {.compatible = "arm,neoverse-e1-pmu",   .data = armv8_neoverse_e1_pmu_init},
1340         {.compatible = "arm,neoverse-n1-pmu",   .data = armv8_neoverse_n1_pmu_init},
1341         {.compatible = "arm,neoverse-n2-pmu",   .data = armv9_neoverse_n2_pmu_init},
1342         {.compatible = "arm,neoverse-v1-pmu",   .data = armv8_neoverse_v1_pmu_init},
1343         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1344         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1345         {.compatible = "nvidia,carmel-pmu",     .data = armv8_nvidia_carmel_pmu_init},
1346         {.compatible = "nvidia,denver-pmu",     .data = armv8_nvidia_denver_pmu_init},
1347         {},
1348 };
1349
1350 static int armv8_pmu_device_probe(struct platform_device *pdev)
1351 {
1352         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1353 }
1354
1355 static struct platform_driver armv8_pmu_driver = {
1356         .driver         = {
1357                 .name   = ARMV8_PMU_PDEV_NAME,
1358                 .of_match_table = armv8_pmu_of_device_ids,
1359                 .suppress_bind_attrs = true,
1360         },
1361         .probe          = armv8_pmu_device_probe,
1362 };
1363
1364 static int __init armv8_pmu_driver_init(void)
1365 {
1366         if (acpi_disabled)
1367                 return platform_driver_register(&armv8_pmu_driver);
1368         else
1369                 return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
1370 }
1371 device_initcall(armv8_pmu_driver_init)
1372
1373 void arch_perf_update_userpage(struct perf_event *event,
1374                                struct perf_event_mmap_page *userpg, u64 now)
1375 {
1376         struct clock_read_data *rd;
1377         unsigned int seq;
1378         u64 ns;
1379
1380         userpg->cap_user_time = 0;
1381         userpg->cap_user_time_zero = 0;
1382         userpg->cap_user_time_short = 0;
1383         userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event);
1384
1385         if (userpg->cap_user_rdpmc) {
1386                 if (event->hw.flags & ARMPMU_EVT_64BIT)
1387                         userpg->pmc_width = 64;
1388                 else
1389                         userpg->pmc_width = 32;
1390         }
1391
1392         do {
1393                 rd = sched_clock_read_begin(&seq);
1394
1395                 if (rd->read_sched_clock != arch_timer_read_counter)
1396                         return;
1397
1398                 userpg->time_mult = rd->mult;
1399                 userpg->time_shift = rd->shift;
1400                 userpg->time_zero = rd->epoch_ns;
1401                 userpg->time_cycles = rd->epoch_cyc;
1402                 userpg->time_mask = rd->sched_clock_mask;
1403
1404                 /*
1405                  * Subtract the cycle base, such that software that
1406                  * doesn't know about cap_user_time_short still 'works'
1407                  * assuming no wraps.
1408                  */
1409                 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1410                 userpg->time_zero -= ns;
1411
1412         } while (sched_clock_read_retry(seq));
1413
1414         userpg->time_offset = userpg->time_zero - now;
1415
1416         /*
1417          * time_shift is not expected to be greater than 31 due to
1418          * the original published conversion algorithm shifting a
1419          * 32-bit value (now specifies a 64-bit value) - refer
1420          * perf_event_mmap_page documentation in perf_event.h.
1421          */
1422         if (userpg->time_shift == 32) {
1423                 userpg->time_shift = 31;
1424                 userpg->time_mult >>= 1;
1425         }
1426
1427         /*
1428          * Internal timekeeping for enabled/running/stopped times
1429          * is always computed with the sched_clock.
1430          */
1431         userpg->cap_user_time = 1;
1432         userpg->cap_user_time_zero = 1;
1433         userpg->cap_user_time_short = 1;
1434 }