1 // SPDX-License-Identifier: GPL-2.0
3 * Support routines for initializing a PCI subsystem
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/cache.h>
22 #include <linux/slab.h>
25 static void pci_std_update_resource(struct pci_dev *dev, int resno)
27 struct pci_bus_region region;
32 struct resource *res = dev->resource + resno;
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
39 * Ignore resources for unimplemented BARs and unused resource slots
45 if (res->flags & IORESOURCE_UNSET)
49 * Ignore non-moveable resources. This might be legacy resources for
50 * which no functional BAR register exists or another important
51 * system resource we shouldn't move around.
53 if (res->flags & IORESOURCE_PCI_FIXED)
56 pcibios_resource_to_bus(dev->bus, ®ion, res);
59 if (res->flags & IORESOURCE_IO) {
60 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
61 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
62 } else if (resno == PCI_ROM_RESOURCE) {
63 mask = PCI_ROM_ADDRESS_MASK;
65 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
66 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
69 if (resno < PCI_ROM_RESOURCE) {
70 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
71 } else if (resno == PCI_ROM_RESOURCE) {
74 * Apparently some Matrox devices have ROM BARs that read
75 * as zero when disabled, so don't update ROM BARs unless
76 * they're enabled. See https://lkml.org/lkml/2005/8/30/138.
78 if (!(res->flags & IORESOURCE_ROM_ENABLE))
81 reg = dev->rom_base_reg;
82 new |= PCI_ROM_ADDRESS_ENABLE;
87 * We can't update a 64-bit BAR atomically, so when possible,
88 * disable decoding so that a half-updated BAR won't conflict
89 * with another device.
91 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
93 pci_read_config_word(dev, PCI_COMMAND, &cmd);
94 pci_write_config_word(dev, PCI_COMMAND,
95 cmd & ~PCI_COMMAND_MEMORY);
98 pci_write_config_dword(dev, reg, new);
99 pci_read_config_dword(dev, reg, &check);
101 if ((new ^ check) & mask) {
102 pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
106 if (res->flags & IORESOURCE_MEM_64) {
107 new = region.start >> 16 >> 16;
108 pci_write_config_dword(dev, reg + 4, new);
109 pci_read_config_dword(dev, reg + 4, &check);
111 pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
117 pci_write_config_word(dev, PCI_COMMAND, cmd);
120 void pci_update_resource(struct pci_dev *dev, int resno)
122 if (resno <= PCI_ROM_RESOURCE)
123 pci_std_update_resource(dev, resno);
124 #ifdef CONFIG_PCI_IOV
125 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
126 pci_iov_update_resource(dev, resno);
130 int pci_claim_resource(struct pci_dev *dev, int resource)
132 struct resource *res = &dev->resource[resource];
133 struct resource *root, *conflict;
135 if (res->flags & IORESOURCE_UNSET) {
136 pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
142 * If we have a shadow copy in RAM, the PCI device doesn't respond
143 * to the shadow range, so we don't need to claim it, and upstream
144 * bridges don't need to route the range to the device.
146 if (res->flags & IORESOURCE_ROM_SHADOW)
149 root = pci_find_parent_resource(dev, res);
151 pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
153 res->flags |= IORESOURCE_UNSET;
157 conflict = request_resource_conflict(root, res);
159 pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
160 resource, res, conflict->name, conflict);
161 res->flags |= IORESOURCE_UNSET;
167 EXPORT_SYMBOL(pci_claim_resource);
169 void pci_disable_bridge_window(struct pci_dev *dev)
171 /* MMIO Base/Limit */
172 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
174 /* Prefetchable MMIO Base/Limit */
175 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
176 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
177 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
181 * Generic function that returns a value indicating that the device's
182 * original BIOS BAR address was not saved and so is not available for
185 * Can be over-ridden by architecture specific code that implements
186 * reinstatement functionality rather than leaving it disabled when
187 * normal allocation attempts fail.
189 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
194 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
195 int resno, resource_size_t size)
197 struct resource *root, *conflict;
198 resource_size_t fw_addr, start, end;
200 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
206 res->start = fw_addr;
207 res->end = res->start + size - 1;
208 res->flags &= ~IORESOURCE_UNSET;
210 root = pci_find_parent_resource(dev, res);
212 if (res->flags & IORESOURCE_IO)
213 root = &ioport_resource;
215 root = &iomem_resource;
218 pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
220 conflict = request_resource_conflict(root, res);
222 pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
223 resno, res, conflict->name, conflict);
226 res->flags |= IORESOURCE_UNSET;
233 * We don't have to worry about legacy ISA devices, so nothing to do here.
234 * This is marked as __weak because multiple architectures define it; it should
235 * eventually go away.
237 resource_size_t __weak pcibios_align_resource(void *data,
238 const struct resource *res,
239 resource_size_t size,
240 resource_size_t align)
245 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
246 int resno, resource_size_t size, resource_size_t align)
248 struct resource *res = dev->resource + resno;
252 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
255 * First, try exact prefetching match. Even if a 64-bit
256 * prefetchable bridge window is below 4GB, we can't put a 32-bit
257 * prefetchable resource in it because pbus_size_mem() assumes a
258 * 64-bit window will contain no 32-bit resources. If we assign
259 * things differently than they were sized, not everything will fit.
261 ret = pci_bus_alloc_resource(bus, res, size, align, min,
262 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
263 pcibios_align_resource, dev);
268 * If the prefetchable window is only 32 bits wide, we can put
269 * 64-bit prefetchable resources in it.
271 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
272 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
273 ret = pci_bus_alloc_resource(bus, res, size, align, min,
275 pcibios_align_resource, dev);
281 * If we didn't find a better match, we can put any memory resource
282 * in a non-prefetchable window. If this resource is 32 bits and
283 * non-prefetchable, the first call already tried the only possibility
284 * so we don't need to try again.
286 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
287 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
288 pcibios_align_resource, dev);
293 static int _pci_assign_resource(struct pci_dev *dev, int resno,
294 resource_size_t size, resource_size_t min_align)
300 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
301 if (!bus->parent || !bus->self->transparent)
309 int pci_assign_resource(struct pci_dev *dev, int resno)
311 struct resource *res = dev->resource + resno;
312 resource_size_t align, size;
315 if (res->flags & IORESOURCE_PCI_FIXED)
318 res->flags |= IORESOURCE_UNSET;
319 align = pci_resource_alignment(dev, res);
321 pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
326 size = resource_size(res);
327 ret = _pci_assign_resource(dev, resno, size, align);
330 * If we failed to assign anything, let's try the address
331 * where firmware left it. That at least has a chance of
332 * working, which is better than just leaving it disabled.
335 pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
336 ret = pci_revert_fw_address(res, dev, resno, size);
340 pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
344 res->flags &= ~IORESOURCE_UNSET;
345 res->flags &= ~IORESOURCE_STARTALIGN;
346 pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
347 if (resno < PCI_BRIDGE_RESOURCES)
348 pci_update_resource(dev, resno);
352 EXPORT_SYMBOL(pci_assign_resource);
354 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
355 resource_size_t min_align)
357 struct resource *res = dev->resource + resno;
359 resource_size_t new_size;
362 if (res->flags & IORESOURCE_PCI_FIXED)
366 res->flags |= IORESOURCE_UNSET;
368 pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
373 /* already aligned with min_align */
374 new_size = resource_size(res) + addsize;
375 ret = _pci_assign_resource(dev, resno, new_size, min_align);
378 pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
379 resno, res, (unsigned long long) addsize);
383 res->flags &= ~IORESOURCE_UNSET;
384 res->flags &= ~IORESOURCE_STARTALIGN;
385 pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
386 resno, res, (unsigned long long) addsize);
387 if (resno < PCI_BRIDGE_RESOURCES)
388 pci_update_resource(dev, resno);
393 void pci_release_resource(struct pci_dev *dev, int resno)
395 struct resource *res = dev->resource + resno;
397 pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
402 release_resource(res);
403 res->end = resource_size(res) - 1;
405 res->flags |= IORESOURCE_UNSET;
407 EXPORT_SYMBOL(pci_release_resource);
409 int pci_resize_resource(struct pci_dev *dev, int resno, int size)
411 struct resource *res = dev->resource + resno;
416 /* Make sure the resource isn't assigned before resizing it. */
417 if (!(res->flags & IORESOURCE_UNSET))
420 pci_read_config_word(dev, PCI_COMMAND, &cmd);
421 if (cmd & PCI_COMMAND_MEMORY)
424 sizes = pci_rebar_get_possible_sizes(dev, resno);
428 if (!(sizes & BIT(size)))
431 old = pci_rebar_get_current_size(dev, resno);
435 ret = pci_rebar_set_size(dev, resno, size);
439 res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
441 /* Check if the new config works by trying to assign everything. */
442 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
449 pci_rebar_set_size(dev, resno, old);
450 res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
453 EXPORT_SYMBOL(pci_resize_resource);
455 int pci_enable_resources(struct pci_dev *dev, int mask)
461 pci_read_config_word(dev, PCI_COMMAND, &cmd);
464 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
465 if (!(mask & (1 << i)))
468 r = &dev->resource[i];
470 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
472 if ((i == PCI_ROM_RESOURCE) &&
473 (!(r->flags & IORESOURCE_ROM_ENABLE)))
476 if (r->flags & IORESOURCE_UNSET) {
477 pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
483 pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
488 if (r->flags & IORESOURCE_IO)
489 cmd |= PCI_COMMAND_IO;
490 if (r->flags & IORESOURCE_MEM)
491 cmd |= PCI_COMMAND_MEMORY;
494 if (cmd != old_cmd) {
495 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
496 pci_write_config_word(dev, PCI_COMMAND, cmd);