2 * Synopsys DesignWare PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irqdomain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci_regs.h>
18 #include <linux/platform_device.h>
20 #include "pcie-designware.h"
22 static struct pci_ops dw_pcie_ops;
24 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
29 if (pp->ops->rd_own_conf)
30 return pp->ops->rd_own_conf(pp, where, size, val);
32 pci = to_dw_pcie_from_pp(pp);
33 return dw_pcie_read(pci->dbi_base + where, size, val);
36 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
41 if (pp->ops->wr_own_conf)
42 return pp->ops->wr_own_conf(pp, where, size, val);
44 pci = to_dw_pcie_from_pp(pp);
45 return dw_pcie_write(pci->dbi_base + where, size, val);
48 static struct irq_chip dw_msi_irq_chip = {
50 .irq_enable = pci_msi_unmask_irq,
51 .irq_disable = pci_msi_mask_irq,
52 .irq_mask = pci_msi_mask_irq,
53 .irq_unmask = pci_msi_unmask_irq,
57 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
61 irqreturn_t ret = IRQ_NONE;
63 for (i = 0; i < MAX_MSI_CTRLS; i++) {
64 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
71 while ((pos = find_next_bit((unsigned long *) &val, 32,
73 irq = irq_find_mapping(pp->irq_domain, i * 32 + pos);
74 generic_handle_irq(irq);
75 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12,
84 void dw_pcie_msi_init(struct pcie_port *pp)
88 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
89 msi_target = virt_to_phys((void *)pp->msi_data);
91 /* program the msi_data */
92 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
93 (u32)(msi_target & 0xffffffff));
94 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
95 (u32)(msi_target >> 32 & 0xffffffff));
98 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
100 unsigned int res, bit, val;
102 res = (irq / 32) * 12;
104 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
106 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
109 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
110 unsigned int nvec, unsigned int pos)
114 for (i = 0; i < nvec; i++) {
115 irq_set_msi_desc_off(irq_base, i, NULL);
116 /* Disable corresponding interrupt on MSI controller */
117 if (pp->ops->msi_clear_irq)
118 pp->ops->msi_clear_irq(pp, pos + i);
120 dw_pcie_msi_clear_irq(pp, pos + i);
123 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
126 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
128 unsigned int res, bit, val;
130 res = (irq / 32) * 12;
132 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
134 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
137 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
140 struct pcie_port *pp;
142 pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
143 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
144 order_base_2(no_irqs));
148 irq = irq_find_mapping(pp->irq_domain, pos0);
153 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
154 * descs so there is no need to allocate descs here. We can therefore
155 * assume that if irq_find_mapping above returns non-zero, then the
156 * descs are also successfully allocated.
159 for (i = 0; i < no_irqs; i++) {
160 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
161 clear_irq_range(pp, irq, i, pos0);
164 /*Enable corresponding interrupt in MSI interrupt controller */
165 if (pp->ops->msi_set_irq)
166 pp->ops->msi_set_irq(pp, pos0 + i);
168 dw_pcie_msi_set_irq(pp, pos0 + i);
172 desc->nvec_used = no_irqs;
173 desc->msi_attrib.multiple = order_base_2(no_irqs);
182 static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
187 if (pp->ops->get_msi_addr)
188 msi_target = pp->ops->get_msi_addr(pp);
190 msi_target = virt_to_phys((void *)pp->msi_data);
192 msg.address_lo = (u32)(msi_target & 0xffffffff);
193 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
195 if (pp->ops->get_msi_data)
196 msg.data = pp->ops->get_msi_data(pp, pos);
200 pci_write_msi_msg(irq, &msg);
203 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
204 struct msi_desc *desc)
207 struct pcie_port *pp = pdev->bus->sysdata;
209 if (desc->msi_attrib.is_msix)
212 irq = assign_irq(1, desc, &pos);
216 dw_msi_setup_msg(pp, irq, pos);
221 static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
224 #ifdef CONFIG_PCI_MSI
226 struct msi_desc *desc;
227 struct pcie_port *pp = pdev->bus->sysdata;
229 /* MSI-X interrupts are not supported */
230 if (type == PCI_CAP_ID_MSIX)
233 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
234 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
236 irq = assign_irq(nvec, desc, &pos);
240 dw_msi_setup_msg(pp, irq, pos);
248 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
250 struct irq_data *data = irq_get_irq_data(irq);
251 struct msi_desc *msi = irq_data_get_msi_desc(data);
252 struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
254 clear_irq_range(pp, irq, 1, data->hwirq);
257 static struct msi_controller dw_pcie_msi_chip = {
258 .setup_irq = dw_msi_setup_irq,
259 .setup_irqs = dw_msi_setup_irqs,
260 .teardown_irq = dw_msi_teardown_irq,
263 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
264 irq_hw_number_t hwirq)
266 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
267 irq_set_chip_data(irq, domain->host_data);
272 static const struct irq_domain_ops msi_domain_ops = {
273 .map = dw_pcie_msi_map,
276 int dw_pcie_host_init(struct pcie_port *pp)
278 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
279 struct device *dev = pci->dev;
280 struct device_node *np = dev->of_node;
281 struct platform_device *pdev = to_platform_device(dev);
282 struct pci_bus *bus, *child;
283 struct pci_host_bridge *bridge;
284 struct resource *cfg_res;
286 struct resource_entry *win, *tmp;
288 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
290 pp->cfg0_size = resource_size(cfg_res) / 2;
291 pp->cfg1_size = resource_size(cfg_res) / 2;
292 pp->cfg0_base = cfg_res->start;
293 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
294 } else if (!pp->va_cfg0_base) {
295 dev_err(dev, "missing *config* reg space\n");
298 bridge = pci_alloc_host_bridge(0);
302 ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
303 &bridge->windows, &pp->io_base);
307 ret = devm_request_pci_bus_resources(dev, &bridge->windows);
311 /* Get the I/O and memory ranges from DT */
312 resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
313 switch (resource_type(win->res)) {
315 ret = pci_remap_iospace(win->res, pp->io_base);
317 dev_warn(dev, "error %d: failed to map resource %pR\n",
319 resource_list_destroy_entry(win);
322 pp->io->name = "I/O";
323 pp->io_size = resource_size(pp->io);
324 pp->io_bus_addr = pp->io->start - win->offset;
329 pp->mem->name = "MEM";
330 pp->mem_size = resource_size(pp->mem);
331 pp->mem_bus_addr = pp->mem->start - win->offset;
335 pp->cfg0_size = resource_size(pp->cfg) / 2;
336 pp->cfg1_size = resource_size(pp->cfg) / 2;
337 pp->cfg0_base = pp->cfg->start;
338 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
346 if (!pci->dbi_base) {
347 pci->dbi_base = devm_pci_remap_cfgspace(dev,
349 resource_size(pp->cfg));
350 if (!pci->dbi_base) {
351 dev_err(dev, "error with ioremap\n");
357 pp->mem_base = pp->mem->start;
359 if (!pp->va_cfg0_base) {
360 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
361 pp->cfg0_base, pp->cfg0_size);
362 if (!pp->va_cfg0_base) {
363 dev_err(dev, "error with ioremap in function\n");
369 if (!pp->va_cfg1_base) {
370 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
373 if (!pp->va_cfg1_base) {
374 dev_err(dev, "error with ioremap\n");
380 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
382 pci->num_viewport = 2;
384 if (IS_ENABLED(CONFIG_PCI_MSI)) {
385 if (!pp->ops->msi_host_init) {
386 pp->irq_domain = irq_domain_add_linear(dev->of_node,
387 MAX_MSI_IRQS, &msi_domain_ops,
389 if (!pp->irq_domain) {
390 dev_err(dev, "irq domain init failed\n");
395 for (i = 0; i < MAX_MSI_IRQS; i++)
396 irq_create_mapping(pp->irq_domain, i);
398 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
404 if (pp->ops->host_init) {
405 ret = pp->ops->host_init(pp);
410 pp->root_bus_nr = pp->busn->start;
412 bridge->dev.parent = dev;
413 bridge->sysdata = pp;
414 bridge->busnr = pp->root_bus_nr;
415 bridge->ops = &dw_pcie_ops;
416 bridge->map_irq = of_irq_parse_and_map_pci;
417 bridge->swizzle_irq = pci_common_swizzle;
418 if (IS_ENABLED(CONFIG_PCI_MSI)) {
419 bridge->msi = &dw_pcie_msi_chip;
420 dw_pcie_msi_chip.dev = dev;
423 ret = pci_scan_root_bus_bridge(bridge);
429 if (pp->ops->scan_bus)
430 pp->ops->scan_bus(pp);
432 pci_bus_size_bridges(bus);
433 pci_bus_assign_resources(bus);
435 list_for_each_entry(child, &bus->children, node)
436 pcie_bus_configure_settings(child);
438 pci_bus_add_devices(bus);
442 pci_free_host_bridge(bridge);
446 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
447 u32 devfn, int where, int size, u32 *val)
450 u32 busdev, cfg_size;
452 void __iomem *va_cfg_base;
453 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
455 if (pp->ops->rd_other_conf)
456 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
458 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
459 PCIE_ATU_FUNC(PCI_FUNC(devfn));
461 if (bus->parent->number == pp->root_bus_nr) {
462 type = PCIE_ATU_TYPE_CFG0;
463 cpu_addr = pp->cfg0_base;
464 cfg_size = pp->cfg0_size;
465 va_cfg_base = pp->va_cfg0_base;
467 type = PCIE_ATU_TYPE_CFG1;
468 cpu_addr = pp->cfg1_base;
469 cfg_size = pp->cfg1_size;
470 va_cfg_base = pp->va_cfg1_base;
473 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
476 ret = dw_pcie_read(va_cfg_base + where, size, val);
477 if (pci->num_viewport <= 2)
478 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
479 PCIE_ATU_TYPE_IO, pp->io_base,
480 pp->io_bus_addr, pp->io_size);
485 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
486 u32 devfn, int where, int size, u32 val)
489 u32 busdev, cfg_size;
491 void __iomem *va_cfg_base;
492 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
494 if (pp->ops->wr_other_conf)
495 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
497 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
498 PCIE_ATU_FUNC(PCI_FUNC(devfn));
500 if (bus->parent->number == pp->root_bus_nr) {
501 type = PCIE_ATU_TYPE_CFG0;
502 cpu_addr = pp->cfg0_base;
503 cfg_size = pp->cfg0_size;
504 va_cfg_base = pp->va_cfg0_base;
506 type = PCIE_ATU_TYPE_CFG1;
507 cpu_addr = pp->cfg1_base;
508 cfg_size = pp->cfg1_size;
509 va_cfg_base = pp->va_cfg1_base;
512 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
515 ret = dw_pcie_write(va_cfg_base + where, size, val);
516 if (pci->num_viewport <= 2)
517 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
518 PCIE_ATU_TYPE_IO, pp->io_base,
519 pp->io_bus_addr, pp->io_size);
524 static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
527 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
529 /* If there is no link, then there is no device */
530 if (bus->number != pp->root_bus_nr) {
531 if (!dw_pcie_link_up(pci))
535 /* access only one slot on each root port */
536 if (bus->number == pp->root_bus_nr && dev > 0)
542 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
545 struct pcie_port *pp = bus->sysdata;
547 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
549 return PCIBIOS_DEVICE_NOT_FOUND;
552 if (bus->number == pp->root_bus_nr)
553 return dw_pcie_rd_own_conf(pp, where, size, val);
555 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
558 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
559 int where, int size, u32 val)
561 struct pcie_port *pp = bus->sysdata;
563 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
564 return PCIBIOS_DEVICE_NOT_FOUND;
566 if (bus->number == pp->root_bus_nr)
567 return dw_pcie_wr_own_conf(pp, where, size, val);
569 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
572 static struct pci_ops dw_pcie_ops = {
573 .read = dw_pcie_rd_conf,
574 .write = dw_pcie_wr_conf,
577 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
581 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
582 if (val == 0xffffffff)
588 void dw_pcie_setup_rc(struct pcie_port *pp)
591 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
596 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
597 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
599 /* setup interrupt pins */
600 dw_pcie_dbi_ro_wr_en(pci);
601 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
604 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
605 dw_pcie_dbi_ro_wr_dis(pci);
607 /* setup bus numbers */
608 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
611 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
613 /* setup command register */
614 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
616 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
617 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
618 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
621 * If the platform provides ->rd_other_conf, it means the platform
622 * uses its own address translation component rather than ATU, so
623 * we should not program the ATU here.
625 if (!pp->ops->rd_other_conf) {
626 /* get iATU unroll support */
627 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
628 dev_dbg(pci->dev, "iATU unroll: %s\n",
629 pci->iatu_unroll_enabled ? "enabled" : "disabled");
631 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
632 PCIE_ATU_TYPE_MEM, pp->mem_base,
633 pp->mem_bus_addr, pp->mem_size);
634 if (pci->num_viewport > 2)
635 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
636 PCIE_ATU_TYPE_IO, pp->io_base,
637 pp->io_bus_addr, pp->io_size);
640 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
642 /* Enable write permission for the DBI read-only register */
643 dw_pcie_dbi_ro_wr_en(pci);
644 /* program correct class for RC */
645 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
646 /* Better disable write permission right after the update */
647 dw_pcie_dbi_ro_wr_dis(pci);
649 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
650 val |= PORT_LOGIC_SPEED_CHANGE;
651 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);