2 * Synopsys DesignWare PCIe Endpoint controller driver
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "pcie-designware.h"
23 #include <linux/pci-epc.h>
24 #include <linux/pci-epf.h>
26 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
28 struct pci_epc *epc = ep->epc;
33 static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
37 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
38 dw_pcie_writel_dbi2(pci, reg, 0x0);
39 dw_pcie_writel_dbi(pci, reg, 0x0);
42 static int dw_pcie_ep_write_header(struct pci_epc *epc,
43 struct pci_epf_header *hdr)
45 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
46 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
48 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
49 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
50 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
51 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
52 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
53 hdr->subclass_code | hdr->baseclass_code << 8);
54 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
55 hdr->cache_line_size);
56 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
57 hdr->subsys_vendor_id);
58 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
59 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
65 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
67 enum dw_pcie_as_type as_type)
71 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
73 free_win = find_first_zero_bit(&ep->ib_window_map,
74 sizeof(ep->ib_window_map));
75 if (free_win >= ep->num_ib_windows) {
76 dev_err(pci->dev, "no free inbound window\n");
80 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
83 dev_err(pci->dev, "Failed to program IB window\n");
87 ep->bar_to_atu[bar] = free_win;
88 set_bit(free_win, &ep->ib_window_map);
93 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
94 u64 pci_addr, size_t size)
97 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
99 free_win = find_first_zero_bit(&ep->ob_window_map,
100 sizeof(ep->ob_window_map));
101 if (free_win >= ep->num_ob_windows) {
102 dev_err(pci->dev, "no free outbound window\n");
106 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
107 phys_addr, pci_addr, size);
109 set_bit(free_win, &ep->ob_window_map);
110 ep->outbound_addr[free_win] = phys_addr;
115 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
117 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
118 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
119 u32 atu_index = ep->bar_to_atu[bar];
121 dw_pcie_ep_reset_bar(pci, bar);
123 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
124 clear_bit(atu_index, &ep->ib_window_map);
127 static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
128 dma_addr_t bar_phys, size_t size, int flags)
131 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
132 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
133 enum dw_pcie_as_type as_type;
134 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
136 if (!(flags & PCI_BASE_ADDRESS_SPACE))
137 as_type = DW_PCIE_AS_MEM;
139 as_type = DW_PCIE_AS_IO;
141 ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
145 dw_pcie_writel_dbi2(pci, reg, size - 1);
146 dw_pcie_writel_dbi(pci, reg, flags);
151 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
156 for (index = 0; index < ep->num_ob_windows; index++) {
157 if (ep->outbound_addr[index] != addr)
166 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
170 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
171 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
173 ret = dw_pcie_find_index(ep, addr, &atu_index);
177 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
178 clear_bit(atu_index, &ep->ob_window_map);
181 static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
182 u64 pci_addr, size_t size)
185 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
186 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
188 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
190 dev_err(pci->dev, "failed to enable address\n");
197 static int dw_pcie_ep_get_msi(struct pci_epc *epc)
202 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
203 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
205 val = dw_pcie_readb_dbi(pci, MSI_MESSAGE_CONTROL);
206 val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
208 lower_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
209 upper_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
211 if (!(lower_addr || upper_addr))
217 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
220 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
221 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
223 val = (encode_int << MSI_CAP_MMC_SHIFT);
224 dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
229 static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
230 enum pci_epc_irq_type type, u8 interrupt_num)
232 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
234 if (!ep->ops->raise_irq)
237 return ep->ops->raise_irq(ep, type, interrupt_num);
240 static void dw_pcie_ep_stop(struct pci_epc *epc)
242 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
243 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
245 if (!pci->ops->stop_link)
248 pci->ops->stop_link(pci);
251 static int dw_pcie_ep_start(struct pci_epc *epc)
253 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
254 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
256 if (!pci->ops->start_link)
259 return pci->ops->start_link(pci);
262 static const struct pci_epc_ops epc_ops = {
263 .write_header = dw_pcie_ep_write_header,
264 .set_bar = dw_pcie_ep_set_bar,
265 .clear_bar = dw_pcie_ep_clear_bar,
266 .map_addr = dw_pcie_ep_map_addr,
267 .unmap_addr = dw_pcie_ep_unmap_addr,
268 .set_msi = dw_pcie_ep_set_msi,
269 .get_msi = dw_pcie_ep_get_msi,
270 .raise_irq = dw_pcie_ep_raise_irq,
271 .start = dw_pcie_ep_start,
272 .stop = dw_pcie_ep_stop,
275 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
277 struct pci_epc *epc = ep->epc;
279 pci_epc_mem_exit(epc);
282 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
287 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
288 struct device *dev = pci->dev;
289 struct device_node *np = dev->of_node;
291 if (!pci->dbi_base || !pci->dbi_base2) {
292 dev_err(dev, "dbi_base/deb_base2 is not populated\n");
296 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
298 dev_err(dev, "unable to read *num-ib-windows* property\n");
302 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
304 dev_err(dev, "unable to read *num-ob-windows* property\n");
308 addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
312 ep->outbound_addr = addr;
314 if (ep->ops->ep_init)
315 ep->ops->ep_init(ep);
317 epc = devm_pci_epc_create(dev, &epc_ops);
319 dev_err(dev, "failed to create epc device\n");
323 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
325 epc->max_functions = 1;
327 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
330 dev_err(dev, "Failed to initialize address space\n");
335 epc_set_drvdata(epc, ep);