2 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/pci.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/resource.h>
28 #include <linux/types.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
32 #include "pcie-designware.h"
34 /* PCIe controller wrapper DRA7XX configuration registers */
36 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
37 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
38 #define ERR_SYS BIT(0)
39 #define ERR_FATAL BIT(1)
40 #define ERR_NONFATAL BIT(2)
41 #define ERR_COR BIT(3)
42 #define ERR_AXI BIT(4)
43 #define ERR_ECRC BIT(5)
44 #define PME_TURN_OFF BIT(8)
45 #define PME_TO_ACK BIT(9)
46 #define PM_PME BIT(10)
47 #define LINK_REQ_RST BIT(11)
48 #define LINK_UP_EVT BIT(12)
49 #define CFG_BME_EVT BIT(13)
50 #define CFG_MSE_EVT BIT(14)
51 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
52 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
53 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
55 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
56 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
62 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
64 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
65 #define DEVICE_TYPE_EP 0x0
66 #define DEVICE_TYPE_LEG_EP 0x1
67 #define DEVICE_TYPE_RC 0x4
69 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
72 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
73 #define LINK_UP BIT(16)
74 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
76 #define EXP_CAP_ID_OFFSET 0x70
78 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
79 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
81 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
82 #define MSI_REQ_GRANT BIT(0)
83 #define MSI_VECTOR_SHIFT 7
87 void __iomem *base; /* DT ti_conf */
88 int phy_count; /* DT phy-names count */
91 struct irq_domain *irq_domain;
92 enum dw_pcie_device_mode mode;
95 struct dra7xx_pcie_of_data {
96 enum dw_pcie_device_mode mode;
99 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
101 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
103 return readl(pcie->base + offset);
106 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
109 writel(value, pcie->base + offset);
112 static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr)
114 return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
117 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
119 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
120 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
122 return !!(reg & LINK_UP);
125 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
127 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
130 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
132 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
135 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
137 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
138 struct device *dev = pci->dev;
140 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
142 if (dw_pcie_link_up(pci)) {
143 dev_err(dev, "link is already up\n");
147 if (dra7xx->link_gen == 1) {
148 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
150 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
151 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
152 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
153 dw_pcie_write(pci->dbi_base + exp_cap_off +
154 PCI_EXP_LNKCAP, 4, reg);
157 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
159 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
160 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
161 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
162 dw_pcie_write(pci->dbi_base + exp_cap_off +
163 PCI_EXP_LNKCTL2, 2, reg);
167 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
169 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
174 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
176 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
177 LEG_EP_INTERRUPTS | MSI);
179 dra7xx_pcie_writel(dra7xx,
180 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
181 MSI | LEG_EP_INTERRUPTS);
184 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
186 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
188 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
192 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
194 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
195 dra7xx_pcie_enable_msi_interrupts(dra7xx);
198 static int dra7xx_pcie_host_init(struct pcie_port *pp)
200 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
201 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
203 dw_pcie_setup_rc(pp);
205 dra7xx_pcie_establish_link(pci);
206 dw_pcie_wait_for_link(pci);
207 dw_pcie_msi_init(pp);
208 dra7xx_pcie_enable_interrupts(dra7xx);
213 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
214 .host_init = dra7xx_pcie_host_init,
217 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
218 irq_hw_number_t hwirq)
220 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
221 irq_set_chip_data(irq, domain->host_data);
226 static const struct irq_domain_ops intx_domain_ops = {
227 .map = dra7xx_pcie_intx_map,
230 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
232 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
233 struct device *dev = pci->dev;
234 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
235 struct device_node *node = dev->of_node;
236 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
238 if (!pcie_intc_node) {
239 dev_err(dev, "No PCIe Intc node found\n");
243 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
244 &intx_domain_ops, pp);
245 if (!dra7xx->irq_domain) {
246 dev_err(dev, "Failed to get a INTx IRQ domain\n");
253 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
255 struct dra7xx_pcie *dra7xx = arg;
256 struct dw_pcie *pci = dra7xx->pci;
257 struct pcie_port *pp = &pci->pp;
260 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
264 dw_handle_msi_irq(pp);
270 generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
275 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
280 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
282 struct dra7xx_pcie *dra7xx = arg;
283 struct dw_pcie *pci = dra7xx->pci;
284 struct device *dev = pci->dev;
285 struct dw_pcie_ep *ep = &pci->ep;
288 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
291 dev_dbg(dev, "System Error\n");
294 dev_dbg(dev, "Fatal Error\n");
296 if (reg & ERR_NONFATAL)
297 dev_dbg(dev, "Non Fatal Error\n");
300 dev_dbg(dev, "Correctable Error\n");
303 dev_dbg(dev, "AXI tag lookup fatal Error\n");
306 dev_dbg(dev, "ECRC Error\n");
308 if (reg & PME_TURN_OFF)
310 "Power Management Event Turn-Off message received\n");
312 if (reg & PME_TO_ACK)
314 "Power Management Turn-Off Ack message received\n");
317 dev_dbg(dev, "PM Power Management Event message received\n");
319 if (reg & LINK_REQ_RST)
320 dev_dbg(dev, "Link Request Reset\n");
322 if (reg & LINK_UP_EVT) {
323 if (dra7xx->mode == DW_PCIE_EP_TYPE)
324 dw_pcie_ep_linkup(ep);
325 dev_dbg(dev, "Link-up state change\n");
328 if (reg & CFG_BME_EVT)
329 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
331 if (reg & CFG_MSE_EVT)
332 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
334 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
339 static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
343 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
344 dw_pcie_writel_dbi2(pci, reg, 0x0);
345 dw_pcie_writel_dbi(pci, reg, 0x0);
348 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
350 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
354 for (bar = BAR_0; bar <= BAR_5; bar++)
355 dw_pcie_ep_reset_bar(pci, bar);
357 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
360 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
362 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
364 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
367 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
372 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
373 reg |= MSI_REQ_GRANT;
374 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
377 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
378 enum pci_epc_irq_type type, u8 interrupt_num)
380 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
381 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
384 case PCI_EPC_IRQ_LEGACY:
385 dra7xx_pcie_raise_legacy_irq(dra7xx);
387 case PCI_EPC_IRQ_MSI:
388 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
391 dev_err(pci->dev, "UNKNOWN IRQ type\n");
397 static struct dw_pcie_ep_ops pcie_ep_ops = {
398 .ep_init = dra7xx_pcie_ep_init,
399 .raise_irq = dra7xx_pcie_raise_irq,
402 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
403 struct platform_device *pdev)
406 struct dw_pcie_ep *ep;
407 struct resource *res;
408 struct device *dev = &pdev->dev;
409 struct dw_pcie *pci = dra7xx->pci;
412 ep->ops = &pcie_ep_ops;
414 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
415 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
419 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
420 pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
424 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
428 ep->phys_base = res->start;
429 ep->addr_size = resource_size(res);
431 ret = dw_pcie_ep_init(ep);
433 dev_err(dev, "failed to initialize endpoint\n");
440 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
441 struct platform_device *pdev)
444 struct dw_pcie *pci = dra7xx->pci;
445 struct pcie_port *pp = &pci->pp;
446 struct device *dev = pci->dev;
447 struct resource *res;
449 pp->irq = platform_get_irq(pdev, 1);
451 dev_err(dev, "missing IRQ resource\n");
455 ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
456 IRQF_SHARED | IRQF_NO_THREAD,
457 "dra7-pcie-msi", dra7xx);
459 dev_err(dev, "failed to request irq\n");
463 ret = dra7xx_pcie_init_irq_domain(pp);
467 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
468 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
472 ret = dw_pcie_host_init(pp);
474 dev_err(dev, "failed to initialize host\n");
481 static const struct dw_pcie_ops dw_pcie_ops = {
482 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
483 .start_link = dra7xx_pcie_establish_link,
484 .stop_link = dra7xx_pcie_stop_link,
485 .link_up = dra7xx_pcie_link_up,
488 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
490 int phy_count = dra7xx->phy_count;
492 while (phy_count--) {
493 phy_power_off(dra7xx->phy[phy_count]);
494 phy_exit(dra7xx->phy[phy_count]);
498 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
500 int phy_count = dra7xx->phy_count;
504 for (i = 0; i < phy_count; i++) {
505 ret = phy_init(dra7xx->phy[i]);
509 ret = phy_power_on(dra7xx->phy[i]);
511 phy_exit(dra7xx->phy[i]);
520 phy_power_off(dra7xx->phy[i]);
521 phy_exit(dra7xx->phy[i]);
527 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
528 .mode = DW_PCIE_RC_TYPE,
531 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
532 .mode = DW_PCIE_EP_TYPE,
535 static const struct of_device_id of_dra7xx_pcie_match[] = {
537 .compatible = "ti,dra7-pcie",
538 .data = &dra7xx_pcie_rc_of_data,
541 .compatible = "ti,dra7-pcie-ep",
542 .data = &dra7xx_pcie_ep_of_data,
548 * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
549 * @dra7xx: the dra7xx device where the workaround should be applied
551 * Access to the PCIe slave port that are not 32-bit aligned will result
552 * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
553 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
556 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
558 static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
561 struct device_node *np = dev->of_node;
562 struct of_phandle_args args;
563 struct regmap *regmap;
565 regmap = syscon_regmap_lookup_by_phandle(np,
566 "ti,syscon-unaligned-access");
567 if (IS_ERR(regmap)) {
568 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
572 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
575 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
579 ret = regmap_update_bits(regmap, args.args[0], args.args[1],
582 dev_err(dev, "failed to enable unaligned access\n");
584 of_node_put(args.np);
589 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
598 struct resource *res;
600 struct pcie_port *pp;
601 struct dra7xx_pcie *dra7xx;
602 struct device *dev = &pdev->dev;
603 struct device_node *np = dev->of_node;
605 struct gpio_desc *reset;
606 const struct of_device_id *match;
607 const struct dra7xx_pcie_of_data *data;
608 enum dw_pcie_device_mode mode;
610 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
614 data = (struct dra7xx_pcie_of_data *)match->data;
615 mode = (enum dw_pcie_device_mode)data->mode;
617 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
621 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
626 pci->ops = &dw_pcie_ops;
629 pp->ops = &dra7xx_pcie_host_ops;
631 irq = platform_get_irq(pdev, 0);
633 dev_err(dev, "missing IRQ resource: %d\n", irq);
637 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
638 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
642 phy_count = of_property_count_strings(np, "phy-names");
644 dev_err(dev, "unable to find the strings\n");
648 phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
652 for (i = 0; i < phy_count; i++) {
653 snprintf(name, sizeof(name), "pcie-phy%d", i);
654 phy[i] = devm_phy_get(dev, name);
656 return PTR_ERR(phy[i]);
662 dra7xx->phy_count = phy_count;
664 ret = dra7xx_pcie_enable_phy(dra7xx);
666 dev_err(dev, "failed to enable phy\n");
670 platform_set_drvdata(pdev, dra7xx);
672 pm_runtime_enable(dev);
673 ret = pm_runtime_get_sync(dev);
675 dev_err(dev, "pm_runtime_get_sync failed\n");
679 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
681 ret = PTR_ERR(reset);
682 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
686 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
688 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
690 dra7xx->link_gen = of_pci_get_max_link_speed(np);
691 if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
692 dra7xx->link_gen = 2;
695 case DW_PCIE_RC_TYPE:
696 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
698 ret = dra7xx_add_pcie_port(dra7xx, pdev);
702 case DW_PCIE_EP_TYPE:
703 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
706 ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
710 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
715 dev_err(dev, "INVALID device type %d\n", mode);
719 ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
720 IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
722 dev_err(dev, "failed to request irq\n");
732 pm_runtime_disable(dev);
733 dra7xx_pcie_disable_phy(dra7xx);
738 #ifdef CONFIG_PM_SLEEP
739 static int dra7xx_pcie_suspend(struct device *dev)
741 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
742 struct dw_pcie *pci = dra7xx->pci;
745 if (dra7xx->mode != DW_PCIE_RC_TYPE)
749 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
750 val &= ~PCI_COMMAND_MEMORY;
751 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
756 static int dra7xx_pcie_resume(struct device *dev)
758 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
759 struct dw_pcie *pci = dra7xx->pci;
762 if (dra7xx->mode != DW_PCIE_RC_TYPE)
766 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
767 val |= PCI_COMMAND_MEMORY;
768 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
773 static int dra7xx_pcie_suspend_noirq(struct device *dev)
775 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
777 dra7xx_pcie_disable_phy(dra7xx);
782 static int dra7xx_pcie_resume_noirq(struct device *dev)
784 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
787 ret = dra7xx_pcie_enable_phy(dra7xx);
789 dev_err(dev, "failed to enable phy\n");
797 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
798 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
799 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
800 dra7xx_pcie_resume_noirq)
803 static struct platform_driver dra7xx_pcie_driver = {
806 .of_match_table = of_dra7xx_pcie_match,
807 .suppress_bind_attrs = true,
808 .pm = &dra7xx_pcie_pm_ops,
811 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);