1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint controller driver for UniPhier SoCs
4 * Copyright 2018 Socionext Inc.
5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/iopoll.h>
15 #include <linux/pci.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
20 #include "pcie-designware.h"
22 /* Link Glue registers */
23 #define PCL_RSTCTRL0 0x0010
24 #define PCL_RSTCTRL_AXI_REG BIT(3)
25 #define PCL_RSTCTRL_AXI_SLAVE BIT(2)
26 #define PCL_RSTCTRL_AXI_MASTER BIT(1)
27 #define PCL_RSTCTRL_PIPE3 BIT(0)
29 #define PCL_RSTCTRL1 0x0020
30 #define PCL_RSTCTRL_PERST BIT(0)
32 #define PCL_RSTCTRL2 0x0024
33 #define PCL_RSTCTRL_PHY_RESET BIT(0)
35 #define PCL_PINCTRL0 0x002c
36 #define PCL_PERST_PLDN_REGEN BIT(12)
37 #define PCL_PERST_NOE_REGEN BIT(11)
38 #define PCL_PERST_OUT_REGEN BIT(8)
39 #define PCL_PERST_PLDN_REGVAL BIT(4)
40 #define PCL_PERST_NOE_REGVAL BIT(3)
41 #define PCL_PERST_OUT_REGVAL BIT(0)
43 #define PCL_PIPEMON 0x0044
44 #define PCL_PCLK_ALIVE BIT(15)
46 #define PCL_MODE 0x8000
47 #define PCL_MODE_REGEN BIT(8)
48 #define PCL_MODE_REGVAL BIT(0)
50 #define PCL_APP_CLK_CTRL 0x8004
51 #define PCL_APP_CLK_REQ BIT(0)
53 #define PCL_APP_READY_CTRL 0x8008
54 #define PCL_APP_LTSSM_ENABLE BIT(0)
56 #define PCL_APP_MSI0 0x8040
57 #define PCL_APP_VEN_MSI_TC_MASK GENMASK(10, 8)
58 #define PCL_APP_VEN_MSI_VECTOR_MASK GENMASK(4, 0)
60 #define PCL_APP_MSI1 0x8044
61 #define PCL_APP_MSI_REQ BIT(0)
63 #define PCL_APP_INTX 0x8074
64 #define PCL_APP_INTX_SYS_INT BIT(0)
66 #define PCL_APP_PM0 0x8078
67 #define PCL_SYS_AUX_PWR_DET BIT(8)
69 /* assertion time of INTx in usec */
70 #define PCL_INTX_WIDTH_USEC 30
72 struct uniphier_pcie_ep_priv {
75 struct clk *clk, *clk_gio;
76 struct reset_control *rst, *rst_gio;
78 const struct uniphier_pcie_ep_soc_data *data;
81 struct uniphier_pcie_ep_soc_data {
83 void (*init)(struct uniphier_pcie_ep_priv *priv);
84 int (*wait)(struct uniphier_pcie_ep_priv *priv);
85 const struct pci_epc_features features;
88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
90 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_ep_priv *priv,
95 val = readl(priv->base + PCL_APP_READY_CTRL);
97 val |= PCL_APP_LTSSM_ENABLE;
99 val &= ~PCL_APP_LTSSM_ENABLE;
100 writel(val, priv->base + PCL_APP_READY_CTRL);
103 static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
108 val = readl(priv->base + PCL_RSTCTRL2);
110 val |= PCL_RSTCTRL_PHY_RESET;
112 val &= ~PCL_RSTCTRL_PHY_RESET;
113 writel(val, priv->base + PCL_RSTCTRL2);
116 static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
121 val = readl(priv->base + PCL_MODE);
122 val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
123 writel(val, priv->base + PCL_MODE);
126 val = readl(priv->base + PCL_APP_CLK_CTRL);
127 val &= ~PCL_APP_CLK_REQ;
128 writel(val, priv->base + PCL_APP_CLK_CTRL);
130 /* deassert PIPE3 and AXI reset */
131 val = readl(priv->base + PCL_RSTCTRL0);
132 val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE
133 | PCL_RSTCTRL_AXI_MASTER | PCL_RSTCTRL_PIPE3;
134 writel(val, priv->base + PCL_RSTCTRL0);
136 uniphier_pcie_ltssm_enable(priv, false);
141 static void uniphier_pcie_nx1_init_ep(struct uniphier_pcie_ep_priv *priv)
146 val = readl(priv->base + PCL_MODE);
147 val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
148 writel(val, priv->base + PCL_MODE);
150 /* use auxiliary power detection */
151 val = readl(priv->base + PCL_APP_PM0);
152 val |= PCL_SYS_AUX_PWR_DET;
153 writel(val, priv->base + PCL_APP_PM0);
156 val = readl(priv->base + PCL_PINCTRL0);
157 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
158 | PCL_PERST_PLDN_REGVAL);
159 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
160 | PCL_PERST_PLDN_REGEN;
161 writel(val, priv->base + PCL_PINCTRL0);
163 uniphier_pcie_ltssm_enable(priv, false);
165 usleep_range(100000, 200000);
167 /* deassert PERST# */
168 val = readl(priv->base + PCL_PINCTRL0);
169 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
170 writel(val, priv->base + PCL_PINCTRL0);
173 static int uniphier_pcie_nx1_wait_ep(struct uniphier_pcie_ep_priv *priv)
178 /* wait PIPE clock */
179 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
180 status & PCL_PCLK_ALIVE, 100000, 1000000);
182 dev_err(priv->pci.dev,
183 "Failed to initialize controller in EP mode\n");
190 static int uniphier_pcie_start_link(struct dw_pcie *pci)
192 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
194 uniphier_pcie_ltssm_enable(priv, true);
199 static void uniphier_pcie_stop_link(struct dw_pcie *pci)
201 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
203 uniphier_pcie_ltssm_enable(priv, false);
206 static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
208 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
211 for (bar = BAR_0; bar <= BAR_5; bar++)
212 dw_pcie_ep_reset_bar(pci, bar);
215 static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep)
217 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
218 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
222 * This makes pulse signal to send INTx to the RC, so this should
223 * be cleared as soon as possible. This sequence is covered with
224 * mutex in pci_epc_raise_irq().
227 val = readl(priv->base + PCL_APP_INTX);
228 val |= PCL_APP_INTX_SYS_INT;
229 writel(val, priv->base + PCL_APP_INTX);
231 udelay(PCL_INTX_WIDTH_USEC);
234 val &= ~PCL_APP_INTX_SYS_INT;
235 writel(val, priv->base + PCL_APP_INTX);
240 static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
241 u8 func_no, u16 interrupt_num)
243 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
244 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
247 val = FIELD_PREP(PCL_APP_VEN_MSI_TC_MASK, func_no)
248 | FIELD_PREP(PCL_APP_VEN_MSI_VECTOR_MASK, interrupt_num - 1);
249 writel(val, priv->base + PCL_APP_MSI0);
251 val = readl(priv->base + PCL_APP_MSI1);
252 val |= PCL_APP_MSI_REQ;
253 writel(val, priv->base + PCL_APP_MSI1);
258 static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
259 unsigned int type, u16 interrupt_num)
261 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
265 return uniphier_pcie_ep_raise_intx_irq(ep);
267 return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
270 dev_err(pci->dev, "UNKNOWN IRQ type (%d)\n", type);
276 static const struct pci_epc_features*
277 uniphier_pcie_get_features(struct dw_pcie_ep *ep)
279 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
280 struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
282 return &priv->data->features;
285 static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
286 .init = uniphier_pcie_ep_init,
287 .raise_irq = uniphier_pcie_ep_raise_irq,
288 .get_features = uniphier_pcie_get_features,
291 static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
295 ret = clk_prepare_enable(priv->clk);
299 ret = clk_prepare_enable(priv->clk_gio);
301 goto out_clk_disable;
303 ret = reset_control_deassert(priv->rst);
305 goto out_clk_gio_disable;
307 ret = reset_control_deassert(priv->rst_gio);
311 if (priv->data->init)
312 priv->data->init(priv);
314 uniphier_pcie_phy_reset(priv, true);
316 ret = phy_init(priv->phy);
318 goto out_rst_gio_assert;
320 uniphier_pcie_phy_reset(priv, false);
322 if (priv->data->wait) {
323 ret = priv->data->wait(priv);
333 reset_control_assert(priv->rst_gio);
335 reset_control_assert(priv->rst);
337 clk_disable_unprepare(priv->clk_gio);
339 clk_disable_unprepare(priv->clk);
344 static const struct dw_pcie_ops dw_pcie_ops = {
345 .start_link = uniphier_pcie_start_link,
346 .stop_link = uniphier_pcie_stop_link,
349 static int uniphier_pcie_ep_probe(struct platform_device *pdev)
351 struct device *dev = &pdev->dev;
352 struct uniphier_pcie_ep_priv *priv;
355 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
359 priv->data = of_device_get_match_data(dev);
360 if (WARN_ON(!priv->data))
364 priv->pci.ops = &dw_pcie_ops;
366 priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
367 if (IS_ERR(priv->base))
368 return PTR_ERR(priv->base);
370 if (priv->data->has_gio) {
371 priv->clk_gio = devm_clk_get(dev, "gio");
372 if (IS_ERR(priv->clk_gio))
373 return PTR_ERR(priv->clk_gio);
375 priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
376 if (IS_ERR(priv->rst_gio))
377 return PTR_ERR(priv->rst_gio);
380 priv->clk = devm_clk_get(dev, "link");
381 if (IS_ERR(priv->clk))
382 return PTR_ERR(priv->clk);
384 priv->rst = devm_reset_control_get_shared(dev, "link");
385 if (IS_ERR(priv->rst))
386 return PTR_ERR(priv->rst);
388 priv->phy = devm_phy_optional_get(dev, "pcie-phy");
389 if (IS_ERR(priv->phy)) {
390 ret = PTR_ERR(priv->phy);
391 dev_err(dev, "Failed to get phy (%d)\n", ret);
395 platform_set_drvdata(pdev, priv);
397 ret = uniphier_pcie_ep_enable(priv);
401 priv->pci.ep.ops = &uniphier_pcie_ep_ops;
402 return dw_pcie_ep_init(&priv->pci.ep);
405 static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
407 .init = uniphier_pcie_pro5_init_ep,
410 .linkup_notifier = false,
412 .msix_capable = false,
414 .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
415 .reserved_bar = BIT(BAR_4),
419 static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
421 .init = uniphier_pcie_nx1_init_ep,
422 .wait = uniphier_pcie_nx1_wait_ep,
424 .linkup_notifier = false,
426 .msix_capable = false,
428 .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
432 static const struct of_device_id uniphier_pcie_ep_match[] = {
434 .compatible = "socionext,uniphier-pro5-pcie-ep",
435 .data = &uniphier_pro5_data,
438 .compatible = "socionext,uniphier-nx1-pcie-ep",
439 .data = &uniphier_nx1_data,
444 static struct platform_driver uniphier_pcie_ep_driver = {
445 .probe = uniphier_pcie_ep_probe,
447 .name = "uniphier-pcie-ep",
448 .of_match_table = uniphier_pcie_ep_match,
449 .suppress_bind_attrs = true,
452 builtin_platform_driver(uniphier_pcie_ep_driver);