1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
40 static const u16 default_tid_to_tx_fifo[] = {
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
63 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
70 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
71 struct iwl_dma_ptr *ptr)
73 if (unlikely(!ptr->addr))
76 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
77 memset(ptr, 0, sizeof(*ptr));
81 * iwl_txq_update_write_ptr - Send new write index to hardware
83 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
87 int txq_id = txq->q.id;
89 if (txq->need_update == 0)
92 /* if we're trying to save power */
93 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
94 /* wake up nic if it's powered down ...
95 * uCode will wake up, and interrupt us again, so next
96 * time we'll skip this part. */
97 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
99 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
100 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
102 iwl_set_bit(priv, CSR_GP_CNTRL,
103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
107 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
108 txq->q.write_ptr | (txq_id << 8));
110 /* else not in power-save mode, uCode will never sleep when we're
111 * trying to tx (during RFKILL, we're not trying to tx). */
113 iwl_write32(priv, HBUS_TARG_WRPTR,
114 txq->q.write_ptr | (txq_id << 8));
116 txq->need_update = 0;
120 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
124 * iwl_tx_queue_free - Deallocate DMA queue.
125 * @txq: Transmit queue to deallocate.
127 * Empty queue by removing and destroying all BD's.
129 * 0-fill, but do not free "txq" descriptor structure.
131 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
133 struct iwl_tx_queue *txq = &priv->txq[txq_id];
134 struct iwl_queue *q = &txq->q;
135 struct pci_dev *dev = priv->pci_dev;
141 /* first, empty all BD's */
142 for (; q->write_ptr != q->read_ptr;
143 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
144 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
146 /* De-alloc array of command/tx buffers */
147 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
150 /* De-alloc circular buffer of TFDs */
152 pci_free_consistent(dev, priv->hw_params.tfd_size *
153 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
155 /* De-alloc array of per-TFD driver data */
159 /* deallocate arrays */
165 /* 0-fill queue descriptor structure */
166 memset(txq, 0, sizeof(*txq));
168 EXPORT_SYMBOL(iwl_tx_queue_free);
171 * iwl_cmd_queue_free - Deallocate DMA queue.
172 * @txq: Transmit queue to deallocate.
174 * Empty queue by removing and destroying all BD's.
176 * 0-fill, but do not free "txq" descriptor structure.
178 void iwl_cmd_queue_free(struct iwl_priv *priv)
180 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
181 struct iwl_queue *q = &txq->q;
182 struct pci_dev *dev = priv->pci_dev;
188 /* De-alloc array of command/tx buffers */
189 for (i = 0; i <= TFD_CMD_SLOTS; i++)
192 /* De-alloc circular buffer of TFDs */
194 pci_free_consistent(dev, priv->hw_params.tfd_size *
195 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
197 /* deallocate arrays */
203 /* 0-fill queue descriptor structure */
204 memset(txq, 0, sizeof(*txq));
206 EXPORT_SYMBOL(iwl_cmd_queue_free);
208 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
211 * Theory of operation
213 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
214 * of buffer descriptors, each of which points to one or more data buffers for
215 * the device to read from or fill. Driver and device exchange status of each
216 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
217 * entries in each circular buffer, to protect against confusing empty and full
220 * The device reads or writes the data in the queues via the device's several
221 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
223 * For Tx queue, there are low mark and high mark limits. If, after queuing
224 * the packet for Tx, free space become < low mark, Tx queue stopped. When
225 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
228 * See more detailed info in iwl-4965-hw.h.
229 ***************************************************/
231 int iwl_queue_space(const struct iwl_queue *q)
233 int s = q->read_ptr - q->write_ptr;
235 if (q->read_ptr > q->write_ptr)
240 /* keep some reserve to not confuse empty and full situations */
246 EXPORT_SYMBOL(iwl_queue_space);
250 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
252 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
253 int count, int slots_num, u32 id)
256 q->n_window = slots_num;
259 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
260 * and iwl_queue_dec_wrap are broken. */
261 BUG_ON(!is_power_of_2(count));
263 /* slots_num must be power-of-two size, otherwise
264 * get_cmd_index is broken. */
265 BUG_ON(!is_power_of_2(slots_num));
267 q->low_mark = q->n_window / 4;
271 q->high_mark = q->n_window / 8;
272 if (q->high_mark < 2)
275 q->write_ptr = q->read_ptr = 0;
281 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
283 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
284 struct iwl_tx_queue *txq, u32 id)
286 struct pci_dev *dev = priv->pci_dev;
287 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
289 /* Driver private data, only for Tx (not command) queues,
290 * not shared with device. */
291 if (id != IWL_CMD_QUEUE_NUM) {
292 txq->txb = kmalloc(sizeof(txq->txb[0]) *
293 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
295 IWL_ERR(priv, "kmalloc for auxiliary BD "
296 "structures failed\n");
303 /* Circular buffer of transmit frame descriptors (TFDs),
304 * shared with device */
305 txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
308 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
323 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
325 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
326 int slots_num, u32 txq_id)
330 int actual_slots = slots_num;
333 * Alloc buffer array for commands (Tx or other types of commands).
334 * For the command queue (#4), allocate command space + one big
335 * command for scan, since scan command is very huge; the system will
336 * not have two scans at the same time, so only one is needed.
337 * For normal Tx queues (all other queues), no super-size command
340 if (txq_id == IWL_CMD_QUEUE_NUM)
343 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
345 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
348 if (!txq->meta || !txq->cmd)
349 goto out_free_arrays;
351 len = sizeof(struct iwl_device_cmd);
352 for (i = 0; i < actual_slots; i++) {
353 /* only happens for cmd queue */
355 len += IWL_MAX_SCAN_SIZE;
357 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
362 /* Alloc driver data array and TFD circular buffer */
363 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
367 txq->need_update = 0;
370 * Aggregation TX queues will get their ID when aggregation begins;
371 * they overwrite the setting done here. The command FIFO doesn't
372 * need an swq_id so don't set one to catch errors, all others can
373 * be set up to the identity mapping.
375 if (txq_id != IWL_CMD_QUEUE_NUM)
376 txq->swq_id = txq_id;
378 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
379 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
380 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
382 /* Initialize queue's high/low-water marks, and head/tail indexes */
383 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
385 /* Tell device where to find queue */
386 priv->cfg->ops->lib->txq_init(priv, txq);
390 for (i = 0; i < actual_slots; i++)
398 EXPORT_SYMBOL(iwl_tx_queue_init);
401 * iwl_hw_txq_ctx_free - Free TXQ Context
403 * Destroy all TX DMA queues and structures
405 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
411 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
413 if (txq_id == IWL_CMD_QUEUE_NUM)
414 iwl_cmd_queue_free(priv);
416 iwl_tx_queue_free(priv, txq_id);
417 iwl_free_dma_ptr(priv, &priv->kw);
419 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
421 /* free tx queue structure */
422 iwl_free_txq_mem(priv);
424 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
427 * iwl_txq_ctx_reset - Reset TX queue context
428 * Destroys all DMA structures and initialize them again
433 int iwl_txq_ctx_reset(struct iwl_priv *priv)
436 int txq_id, slots_num;
439 /* Free all tx/cmd queues and keep-warm buffer */
440 iwl_hw_txq_ctx_free(priv);
442 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
443 priv->hw_params.scd_bc_tbls_size);
445 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
448 /* Alloc keep-warm buffer */
449 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
451 IWL_ERR(priv, "Keep Warm allocation failed\n");
455 /* allocate tx queue structure */
456 ret = iwl_alloc_txq_mem(priv);
460 spin_lock_irqsave(&priv->lock, flags);
462 /* Turn off all Tx DMA fifos */
463 priv->cfg->ops->lib->txq_set_sched(priv, 0);
465 /* Tell NIC where to find the "keep warm" buffer */
466 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
468 spin_unlock_irqrestore(&priv->lock, flags);
470 /* Alloc and init all Tx queues, including the command queue (#4) */
471 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
472 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
473 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
474 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
477 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
485 iwl_hw_txq_ctx_free(priv);
486 iwl_free_dma_ptr(priv, &priv->kw);
488 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
494 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
496 void iwl_txq_ctx_stop(struct iwl_priv *priv)
501 /* Turn off all Tx DMA fifos */
502 spin_lock_irqsave(&priv->lock, flags);
504 priv->cfg->ops->lib->txq_set_sched(priv, 0);
506 /* Stop each Tx DMA channel, and wait for it to be idle */
507 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
508 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
509 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
510 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
513 spin_unlock_irqrestore(&priv->lock, flags);
515 /* Deallocate memory for all Tx queues */
516 iwl_hw_txq_ctx_free(priv);
518 EXPORT_SYMBOL(iwl_txq_ctx_stop);
521 * handle build REPLY_TX command notification.
523 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
524 struct iwl_tx_cmd *tx_cmd,
525 struct ieee80211_tx_info *info,
526 struct ieee80211_hdr *hdr,
529 __le16 fc = hdr->frame_control;
530 __le32 tx_flags = tx_cmd->tx_flags;
532 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
533 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
534 tx_flags |= TX_CMD_FLG_ACK_MSK;
535 if (ieee80211_is_mgmt(fc))
536 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
537 if (ieee80211_is_probe_resp(fc) &&
538 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
539 tx_flags |= TX_CMD_FLG_TSF_MSK;
541 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
542 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
545 if (ieee80211_is_back_req(fc))
546 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
549 tx_cmd->sta_id = std_id;
550 if (ieee80211_has_morefrags(fc))
551 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
553 if (ieee80211_is_data_qos(fc)) {
554 u8 *qc = ieee80211_get_qos_ctl(hdr);
555 tx_cmd->tid_tspec = qc[0] & 0xf;
556 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
558 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
561 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
563 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
564 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
566 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
567 if (ieee80211_is_mgmt(fc)) {
568 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
569 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
571 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
573 tx_cmd->timeout.pm_frame_timeout = 0;
576 tx_cmd->driver_txop = 0;
577 tx_cmd->tx_flags = tx_flags;
578 tx_cmd->next_frame_len = 0;
581 #define RTS_HCCA_RETRY_LIMIT 3
582 #define RTS_DFAULT_RETRY_LIMIT 60
584 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
585 struct iwl_tx_cmd *tx_cmd,
586 struct ieee80211_tx_info *info,
587 __le16 fc, int is_hcca)
595 /* Set retry limit on DATA packets and Probe Responses*/
596 if (ieee80211_is_probe_resp(fc))
597 data_retry_limit = 3;
599 data_retry_limit = IWL_DEFAULT_TX_RETRY;
600 tx_cmd->data_retry_limit = data_retry_limit;
602 /* Set retry limit on RTS packets */
603 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
604 RTS_DFAULT_RETRY_LIMIT;
605 if (data_retry_limit < rts_retry_limit)
606 rts_retry_limit = data_retry_limit;
607 tx_cmd->rts_retry_limit = rts_retry_limit;
609 /* DATA packets will use the uCode station table for rate/antenna
611 if (ieee80211_is_data(fc)) {
612 tx_cmd->initial_rate_index = 0;
613 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
618 * If the current TX rate stored in mac80211 has the MCS bit set, it's
619 * not really a TX rate. Thus, we use the lowest supported rate for
620 * this band. Also use the lowest supported rate if the stored rate
623 rate_idx = info->control.rates[0].idx;
624 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
625 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
626 rate_idx = rate_lowest_index(&priv->bands[info->band],
628 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
629 if (info->band == IEEE80211_BAND_5GHZ)
630 rate_idx += IWL_FIRST_OFDM_RATE;
631 /* Get PLCP rate for tx_cmd->rate_n_flags */
632 rate_plcp = iwl_rates[rate_idx].plcp;
633 /* Zero out flags for this packet */
636 /* Set CCK flag as needed */
637 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
638 rate_flags |= RATE_MCS_CCK_MSK;
640 /* Set up RTS and CTS flags for certain packets */
641 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
642 case cpu_to_le16(IEEE80211_STYPE_AUTH):
643 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
644 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
645 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
646 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
647 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
648 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
655 /* Set up antennas */
656 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
657 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
659 /* Set the rate in the TX cmd */
660 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
663 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
664 struct ieee80211_tx_info *info,
665 struct iwl_tx_cmd *tx_cmd,
666 struct sk_buff *skb_frag,
669 struct ieee80211_key_conf *keyconf = info->control.hw_key;
671 switch (keyconf->alg) {
673 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
674 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
675 if (info->flags & IEEE80211_TX_CTL_AMPDU)
676 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
677 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
681 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
682 ieee80211_get_tkip_key(keyconf, skb_frag,
683 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
684 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
688 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
689 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
691 if (keyconf->keylen == WEP_KEY_LEN_128)
692 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
694 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
696 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
697 "with key %d\n", keyconf->keyidx);
701 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
707 * start REPLY_TX command process
709 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
711 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
712 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
713 struct iwl_tx_queue *txq;
715 struct iwl_device_cmd *out_cmd;
716 struct iwl_cmd_meta *out_meta;
717 struct iwl_tx_cmd *tx_cmd;
719 dma_addr_t phys_addr;
720 dma_addr_t txcmd_phys;
721 dma_addr_t scratch_phys;
722 u16 len, len_org, firstlen, secondlen;
727 u8 wait_write_ptr = 0;
733 spin_lock_irqsave(&priv->lock, flags);
734 if (iwl_is_rfkill(priv)) {
735 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
739 fc = hdr->frame_control;
741 #ifdef CONFIG_IWLWIFI_DEBUG
742 if (ieee80211_is_auth(fc))
743 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
744 else if (ieee80211_is_assoc_req(fc))
745 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
746 else if (ieee80211_is_reassoc_req(fc))
747 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
750 /* drop all non-injected data frame if we are not associated */
751 if (ieee80211_is_data(fc) &&
752 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
753 (!iwl_is_associated(priv) ||
754 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
755 !priv->assoc_station_added)) {
756 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
760 hdr_len = ieee80211_hdrlen(fc);
762 /* Find (or create) index into station table for destination station */
763 if (info->flags & IEEE80211_TX_CTL_INJECTED)
764 sta_id = priv->hw_params.bcast_sta_id;
766 sta_id = iwl_get_sta_id(priv, hdr);
767 if (sta_id == IWL_INVALID_STATION) {
768 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
773 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
775 txq_id = skb_get_queue_mapping(skb);
776 if (ieee80211_is_data_qos(fc)) {
777 qc = ieee80211_get_qos_ctl(hdr);
778 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
779 if (unlikely(tid >= MAX_TID_COUNT))
781 seq_number = priv->stations[sta_id].tid[tid].seq_number;
782 seq_number &= IEEE80211_SCTL_SEQ;
783 hdr->seq_ctrl = hdr->seq_ctrl &
784 cpu_to_le16(IEEE80211_SCTL_FRAG);
785 hdr->seq_ctrl |= cpu_to_le16(seq_number);
787 /* aggregation is on for this <sta,tid> */
788 if (info->flags & IEEE80211_TX_CTL_AMPDU)
789 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
792 txq = &priv->txq[txq_id];
793 swq_id = txq->swq_id;
796 if (unlikely(iwl_queue_space(q) < q->high_mark))
799 if (ieee80211_is_data_qos(fc))
800 priv->stations[sta_id].tid[tid].tfds_in_queue++;
802 /* Set up driver data for this TFD */
803 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
804 txq->txb[q->write_ptr].skb[0] = skb;
806 /* Set up first empty entry in queue's array of Tx/cmd buffers */
807 out_cmd = txq->cmd[q->write_ptr];
808 out_meta = &txq->meta[q->write_ptr];
809 tx_cmd = &out_cmd->cmd.tx;
810 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
811 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
814 * Set up the Tx-command (not MAC!) header.
815 * Store the chosen Tx queue and TFD index within the sequence field;
816 * after Tx, uCode's Tx response will return this value so driver can
817 * locate the frame within the tx queue and do post-tx processing.
819 out_cmd->hdr.cmd = REPLY_TX;
820 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
821 INDEX_TO_SEQ(q->write_ptr)));
823 /* Copy MAC header from skb into command buffer */
824 memcpy(tx_cmd->hdr, hdr, hdr_len);
827 /* Total # bytes to be transmitted */
829 tx_cmd->len = cpu_to_le16(len);
831 if (info->control.hw_key)
832 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
834 /* TODO need this for burst mode later on */
835 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
836 iwl_dbg_log_tx_data_frame(priv, len, hdr);
838 /* set is_hcca to 0; it probably will never be implemented */
839 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
841 iwl_update_stats(priv, true, fc, len);
843 * Use the first empty entry in this queue's command buffer array
844 * to contain the Tx command and MAC header concatenated together
845 * (payload data will be in another buffer).
846 * Size of this varies, due to varying MAC header length.
847 * If end is not dword aligned, we'll have 2 extra bytes at the end
848 * of the MAC header (device reads on dword boundaries).
849 * We'll tell device about this padding later.
851 len = sizeof(struct iwl_tx_cmd) +
852 sizeof(struct iwl_cmd_header) + hdr_len;
855 firstlen = len = (len + 3) & ~3;
862 /* Tell NIC about any 2-byte padding after MAC header */
864 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
866 /* Physical address of this Tx command's header (not MAC header!),
867 * within command buffer array. */
868 txcmd_phys = pci_map_single(priv->pci_dev,
870 PCI_DMA_BIDIRECTIONAL);
871 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
872 pci_unmap_len_set(out_meta, len, len);
873 /* Add buffer containing Tx command and MAC(!) header to TFD's
875 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
876 txcmd_phys, len, 1, 0);
878 if (!ieee80211_has_morefrags(hdr->frame_control)) {
879 txq->need_update = 1;
881 priv->stations[sta_id].tid[tid].seq_number = seq_number;
884 txq->need_update = 0;
887 /* Set up TFD's 2nd entry to point directly to remainder of skb,
888 * if any (802.11 null frames have no payload). */
889 secondlen = len = skb->len - hdr_len;
891 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
892 len, PCI_DMA_TODEVICE);
893 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
898 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
899 offsetof(struct iwl_tx_cmd, scratch);
901 len = sizeof(struct iwl_tx_cmd) +
902 sizeof(struct iwl_cmd_header) + hdr_len;
903 /* take back ownership of DMA buffer to enable update */
904 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
905 len, PCI_DMA_BIDIRECTIONAL);
906 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
907 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
909 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
910 le16_to_cpu(out_cmd->hdr.sequence));
911 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
912 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
913 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
915 /* Set up entry for this TFD in Tx byte-count array */
916 if (info->flags & IEEE80211_TX_CTL_AMPDU)
917 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
918 le16_to_cpu(tx_cmd->len));
920 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
921 len, PCI_DMA_BIDIRECTIONAL);
923 trace_iwlwifi_dev_tx(priv,
924 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
925 sizeof(struct iwl_tfd),
926 &out_cmd->hdr, firstlen,
927 skb->data + hdr_len, secondlen);
929 /* Tell device the write index *just past* this latest filled TFD */
930 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
931 ret = iwl_txq_update_write_ptr(priv, txq);
932 spin_unlock_irqrestore(&priv->lock, flags);
937 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
938 if (wait_write_ptr) {
939 spin_lock_irqsave(&priv->lock, flags);
940 txq->need_update = 1;
941 iwl_txq_update_write_ptr(priv, txq);
942 spin_unlock_irqrestore(&priv->lock, flags);
944 iwl_stop_queue(priv, txq->swq_id);
951 spin_unlock_irqrestore(&priv->lock, flags);
954 EXPORT_SYMBOL(iwl_tx_skb);
956 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
959 * iwl_enqueue_hcmd - enqueue a uCode command
960 * @priv: device private data point
961 * @cmd: a point to the ucode command structure
963 * The function returns < 0 values to indicate the operation is
964 * failed. On success, it turns the index (> 0) of command in the
967 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
969 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
970 struct iwl_queue *q = &txq->q;
971 struct iwl_device_cmd *out_cmd;
972 struct iwl_cmd_meta *out_meta;
973 dma_addr_t phys_addr;
979 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
980 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
982 /* If any of the command structures end up being larger than
983 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
984 * we will need to increase the size of the TFD entries */
985 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
986 !(cmd->flags & CMD_SIZE_HUGE));
988 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
989 IWL_WARN(priv, "Not sending command - %s KILL\n",
990 iwl_is_rfkill(priv) ? "RF" : "CT");
994 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
995 IWL_ERR(priv, "No space for Tx\n");
996 if (iwl_within_ct_kill_margin(priv))
997 iwl_tt_enter_ct_kill(priv);
999 IWL_ERR(priv, "Restarting adapter due to queue full\n");
1000 queue_work(priv->workqueue, &priv->restart);
1005 spin_lock_irqsave(&priv->hcmd_lock, flags);
1007 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1008 out_cmd = txq->cmd[idx];
1009 out_meta = &txq->meta[idx];
1011 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1012 out_meta->flags = cmd->flags;
1013 if (cmd->flags & CMD_WANT_SKB)
1014 out_meta->source = cmd;
1015 if (cmd->flags & CMD_ASYNC)
1016 out_meta->callback = cmd->callback;
1018 out_cmd->hdr.cmd = cmd->id;
1019 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1021 /* At this point, the out_cmd now has all of the incoming cmd
1024 out_cmd->hdr.flags = 0;
1025 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1026 INDEX_TO_SEQ(q->write_ptr));
1027 if (cmd->flags & CMD_SIZE_HUGE)
1028 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1029 len = sizeof(struct iwl_device_cmd);
1030 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1033 #ifdef CONFIG_IWLWIFI_DEBUG
1034 switch (out_cmd->hdr.cmd) {
1035 case REPLY_TX_LINK_QUALITY_CMD:
1036 case SENSITIVITY_CMD:
1037 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1038 "%d bytes at %d[%d]:%d\n",
1039 get_cmd_string(out_cmd->hdr.cmd),
1041 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1042 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1045 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1046 "%d bytes at %d[%d]:%d\n",
1047 get_cmd_string(out_cmd->hdr.cmd),
1049 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1050 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1053 txq->need_update = 1;
1055 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1056 /* Set up entry in queue's byte count circular buffer */
1057 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1059 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1060 fix_size, PCI_DMA_BIDIRECTIONAL);
1061 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1062 pci_unmap_len_set(out_meta, len, fix_size);
1064 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1066 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1067 phys_addr, fix_size, 1,
1070 /* Increment and update queue's write index */
1071 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1072 ret = iwl_txq_update_write_ptr(priv, txq);
1074 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1075 return ret ? ret : idx;
1078 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1080 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1081 struct iwl_queue *q = &txq->q;
1082 struct iwl_tx_info *tx_info;
1085 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1086 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1087 "is out of range [0-%d] %d %d.\n", txq_id,
1088 index, q->n_bd, q->write_ptr, q->read_ptr);
1092 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1093 q->read_ptr != index;
1094 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1096 tx_info = &txq->txb[txq->q.read_ptr];
1097 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1098 tx_info->skb[0] = NULL;
1100 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1101 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1103 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1108 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1112 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1114 * When FW advances 'R' index, all entries between old and new 'R' index
1115 * need to be reclaimed. As result, some free space forms. If there is
1116 * enough free space (> low mark), wake the stack that feeds us.
1118 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1119 int idx, int cmd_idx)
1121 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1122 struct iwl_queue *q = &txq->q;
1125 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1126 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1127 "is out of range [0-%d] %d %d.\n", txq_id,
1128 idx, q->n_bd, q->write_ptr, q->read_ptr);
1132 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1133 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1136 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1137 q->write_ptr, q->read_ptr);
1138 queue_work(priv->workqueue, &priv->restart);
1145 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1146 * @rxb: Rx buffer to reclaim
1148 * If an Rx buffer has an async callback associated with it the callback
1149 * will be executed. The attached skb (if present) will only be freed
1150 * if the callback returns 1
1152 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1154 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1155 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1156 int txq_id = SEQ_TO_QUEUE(sequence);
1157 int index = SEQ_TO_INDEX(sequence);
1159 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1160 struct iwl_device_cmd *cmd;
1161 struct iwl_cmd_meta *meta;
1163 /* If a Tx command is being handled and it isn't in the actual
1164 * command queue then there a command routing bug has been introduced
1165 * in the queue management code. */
1166 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1167 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1169 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1170 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1171 iwl_print_hex_error(priv, pkt, 32);
1175 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1176 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1177 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1179 pci_unmap_single(priv->pci_dev,
1180 pci_unmap_addr(meta, mapping),
1181 pci_unmap_len(meta, len),
1182 PCI_DMA_BIDIRECTIONAL);
1184 /* Input error checking is done when commands are added to queue. */
1185 if (meta->flags & CMD_WANT_SKB) {
1186 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1188 } else if (meta->callback)
1189 meta->callback(priv, cmd, pkt);
1191 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1193 if (!(meta->flags & CMD_ASYNC)) {
1194 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1195 wake_up_interruptible(&priv->wait_command_queue);
1198 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1201 * Find first available (lowest unused) Tx Queue, mark it "active".
1202 * Called only when finding queue for aggregation.
1203 * Should never return anything < 7, because they should already
1204 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1206 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1210 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1211 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1216 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1222 unsigned long flags;
1223 struct iwl_tid_data *tid_data;
1225 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1226 tx_fifo = default_tid_to_tx_fifo[tid];
1230 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1233 sta_id = iwl_find_station(priv, ra);
1234 if (sta_id == IWL_INVALID_STATION) {
1235 IWL_ERR(priv, "Start AGG on invalid station\n");
1238 if (unlikely(tid >= MAX_TID_COUNT))
1241 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1242 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1246 txq_id = iwl_txq_ctx_activate_free(priv);
1248 IWL_ERR(priv, "No free aggregation queue available\n");
1252 spin_lock_irqsave(&priv->sta_lock, flags);
1253 tid_data = &priv->stations[sta_id].tid[tid];
1254 *ssn = SEQ_TO_SN(tid_data->seq_number);
1255 tid_data->agg.txq_id = txq_id;
1256 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1257 spin_unlock_irqrestore(&priv->sta_lock, flags);
1259 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1264 if (tid_data->tfds_in_queue == 0) {
1265 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1266 tid_data->agg.state = IWL_AGG_ON;
1267 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1269 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1270 tid_data->tfds_in_queue);
1271 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1275 EXPORT_SYMBOL(iwl_tx_agg_start);
1277 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1279 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1280 struct iwl_tid_data *tid_data;
1281 int ret, write_ptr, read_ptr;
1282 unsigned long flags;
1285 IWL_ERR(priv, "ra = NULL\n");
1289 if (unlikely(tid >= MAX_TID_COUNT))
1292 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1293 tx_fifo_id = default_tid_to_tx_fifo[tid];
1297 sta_id = iwl_find_station(priv, ra);
1299 if (sta_id == IWL_INVALID_STATION) {
1300 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1304 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1305 IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1307 tid_data = &priv->stations[sta_id].tid[tid];
1308 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1309 txq_id = tid_data->agg.txq_id;
1310 write_ptr = priv->txq[txq_id].q.write_ptr;
1311 read_ptr = priv->txq[txq_id].q.read_ptr;
1313 /* The queue is not empty */
1314 if (write_ptr != read_ptr) {
1315 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1316 priv->stations[sta_id].tid[tid].agg.state =
1317 IWL_EMPTYING_HW_QUEUE_DELBA;
1321 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1322 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1324 spin_lock_irqsave(&priv->lock, flags);
1325 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1327 spin_unlock_irqrestore(&priv->lock, flags);
1332 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1336 EXPORT_SYMBOL(iwl_tx_agg_stop);
1338 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1340 struct iwl_queue *q = &priv->txq[txq_id].q;
1341 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1342 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1344 switch (priv->stations[sta_id].tid[tid].agg.state) {
1345 case IWL_EMPTYING_HW_QUEUE_DELBA:
1346 /* We are reclaiming the last packet of the */
1347 /* aggregated HW queue */
1348 if ((txq_id == tid_data->agg.txq_id) &&
1349 (q->read_ptr == q->write_ptr)) {
1350 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1351 int tx_fifo = default_tid_to_tx_fifo[tid];
1352 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1353 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1355 tid_data->agg.state = IWL_AGG_OFF;
1356 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1359 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1360 /* We are reclaiming the last packet of the queue */
1361 if (tid_data->tfds_in_queue == 0) {
1362 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1363 tid_data->agg.state = IWL_AGG_ON;
1364 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1370 EXPORT_SYMBOL(iwl_txq_check_empty);
1373 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1375 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1376 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1378 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1379 struct iwl_ht_agg *agg,
1380 struct iwl_compressed_ba_resp *ba_resp)
1384 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1385 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1388 struct ieee80211_tx_info *info;
1390 if (unlikely(!agg->wait_for_ba)) {
1391 IWL_ERR(priv, "Received BA when not expected\n");
1395 /* Mark that the expected block-ack response arrived */
1396 agg->wait_for_ba = 0;
1397 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1399 /* Calculate shift to align block-ack bits with our Tx window bits */
1400 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1401 if (sh < 0) /* tbw something is wrong with indices */
1404 /* don't use 64-bit values for now */
1405 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1407 if (agg->frame_count > (64 - sh)) {
1408 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1412 /* check for success or failure according to the
1413 * transmitted bitmap and block-ack bitmap */
1414 bitmap &= agg->bitmap;
1416 /* For each frame attempted in aggregation,
1417 * update driver's record of tx frame's status. */
1418 for (i = 0; i < agg->frame_count ; i++) {
1419 ack = bitmap & (1ULL << i);
1421 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1422 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1423 agg->start_idx + i);
1426 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1427 memset(&info->status, 0, sizeof(info->status));
1428 info->flags |= IEEE80211_TX_STAT_ACK;
1429 info->flags |= IEEE80211_TX_STAT_AMPDU;
1430 info->status.ampdu_ack_map = successes;
1431 info->status.ampdu_ack_len = agg->frame_count;
1432 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1434 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1440 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1442 * Handles block-acknowledge notification from device, which reports success
1443 * of frames sent via aggregation.
1445 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1446 struct iwl_rx_mem_buffer *rxb)
1448 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1449 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1450 struct iwl_tx_queue *txq = NULL;
1451 struct iwl_ht_agg *agg;
1456 /* "flow" corresponds to Tx queue */
1457 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1459 /* "ssn" is start of block-ack Tx window, corresponds to index
1460 * (in Tx queue's circular buffer) of first TFD/frame in window */
1461 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1463 if (scd_flow >= priv->hw_params.max_txq_num) {
1465 "BUG_ON scd_flow is bigger than number of queues\n");
1469 txq = &priv->txq[scd_flow];
1470 sta_id = ba_resp->sta_id;
1472 agg = &priv->stations[sta_id].tid[tid].agg;
1474 /* Find index just before block-ack window */
1475 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1477 /* TODO: Need to get this copy more safely - now good for debug */
1479 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1482 (u8 *) &ba_resp->sta_addr_lo32,
1484 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1485 "%d, scd_ssn = %d\n",
1488 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1491 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1493 (unsigned long long)agg->bitmap);
1495 /* Update driver's record of ACK vs. not for each frame in window */
1496 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1498 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1499 * block-ack window (we assume that they've been successfully
1500 * transmitted ... if not, it's too late anyway). */
1501 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1502 /* calculate mac80211 ampdu sw queue to wake */
1503 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1504 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1506 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1507 priv->mac80211_registered &&
1508 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1509 iwl_wake_queue(priv, txq->swq_id);
1511 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1514 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1516 #ifdef CONFIG_IWLWIFI_DEBUG
1517 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1519 const char *iwl_get_tx_fail_reason(u32 status)
1521 switch (status & TX_STATUS_MSK) {
1522 case TX_STATUS_SUCCESS:
1524 TX_STATUS_ENTRY(SHORT_LIMIT);
1525 TX_STATUS_ENTRY(LONG_LIMIT);
1526 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1527 TX_STATUS_ENTRY(MGMNT_ABORT);
1528 TX_STATUS_ENTRY(NEXT_FRAG);
1529 TX_STATUS_ENTRY(LIFE_EXPIRE);
1530 TX_STATUS_ENTRY(DEST_PS);
1531 TX_STATUS_ENTRY(ABORTED);
1532 TX_STATUS_ENTRY(BT_RETRY);
1533 TX_STATUS_ENTRY(STA_INVALID);
1534 TX_STATUS_ENTRY(FRAG_DROPPED);
1535 TX_STATUS_ENTRY(TID_DISABLE);
1536 TX_STATUS_ENTRY(FRAME_FLUSHED);
1537 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1538 TX_STATUS_ENTRY(TX_LOCKED);
1539 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1544 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1545 #endif /* CONFIG_IWLWIFI_DEBUG */