drivers/net/wireless/intel/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
   6  *
   7  * Portions of this file are derived from the ipw3945 project, as well
   8  * as portions of the ieee80211 subsystem header files.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/sched.h>
  32 #include <linux/wait.h>
  33 #include <linux/gfp.h>
  34
  35 #include "iwl-prph.h"
  36 #include "iwl-io.h"
  37 #include "internal.h"
  38 #include "iwl-op-mode.h"
  39
  40 /******************************************************************************
  41  *
  42  * RX path functions
  43  *
  44  ******************************************************************************/
  45
  46 /*
  47  * Rx theory of operation
  48  *
  49  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  50  * each of which point to Receive Buffers to be filled by the NIC.  These get
  51  * used not only for Rx frames, but for any command response or notification
  52  * from the NIC.  The driver and NIC manage the Rx buffers by means
  53  * of indexes into the circular buffer.
  54  *
  55  * Rx Queue Indexes
  56  * The host/firmware share two index registers for managing the Rx buffers.
  57  *
  58  * The READ index maps to the first position that the firmware may be writing
  59  * to -- the driver can read up to (but not including) this position and get
  60  * good data.
  61  * The READ index is managed by the firmware once the card is enabled.
  62  *
  63  * The WRITE index maps to the last position the driver has read from -- the
  64  * position preceding WRITE is the last slot the firmware can place a packet.
  65  *
  66  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  67  * WRITE = READ.
  68  *
  69  * During initialization, the host sets up the READ queue position to the first
  70  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  71  *
  72  * When the firmware places a packet in a buffer, it will advance the READ index
  73  * and fire the RX interrupt.  The driver can then query the READ index and
  74  * process as many packets as possible, moving the WRITE index forward as it
  75  * resets the Rx queue buffers with new memory.
  76  *
  77  * The management in the driver is as follows:
  78  * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
  79  *   When the interrupt handler is called, the request is processed.
  80  *   The page is either stolen - transferred to the upper layer
  81  *   or reused - added immediately to the iwl->rxq->rx_free list.
  82  * + When the page is stolen - the driver updates the matching queue's used
  83  *   count, detaches the RBD and transfers it to the queue used list.
  84  *   When there are two used RBDs - they are transferred to the allocator empty
  85  *   list. Work is then scheduled for the allocator to start allocating
  86  *   eight buffers.
  87  *   When there are another 6 used RBDs - they are transferred to the allocator
  88  *   empty list and the driver tries to claim the pre-allocated buffers and
  89  *   add them to iwl->rxq->rx_free. If it fails - it continues to claim them
  90  *   until ready.
  91  *   When there are 8+ buffers in the free list - either from allocation or from
  92  *   8 reused unstolen pages - restock is called to update the FW and indexes.
  93  * + In order to make sure the allocator always has RBDs to use for allocation
  94  *   the allocator has initial pool in the size of num_queues*(8-2) - the
  95  *   maximum missing RBDs per allocation request (request posted with 2
  96  *    empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
  97  *   The queues supplies the recycle of the rest of the RBDs.
  98  * + A received packet is processed and handed to the kernel network stack,
  99  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 100  * + If there are no allocated buffers in iwl->rxq->rx_free,
 101  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
 102  *   If there were enough free buffers and RX_STALLED is set it is cleared.
 103  *
 104  *
 105  * Driver sequence:
 106  *
 107  * iwl_rxq_alloc()            Allocates rx_free
 108  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
 109  *                            iwl_pcie_rxq_restock.
 110  *                            Used only during initialization.
 111  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
 112  *                            queue, updates firmware pointers, and updates
 113  *                            the WRITE index.
 114  * iwl_pcie_rx_allocator()     Background work for allocating pages.
 115  *
 116  * -- enable interrupts --
 117  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 118  *                            READ INDEX, detaching the SKB from the pool.
 119  *                            Moves the packet buffer from queue to rx_used.
 120  *                            Posts and claims requests to the allocator.
 121  *                            Calls iwl_pcie_rxq_restock to refill any empty
 122  *                            slots.
 123  *
 124  * RBD life-cycle:
 125  *
 126  * Init:
 127  * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
 128  *
 129  * Regular Receive interrupt:
 130  * Page Stolen:
 131  * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
 132  * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
 133  * Page not Stolen:
 134  * rxq.queue -> rxq.rx_free -> rxq.queue
 135  * ...
 136  *
 137  */
 138
 139 /*
 140  * iwl_rxq_space - Return number of free slots available in queue.
 141  */
 142 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 143 {
 144         /* Make sure rx queue size is a power of 2 */
 145         WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
 146
 147         /*
 148          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 149          * between empty and completely full queues.
 150          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 151          * defined for negative dividends.
 152          */
 153         return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
 154 }
 155
 156 /*
 157  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 158  */
 159 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 160 {
 161         return cpu_to_le32((u32)(dma_addr >> 8));
 162 }
 163
 164 /*
 165  * iwl_pcie_rx_stop - stops the Rx DMA
 166  */
 167 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 168 {
 169         if (trans->cfg->mq_rx_supported) {
 170                 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
 171                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
 172                                            RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 173         } else {
 174                 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 175                 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 176                                            FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 177                                            1000);
 178         }
 179 }
 180
 181 /*
 182  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 183  */
 184 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 185                                     struct iwl_rxq *rxq)
 186 {
 187         u32 reg;
 188
 189         lockdep_assert_held(&rxq->lock);
 190
 191         /*
 192          * explicitly wake up the NIC if:
 193          * 1. shadow registers aren't enabled
 194          * 2. there is a chance that the NIC is asleep
 195          */
 196         if (!trans->cfg->base_params->shadow_reg_enable &&
 197             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 198                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 199
 200                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 201                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 202                                        reg);
 203                         iwl_set_bit(trans, CSR_GP_CNTRL,
 204                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 205                         rxq->need_update = true;
 206                         return;
 207                 }
 208         }
 209
 210         rxq->write_actual = round_down(rxq->write, 8);
 211         if (trans->cfg->mq_rx_supported)
 212                 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
 213                             rxq->write_actual);
 214         else
 215                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 216 }
 217
 218 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 219 {
 220         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 221         int i;
 222
 223         for (i = 0; i < trans->num_rx_queues; i++) {
 224                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 225
 226                 if (!rxq->need_update)
 227                         continue;
 228                 spin_lock(&rxq->lock);
 229                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 230                 rxq->need_update = false;
 231                 spin_unlock(&rxq->lock);
 232         }
 233 }
 234
 235 /*
 236  * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
 237  */
 238 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
 239                                   struct iwl_rxq *rxq)
 240 {
 241         struct iwl_rx_mem_buffer *rxb;
 242
 243         /*
 244          * If the device isn't enabled - no need to try to add buffers...
 245          * This can happen when we stop the device and still have an interrupt
 246          * pending. We stop the APM before we sync the interrupts because we
 247          * have to (see comment there). On the other hand, since the APM is
 248          * stopped, we cannot access the HW (in particular not prph).
 249          * So don't try to restock if the APM has been already stopped.
 250          */
 251         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 252                 return;
 253
 254         spin_lock(&rxq->lock);
 255         while (rxq->free_count) {
 256                 __le64 *bd = (__le64 *)rxq->bd;
 257
 258                 /* Get next free Rx buffer, remove from free list */
 259                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 260                                        list);
 261                 list_del(&rxb->list);
 262                 rxb->invalid = false;
 263                 /* 12 first bits are expected to be empty */
 264                 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
 265                 /* Point to Rx buffer via next RBD in circular buffer */
 266                 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
 267                 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK;
 268                 rxq->free_count--;
 269         }
 270         spin_unlock(&rxq->lock);
 271
 272         /*
 273          * If we've added more space for the firmware to place data, tell it.
 274          * Increment device's write pointer in multiples of 8.
 275          */
 276         if (rxq->write_actual != (rxq->write & ~0x7)) {
 277                 spin_lock(&rxq->lock);
 278                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 279                 spin_unlock(&rxq->lock);
 280         }
 281 }
 282
 283 /*
 284  * iwl_pcie_rxsq_restock - restock implementation for single queue rx
 285  */
 286 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
 287                                   struct iwl_rxq *rxq)
 288 {
 289         struct iwl_rx_mem_buffer *rxb;
 290
 291         /*
 292          * If the device isn't enabled - not need to try to add buffers...
 293          * This can happen when we stop the device and still have an interrupt
 294          * pending. We stop the APM before we sync the interrupts because we
 295          * have to (see comment there). On the other hand, since the APM is
 296          * stopped, we cannot access the HW (in particular not prph).
 297          * So don't try to restock if the APM has been already stopped.
 298          */
 299         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 300                 return;
 301
 302         spin_lock(&rxq->lock);
 303         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 304                 __le32 *bd = (__le32 *)rxq->bd;
 305                 /* The overwritten rxb must be a used one */
 306                 rxb = rxq->queue[rxq->write];
 307                 BUG_ON(rxb && rxb->page);
 308
 309                 /* Get next free Rx buffer, remove from free list */
 310                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 311                                        list);
 312                 list_del(&rxb->list);
 313                 rxb->invalid = false;
 314
 315                 /* Point to Rx buffer via next RBD in circular buffer */
 316                 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 317                 rxq->queue[rxq->write] = rxb;
 318                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 319                 rxq->free_count--;
 320         }
 321         spin_unlock(&rxq->lock);
 322
 323         /* If we've added more space for the firmware to place data, tell it.
 324          * Increment device's write pointer in multiples of 8. */
 325         if (rxq->write_actual != (rxq->write & ~0x7)) {
 326                 spin_lock(&rxq->lock);
 327                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 328                 spin_unlock(&rxq->lock);
 329         }
 330 }
 331
 332 /*
 333  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 334  *
 335  * If there are slots in the RX queue that need to be restocked,
 336  * and we have free pre-allocated buffers, fill the ranks as much
 337  * as we can, pulling from rx_free.
 338  *
 339  * This moves the 'write' index forward to catch up with 'processed', and
 340  * also updates the memory address in the firmware to reference the new
 341  * target buffer.
 342  */
 343 static
 344 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
 345 {
 346         if (trans->cfg->mq_rx_supported)
 347                 iwl_pcie_rxmq_restock(trans, rxq);
 348         else
 349                 iwl_pcie_rxsq_restock(trans, rxq);
 350 }
 351
 352 /*
 353  * iwl_pcie_rx_alloc_page - allocates and returns a page.
 354  *
 355  */
 356 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
 357                                            gfp_t priority)
 358 {
 359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 360         struct page *page;
 361         gfp_t gfp_mask = priority;
 362
 363         if (trans_pcie->rx_page_order > 0)
 364                 gfp_mask |= __GFP_COMP;
 365
 366         /* Alloc a new receive buffer */
 367         page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 368         if (!page) {
 369                 if (net_ratelimit())
 370                         IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
 371                                        trans_pcie->rx_page_order);
 372                 /*
 373                  * Issue an error if we don't have enough pre-allocated
 374                   * buffers.
 375 `                */
 376                 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
 377                         IWL_CRIT(trans,
 378                                  "Failed to alloc_pages\n");
 379                 return NULL;
 380         }
 381         return page;
 382 }
 383
 384 /*
 385  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 386  *
 387  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 388  * a page must be allocated and the RBD must point to the page. This function
 389  * doesn't change the HW pointer but handles the list of pages that is used by
 390  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 391  * allocated buffers.
 392  */
 393 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
 394                                    struct iwl_rxq *rxq)
 395 {
 396         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 397         struct iwl_rx_mem_buffer *rxb;
 398         struct page *page;
 399
 400         while (1) {
 401                 spin_lock(&rxq->lock);
 402                 if (list_empty(&rxq->rx_used)) {
 403                         spin_unlock(&rxq->lock);
 404                         return;
 405                 }
 406                 spin_unlock(&rxq->lock);
 407
 408                 /* Alloc a new receive buffer */
 409                 page = iwl_pcie_rx_alloc_page(trans, priority);
 410                 if (!page)
 411                         return;
 412
 413                 spin_lock(&rxq->lock);
 414
 415                 if (list_empty(&rxq->rx_used)) {
 416                         spin_unlock(&rxq->lock);
 417                         __free_pages(page, trans_pcie->rx_page_order);
 418                         return;
 419                 }
 420                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 421                                        list);
 422                 list_del(&rxb->list);
 423                 spin_unlock(&rxq->lock);
 424
 425                 BUG_ON(rxb->page);
 426                 rxb->page = page;
 427                 /* Get physical address of the RB */
 428                 rxb->page_dma =
 429                         dma_map_page(trans->dev, page, 0,
 430                                      PAGE_SIZE << trans_pcie->rx_page_order,
 431                                      DMA_FROM_DEVICE);
 432                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 433                         rxb->page = NULL;
 434                         spin_lock(&rxq->lock);
 435                         list_add(&rxb->list, &rxq->rx_used);
 436                         spin_unlock(&rxq->lock);
 437                         __free_pages(page, trans_pcie->rx_page_order);
 438                         return;
 439                 }
 440
 441                 spin_lock(&rxq->lock);
 442
 443                 list_add_tail(&rxb->list, &rxq->rx_free);
 444                 rxq->free_count++;
 445
 446                 spin_unlock(&rxq->lock);
 447         }
 448 }
 449
 450 static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
 451 {
 452         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 453         int i;
 454
 455         for (i = 0; i < RX_POOL_SIZE; i++) {
 456                 if (!trans_pcie->rx_pool[i].page)
 457                         continue;
 458                 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
 459                                PAGE_SIZE << trans_pcie->rx_page_order,
 460                                DMA_FROM_DEVICE);
 461                 __free_pages(trans_pcie->rx_pool[i].page,
 462                              trans_pcie->rx_page_order);
 463                 trans_pcie->rx_pool[i].page = NULL;
 464         }
 465 }
 466
 467 /*
 468  * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
 469  *
 470  * Allocates for each received request 8 pages
 471  * Called as a scheduled work item.
 472  */
 473 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
 474 {
 475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 476         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 477         struct list_head local_empty;
 478         int pending = atomic_xchg(&rba->req_pending, 0);
 479
 480         IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending);
 481
 482         /* If we were scheduled - there is at least one request */
 483         spin_lock(&rba->lock);
 484         /* swap out the rba->rbd_empty to a local list */
 485         list_replace_init(&rba->rbd_empty, &local_empty);
 486         spin_unlock(&rba->lock);
 487
 488         while (pending) {
 489                 int i;
 490                 LIST_HEAD(local_allocated);
 491                 gfp_t gfp_mask = GFP_KERNEL;
 492
 493                 /* Do not post a warning if there are only a few requests */
 494                 if (pending < RX_PENDING_WATERMARK)
 495                         gfp_mask |= __GFP_NOWARN;
 496
 497                 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
 498                         struct iwl_rx_mem_buffer *rxb;
 499                         struct page *page;
 500
 501                         /* List should never be empty - each reused RBD is
 502                          * returned to the list, and initial pool covers any
 503                          * possible gap between the time the page is allocated
 504                          * to the time the RBD is added.
 505                          */
 506                         BUG_ON(list_empty(&local_empty));
 507                         /* Get the first rxb from the rbd list */
 508                         rxb = list_first_entry(&local_empty,
 509                                                struct iwl_rx_mem_buffer, list);
 510                         BUG_ON(rxb->page);
 511
 512                         /* Alloc a new receive buffer */
 513                         page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
 514                         if (!page)
 515                                 continue;
 516                         rxb->page = page;
 517
 518                         /* Get physical address of the RB */
 519                         rxb->page_dma = dma_map_page(trans->dev, page, 0,
 520                                         PAGE_SIZE << trans_pcie->rx_page_order,
 521                                         DMA_FROM_DEVICE);
 522                         if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 523                                 rxb->page = NULL;
 524                                 __free_pages(page, trans_pcie->rx_page_order);
 525                                 continue;
 526                         }
 527
 528                         /* move the allocated entry to the out list */
 529                         list_move(&rxb->list, &local_allocated);
 530                         i++;
 531                 }
 532
 533                 pending--;
 534                 if (!pending) {
 535                         pending = atomic_xchg(&rba->req_pending, 0);
 536                         IWL_DEBUG_RX(trans,
 537                                      "Pending allocation requests = %d\n",
 538                                      pending);
 539                 }
 540
 541                 spin_lock(&rba->lock);
 542                 /* add the allocated rbds to the allocator allocated list */
 543                 list_splice_tail(&local_allocated, &rba->rbd_allocated);
 544                 /* get more empty RBDs for current pending requests */
 545                 list_splice_tail_init(&rba->rbd_empty, &local_empty);
 546                 spin_unlock(&rba->lock);
 547
 548                 atomic_inc(&rba->req_ready);
 549         }
 550
 551         spin_lock(&rba->lock);
 552         /* return unused rbds to the allocator empty list */
 553         list_splice_tail(&local_empty, &rba->rbd_empty);
 554         spin_unlock(&rba->lock);
 555 }
 556
 557 /*
 558  * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
 559 .*
 560 .* Called by queue when the queue posted allocation request and
 561  * has freed 8 RBDs in order to restock itself.
 562  * This function directly moves the allocated RBs to the queue's ownership
 563  * and updates the relevant counters.
 564  */
 565 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
 566                                       struct iwl_rxq *rxq)
 567 {
 568         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 569         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 570         int i;
 571
 572         lockdep_assert_held(&rxq->lock);
 573
 574         /*
 575          * atomic_dec_if_positive returns req_ready - 1 for any scenario.
 576          * If req_ready is 0 atomic_dec_if_positive will return -1 and this
 577          * function will return early, as there are no ready requests.
 578          * atomic_dec_if_positive will perofrm the *actual* decrement only if
 579          * req_ready > 0, i.e. - there are ready requests and the function
 580          * hands one request to the caller.
 581          */
 582         if (atomic_dec_if_positive(&rba->req_ready) < 0)
 583                 return;
 584
 585         spin_lock(&rba->lock);
 586         for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
 587                 /* Get next free Rx buffer, remove it from free list */
 588                 struct iwl_rx_mem_buffer *rxb =
 589                         list_first_entry(&rba->rbd_allocated,
 590                                          struct iwl_rx_mem_buffer, list);
 591
 592                 list_move(&rxb->list, &rxq->rx_free);
 593         }
 594         spin_unlock(&rba->lock);
 595
 596         rxq->used_count -= RX_CLAIM_REQ_ALLOC;
 597         rxq->free_count += RX_CLAIM_REQ_ALLOC;
 598 }
 599
 600 void iwl_pcie_rx_allocator_work(struct work_struct *data)
 601 {
 602         struct iwl_rb_allocator *rba_p =
 603                 container_of(data, struct iwl_rb_allocator, rx_alloc);
 604         struct iwl_trans_pcie *trans_pcie =
 605                 container_of(rba_p, struct iwl_trans_pcie, rba);
 606
 607         iwl_pcie_rx_allocator(trans_pcie->trans);
 608 }
 609
 610 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 611 {
 612         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 613         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 614         struct device *dev = trans->dev;
 615         int i;
 616         int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) :
 617                                                       sizeof(__le32);
 618
 619         if (WARN_ON(trans_pcie->rxq))
 620                 return -EINVAL;
 621
 622         trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
 623                                   GFP_KERNEL);
 624         if (!trans_pcie->rxq)
 625                 return -EINVAL;
 626
 627         spin_lock_init(&rba->lock);
 628
 629         for (i = 0; i < trans->num_rx_queues; i++) {
 630                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 631
 632                 spin_lock_init(&rxq->lock);
 633                 if (trans->cfg->mq_rx_supported)
 634                         rxq->queue_size = MQ_RX_TABLE_SIZE;
 635                 else
 636                         rxq->queue_size = RX_QUEUE_SIZE;
 637
 638                 /*
 639                  * Allocate the circular buffer of Read Buffer Descriptors
 640                  * (RBDs)
 641                  */
 642                 rxq->bd = dma_zalloc_coherent(dev,
 643                                              free_size * rxq->queue_size,
 644                                              &rxq->bd_dma, GFP_KERNEL);
 645                 if (!rxq->bd)
 646                         goto err;
 647
 648                 if (trans->cfg->mq_rx_supported) {
 649                         rxq->used_bd = dma_zalloc_coherent(dev,
 650                                                            sizeof(__le32) *
 651                                                            rxq->queue_size,
 652                                                            &rxq->used_bd_dma,
 653                                                            GFP_KERNEL);
 654                         if (!rxq->used_bd)
 655                                 goto err;
 656                 }
 657
 658                 /*Allocate the driver's pointer to receive buffer status */
 659                 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 660                                                    &rxq->rb_stts_dma,
 661                                                    GFP_KERNEL);
 662                 if (!rxq->rb_stts)
 663                         goto err;
 664         }
 665         return 0;
 666
 667 err:
 668         for (i = 0; i < trans->num_rx_queues; i++) {
 669                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 670
 671                 if (rxq->bd)
 672                         dma_free_coherent(dev, free_size * rxq->queue_size,
 673                                           rxq->bd, rxq->bd_dma);
 674                 rxq->bd_dma = 0;
 675                 rxq->bd = NULL;
 676
 677                 if (rxq->rb_stts)
 678                         dma_free_coherent(trans->dev,
 679                                           sizeof(struct iwl_rb_status),
 680                                           rxq->rb_stts, rxq->rb_stts_dma);
 681
 682                 if (rxq->used_bd)
 683                         dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size,
 684                                           rxq->used_bd, rxq->used_bd_dma);
 685                 rxq->used_bd_dma = 0;
 686                 rxq->used_bd = NULL;
 687         }
 688         kfree(trans_pcie->rxq);
 689
 690         return -ENOMEM;
 691 }
 692
 693 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 694 {
 695         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 696         u32 rb_size;
 697         unsigned long flags;
 698         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 699
 700         switch (trans_pcie->rx_buf_size) {
 701         case IWL_AMSDU_4K:
 702                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 703                 break;
 704         case IWL_AMSDU_8K:
 705                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 706                 break;
 707         case IWL_AMSDU_12K:
 708                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
 709                 break;
 710         default:
 711                 WARN_ON(1);
 712                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 713         }
 714
 715         if (!iwl_trans_grab_nic_access(trans, &flags))
 716                 return;
 717
 718         /* Stop Rx DMA */
 719         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 720         /* reset and flush pointers */
 721         iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 722         iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 723         iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 724
 725         /* Reset driver's Rx queue write index */
 726         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 727
 728         /* Tell device where to find RBD circular buffer in DRAM */
 729         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 730                     (u32)(rxq->bd_dma >> 8));
 731
 732         /* Tell device where in DRAM to update its Rx status */
 733         iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 734                     rxq->rb_stts_dma >> 4);
 735
 736         /* Enable Rx DMA
 737          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 738          *      the credit mechanism in 5000 HW RX FIFO
 739          * Direct rx interrupts to hosts
 740          * Rx buffer size 4 or 8k or 12k
 741          * RB timeout 0x10
 742          * 256 RBDs
 743          */
 744         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 745                     FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 746                     FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 747                     FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 748                     rb_size |
 749                     (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 750                     (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 751
 752         iwl_trans_release_nic_access(trans, &flags);
 753
 754         /* Set interrupt coalescing timer to default (2048 usecs) */
 755         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 756
 757         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 758         if (trans->cfg->host_interrupt_operation_mode)
 759                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 760 }
 761
 762 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable)
 763 {
 764         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000)
 765                 return;
 766
 767         if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP)
 768                 return;
 769
 770         if (!trans->cfg->integrated)
 771                 return;
 772
 773         /*
 774          * Turn on the chicken-bits that cause MAC wakeup for RX-related
 775          * values.
 776          * This costs some power, but needed for W/A 9000 integrated A-step
 777          * bug where shadow registers are not in the retention list and their
 778          * value is lost when NIC powers down
 779          */
 780         iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 781                     CSR_MAC_SHADOW_REG_CTRL_RX_WAKE);
 782         iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2,
 783                     CSR_MAC_SHADOW_REG_CTL2_RX_WAKE);
 784 }
 785
 786 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 787 {
 788         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 789         u32 rb_size, enabled = 0;
 790         unsigned long flags;
 791         int i;
 792
 793         switch (trans_pcie->rx_buf_size) {
 794         case IWL_AMSDU_4K:
 795                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 796                 break;
 797         case IWL_AMSDU_8K:
 798                 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
 799                 break;
 800         case IWL_AMSDU_12K:
 801                 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
 802                 break;
 803         default:
 804                 WARN_ON(1);
 805                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 806         }
 807
 808         if (!iwl_trans_grab_nic_access(trans, &flags))
 809                 return;
 810
 811         /* Stop Rx DMA */
 812         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 813         /* disable free amd used rx queue operation */
 814         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
 815
 816         for (i = 0; i < trans->num_rx_queues; i++) {
 817                 /* Tell device where to find RBD free table in DRAM */
 818                 iwl_write_prph64_no_grab(trans,
 819                                          RFH_Q_FRBDCB_BA_LSB(i),
 820                                          trans_pcie->rxq[i].bd_dma);
 821                 /* Tell device where to find RBD used table in DRAM */
 822                 iwl_write_prph64_no_grab(trans,
 823                                          RFH_Q_URBDCB_BA_LSB(i),
 824                                          trans_pcie->rxq[i].used_bd_dma);
 825                 /* Tell device where in DRAM to update its Rx status */
 826                 iwl_write_prph64_no_grab(trans,
 827                                          RFH_Q_URBD_STTS_WPTR_LSB(i),
 828                                          trans_pcie->rxq[i].rb_stts_dma);
 829                 /* Reset device indice tables */
 830                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
 831                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
 832                 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
 833
 834                 enabled |= BIT(i) | BIT(i + 16);
 835         }
 836
 837         /*
 838          * Enable Rx DMA
 839          * Rx buffer size 4 or 8k or 12k
 840          * Min RB size 4 or 8
 841          * Drop frames that exceed RB size
 842          * 512 RBDs
 843          */
 844         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
 845                                RFH_DMA_EN_ENABLE_VAL | rb_size |
 846                                RFH_RXF_DMA_MIN_RB_4_8 |
 847                                RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
 848                                RFH_RXF_DMA_RBDCB_SIZE_512);
 849
 850         /*
 851          * Activate DMA snooping.
 852          * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
 853          * Default queue is 0
 854          */
 855         iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
 856                                RFH_GEN_CFG_RFH_DMA_SNOOP |
 857                                RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
 858                                RFH_GEN_CFG_SERVICE_DMA_SNOOP |
 859                                RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
 860                                                trans->cfg->integrated ?
 861                                                RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
 862                                                RFH_GEN_CFG_RB_CHUNK_SIZE_128));
 863         /* Enable the relevant rx queues */
 864         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
 865
 866         iwl_trans_release_nic_access(trans, &flags);
 867
 868         /* Set interrupt coalescing timer to default (2048 usecs) */
 869         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 870
 871         iwl_pcie_enable_rx_wake(trans, true);
 872 }
 873
 874 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 875 {
 876         lockdep_assert_held(&rxq->lock);
 877
 878         INIT_LIST_HEAD(&rxq->rx_free);
 879         INIT_LIST_HEAD(&rxq->rx_used);
 880         rxq->free_count = 0;
 881         rxq->used_count = 0;
 882 }
 883
 884 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
 885 {
 886         WARN_ON(1);
 887         return 0;
 888 }
 889
 890 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
 891 {
 892         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 893         struct iwl_rxq *def_rxq;
 894         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 895         int i, err, queue_size, allocator_pool_size, num_alloc;
 896
 897         if (!trans_pcie->rxq) {
 898                 err = iwl_pcie_rx_alloc(trans);
 899                 if (err)
 900                         return err;
 901         }
 902         def_rxq = trans_pcie->rxq;
 903
 904         spin_lock(&rba->lock);
 905         atomic_set(&rba->req_pending, 0);
 906         atomic_set(&rba->req_ready, 0);
 907         INIT_LIST_HEAD(&rba->rbd_allocated);
 908         INIT_LIST_HEAD(&rba->rbd_empty);
 909         spin_unlock(&rba->lock);
 910
 911         /* free all first - we might be reconfigured for a different size */
 912         iwl_pcie_free_rbs_pool(trans);
 913
 914         for (i = 0; i < RX_QUEUE_SIZE; i++)
 915                 def_rxq->queue[i] = NULL;
 916
 917         for (i = 0; i < trans->num_rx_queues; i++) {
 918                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 919
 920                 rxq->id = i;
 921
 922                 spin_lock(&rxq->lock);
 923                 /*
 924                  * Set read write pointer to reflect that we have processed
 925                  * and used all buffers, but have not restocked the Rx queue
 926                  * with fresh buffers
 927                  */
 928                 rxq->read = 0;
 929                 rxq->write = 0;
 930                 rxq->write_actual = 0;
 931                 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 932
 933                 iwl_pcie_rx_init_rxb_lists(rxq);
 934
 935                 if (!rxq->napi.poll)
 936                         netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
 937                                        iwl_pcie_dummy_napi_poll, 64);
 938
 939                 spin_unlock(&rxq->lock);
 940         }
 941
 942         /* move the pool to the default queue and allocator ownerships */
 943         queue_size = trans->cfg->mq_rx_supported ?
 944                      MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
 945         allocator_pool_size = trans->num_rx_queues *
 946                 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
 947         num_alloc = queue_size + allocator_pool_size;
 948         BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
 949                      ARRAY_SIZE(trans_pcie->rx_pool));
 950         for (i = 0; i < num_alloc; i++) {
 951                 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
 952
 953                 if (i < allocator_pool_size)
 954                         list_add(&rxb->list, &rba->rbd_empty);
 955                 else
 956                         list_add(&rxb->list, &def_rxq->rx_used);
 957                 trans_pcie->global_table[i] = rxb;
 958                 rxb->vid = (u16)(i + 1);
 959                 rxb->invalid = true;
 960         }
 961
 962         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
 963
 964         return 0;
 965 }
 966
 967 int iwl_pcie_rx_init(struct iwl_trans *trans)
 968 {
 969         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 970         int ret = _iwl_pcie_rx_init(trans);
 971
 972         if (ret)
 973                 return ret;
 974
 975         if (trans->cfg->mq_rx_supported)
 976                 iwl_pcie_rx_mq_hw_init(trans);
 977         else
 978                 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
 979
 980         iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
 981
 982         spin_lock(&trans_pcie->rxq->lock);
 983         iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
 984         spin_unlock(&trans_pcie->rxq->lock);
 985
 986         return 0;
 987 }
 988
 989 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
 990 {
 991         /*
 992          * We don't configure the RFH.
 993          * Restock will be done at alive, after firmware configured the RFH.
 994          */
 995         return _iwl_pcie_rx_init(trans);
 996 }
 997
 998 void iwl_pcie_rx_free(struct iwl_trans *trans)
 999 {
1000         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1001         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1002         int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) :
1003                                               sizeof(__le32);
1004         int i;
1005
1006         /*
1007          * if rxq is NULL, it means that nothing has been allocated,
1008          * exit now
1009          */
1010         if (!trans_pcie->rxq) {
1011                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1012                 return;
1013         }
1014
1015         cancel_work_sync(&rba->rx_alloc);
1016
1017         iwl_pcie_free_rbs_pool(trans);
1018
1019         for (i = 0; i < trans->num_rx_queues; i++) {
1020                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1021
1022                 if (rxq->bd)
1023                         dma_free_coherent(trans->dev,
1024                                           free_size * rxq->queue_size,
1025                                           rxq->bd, rxq->bd_dma);
1026                 rxq->bd_dma = 0;
1027                 rxq->bd = NULL;
1028
1029                 if (rxq->rb_stts)
1030                         dma_free_coherent(trans->dev,
1031                                           sizeof(struct iwl_rb_status),
1032                                           rxq->rb_stts, rxq->rb_stts_dma);
1033                 else
1034                         IWL_DEBUG_INFO(trans,
1035                                        "Free rxq->rb_stts which is NULL\n");
1036
1037                 if (rxq->used_bd)
1038                         dma_free_coherent(trans->dev,
1039                                           sizeof(__le32) * rxq->queue_size,
1040                                           rxq->used_bd, rxq->used_bd_dma);
1041                 rxq->used_bd_dma = 0;
1042                 rxq->used_bd = NULL;
1043
1044                 if (rxq->napi.poll)
1045                         netif_napi_del(&rxq->napi);
1046         }
1047         kfree(trans_pcie->rxq);
1048 }
1049
1050 /*
1051  * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1052  *
1053  * Called when a RBD can be reused. The RBD is transferred to the allocator.
1054  * When there are 2 empty RBDs - a request for allocation is posted
1055  */
1056 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1057                                   struct iwl_rx_mem_buffer *rxb,
1058                                   struct iwl_rxq *rxq, bool emergency)
1059 {
1060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1062
1063         /* Move the RBD to the used list, will be moved to allocator in batches
1064          * before claiming or posting a request*/
1065         list_add_tail(&rxb->list, &rxq->rx_used);
1066
1067         if (unlikely(emergency))
1068                 return;
1069
1070         /* Count the allocator owned RBDs */
1071         rxq->used_count++;
1072
1073         /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1074          * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1075          * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1076          * after but we still need to post another request.
1077          */
1078         if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1079                 /* Move the 2 RBDs to the allocator ownership.
1080                  Allocator has another 6 from pool for the request completion*/
1081                 spin_lock(&rba->lock);
1082                 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1083                 spin_unlock(&rba->lock);
1084
1085                 atomic_inc(&rba->req_pending);
1086                 queue_work(rba->alloc_wq, &rba->rx_alloc);
1087         }
1088 }
1089
1090 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1091                                 struct iwl_rxq *rxq,
1092                                 struct iwl_rx_mem_buffer *rxb,
1093                                 bool emergency)
1094 {
1095         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1096         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1097         bool page_stolen = false;
1098         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1099         u32 offset = 0;
1100
1101         if (WARN_ON(!rxb))
1102                 return;
1103
1104         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1105
1106         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1107                 struct iwl_rx_packet *pkt;
1108                 u16 sequence;
1109                 bool reclaim;
1110                 int index, cmd_index, len;
1111                 struct iwl_rx_cmd_buffer rxcb = {
1112                         ._offset = offset,
1113                         ._rx_page_order = trans_pcie->rx_page_order,
1114                         ._page = rxb->page,
1115                         ._page_stolen = false,
1116                         .truesize = max_len,
1117                 };
1118
1119                 pkt = rxb_addr(&rxcb);
1120
1121                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1122                         IWL_DEBUG_RX(trans,
1123                                      "Q %d: RB end marker at offset %d\n",
1124                                      rxq->id, offset);
1125                         break;
1126                 }
1127
1128                 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1129                         FH_RSCSR_RXQ_POS != rxq->id,
1130                      "frame on invalid queue - is on %d and indicates %d\n",
1131                      rxq->id,
1132                      (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1133                         FH_RSCSR_RXQ_POS);
1134
1135                 IWL_DEBUG_RX(trans,
1136                              "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1137                              rxq->id, offset,
1138                              iwl_get_cmd_string(trans,
1139                                                 iwl_cmd_id(pkt->hdr.cmd,
1140                                                            pkt->hdr.group_id,
1141                                                            0)),
1142                              pkt->hdr.group_id, pkt->hdr.cmd,
1143                              le16_to_cpu(pkt->hdr.sequence));
1144
1145                 len = iwl_rx_packet_len(pkt);
1146                 len += sizeof(u32); /* account for status word */
1147                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1148                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1149
1150                 /* Reclaim a command buffer only if this packet is a response
1151                  *   to a (driver-originated) command.
1152                  * If the packet (e.g. Rx frame) originated from uCode,
1153                  *   there is no command buffer to reclaim.
1154                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1155                  *   but apparently a few don't get set; catch them here. */
1156                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1157                 if (reclaim && !pkt->hdr.group_id) {
1158                         int i;
1159
1160                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1161                                 if (trans_pcie->no_reclaim_cmds[i] ==
1162                                                         pkt->hdr.cmd) {
1163                                         reclaim = false;
1164                                         break;
1165                                 }
1166                         }
1167                 }
1168
1169                 sequence = le16_to_cpu(pkt->hdr.sequence);
1170                 index = SEQ_TO_INDEX(sequence);
1171                 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1172
1173                 if (rxq->id == 0)
1174                         iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1175                                        &rxcb);
1176                 else
1177                         iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1178                                            &rxcb, rxq->id);
1179
1180                 if (reclaim) {
1181                         kzfree(txq->entries[cmd_index].free_buf);
1182                         txq->entries[cmd_index].free_buf = NULL;
1183                 }
1184
1185                 /*
1186                  * After here, we should always check rxcb._page_stolen,
1187                  * if it is true then one of the handlers took the page.
1188                  */
1189
1190                 if (reclaim) {
1191                         /* Invoke any callbacks, transfer the buffer to caller,
1192                          * and fire off the (possibly) blocking
1193                          * iwl_trans_send_cmd()
1194                          * as we reclaim the driver command queue */
1195                         if (!rxcb._page_stolen)
1196                                 iwl_pcie_hcmd_complete(trans, &rxcb);
1197                         else
1198                                 IWL_WARN(trans, "Claim null rxb?\n");
1199                 }
1200
1201                 page_stolen |= rxcb._page_stolen;
1202                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1203         }
1204
1205         /* page was stolen from us -- free our reference */
1206         if (page_stolen) {
1207                 __free_pages(rxb->page, trans_pcie->rx_page_order);
1208                 rxb->page = NULL;
1209         }
1210
1211         /* Reuse the page if possible. For notification packets and
1212          * SKBs that fail to Rx correctly, add them back into the
1213          * rx_free list for reuse later. */
1214         if (rxb->page != NULL) {
1215                 rxb->page_dma =
1216                         dma_map_page(trans->dev, rxb->page, 0,
1217                                      PAGE_SIZE << trans_pcie->rx_page_order,
1218                                      DMA_FROM_DEVICE);
1219                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1220                         /*
1221                          * free the page(s) as well to not break
1222                          * the invariant that the items on the used
1223                          * list have no page(s)
1224                          */
1225                         __free_pages(rxb->page, trans_pcie->rx_page_order);
1226                         rxb->page = NULL;
1227                         iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1228                 } else {
1229                         list_add_tail(&rxb->list, &rxq->rx_free);
1230                         rxq->free_count++;
1231                 }
1232         } else
1233                 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1234 }
1235
1236 /*
1237  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1238  */
1239 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1240 {
1241         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1242         struct iwl_rxq *rxq = &trans_pcie->rxq[queue];
1243         u32 r, i, count = 0;
1244         bool emergency = false;
1245
1246 restart:
1247         spin_lock(&rxq->lock);
1248         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1249          * buffer that the driver may process (last buffer filled by ucode). */
1250         r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
1251         i = rxq->read;
1252
1253         /* W/A 9000 device step A0 wrap-around bug */
1254         r &= (rxq->queue_size - 1);
1255
1256         /* Rx interrupt, but nothing sent from uCode */
1257         if (i == r)
1258                 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1259
1260         while (i != r) {
1261                 struct iwl_rx_mem_buffer *rxb;
1262
1263                 if (unlikely(rxq->used_count == rxq->queue_size / 2))
1264                         emergency = true;
1265
1266                 if (trans->cfg->mq_rx_supported) {
1267                         /*
1268                          * used_bd is a 32 bit but only 12 are used to retrieve
1269                          * the vid
1270                          */
1271                         u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF;
1272
1273                         if (WARN(!vid ||
1274                                  vid > ARRAY_SIZE(trans_pcie->global_table),
1275                                  "Invalid rxb index from HW %u\n", (u32)vid)) {
1276                                 iwl_force_nmi(trans);
1277                                 goto out;
1278                         }
1279                         rxb = trans_pcie->global_table[vid - 1];
1280                         if (WARN(rxb->invalid,
1281                                  "Invalid rxb from HW %u\n", (u32)vid)) {
1282                                 iwl_force_nmi(trans);
1283                                 goto out;
1284                         }
1285                         rxb->invalid = true;
1286                 } else {
1287                         rxb = rxq->queue[i];
1288                         rxq->queue[i] = NULL;
1289                 }
1290
1291                 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1292                 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency);
1293
1294                 i = (i + 1) & (rxq->queue_size - 1);
1295
1296                 /*
1297                  * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1298                  * try to claim the pre-allocated buffers from the allocator.
1299                  * If not ready - will try to reclaim next time.
1300                  * There is no need to reschedule work - allocator exits only
1301                  * on success
1302                  */
1303                 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1304                         iwl_pcie_rx_allocator_get(trans, rxq);
1305
1306                 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1307                         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1308
1309                         /* Add the remaining empty RBDs for allocator use */
1310                         spin_lock(&rba->lock);
1311                         list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1312                         spin_unlock(&rba->lock);
1313                 } else if (emergency) {
1314                         count++;
1315                         if (count == 8) {
1316                                 count = 0;
1317                                 if (rxq->used_count < rxq->queue_size / 3)
1318                                         emergency = false;
1319
1320                                 rxq->read = i;
1321                                 spin_unlock(&rxq->lock);
1322                                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1323                                 iwl_pcie_rxq_restock(trans, rxq);
1324                                 goto restart;
1325                         }
1326                 }
1327         }
1328 out:
1329         /* Backtrack one entry */
1330         rxq->read = i;
1331         spin_unlock(&rxq->lock);
1332
1333         /*
1334          * handle a case where in emergency there are some unallocated RBDs.
1335          * those RBDs are in the used list, but are not tracked by the queue's
1336          * used_count which counts allocator owned RBDs.
1337          * unallocated emergency RBDs must be allocated on exit, otherwise
1338          * when called again the function may not be in emergency mode and
1339          * they will be handed to the allocator with no tracking in the RBD
1340          * allocator counters, which will lead to them never being claimed back
1341          * by the queue.
1342          * by allocating them here, they are now in the queue free list, and
1343          * will be restocked by the next call of iwl_pcie_rxq_restock.
1344          */
1345         if (unlikely(emergency && count))
1346                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1347
1348         if (rxq->napi.poll)
1349                 napi_gro_flush(&rxq->napi, false);
1350
1351         iwl_pcie_rxq_restock(trans, rxq);
1352 }
1353
1354 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1355 {
1356         u8 queue = entry->entry;
1357         struct msix_entry *entries = entry - queue;
1358
1359         return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1360 }
1361
1362 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
1363                                       struct msix_entry *entry)
1364 {
1365         /*
1366          * Before sending the interrupt the HW disables it to prevent
1367          * a nested interrupt. This is done by writing 1 to the corresponding
1368          * bit in the mask register. After handling the interrupt, it should be
1369          * re-enabled by clearing this bit. This register is defined as
1370          * write 1 clear (W1C) register, meaning that it's being clear
1371          * by writing 1 to the bit.
1372          */
1373         iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
1374 }
1375
1376 /*
1377  * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1378  * This interrupt handler should be used with RSS queue only.
1379  */
1380 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1381 {
1382         struct msix_entry *entry = dev_id;
1383         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1384         struct iwl_trans *trans = trans_pcie->trans;
1385
1386         trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1387
1388         if (WARN_ON(entry->entry >= trans->num_rx_queues))
1389                 return IRQ_NONE;
1390
1391         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1392
1393         local_bh_disable();
1394         iwl_pcie_rx_handle(trans, entry->entry);
1395         local_bh_enable();
1396
1397         iwl_pcie_clear_irq(trans, entry);
1398
1399         lock_map_release(&trans->sync_cmd_lockdep_map);
1400
1401         return IRQ_HANDLED;
1402 }
1403
1404 /*
1405  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1406  */
1407 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1408 {
1409         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1410         int i;
1411
1412         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1413         if (trans->cfg->internal_wimax_coex &&
1414             !trans->cfg->apmg_not_supported &&
1415             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1416                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
1417              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1418                             APMG_PS_CTRL_VAL_RESET_REQ))) {
1419                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1420                 iwl_op_mode_wimax_active(trans->op_mode);
1421                 wake_up(&trans_pcie->wait_command_queue);
1422                 return;
1423         }
1424
1425         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1426                 if (!trans_pcie->txq[i])
1427                         continue;
1428                 del_timer(&trans_pcie->txq[i]->stuck_timer);
1429         }
1430
1431         /* The STATUS_FW_ERROR bit is set in this function. This must happen
1432          * before we wake up the command caller, to ensure a proper cleanup. */
1433         iwl_trans_fw_error(trans);
1434
1435         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1436         wake_up(&trans_pcie->wait_command_queue);
1437 }
1438
1439 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1440 {
1441         u32 inta;
1442
1443         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1444
1445         trace_iwlwifi_dev_irq(trans->dev);
1446
1447         /* Discover which interrupts are active/pending */
1448         inta = iwl_read32(trans, CSR_INT);
1449
1450         /* the thread will service interrupts and re-enable them */
1451         return inta;
1452 }
1453
1454 /* a device (PCI-E) page is 4096 bytes long */
1455 #define ICT_SHIFT       12
1456 #define ICT_SIZE        (1 << ICT_SHIFT)
1457 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1458
1459 /* interrupt handler using ict table, with this interrupt driver will
1460  * stop using INTA register to get device's interrupt, reading this register
1461  * is expensive, device will write interrupts in ICT dram table, increment
1462  * index then will fire interrupt to driver, driver will OR all ICT table
1463  * entries from current index up to table entry with 0 value. the result is
1464  * the interrupt we need to service, driver will set the entries back to 0 and
1465  * set index.
1466  */
1467 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1468 {
1469         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1470         u32 inta;
1471         u32 val = 0;
1472         u32 read;
1473
1474         trace_iwlwifi_dev_irq(trans->dev);
1475
1476         /* Ignore interrupt if there's nothing in NIC to service.
1477          * This may be due to IRQ shared with another device,
1478          * or due to sporadic interrupts thrown from our NIC. */
1479         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1480         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1481         if (!read)
1482                 return 0;
1483
1484         /*
1485          * Collect all entries up to the first 0, starting from ict_index;
1486          * note we already read at ict_index.
1487          */
1488         do {
1489                 val |= read;
1490                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1491                                 trans_pcie->ict_index, read);
1492                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1493                 trans_pcie->ict_index =
1494                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1495
1496                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1497                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1498                                            read);
1499         } while (read);
1500
1501         /* We should not get this value, just ignore it. */
1502         if (val == 0xffffffff)
1503                 val = 0;
1504
1505         /*
1506          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1507          * (bit 15 before shifting it to 31) to clear when using interrupt
1508          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1509          * so we use them to decide on the real state of the Rx bit.
1510          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1511          */
1512         if (val & 0xC0000)
1513                 val |= 0x8000;
1514
1515         inta = (0xff & val) | ((0xff00 & val) << 16);
1516         return inta;
1517 }
1518
1519 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1520 {
1521         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1522         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1523         bool hw_rfkill, prev, report;
1524
1525         mutex_lock(&trans_pcie->mutex);
1526         prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1527         hw_rfkill = iwl_is_rfkill_set(trans);
1528         if (hw_rfkill) {
1529                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1530                 set_bit(STATUS_RFKILL_HW, &trans->status);
1531         }
1532         if (trans_pcie->opmode_down)
1533                 report = hw_rfkill;
1534         else
1535                 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1536
1537         IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1538                  hw_rfkill ? "disable radio" : "enable radio");
1539
1540         isr_stats->rfkill++;
1541
1542         if (prev != report)
1543                 iwl_trans_pcie_rf_kill(trans, report);
1544         mutex_unlock(&trans_pcie->mutex);
1545
1546         if (hw_rfkill) {
1547                 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1548                                        &trans->status))
1549                         IWL_DEBUG_RF_KILL(trans,
1550                                           "Rfkill while SYNC HCMD in flight\n");
1551                 wake_up(&trans_pcie->wait_command_queue);
1552         } else {
1553                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1554                 if (trans_pcie->opmode_down)
1555                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1556         }
1557 }
1558
1559 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1560 {
1561         struct iwl_trans *trans = dev_id;
1562         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1563         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1564         u32 inta = 0;
1565         u32 handled = 0;
1566
1567         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1568
1569         spin_lock(&trans_pcie->irq_lock);
1570
1571         /* dram interrupt table not set yet,
1572          * use legacy interrupt.
1573          */
1574         if (likely(trans_pcie->use_ict))
1575                 inta = iwl_pcie_int_cause_ict(trans);
1576         else
1577                 inta = iwl_pcie_int_cause_non_ict(trans);
1578
1579         if (iwl_have_debug_level(IWL_DL_ISR)) {
1580                 IWL_DEBUG_ISR(trans,
1581                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1582                               inta, trans_pcie->inta_mask,
1583                               iwl_read32(trans, CSR_INT_MASK),
1584                               iwl_read32(trans, CSR_FH_INT_STATUS));
1585                 if (inta & (~trans_pcie->inta_mask))
1586                         IWL_DEBUG_ISR(trans,
1587                                       "We got a masked interrupt (0x%08x)\n",
1588                                       inta & (~trans_pcie->inta_mask));
1589         }
1590
1591         inta &= trans_pcie->inta_mask;
1592
1593         /*
1594          * Ignore interrupt if there's nothing in NIC to service.
1595          * This may be due to IRQ shared with another device,
1596          * or due to sporadic interrupts thrown from our NIC.
1597          */
1598         if (unlikely(!inta)) {
1599                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1600                 /*
1601                  * Re-enable interrupts here since we don't
1602                  * have anything to service
1603                  */
1604                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1605                         _iwl_enable_interrupts(trans);
1606                 spin_unlock(&trans_pcie->irq_lock);
1607                 lock_map_release(&trans->sync_cmd_lockdep_map);
1608                 return IRQ_NONE;
1609         }
1610
1611         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1612                 /*
1613                  * Hardware disappeared. It might have
1614                  * already raised an interrupt.
1615                  */
1616                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1617                 spin_unlock(&trans_pcie->irq_lock);
1618                 goto out;
1619         }
1620
1621         /* Ack/clear/reset pending uCode interrupts.
1622          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1623          */
1624         /* There is a hardware bug in the interrupt mask function that some
1625          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1626          * they are disabled in the CSR_INT_MASK register. Furthermore the
1627          * ICT interrupt handling mechanism has another bug that might cause
1628          * these unmasked interrupts fail to be detected. We workaround the
1629          * hardware bugs here by ACKing all the possible interrupts so that
1630          * interrupt coalescing can still be achieved.
1631          */
1632         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1633
1634         if (iwl_have_debug_level(IWL_DL_ISR))
1635                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1636                               inta, iwl_read32(trans, CSR_INT_MASK));
1637
1638         spin_unlock(&trans_pcie->irq_lock);
1639
1640         /* Now service all interrupt bits discovered above. */
1641         if (inta & CSR_INT_BIT_HW_ERR) {
1642                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
1643
1644                 /* Tell the device to stop sending interrupts */
1645                 iwl_disable_interrupts(trans);
1646
1647                 isr_stats->hw++;
1648                 iwl_pcie_irq_handle_error(trans);
1649
1650                 handled |= CSR_INT_BIT_HW_ERR;
1651
1652                 goto out;
1653         }
1654
1655         if (iwl_have_debug_level(IWL_DL_ISR)) {
1656                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1657                 if (inta & CSR_INT_BIT_SCD) {
1658                         IWL_DEBUG_ISR(trans,
1659                                       "Scheduler finished to transmit the frame/frames.\n");
1660                         isr_stats->sch++;
1661                 }
1662
1663                 /* Alive notification via Rx interrupt will do the real work */
1664                 if (inta & CSR_INT_BIT_ALIVE) {
1665                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1666                         isr_stats->alive++;
1667                         if (trans->cfg->gen2) {
1668                                 /*
1669                                  * We can restock, since firmware configured
1670                                  * the RFH
1671                                  */
1672                                 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1673                         }
1674                 }
1675         }
1676
1677         /* Safely ignore these bits for debug checks below */
1678         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1679
1680         /* HW RF KILL switch toggled */
1681         if (inta & CSR_INT_BIT_RF_KILL) {
1682                 iwl_pcie_handle_rfkill_irq(trans);
1683                 handled |= CSR_INT_BIT_RF_KILL;
1684         }
1685
1686         /* Chip got too hot and stopped itself */
1687         if (inta & CSR_INT_BIT_CT_KILL) {
1688                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1689                 isr_stats->ctkill++;
1690                 handled |= CSR_INT_BIT_CT_KILL;
1691         }
1692
1693         /* Error detected by uCode */
1694         if (inta & CSR_INT_BIT_SW_ERR) {
1695                 IWL_ERR(trans, "Microcode SW error detected. "
1696                         " Restarting 0x%X.\n", inta);
1697                 isr_stats->sw++;
1698                 iwl_pcie_irq_handle_error(trans);
1699                 handled |= CSR_INT_BIT_SW_ERR;
1700         }
1701
1702         /* uCode wakes up after power-down sleep */
1703         if (inta & CSR_INT_BIT_WAKEUP) {
1704                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1705                 iwl_pcie_rxq_check_wrptr(trans);
1706                 iwl_pcie_txq_check_wrptrs(trans);
1707
1708                 isr_stats->wakeup++;
1709
1710                 handled |= CSR_INT_BIT_WAKEUP;
1711         }
1712
1713         /* All uCode command responses, including Tx command responses,
1714          * Rx "responses" (frame-received notification), and other
1715          * notifications from uCode come through here*/
1716         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1717                     CSR_INT_BIT_RX_PERIODIC)) {
1718                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1719                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1720                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1721                         iwl_write32(trans, CSR_FH_INT_STATUS,
1722                                         CSR_FH_INT_RX_MASK);
1723                 }
1724                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1725                         handled |= CSR_INT_BIT_RX_PERIODIC;
1726                         iwl_write32(trans,
1727                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1728                 }
1729                 /* Sending RX interrupt require many steps to be done in the
1730                  * the device:
1731                  * 1- write interrupt to current index in ICT table.
1732                  * 2- dma RX frame.
1733                  * 3- update RX shared data to indicate last write index.
1734                  * 4- send interrupt.
1735                  * This could lead to RX race, driver could receive RX interrupt
1736                  * but the shared data changes does not reflect this;
1737                  * periodic interrupt will detect any dangling Rx activity.
1738                  */
1739
1740                 /* Disable periodic interrupt; we use it as just a one-shot. */
1741                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1742                             CSR_INT_PERIODIC_DIS);
1743
1744                 /*
1745                  * Enable periodic interrupt in 8 msec only if we received
1746                  * real RX interrupt (instead of just periodic int), to catch
1747                  * any dangling Rx interrupt.  If it was just the periodic
1748                  * interrupt, there was no dangling Rx activity, and no need
1749                  * to extend the periodic interrupt; one-shot is enough.
1750                  */
1751                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1752                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1753                                    CSR_INT_PERIODIC_ENA);
1754
1755                 isr_stats->rx++;
1756
1757                 local_bh_disable();
1758                 iwl_pcie_rx_handle(trans, 0);
1759                 local_bh_enable();
1760         }
1761
1762         /* This "Tx" DMA channel is used only for loading uCode */
1763         if (inta & CSR_INT_BIT_FH_TX) {
1764                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1765                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1766                 isr_stats->tx++;
1767                 handled |= CSR_INT_BIT_FH_TX;
1768                 /* Wake up uCode load routine, now that load is complete */
1769                 trans_pcie->ucode_write_complete = true;
1770                 wake_up(&trans_pcie->ucode_write_waitq);
1771         }
1772
1773         if (inta & ~handled) {
1774                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1775                 isr_stats->unhandled++;
1776         }
1777
1778         if (inta & ~(trans_pcie->inta_mask)) {
1779                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1780                          inta & ~trans_pcie->inta_mask);
1781         }
1782
1783         spin_lock(&trans_pcie->irq_lock);
1784         /* only Re-enable all interrupt if disabled by irq */
1785         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1786                 _iwl_enable_interrupts(trans);
1787         /* we are loading the firmware, enable FH_TX interrupt only */
1788         else if (handled & CSR_INT_BIT_FH_TX)
1789                 iwl_enable_fw_load_int(trans);
1790         /* Re-enable RF_KILL if it occurred */
1791         else if (handled & CSR_INT_BIT_RF_KILL)
1792                 iwl_enable_rfkill_int(trans);
1793         spin_unlock(&trans_pcie->irq_lock);
1794
1795 out:
1796         lock_map_release(&trans->sync_cmd_lockdep_map);
1797         return IRQ_HANDLED;
1798 }
1799
1800 /******************************************************************************
1801  *
1802  * ICT functions
1803  *
1804  ******************************************************************************/
1805
1806 /* Free dram table */
1807 void iwl_pcie_free_ict(struct iwl_trans *trans)
1808 {
1809         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1810
1811         if (trans_pcie->ict_tbl) {
1812                 dma_free_coherent(trans->dev, ICT_SIZE,
1813                                   trans_pcie->ict_tbl,
1814                                   trans_pcie->ict_tbl_dma);
1815                 trans_pcie->ict_tbl = NULL;
1816                 trans_pcie->ict_tbl_dma = 0;
1817         }
1818 }
1819
1820 /*
1821  * allocate dram shared table, it is an aligned memory
1822  * block of ICT_SIZE.
1823  * also reset all data related to ICT table interrupt.
1824  */
1825 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1826 {
1827         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1828
1829         trans_pcie->ict_tbl =
1830                 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1831                                    &trans_pcie->ict_tbl_dma,
1832                                    GFP_KERNEL);
1833         if (!trans_pcie->ict_tbl)
1834                 return -ENOMEM;
1835
1836         /* just an API sanity check ... it is guaranteed to be aligned */
1837         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1838                 iwl_pcie_free_ict(trans);
1839                 return -EINVAL;
1840         }
1841
1842         return 0;
1843 }
1844
1845 /* Device is going up inform it about using ICT interrupt table,
1846  * also we need to tell the driver to start using ICT interrupt.
1847  */
1848 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1849 {
1850         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1851         u32 val;
1852
1853         if (!trans_pcie->ict_tbl)
1854                 return;
1855
1856         spin_lock(&trans_pcie->irq_lock);
1857         _iwl_disable_interrupts(trans);
1858
1859         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1860
1861         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1862
1863         val |= CSR_DRAM_INT_TBL_ENABLE |
1864                CSR_DRAM_INIT_TBL_WRAP_CHECK |
1865                CSR_DRAM_INIT_TBL_WRITE_POINTER;
1866
1867         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1868
1869         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1870         trans_pcie->use_ict = true;
1871         trans_pcie->ict_index = 0;
1872         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1873         _iwl_enable_interrupts(trans);
1874         spin_unlock(&trans_pcie->irq_lock);
1875 }
1876
1877 /* Device is going down disable ict interrupt usage */
1878 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1879 {
1880         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1881
1882         spin_lock(&trans_pcie->irq_lock);
1883         trans_pcie->use_ict = false;
1884         spin_unlock(&trans_pcie->irq_lock);
1885 }
1886
1887 irqreturn_t iwl_pcie_isr(int irq, void *data)
1888 {
1889         struct iwl_trans *trans = data;
1890
1891         if (!trans)
1892                 return IRQ_NONE;
1893
1894         /* Disable (but don't clear!) interrupts here to avoid
1895          * back-to-back ISRs and sporadic interrupts from our NIC.
1896          * If we have something to service, the tasklet will re-enable ints.
1897          * If we *don't* have something, we'll re-enable before leaving here.
1898          */
1899         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1900
1901         return IRQ_WAKE_THREAD;
1902 }
1903
1904 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
1905 {
1906         return IRQ_WAKE_THREAD;
1907 }
1908
1909 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
1910 {
1911         struct msix_entry *entry = dev_id;
1912         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1913         struct iwl_trans *trans = trans_pcie->trans;
1914         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1915         u32 inta_fh, inta_hw;
1916
1917         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1918
1919         spin_lock(&trans_pcie->irq_lock);
1920         inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
1921         inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
1922         /*
1923          * Clear causes registers to avoid being handling the same cause.
1924          */
1925         iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
1926         iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
1927         spin_unlock(&trans_pcie->irq_lock);
1928
1929         trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
1930
1931         if (unlikely(!(inta_fh | inta_hw))) {
1932                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1933                 lock_map_release(&trans->sync_cmd_lockdep_map);
1934                 return IRQ_NONE;
1935         }
1936
1937         if (iwl_have_debug_level(IWL_DL_ISR))
1938                 IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n",
1939                               inta_fh,
1940                               iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
1941
1942         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
1943             inta_fh & MSIX_FH_INT_CAUSES_Q0) {
1944                 local_bh_disable();
1945                 iwl_pcie_rx_handle(trans, 0);
1946                 local_bh_enable();
1947         }
1948
1949         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
1950             inta_fh & MSIX_FH_INT_CAUSES_Q1) {
1951                 local_bh_disable();
1952                 iwl_pcie_rx_handle(trans, 1);
1953                 local_bh_enable();
1954         }
1955
1956         /* This "Tx" DMA channel is used only for loading uCode */
1957         if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
1958                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1959                 isr_stats->tx++;
1960                 /*
1961                  * Wake up uCode load routine,
1962                  * now that load is complete
1963                  */
1964                 trans_pcie->ucode_write_complete = true;
1965                 wake_up(&trans_pcie->ucode_write_waitq);
1966         }
1967
1968         /* Error detected by uCode */
1969         if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
1970             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) {
1971                 IWL_ERR(trans,
1972                         "Microcode SW error detected. Restarting 0x%X.\n",
1973                         inta_fh);
1974                 isr_stats->sw++;
1975                 iwl_pcie_irq_handle_error(trans);
1976         }
1977
1978         /* After checking FH register check HW register */
1979         if (iwl_have_debug_level(IWL_DL_ISR))
1980                 IWL_DEBUG_ISR(trans,
1981                               "ISR inta_hw 0x%08x, enabled 0x%08x\n",
1982                               inta_hw,
1983                               iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
1984
1985         /* Alive notification via Rx interrupt will do the real work */
1986         if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
1987                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1988                 isr_stats->alive++;
1989                 if (trans->cfg->gen2) {
1990                         /* We can restock, since firmware configured the RFH */
1991                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1992                 }
1993         }
1994
1995         /* uCode wakes up after power-down sleep */
1996         if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
1997                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1998                 iwl_pcie_rxq_check_wrptr(trans);
1999                 iwl_pcie_txq_check_wrptrs(trans);
2000
2001                 isr_stats->wakeup++;
2002         }
2003
2004         /* Chip got too hot and stopped itself */
2005         if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2006                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2007                 isr_stats->ctkill++;
2008         }
2009
2010         /* HW RF KILL switch toggled */
2011         if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2012                 iwl_pcie_handle_rfkill_irq(trans);
2013
2014         if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2015                 IWL_ERR(trans,
2016                         "Hardware error detected. Restarting.\n");
2017
2018                 isr_stats->hw++;
2019                 iwl_pcie_irq_handle_error(trans);
2020         }
2021
2022         iwl_pcie_clear_irq(trans, entry);
2023
2024         lock_map_release(&trans->sync_cmd_lockdep_map);
2025
2026         return IRQ_HANDLED;
2027 }