1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #ifndef __iwl_fw_api_debug_h__
8 #define __iwl_fw_api_debug_h__
11 * enum iwl_debug_cmds - debug commands
16 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
17 * &struct iwl_dbg_mem_access_rsp
22 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
23 * &struct iwl_dbg_mem_access_rsp
28 * updates the enabled event severities
29 * &struct iwl_dbg_host_event_cfg_cmd
33 * @INVALID_WR_PTR_CMD: invalid write pointer, set in the TFD
34 * when it's not in use
36 INVALID_WR_PTR_CMD = 0x6,
38 * @DBGC_SUSPEND_RESUME:
39 * DBGC suspend/resume commad. Uses a single dword as data:
40 * 0 - resume DBGC recording
41 * 1 - suspend DBGC recording
43 DBGC_SUSPEND_RESUME = 0x7,
46 * passes DRAM buffers to a DBGC
47 * &struct iwl_buf_alloc_cmd
49 BUFFER_ALLOCATION = 0x8,
52 * sends command to fw to get TAS status
53 * the response is &struct iwl_mvm_tas_status_resp
57 * @FW_DUMP_COMPLETE_CMD:
58 * sends command to fw once dump collection completed
59 * &struct iwl_dbg_dump_complete_cmd
61 FW_DUMP_COMPLETE_CMD = 0xB,
64 * clears the firmware's internal buffer
67 FW_CLEAR_BUFFER = 0xD,
69 * @MFU_ASSERT_DUMP_NTF:
70 * &struct iwl_mfu_assert_dump_notif
72 MFU_ASSERT_DUMP_NTF = 0xFE,
75 /* Error response/notification */
77 FW_ERR_UNKNOWN_CMD = 0x0,
78 FW_ERR_INVALID_CMD_PARAM = 0x1,
80 FW_ERR_ARC_MEMORY = 0x3,
81 FW_ERR_ARC_CODE = 0x4,
82 FW_ERR_WATCH_DOG = 0x5,
83 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
84 FW_ERR_WEP_KEY_SIZE = 0x11,
85 FW_ERR_OBSOLETE_FUNC = 0x12,
86 FW_ERR_UNEXPECTED = 0xFE,
90 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations
91 * dbgc suspend resume command operations
92 * @DBGC_RESUME_CMD: resume dbgc recording
93 * @DBGC_SUSPEND_CMD: stop dbgc recording
95 enum iwl_dbg_suspend_resume_cmds {
101 * struct iwl_error_resp - FW error indication
102 * ( REPLY_ERROR = 0x2 )
103 * @error_type: one of FW_ERR_*
104 * @cmd_id: the command ID for which the error occurred
105 * @reserved1: reserved
106 * @bad_cmd_seq_num: sequence number of the erroneous command
107 * @error_service: which service created the error, applicable only if
108 * error_type = 2, otherwise 0
109 * @timestamp: TSF in usecs.
111 struct iwl_error_resp {
115 __le16 bad_cmd_seq_num;
116 __le32 error_service;
120 #define TX_FIFO_MAX_NUM_9000 8
121 #define TX_FIFO_MAX_NUM 15
122 #define RX_FIFO_MAX_NUM 2
123 #define TX_FIFO_INTERNAL_MAX_NUM 6
126 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
128 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
130 * @shared_mem_size: shared memory size
131 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
132 * 0x0 as accessible only via DBGM RDAT)
133 * @sample_buff_size: internal sample buff size
134 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
135 * 8000 HW set to 0x0 as not accessible)
136 * @txfifo_size: size of TXF0 ... TXF7
137 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
138 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
139 * when paging is not supported this should be 0
140 * @page_buff_size: size of %page_buff_addr
141 * @rxfifo_addr: Start address of rxFifo
142 * @internal_txfifo_addr: start address of internalFifo
143 * @internal_txfifo_size: internal fifos' size
145 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
146 * set, the last 3 members don't exist.
148 struct iwl_shared_mem_cfg_v2 {
149 __le32 shared_mem_addr;
150 __le32 shared_mem_size;
151 __le32 sample_buff_addr;
152 __le32 sample_buff_size;
154 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
155 __le32 rxfifo_size[RX_FIFO_MAX_NUM];
156 __le32 page_buff_addr;
157 __le32 page_buff_size;
159 __le32 internal_txfifo_addr;
160 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
161 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
164 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
166 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
167 * @txfifo_size: size of TX FIFOs
168 * @rxfifo1_addr: RXF1 addr
169 * @rxfifo1_size: RXF1 size
171 struct iwl_shared_mem_lmac_cfg {
173 __le32 txfifo_size[TX_FIFO_MAX_NUM];
177 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
180 * struct iwl_shared_mem_cfg - Shared memory configuration information
182 * @shared_mem_addr: shared memory address
183 * @shared_mem_size: shared memory size
184 * @sample_buff_addr: internal sample (mon/adc) buff addr
185 * @sample_buff_size: internal sample buff size
186 * @rxfifo2_addr: start addr of RXF2
187 * @rxfifo2_size: size of RXF2
188 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
189 * when paging is not supported this should be 0
190 * @page_buff_size: size of %page_buff_addr
191 * @lmac_num: number of LMACs (1 or 2)
192 * @lmac_smem: per - LMAC smem data
193 * @rxfifo2_control_addr: start addr of RXF2C
194 * @rxfifo2_control_size: size of RXF2C
196 struct iwl_shared_mem_cfg {
197 __le32 shared_mem_addr;
198 __le32 shared_mem_size;
199 __le32 sample_buff_addr;
200 __le32 sample_buff_size;
203 __le32 page_buff_addr;
204 __le32 page_buff_size;
206 struct iwl_shared_mem_lmac_cfg lmac_smem[3];
207 __le32 rxfifo2_control_addr;
208 __le32 rxfifo2_control_size;
209 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */
212 * struct iwl_mfuart_load_notif_v1 - mfuart image version & status
213 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
214 * @installed_ver: installed image version
215 * @external_ver: external image version
216 * @status: MFUART loading status
217 * @duration: MFUART loading time
219 struct iwl_mfuart_load_notif_v1 {
220 __le32 installed_ver;
224 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */
227 * struct iwl_mfuart_load_notif - mfuart image version & status
228 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
229 * @installed_ver: installed image version
230 * @external_ver: external image version
231 * @status: MFUART loading status
232 * @duration: MFUART loading time
233 * @image_size: MFUART image size in bytes
235 struct iwl_mfuart_load_notif {
236 __le32 installed_ver;
240 /* image size valid only in v2 of the command */
242 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
245 * struct iwl_mfu_assert_dump_notif - mfuart dump logs
246 * ( MFU_ASSERT_DUMP_NTF = 0xfe )
247 * @assert_id: mfuart assert id that cause the notif
248 * @curr_reset_num: number of asserts since uptime
249 * @index_num: current chunk id
250 * @parts_num: total number of chunks
251 * @data_size: number of data bytes sent
254 struct iwl_mfu_assert_dump_notif {
256 __le32 curr_reset_num;
261 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
264 * enum iwl_mvm_marker_id - marker ids
266 * The ids for different type of markers to insert into the usniffer logs
268 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
269 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
271 enum iwl_mvm_marker_id {
272 MARKER_ID_TX_FRAME_LATENCY = 1,
273 MARKER_ID_SYNC_CLOCK = 2,
274 }; /* MARKER_ID_API_E_VER_2 */
277 * struct iwl_mvm_marker - mark info into the usniffer logs
279 * (MARKER_CMD = 0xcb)
281 * Mark the UTC time stamp into the usniffer logs together with additional
282 * metadata, so the usniffer output can be parsed.
283 * In the command response the ucode will return the GP2 time.
285 * @dw_len: The amount of dwords following this byte including this byte.
286 * @marker_id: A unique marker id (iwl_mvm_marker_id).
287 * @reserved: reserved.
288 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
289 * @metadata: additional meta data that will be written to the unsiffer log
291 struct iwl_mvm_marker {
297 } __packed; /* MARKER_API_S_VER_1 */
300 * struct iwl_mvm_marker_rsp - Response to marker cmd
302 * @gp2: The gp2 clock value in the FW
304 struct iwl_mvm_marker_rsp {
308 /* Operation types for the debug mem access */
310 DEBUG_MEM_OP_READ = 0,
311 DEBUG_MEM_OP_WRITE = 1,
312 DEBUG_MEM_OP_WRITE_BYTES = 2,
315 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
318 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
319 * @op: DEBUG_MEM_OP_*
320 * @addr: address to read/write from/to
321 * @len: in dwords, to read/write
322 * @data: for write opeations, contains the source buffer
324 struct iwl_dbg_mem_access_cmd {
329 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
331 /* Status responses for the debug mem access */
333 DEBUG_MEM_STATUS_SUCCESS = 0x0,
334 DEBUG_MEM_STATUS_FAILED = 0x1,
335 DEBUG_MEM_STATUS_LOCKED = 0x2,
336 DEBUG_MEM_STATUS_HIDDEN = 0x3,
337 DEBUG_MEM_STATUS_LENGTH = 0x4,
341 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
342 * @status: DEBUG_MEM_STATUS_*
343 * @len: read dwords (0 for write operations)
344 * @data: contains the read DWs
346 struct iwl_dbg_mem_access_rsp {
350 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
353 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command
354 * @operation: suspend or resume operation, uses
355 * &enum iwl_dbg_suspend_resume_cmds
357 struct iwl_dbg_suspend_resume_cmd {
361 #define BUF_ALLOC_MAX_NUM_FRAGS 16
364 * struct iwl_buf_alloc_frag - a DBGC fragment
365 * @addr: base address of the fragment
366 * @size: size of the fragment
368 struct iwl_buf_alloc_frag {
371 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
374 * struct iwl_buf_alloc_cmd - buffer allocation command
375 * @alloc_id: &enum iwl_fw_ini_allocation_id
376 * @buf_location: &enum iwl_fw_ini_buffer_location
377 * @num_frags: number of fragments
378 * @frags: fragments array
380 struct iwl_buf_alloc_cmd {
384 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS];
385 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */
387 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210
388 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF
391 * struct iwl_dram_info - DRAM fragments allocation struct
393 * Driver will fill in the first 1K(+) of the pointed DRAM fragment
395 * @first_word: magic word value
396 * @second_word: magic word value
397 * @framfrags: DRAM fragmentaion detail
399 struct iwl_dram_info {
402 struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1];
403 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
406 * struct iwl_dbgc1_info - DBGC1 address and size
408 * Driver will fill the dbcg1 address and size at address based on config TLV.
410 * @first_word: all 0 set as identifier
411 * @dbgc1_add_lsb: LSB bits of DBGC1 physical address
412 * @dbgc1_add_msb: MSB bits of DBGC1 physical address
413 * @dbgc1_size: DBGC1 size
415 struct iwl_dbgc1_info {
417 __le32 dbgc1_add_lsb;
418 __le32 dbgc1_add_msb;
420 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
423 * struct iwl_dbg_host_event_cfg_cmd
424 * @enabled_severities: enabled severities
426 struct iwl_dbg_host_event_cfg_cmd {
427 __le32 enabled_severities;
428 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */
431 * struct iwl_dbg_dump_complete_cmd - dump complete cmd
433 * @tp: timepoint whose dump has completed
434 * @tp_data: timepoint data
436 struct iwl_dbg_dump_complete_cmd {
439 } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */
441 #define TAS_LMAC_BAND_HB 0
442 #define TAS_LMAC_BAND_LB 1
443 #define TAS_LMAC_BAND_UHB 2
444 #define TAS_LMAC_BAND_INVALID 3
447 * struct iwl_mvm_tas_status_per_mac - tas status per lmac
448 * @static_status: tas statically enabled or disabled per lmac - TRUE/FALSE
449 * @static_dis_reason: TAS static disable reason, uses
450 * &enum iwl_mvm_tas_statically_disabled_reason
451 * @dynamic_status: Current TAS status. uses
452 * &enum iwl_mvm_tas_dyna_status
453 * @near_disconnection: is TAS currently near disconnection per lmac? - TRUE/FALSE
454 * @max_reg_pwr_limit: Regulatory power limits in dBm
455 * @sar_limit: SAR limits per lmac in dBm
456 * @band: Band per lmac
457 * @reserved: reserved
459 struct iwl_mvm_tas_status_per_mac {
461 u8 static_dis_reason;
463 u8 near_disconnection;
464 __le16 max_reg_pwr_limit;
468 } __packed; /*DEBUG_GET_TAS_STATUS_PER_MAC_S_VER_1*/
471 * struct iwl_mvm_tas_status_resp - Response to GET_TAS_STATUS
472 * @tas_fw_version: TAS FW version
473 * @is_uhb_for_usa_enable: is UHB enabled in USA? - TRUE/FALSE
474 * @curr_mcc: current mcc
475 * @block_list: country block list
476 * @tas_status_mac: TAS status per lmac, uses
477 * &struct iwl_mvm_tas_status_per_mac
478 * @in_dual_radio: is TAS in dual radio? - TRUE/FALSE
479 * @reserved: reserved
481 struct iwl_mvm_tas_status_resp {
483 u8 is_uhb_for_usa_enable;
485 __le16 block_list[16];
486 struct iwl_mvm_tas_status_per_mac tas_status_mac[2];
489 } __packed; /*DEBUG_GET_TAS_STATUS_RSP_API_S_VER_3*/
492 * enum iwl_mvm_tas_dyna_status - TAS current running status
493 * @TAS_DYNA_INACTIVE: TAS status is inactive
494 * @TAS_DYNA_INACTIVE_MVM_MODE: TAS is disabled due because FW is in MVM mode
495 * or is in softap mode.
496 * @TAS_DYNA_INACTIVE_TRIGGER_MODE: TAS is disabled because FW is in
497 * multi user trigger mode
498 * @TAS_DYNA_INACTIVE_BLOCK_LISTED: TAS is disabled because current mcc
500 * @TAS_DYNA_INACTIVE_UHB_NON_US: TAS is disabled because current band is UHB
501 * and current mcc is USA
502 * @TAS_DYNA_ACTIVE: TAS is currently active
503 * @TAS_DYNA_STATUS_MAX: TAS status max value
505 enum iwl_mvm_tas_dyna_status {
507 TAS_DYNA_INACTIVE_MVM_MODE,
508 TAS_DYNA_INACTIVE_TRIGGER_MODE,
509 TAS_DYNA_INACTIVE_BLOCK_LISTED,
510 TAS_DYNA_INACTIVE_UHB_NON_US,
514 }; /*_TAS_DYNA_STATUS_E*/
517 * enum iwl_mvm_tas_statically_disabled_reason - TAS statically disabled reason
518 * @TAS_DISABLED_DUE_TO_BIOS: TAS is disabled because TAS is disabled in BIOS
519 * @TAS_DISABLED_DUE_TO_SAR_6DBM: TAS is disabled because SAR limit is less than 6 Dbm
520 * @TAS_DISABLED_REASON_INVALID: TAS disable reason is invalid
521 * @TAS_DISABLED_REASON_MAX: TAS disable reason max value
523 enum iwl_mvm_tas_statically_disabled_reason {
524 TAS_DISABLED_DUE_TO_BIOS,
525 TAS_DISABLED_DUE_TO_SAR_6DBM,
526 TAS_DISABLED_REASON_INVALID,
528 TAS_DISABLED_REASON_MAX,
529 }; /*_TAS_STATICALLY_DISABLED_REASON_E*/
532 * enum iwl_fw_dbg_config_cmd_type - types of FW debug config command
533 * @DEBUG_TOKEN_CONFIG_TYPE: token config type
535 enum iwl_fw_dbg_config_cmd_type {
536 DEBUG_TOKEN_CONFIG_TYPE = 0x2B,
537 }; /* LDBG_CFG_CMD_TYPE_API_E_VER_1 */
539 /* this token disables debug asserts in the firmware */
540 #define IWL_FW_DBG_CONFIG_TOKEN 0x00010001
543 * struct iwl_fw_dbg_config_cmd - configure FW debug
545 * @type: according to &enum iwl_fw_dbg_config_cmd_type
546 * @conf: FW configuration
548 struct iwl_fw_dbg_config_cmd {
551 } __packed; /* LDBG_CFG_CMD_API_S_VER_7 */
553 #endif /* __iwl_fw_api_debug_h__ */