drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  59 {//TODO
  60 }
  61
  62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  63 {//TODO
  64 }
  65
  66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  67                                                         bool ignore_tssi)
  68 {//TODO
  69         return B43_TXPWR_RES_DONE;
  70 }
  71
  72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  73                                      const struct b43_nphy_channeltab_entry *e)
  74 {
  75         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  77         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  78         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  79         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  80         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  81         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  82         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  83         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  84         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  86         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  88         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  89         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  90         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  91         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  93         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  94         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  95         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  96         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  97 }
  98
  99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 100                                    const struct b43_nphy_channeltab_entry *e)
 101 {
 102         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 103         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 104         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 105         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 106         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 107         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 108 }
 109
 110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 111 {
 112         //TODO
 113 }
 114
 115 /* Tune the hardware to a new channel. */
 116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 117 {
 118         const struct b43_nphy_channeltab_entry *tabent;
 119
 120         tabent = b43_nphy_get_chantabent(dev, channel);
 121         if (!tabent)
 122                 return -ESRCH;
 123
 124         //FIXME enable/disable band select upper20 in RXCTL
 125         if (0 /*FIXME 5Ghz*/)
 126                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 127         else
 128                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 129         b43_chantab_radio_upload(dev, tabent);
 130         udelay(50);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 133         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 134         udelay(300);
 135         if (0 /*FIXME 5Ghz*/)
 136                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 137         else
 138                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 139         b43_chantab_phy_upload(dev, tabent);
 140         b43_nphy_tx_power_fix(dev);
 141
 142         return 0;
 143 }
 144
 145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 146 {
 147         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 148                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 149         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 150                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 151                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 152         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 153                     B43_NPHY_RFCTL_CMD_PORFORCE);
 154 }
 155
 156 static void b43_radio_init2055_post(struct b43_wldev *dev)
 157 {
 158         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 159         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 160         int i;
 161         u16 val;
 162
 163         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 164         msleep(1);
 165         if ((sprom->revision != 4) ||
 166            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 167                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 168                     (binfo->type != 0x46D) ||
 169                     (binfo->rev < 0x41)) {
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 172                         msleep(1);
 173                 }
 174         }
 175         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 176         msleep(1);
 177         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 178         msleep(1);
 179         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 180         msleep(1);
 181         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 182         msleep(1);
 183         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 184         msleep(1);
 185         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 186         msleep(1);
 187         for (i = 0; i < 100; i++) {
 188                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 189                 if (val & 0x80)
 190                         break;
 191                 udelay(10);
 192         }
 193         msleep(1);
 194         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 195         msleep(1);
 196         nphy_channel_switch(dev, dev->phy.channel);
 197         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 199         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 200         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 201 }
 202
 203 /* Initialize a Broadcom 2055 N-radio */
 204 static void b43_radio_init2055(struct b43_wldev *dev)
 205 {
 206         b43_radio_init2055_pre(dev);
 207         if (b43_status(dev) < B43_STAT_INITIALIZED)
 208                 b2055_upload_inittab(dev, 0, 1);
 209         else
 210                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 211         b43_radio_init2055_post(dev);
 212 }
 213
 214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 215 {
 216         b43_radio_init2055(dev);
 217 }
 218
 219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 220 {
 221         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 222                      ~B43_NPHY_RFCTL_CMD_EN);
 223 }
 224
 225 /*
 226  * Upload the N-PHY tables.
 227  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 228  */
 229 static void b43_nphy_tables_init(struct b43_wldev *dev)
 230 {
 231         if (dev->phy.rev < 3)
 232                 b43_nphy_rev0_1_2_tables_init(dev);
 233         else
 234                 b43_nphy_rev3plus_tables_init(dev);
 235 }
 236
 237 static void b43_nphy_workarounds(struct b43_wldev *dev)
 238 {
 239         struct b43_phy *phy = &dev->phy;
 240         unsigned int i;
 241
 242         b43_phy_set(dev, B43_NPHY_IQFLIP,
 243                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 244         if (1 /* FIXME band is 2.4GHz */) {
 245                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 246                             B43_NPHY_CLASSCTL_CCKEN);
 247         } else {
 248                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 249                              ~B43_NPHY_CLASSCTL_CCKEN);
 250         }
 251         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 252         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 253
 254         /* Fixup some tables */
 255         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 256         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 257         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 258         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 259         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 260         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 265
 266         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 267         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 268         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 269         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 270
 271         //TODO set RF sequence
 272
 273         /* Set narrowband clip threshold */
 274         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 275         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 276
 277         /* Set wideband clip 2 threshold */
 278         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 279                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 280                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 281         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 282                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 283                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 284
 285         /* Set Clip 2 detect */
 286         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 287                     B43_NPHY_C1_CGAINI_CL2DETECT);
 288         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 289                     B43_NPHY_C2_CGAINI_CL2DETECT);
 290
 291         if (0 /*FIXME*/) {
 292                 /* Set dwell lengths */
 293                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 294                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 295                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 296                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 297
 298                 /* Set gain backoff */
 299                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 300                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 301                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 302                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 303                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 304                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 305
 306                 /* Set HPVGA2 index */
 307                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 308                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 309                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 310                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 311                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 312                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 313
 314                 //FIXME verify that the specs really mean to use autoinc here.
 315                 for (i = 0; i < 3; i++)
 316                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 317         }
 318
 319         /* Set minimum gain value */
 320         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 321                         ~B43_NPHY_C1_MINGAIN,
 322                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 323         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 324                         ~B43_NPHY_C2_MINGAIN,
 325                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 326
 327         if (phy->rev < 2) {
 328                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 329                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 330         }
 331
 332         /* Set phase track alpha and beta */
 333         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 334         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 335         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 336         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 337         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 338         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 339 }
 340
 341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 342 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 343 {
 344         struct b43_phy_n *nphy = dev->phy.n;
 345         enum ieee80211_band band;
 346         u16 tmp;
 347
 348         if (!enable) {
 349                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 350                                                        B43_NPHY_RFCTL_INTC1);
 351                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 352                                                        B43_NPHY_RFCTL_INTC2);
 353                 band = b43_current_band(dev->wl);
 354                 if (dev->phy.rev >= 3) {
 355                         if (band == IEEE80211_BAND_5GHZ)
 356                                 tmp = 0x600;
 357                         else
 358                                 tmp = 0x480;
 359                 } else {
 360                         if (band == IEEE80211_BAND_5GHZ)
 361                                 tmp = 0x180;
 362                         else
 363                                 tmp = 0x120;
 364                 }
 365                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 366                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 367         } else {
 368                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 369                                 nphy->rfctrl_intc1_save);
 370                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 371                                 nphy->rfctrl_intc2_save);
 372         }
 373 }
 374
 375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 376 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 377 {
 378         struct b43_phy_n *nphy = dev->phy.n;
 379         u16 tmp;
 380         enum ieee80211_band band = b43_current_band(dev->wl);
 381         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 382                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 383
 384         if (dev->phy.rev >= 3) {
 385                 if (ipa) {
 386                         tmp = 4;
 387                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 388                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 389                 }
 390
 391                 tmp = 1;
 392                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 393                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 394         }
 395 }
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 398 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 399 {
 400         u32 tmslow;
 401
 402         if (dev->phy.type != B43_PHYTYPE_N)
 403                 return;
 404
 405         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 406         if (force)
 407                 tmslow |= SSB_TMSLOW_FGC;
 408         else
 409                 tmslow &= ~SSB_TMSLOW_FGC;
 410         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 411 }
 412
 413 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 414 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 415 {
 416         u16 bbcfg;
 417
 418         b43_nphy_bmac_clock_fgc(dev, 1);
 419         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 420         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 421         udelay(1);
 422         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 423         b43_nphy_bmac_clock_fgc(dev, 0);
 424         /* TODO: N PHY Force RF Seq with argument 2 */
 425 }
 426
 427 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 428 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 429 {
 430         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 431
 432         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 433         if (preamble == 1)
 434                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 435         else
 436                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 437
 438         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 439 }
 440
 441 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 442 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 443                                 u16 samps, u8 time, bool wait)
 444 {
 445         int i;
 446         u16 tmp;
 447
 448         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 449         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 450         if (wait)
 451                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 452         else
 453                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 454
 455         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 456
 457         for (i = 1000; i; i--) {
 458                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 459                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 460                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 461                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 462                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 463                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 464                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 465                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 466
 467                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 468                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 469                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 470                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 471                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 472                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 473                         return;
 474                 }
 475                 udelay(10);
 476         }
 477         memset(est, 0, sizeof(*est));
 478 }
 479
 480 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 481 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 482                                         struct b43_phy_n_iq_comp *pcomp)
 483 {
 484         if (write) {
 485                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 486                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 487                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 488                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 489         } else {
 490                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 491                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 492                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 493                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 494         }
 495 }
 496
 497 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 498 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 499 {
 500         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 501
 502         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 503         if (core == 0) {
 504                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 505                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 506         } else {
 507                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 508                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 509         }
 510         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 511         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 512         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 513         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 514         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 515         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 516         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 517         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 518 }
 519
 520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 521 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 522 {
 523         u8 rxval, txval;
 524         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 525
 526         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 527         if (core == 0) {
 528                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 529                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 530         } else {
 531                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 532                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 533         }
 534         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 535         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 536         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 537         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 538         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 539         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 540         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 541         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 542
 543         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 544         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 545
 546         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 547                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 548         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 549                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 550         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 551                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 552         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 553                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 554
 555         if (core == 0) {
 556                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 557                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 558         } else {
 559                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 560                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 561         }
 562
 563         /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
 564         /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
 565         /* TODO: Call N PHY RF Seq with 0 as argument */
 566
 567         if (core == 0) {
 568                 rxval = 1;
 569                 txval = 8;
 570         } else {
 571                 rxval = 4;
 572                 txval = 2;
 573         }
 574
 575         /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
 576         /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
 577 }
 578
 579 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 580 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 581 {
 582         int i;
 583         s32 iq;
 584         u32 ii;
 585         u32 qq;
 586         int iq_nbits, qq_nbits;
 587         int arsh, brsh;
 588         u16 tmp, a, b;
 589
 590         struct nphy_iq_est est;
 591         struct b43_phy_n_iq_comp old;
 592         struct b43_phy_n_iq_comp new = { };
 593         bool error = false;
 594
 595         if (mask == 0)
 596                 return;
 597
 598         b43_nphy_rx_iq_coeffs(dev, false, &old);
 599         b43_nphy_rx_iq_coeffs(dev, true, &new);
 600         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 601         new = old;
 602
 603         for (i = 0; i < 2; i++) {
 604                 if (i == 0 && (mask & 1)) {
 605                         iq = est.iq0_prod;
 606                         ii = est.i0_pwr;
 607                         qq = est.q0_pwr;
 608                 } else if (i == 1 && (mask & 2)) {
 609                         iq = est.iq1_prod;
 610                         ii = est.i1_pwr;
 611                         qq = est.q1_pwr;
 612                 } else {
 613                         B43_WARN_ON(1);
 614                         continue;
 615                 }
 616
 617                 if (ii + qq < 2) {
 618                         error = true;
 619                         break;
 620                 }
 621
 622                 iq_nbits = fls(abs(iq));
 623                 qq_nbits = fls(qq);
 624
 625                 arsh = iq_nbits - 20;
 626                 if (arsh >= 0) {
 627                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 628                         tmp = ii >> arsh;
 629                 } else {
 630                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 631                         tmp = ii << -arsh;
 632                 }
 633                 if (tmp == 0) {
 634                         error = true;
 635                         break;
 636                 }
 637                 a /= tmp;
 638
 639                 brsh = qq_nbits - 11;
 640                 if (brsh >= 0) {
 641                         b = (qq << (31 - qq_nbits));
 642                         tmp = ii >> brsh;
 643                 } else {
 644                         b = (qq << (31 - qq_nbits));
 645                         tmp = ii << -brsh;
 646                 }
 647                 if (tmp == 0) {
 648                         error = true;
 649                         break;
 650                 }
 651                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 652
 653                 if (i == 0 && (mask & 0x1)) {
 654                         if (dev->phy.rev >= 3) {
 655                                 new.a0 = a & 0x3FF;
 656                                 new.b0 = b & 0x3FF;
 657                         } else {
 658                                 new.a0 = b & 0x3FF;
 659                                 new.b0 = a & 0x3FF;
 660                         }
 661                 } else if (i == 1 && (mask & 0x2)) {
 662                         if (dev->phy.rev >= 3) {
 663                                 new.a1 = a & 0x3FF;
 664                                 new.b1 = b & 0x3FF;
 665                         } else {
 666                                 new.a1 = b & 0x3FF;
 667                                 new.b1 = a & 0x3FF;
 668                         }
 669                 }
 670         }
 671
 672         if (error)
 673                 new = old;
 674
 675         b43_nphy_rx_iq_coeffs(dev, true, &new);
 676 }
 677
 678 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 679 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 680 {
 681         u16 array[4];
 682         int i;
 683
 684         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 685         for (i = 0; i < 4; i++)
 686                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 687
 688         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 689         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 690         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 691         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 692 }
 693
 694 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 695 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 696 {
 697         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 698         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 699 }
 700
 701 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 702 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 703 {
 704         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 705         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 706 }
 707
 708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 709 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 710 {
 711         u16 tmp;
 712
 713         if (dev->dev->id.revision == 16)
 714                 b43_mac_suspend(dev);
 715
 716         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 717         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 718                 B43_NPHY_CLASSCTL_WAITEDEN);
 719         tmp &= ~mask;
 720         tmp |= (val & mask);
 721         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 722
 723         if (dev->dev->id.revision == 16)
 724                 b43_mac_enable(dev);
 725
 726         return tmp;
 727 }
 728
 729 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 730 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 731 {
 732         struct b43_phy *phy = &dev->phy;
 733         struct b43_phy_n *nphy = phy->n;
 734
 735         if (enable) {
 736                 u16 clip[] = { 0xFFFF, 0xFFFF };
 737                 if (nphy->deaf_count++ == 0) {
 738                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 739                         b43_nphy_classifier(dev, 0x7, 0);
 740                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 741                         b43_nphy_write_clip_detection(dev, clip);
 742                 }
 743                 b43_nphy_reset_cca(dev);
 744         } else {
 745                 if (--nphy->deaf_count == 0) {
 746                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 747                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 748                 }
 749         }
 750 }
 751
 752 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 753 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 754 {
 755         struct b43_phy_n *nphy = dev->phy.n;
 756         u16 tmp;
 757
 758         if (nphy->hang_avoid)
 759                 b43_nphy_stay_in_carrier_search(dev, 1);
 760
 761         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 762         if (tmp & 0x1)
 763                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 764         else if (tmp & 0x2)
 765                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 766
 767         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 768
 769         if (nphy->bb_mult_save & 0x80000000) {
 770                 tmp = nphy->bb_mult_save & 0xFFFF;
 771                 /* TODO: Write an N PHY Table with ID 15, length 1, offset 87,
 772                         width 16 and data from tmp */
 773                 nphy->bb_mult_save = 0;
 774         }
 775
 776         if (nphy->hang_avoid)
 777                 b43_nphy_stay_in_carrier_search(dev, 0);
 778 }
 779
 780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
 781 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
 782 {
 783         struct b43_phy_n *nphy = dev->phy.n;
 784         int i, j;
 785         u32 tmp;
 786         u32 cur_real, cur_imag, real_part, imag_part;
 787
 788         u16 buffer[7];
 789
 790         if (nphy->hang_avoid)
 791                 b43_nphy_stay_in_carrier_search(dev, true);
 792
 793         /* TODO: Read an N PHY Table with ID 15, length 7, offset 80,
 794                 width 16, and data pointer buffer */
 795
 796         for (i = 0; i < 2; i++) {
 797                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
 798                         (buffer[i * 2 + 1] & 0x3FF);
 799                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 800                                 (((i + 26) << 10) | 320));
 801                 for (j = 0; j < 128; j++) {
 802                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
 803                                         ((tmp >> 16) & 0xFFFF));
 804                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 805                                         (tmp & 0xFFFF));
 806                 }
 807         }
 808
 809         for (i = 0; i < 2; i++) {
 810                 tmp = buffer[5 + i];
 811                 real_part = (tmp >> 8) & 0xFF;
 812                 imag_part = (tmp & 0xFF);
 813                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 814                                 (((i + 26) << 10) | 448));
 815
 816                 if (dev->phy.rev >= 3) {
 817                         cur_real = real_part;
 818                         cur_imag = imag_part;
 819                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
 820                 }
 821
 822                 for (j = 0; j < 128; j++) {
 823                         if (dev->phy.rev < 3) {
 824                                 cur_real = (real_part * loscale[j] + 128) >> 8;
 825                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
 826                                 tmp = ((cur_real & 0xFF) << 8) |
 827                                         (cur_imag & 0xFF);
 828                         }
 829                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
 830                                         ((tmp >> 16) & 0xFFFF));
 831                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 832                                         (tmp & 0xFFFF));
 833                 }
 834         }
 835
 836         if (dev->phy.rev >= 3) {
 837                 b43_shm_write16(dev, B43_SHM_SHARED,
 838                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
 839                 b43_shm_write16(dev, B43_SHM_SHARED,
 840                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
 841         }
 842
 843         if (nphy->hang_avoid)
 844                 b43_nphy_stay_in_carrier_search(dev, false);
 845 }
 846
 847 enum b43_nphy_rf_sequence {
 848         B43_RFSEQ_RX2TX,
 849         B43_RFSEQ_TX2RX,
 850         B43_RFSEQ_RESET2RX,
 851         B43_RFSEQ_UPDATE_GAINH,
 852         B43_RFSEQ_UPDATE_GAINL,
 853         B43_RFSEQ_UPDATE_GAINU,
 854 };
 855
 856 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 857                                        enum b43_nphy_rf_sequence seq)
 858 {
 859         static const u16 trigger[] = {
 860                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 861                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 862                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 863                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 864                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 865                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 866         };
 867         int i;
 868
 869         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 870
 871         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 872                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 873         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 874         for (i = 0; i < 200; i++) {
 875                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 876                         goto ok;
 877                 msleep(1);
 878         }
 879         b43err(dev->wl, "RF sequence status timeout\n");
 880 ok:
 881         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 882                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 883 }
 884
 885 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 886 {
 887         unsigned int i;
 888         u16 val;
 889
 890         val = 0x1E1F;
 891         for (i = 0; i < 14; i++) {
 892                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 893                 val -= 0x202;
 894         }
 895         val = 0x3E3F;
 896         for (i = 0; i < 16; i++) {
 897                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 898                 val -= 0x202;
 899         }
 900         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 901 }
 902
 903 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 904 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 905                                        s8 offset, u8 core, u8 rail, u8 type)
 906 {
 907         u16 tmp;
 908         bool core1or5 = (core == 1) || (core == 5);
 909         bool core2or5 = (core == 2) || (core == 5);
 910
 911         offset = clamp_val(offset, -32, 31);
 912         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 913
 914         if (core1or5 && (rail == 0) && (type == 2))
 915                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 916         if (core1or5 && (rail == 1) && (type == 2))
 917                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 918         if (core2or5 && (rail == 0) && (type == 2))
 919                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 920         if (core2or5 && (rail == 1) && (type == 2))
 921                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 922         if (core1or5 && (rail == 0) && (type == 0))
 923                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 924         if (core1or5 && (rail == 1) && (type == 0))
 925                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 926         if (core2or5 && (rail == 0) && (type == 0))
 927                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 928         if (core2or5 && (rail == 1) && (type == 0))
 929                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 930         if (core1or5 && (rail == 0) && (type == 1))
 931                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 932         if (core1or5 && (rail == 1) && (type == 1))
 933                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 934         if (core2or5 && (rail == 0) && (type == 1))
 935                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
 936         if (core2or5 && (rail == 1) && (type == 1))
 937                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
 938         if (core1or5 && (rail == 0) && (type == 6))
 939                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
 940         if (core1or5 && (rail == 1) && (type == 6))
 941                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
 942         if (core2or5 && (rail == 0) && (type == 6))
 943                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
 944         if (core2or5 && (rail == 1) && (type == 6))
 945                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
 946         if (core1or5 && (rail == 0) && (type == 3))
 947                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
 948         if (core1or5 && (rail == 1) && (type == 3))
 949                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
 950         if (core2or5 && (rail == 0) && (type == 3))
 951                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
 952         if (core2or5 && (rail == 1) && (type == 3))
 953                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
 954         if (core1or5 && (type == 4))
 955                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
 956         if (core2or5 && (type == 4))
 957                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
 958         if (core1or5 && (type == 5))
 959                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
 960         if (core2or5 && (type == 5))
 961                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 962 }
 963
 964 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
 965 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
 966 {
 967         u16 val;
 968
 969         if (dev->phy.rev >= 3) {
 970                 /* TODO */
 971         } else {
 972                 if (type < 3)
 973                         val = 0;
 974                 else if (type == 6)
 975                         val = 1;
 976                 else if (type == 3)
 977                         val = 2;
 978                 else
 979                         val = 3;
 980
 981                 val = (val << 12) | (val << 14);
 982                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
 983                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
 984
 985                 if (type < 3) {
 986                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
 987                                         (type + 1) << 4);
 988                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
 989                                         (type + 1) << 4);
 990                 }
 991
 992                 /* TODO use some definitions */
 993                 if (code == 0) {
 994                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
 995                         if (type < 3) {
 996                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 997                                                 0xFEC7, 0);
 998                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 999                                                 0xEFDC, 0);
1000                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1001                                                 0xFFFE, 0);
1002                                 udelay(20);
1003                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1004                                                 0xFFFE, 0);
1005                         }
1006                 } else {
1007                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1008                                         0x3000);
1009                         if (type < 3) {
1010                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1011                                                 0xFEC7, 0x0180);
1012                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1013                                                 0xEFDC, (code << 1 | 0x1021));
1014                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1015                                                 0xFFFE, 0x0001);
1016                                 udelay(20);
1017                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1018                                                 0xFFFE, 0);
1019                         }
1020                 }
1021         }
1022 }
1023
1024 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1025 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1026 {
1027         int i;
1028         for (i = 0; i < 2; i++) {
1029                 if (type == 2) {
1030                         if (i == 0) {
1031                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1032                                                   0xFC, buf[0]);
1033                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1034                                                   0xFC, buf[1]);
1035                         } else {
1036                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1037                                                   0xFC, buf[2 * i]);
1038                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1039                                                   0xFC, buf[2 * i + 1]);
1040                         }
1041                 } else {
1042                         if (i == 0)
1043                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1044                                                   0xF3, buf[0] << 2);
1045                         else
1046                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1047                                                   0xF3, buf[2 * i + 1] << 2);
1048                 }
1049         }
1050 }
1051
1052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1053 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1054                                 u8 nsamp)
1055 {
1056         int i;
1057         int out;
1058         u16 save_regs_phy[9];
1059         u16 s[2];
1060
1061         if (dev->phy.rev >= 3) {
1062                 save_regs_phy[0] = b43_phy_read(dev,
1063                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1064                 save_regs_phy[1] = b43_phy_read(dev,
1065                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1066                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1067                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1068                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1069                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1070                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1071                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1072         }
1073
1074         b43_nphy_rssi_select(dev, 5, type);
1075
1076         if (dev->phy.rev < 2) {
1077                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1078                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1079         }
1080
1081         for (i = 0; i < 4; i++)
1082                 buf[i] = 0;
1083
1084         for (i = 0; i < nsamp; i++) {
1085                 if (dev->phy.rev < 2) {
1086                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1087                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1088                 } else {
1089                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1090                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1091                 }
1092
1093                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1094                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1095                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1096                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1097         }
1098         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1099                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1100
1101         if (dev->phy.rev < 2)
1102                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1103
1104         if (dev->phy.rev >= 3) {
1105                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1106                                 save_regs_phy[0]);
1107                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1108                                 save_regs_phy[1]);
1109                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1110                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1111                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1112                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1113                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1114                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1115         }
1116
1117         return out;
1118 }
1119
1120 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1121 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1122 {
1123         int i, j;
1124         u8 state[4];
1125         u8 code, val;
1126         u16 class, override;
1127         u8 regs_save_radio[2];
1128         u16 regs_save_phy[2];
1129         s8 offset[4];
1130
1131         u16 clip_state[2];
1132         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1133         s32 results_min[4] = { };
1134         u8 vcm_final[4] = { };
1135         s32 results[4][4] = { };
1136         s32 miniq[4][2] = { };
1137
1138         if (type == 2) {
1139                 code = 0;
1140                 val = 6;
1141         } else if (type < 2) {
1142                 code = 25;
1143                 val = 4;
1144         } else {
1145                 B43_WARN_ON(1);
1146                 return;
1147         }
1148
1149         class = b43_nphy_classifier(dev, 0, 0);
1150         b43_nphy_classifier(dev, 7, 4);
1151         b43_nphy_read_clip_detection(dev, clip_state);
1152         b43_nphy_write_clip_detection(dev, clip_off);
1153
1154         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1155                 override = 0x140;
1156         else
1157                 override = 0x110;
1158
1159         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1160         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1161         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1162         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1163
1164         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1165         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1166         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1167         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1168
1169         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1170         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1171         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1172         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1173         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1174         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1175
1176         b43_nphy_rssi_select(dev, 5, type);
1177         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1178         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1179
1180         for (i = 0; i < 4; i++) {
1181                 u8 tmp[4];
1182                 for (j = 0; j < 4; j++)
1183                         tmp[j] = i;
1184                 if (type != 1)
1185                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1186                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1187                 if (type < 2)
1188                         for (j = 0; j < 2; j++)
1189                                 miniq[i][j] = min(results[i][2 * j],
1190                                                 results[i][2 * j + 1]);
1191         }
1192
1193         for (i = 0; i < 4; i++) {
1194                 s32 mind = 40;
1195                 u8 minvcm = 0;
1196                 s32 minpoll = 249;
1197                 s32 curr;
1198                 for (j = 0; j < 4; j++) {
1199                         if (type == 2)
1200                                 curr = abs(results[j][i]);
1201                         else
1202                                 curr = abs(miniq[j][i / 2] - code * 8);
1203
1204                         if (curr < mind) {
1205                                 mind = curr;
1206                                 minvcm = j;
1207                         }
1208
1209                         if (results[j][i] < minpoll)
1210                                 minpoll = results[j][i];
1211                 }
1212                 results_min[i] = minpoll;
1213                 vcm_final[i] = minvcm;
1214         }
1215
1216         if (type != 1)
1217                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1218
1219         for (i = 0; i < 4; i++) {
1220                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1221
1222                 if (offset[i] < 0)
1223                         offset[i] = -((abs(offset[i]) + 4) / 8);
1224                 else
1225                         offset[i] = (offset[i] + 4) / 8;
1226
1227                 if (results_min[i] == 248)
1228                         offset[i] = code - 32;
1229
1230                 if (i % 2 == 0)
1231                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1232                                                         type);
1233                 else
1234                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1235                                                         type);
1236         }
1237
1238         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1239         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1240
1241         switch (state[2]) {
1242         case 1:
1243                 b43_nphy_rssi_select(dev, 1, 2);
1244                 break;
1245         case 4:
1246                 b43_nphy_rssi_select(dev, 1, 0);
1247                 break;
1248         case 2:
1249                 b43_nphy_rssi_select(dev, 1, 1);
1250                 break;
1251         default:
1252                 b43_nphy_rssi_select(dev, 1, 1);
1253                 break;
1254         }
1255
1256         switch (state[3]) {
1257         case 1:
1258                 b43_nphy_rssi_select(dev, 2, 2);
1259                 break;
1260         case 4:
1261                 b43_nphy_rssi_select(dev, 2, 0);
1262                 break;
1263         default:
1264                 b43_nphy_rssi_select(dev, 2, 1);
1265                 break;
1266         }
1267
1268         b43_nphy_rssi_select(dev, 0, type);
1269
1270         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1271         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1272         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1273         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1274
1275         b43_nphy_classifier(dev, 7, class);
1276         b43_nphy_write_clip_detection(dev, clip_state);
1277 }
1278
1279 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1280 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1281 {
1282         /* TODO */
1283 }
1284
1285 /*
1286  * RSSI Calibration
1287  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1288  */
1289 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1290 {
1291         if (dev->phy.rev >= 3) {
1292                 b43_nphy_rev3_rssi_cal(dev);
1293         } else {
1294                 b43_nphy_rev2_rssi_cal(dev, 2);
1295                 b43_nphy_rev2_rssi_cal(dev, 0);
1296                 b43_nphy_rev2_rssi_cal(dev, 1);
1297         }
1298 }
1299
1300 /*
1301  * Restore RSSI Calibration
1302  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1303  */
1304 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1305 {
1306         struct b43_phy_n *nphy = dev->phy.n;
1307
1308         u16 *rssical_radio_regs = NULL;
1309         u16 *rssical_phy_regs = NULL;
1310
1311         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1312                 if (!nphy->rssical_chanspec_2G)
1313                         return;
1314                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1315                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1316         } else {
1317                 if (!nphy->rssical_chanspec_5G)
1318                         return;
1319                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1320                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1321         }
1322
1323         /* TODO use some definitions */
1324         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1325         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1326
1327         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1328         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1329         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1330         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1331
1332         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1333         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1334         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1335         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1336
1337         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1338         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1339         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1340         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1341 }
1342
1343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1344 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1345 {
1346         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1347                 if (dev->phy.rev >= 6) {
1348                         /* TODO If the chip is 47162
1349                                 return txpwrctrl_tx_gain_ipa_rev5 */
1350                         return txpwrctrl_tx_gain_ipa_rev6;
1351                 } else if (dev->phy.rev >= 5) {
1352                         return txpwrctrl_tx_gain_ipa_rev5;
1353                 } else {
1354                         return txpwrctrl_tx_gain_ipa;
1355                 }
1356         } else {
1357                 return txpwrctrl_tx_gain_ipa_5g;
1358         }
1359 }
1360
1361 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1362 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1363 {
1364         struct b43_phy_n *nphy = dev->phy.n;
1365         u16 *save = nphy->tx_rx_cal_radio_saveregs;
1366
1367         if (dev->phy.rev >= 3) {
1368                 /* TODO */
1369         } else {
1370                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1371                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1372
1373                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1374                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1375
1376                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1377                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1378
1379                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1380                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1381
1382                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1383                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1384
1385                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1386                     B43_NPHY_BANDCTL_5GHZ)) {
1387                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1388                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1389                 } else {
1390                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1391                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1392                 }
1393
1394                 if (dev->phy.rev < 2) {
1395                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1396                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1397                 } else {
1398                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1399                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1400                 }
1401         }
1402 }
1403
1404 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1405 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1406                                         struct nphy_txgains target,
1407                                         struct nphy_iqcal_params *params)
1408 {
1409         int i, j, indx;
1410         u16 gain;
1411
1412         if (dev->phy.rev >= 3) {
1413                 params->txgm = target.txgm[core];
1414                 params->pga = target.pga[core];
1415                 params->pad = target.pad[core];
1416                 params->ipa = target.ipa[core];
1417                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1418                                         (params->pad << 4) | (params->ipa);
1419                 for (j = 0; j < 5; j++)
1420                         params->ncorr[j] = 0x79;
1421         } else {
1422                 gain = (target.pad[core]) | (target.pga[core] << 4) |
1423                         (target.txgm[core] << 8);
1424
1425                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1426                         1 : 0;
1427                 for (i = 0; i < 9; i++)
1428                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
1429                                 break;
1430                 i = min(i, 8);
1431
1432                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1433                 params->pga = tbl_iqcal_gainparams[indx][i][2];
1434                 params->pad = tbl_iqcal_gainparams[indx][i][3];
1435                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1436                                         (params->pad << 2);
1437                 for (j = 0; j < 4; j++)
1438                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1439         }
1440 }
1441
1442 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1443 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1444 {
1445         struct b43_phy_n *nphy = dev->phy.n;
1446         int i;
1447         u16 scale, entry;
1448
1449         u16 tmp = nphy->txcal_bbmult;
1450         if (core == 0)
1451                 tmp >>= 8;
1452         tmp &= 0xff;
1453
1454         for (i = 0; i < 18; i++) {
1455                 scale = (ladder_lo[i].percent * tmp) / 100;
1456                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
1457                 /* TODO: Write an N PHY Table with ID 15, length 1,
1458                         offset i, width 16, and data entry */
1459
1460                 scale = (ladder_iq[i].percent * tmp) / 100;
1461                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
1462                 /* TODO: Write an N PHY Table with ID 15, length 1,
1463                         offset i + 32, width 16, and data entry */
1464         }
1465 }
1466
1467 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1468 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1469 {
1470         struct b43_phy_n *nphy = dev->phy.n;
1471
1472         u16 curr_gain[2];
1473         struct nphy_txgains target;
1474         const u32 *table = NULL;
1475
1476         if (nphy->txpwrctrl == 0) {
1477                 int i;
1478
1479                 if (nphy->hang_avoid)
1480                         b43_nphy_stay_in_carrier_search(dev, true);
1481                 /* TODO: Read an N PHY Table with ID 7, length 2,
1482                         offset 0x110, width 16, and curr_gain */
1483                 if (nphy->hang_avoid)
1484                         b43_nphy_stay_in_carrier_search(dev, false);
1485
1486                 for (i = 0; i < 2; ++i) {
1487                         if (dev->phy.rev >= 3) {
1488                                 target.ipa[i] = curr_gain[i] & 0x000F;
1489                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1490                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1491                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1492                         } else {
1493                                 target.ipa[i] = curr_gain[i] & 0x0003;
1494                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1495                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1496                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1497                         }
1498                 }
1499         } else {
1500                 int i;
1501                 u16 index[2];
1502                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1503                         B43_NPHY_TXPCTL_STAT_BIDX) >>
1504                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1505                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1506                         B43_NPHY_TXPCTL_STAT_BIDX) >>
1507                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1508
1509                 for (i = 0; i < 2; ++i) {
1510                         if (dev->phy.rev >= 3) {
1511                                 enum ieee80211_band band =
1512                                         b43_current_band(dev->wl);
1513
1514                                 if ((nphy->ipa2g_on &&
1515                                      band == IEEE80211_BAND_2GHZ) ||
1516                                     (nphy->ipa5g_on &&
1517                                      band == IEEE80211_BAND_5GHZ)) {
1518                                         table = b43_nphy_get_ipa_gain_table(dev);
1519                                 } else {
1520                                         if (band == IEEE80211_BAND_5GHZ) {
1521                                                 if (dev->phy.rev == 3)
1522                                                         table = b43_ntab_tx_gain_rev3_5ghz;
1523                                                 else if (dev->phy.rev == 4)
1524                                                         table = b43_ntab_tx_gain_rev4_5ghz;
1525                                                 else
1526                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
1527                                         } else {
1528                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
1529                                         }
1530                                 }
1531
1532                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1533                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1534                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1535                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1536                         } else {
1537                                 table = b43_ntab_tx_gain_rev0_1_2;
1538
1539                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1540                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1541                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1542                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1543                         }
1544                 }
1545         }
1546
1547         return target;
1548 }
1549
1550 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1551 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1552 {
1553         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1554
1555         if (dev->phy.rev >= 3) {
1556                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1557                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1558                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1559                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1560                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
1561                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1562                         width 16, and data from regs[5] */
1563                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1564                         width 16, and data from regs[6] */
1565                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1566                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1567                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1568                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1569                 b43_nphy_reset_cca(dev);
1570         } else {
1571                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1572                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1573                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
1574                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1575                         width 16, and data from regs[3] */
1576                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1577                         width 16, and data from regs[4] */
1578                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1579                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1580         }
1581 }
1582
1583 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1584 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1585 {
1586         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1587         u16 tmp;
1588
1589         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1590         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1591         if (dev->phy.rev >= 3) {
1592                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1593                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1594
1595                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1596                 regs[2] = tmp;
1597                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1598
1599                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1600                 regs[3] = tmp;
1601                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1602
1603                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
1604                 b43_phy_mask(dev, B43_NPHY_BBCFG, ~B43_NPHY_BBCFG_RSTRX);
1605
1606                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 3,
1607                         width 16, and data pointing to tmp */
1608                 regs[5] = tmp;
1609
1610                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1611                         width 16, and data 0 */
1612                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 19,
1613                         width 16, and data pointing to tmp */
1614                 regs[6] = tmp;
1615
1616                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1617                         width 16, and data 0 */
1618                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1619                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1620
1621                 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1622                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1623                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1624
1625                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1626                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1627                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1628                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1629         } else {
1630                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1631                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1632                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1633                 regs[2] = tmp;
1634                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
1635                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 2,
1636                         width 16, and data pointing to tmp */
1637                 regs[3] = tmp;
1638                 tmp |= 0x2000;
1639                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1640                         width 16, and data pointer tmp */
1641                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 18,
1642                         width 16, and data pointer tmp */
1643                 regs[4] = tmp;
1644                 tmp |= 0x2000;
1645                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1646                         width 16, and data pointer tmp */
1647                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1648                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1649                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1650                         tmp = 0x0180;
1651                 else
1652                         tmp = 0x0120;
1653                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1654                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1655         }
1656 }
1657
1658 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1659 static void b43_nphy_restore_cal(struct b43_wldev *dev)
1660 {
1661         struct b43_phy_n *nphy = dev->phy.n;
1662
1663         u16 coef[4];
1664         u16 *loft = NULL;
1665         u16 *table = NULL;
1666
1667         int i;
1668         u16 *txcal_radio_regs = NULL;
1669         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1670
1671         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1672                 if (nphy->iqcal_chanspec_2G == 0)
1673                         return;
1674                 table = nphy->cal_cache.txcal_coeffs_2G;
1675                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1676         } else {
1677                 if (nphy->iqcal_chanspec_5G == 0)
1678                         return;
1679                 table = nphy->cal_cache.txcal_coeffs_5G;
1680                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1681         }
1682
1683         /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1684                 width 16, and data from table */
1685
1686         for (i = 0; i < 4; i++) {
1687                 if (dev->phy.rev >= 3)
1688                         table[i] = coef[i];
1689                 else
1690                         coef[i] = 0;
1691         }
1692
1693         /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1694                 width 16, and data from coef */
1695         /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1696                 width 16 and data from loft */
1697         /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1698                 width 16 and data from loft */
1699
1700         if (dev->phy.rev < 2)
1701                 b43_nphy_tx_iq_workaround(dev);
1702
1703         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1704                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1705                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1706         } else {
1707                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1708                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1709         }
1710
1711         /* TODO use some definitions */
1712         if (dev->phy.rev >= 3) {
1713                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1714                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1715                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1716                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1717                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1718                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1719                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1720                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1721         } else {
1722                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1723                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1724                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1725                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1726         }
1727         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1728 }
1729
1730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1731 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1732                                 struct nphy_txgains target,
1733                                 bool full, bool mphase)
1734 {
1735         struct b43_phy_n *nphy = dev->phy.n;
1736         int i;
1737         int error = 0;
1738         int freq;
1739         bool avoid = false;
1740         u8 length;
1741         u16 tmp, core, type, count, max, numb, last, cmd;
1742         const u16 *table;
1743         bool phy6or5x;
1744
1745         u16 buffer[11];
1746         u16 diq_start = 0;
1747         u16 save[2];
1748         u16 gain[2];
1749         struct nphy_iqcal_params params[2];
1750         bool updated[2] = { };
1751
1752         b43_nphy_stay_in_carrier_search(dev, true);
1753
1754         if (dev->phy.rev >= 4) {
1755                 avoid = nphy->hang_avoid;
1756                 nphy->hang_avoid = 0;
1757         }
1758
1759         /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1760                 width 16, and data pointer save */
1761
1762         for (i = 0; i < 2; i++) {
1763                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
1764                 gain[i] = params[i].cal_gain;
1765         }
1766         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1767                 width 16, and data pointer gain */
1768
1769         b43_nphy_tx_cal_radio_setup(dev);
1770         b43_nphy_tx_cal_phy_setup(dev);
1771
1772         phy6or5x = dev->phy.rev >= 6 ||
1773                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
1774                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
1775         if (phy6or5x) {
1776                 /* TODO */
1777         }
1778
1779         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
1780
1781         if (1 /* FIXME: the band width is 20 MHz */)
1782                 freq = 2500;
1783         else
1784                 freq = 5000;
1785
1786         if (nphy->mphase_cal_phase_id > 2)
1787                 ;/* TODO: Call N PHY Run Samples with (band width * 8),
1788                         0xFFFF, 0, 1, 0 as arguments */
1789         else
1790                 ;/* TODO: Call N PHY TX Tone with freq, 250, 1, 0 as arguments
1791                         and save result as error */
1792
1793         if (error == 0) {
1794                 if (nphy->mphase_cal_phase_id > 2) {
1795                         table = nphy->mphase_txcal_bestcoeffs;
1796                         length = 11;
1797                         if (dev->phy.rev < 3)
1798                                 length -= 2;
1799                 } else {
1800                         if (!full && nphy->txiqlocal_coeffsvalid) {
1801                                 table = nphy->txiqlocal_bestc;
1802                                 length = 11;
1803                                 if (dev->phy.rev < 3)
1804                                         length -= 2;
1805                         } else {
1806                                 full = true;
1807                                 if (dev->phy.rev >= 3) {
1808                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
1809                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
1810                                 } else {
1811                                         table = tbl_tx_iqlo_cal_startcoefs;
1812                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
1813                                 }
1814                         }
1815                 }
1816
1817                 /* TODO: Write an N PHY Table with ID 15, length from above,
1818                         offset 64, width 16, and the data pointer from above */
1819
1820                 if (full) {
1821                         if (dev->phy.rev >= 3)
1822                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
1823                         else
1824                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
1825                 } else {
1826                         if (dev->phy.rev >= 3)
1827                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
1828                         else
1829                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
1830                 }
1831
1832                 if (mphase) {
1833                         count = nphy->mphase_txcal_cmdidx;
1834                         numb = min(max,
1835                                 (u16)(count + nphy->mphase_txcal_numcmds));
1836                 } else {
1837                         count = 0;
1838                         numb = max;
1839                 }
1840
1841                 for (; count < numb; count++) {
1842                         if (full) {
1843                                 if (dev->phy.rev >= 3)
1844                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
1845                                 else
1846                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
1847                         } else {
1848                                 if (dev->phy.rev >= 3)
1849                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
1850                                 else
1851                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
1852                         }
1853
1854                         core = (cmd & 0x3000) >> 12;
1855                         type = (cmd & 0x0F00) >> 8;
1856
1857                         if (phy6or5x && updated[core] == 0) {
1858                                 b43_nphy_update_tx_cal_ladder(dev, core);
1859                                 updated[core] = 1;
1860                         }
1861
1862                         tmp = (params[core].ncorr[type] << 8) | 0x66;
1863                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
1864
1865                         if (type == 1 || type == 3 || type == 4) {
1866                                 /* TODO: Read an N PHY Table with ID 15,
1867                                         length 1, offset 69 + core,
1868                                         width 16, and data pointer buffer */
1869                                 diq_start = buffer[0];
1870                                 buffer[0] = 0;
1871                                 /* TODO: Write an N PHY Table with ID 15,
1872                                         length 1, offset 69 + core, width 16,
1873                                         and data of 0 */
1874                         }
1875
1876                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
1877                         for (i = 0; i < 2000; i++) {
1878                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
1879                                 if (tmp & 0xC000)
1880                                         break;
1881                                 udelay(10);
1882                         }
1883
1884                         /* TODO: Read an N PHY Table with ID 15,
1885                                 length table_length, offset 96, width 16,
1886                                 and data pointer buffer */
1887                         /* TODO: Write an N PHY Table with ID 15,
1888                                 length table_length, offset 64, width 16,
1889                                 and data pointer buffer */
1890
1891                         if (type == 1 || type == 3 || type == 4)
1892                                 buffer[0] = diq_start;
1893                 }
1894
1895                 if (mphase)
1896                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
1897
1898                 last = (dev->phy.rev < 3) ? 6 : 7;
1899
1900                 if (!mphase || nphy->mphase_cal_phase_id == last) {
1901                         /* TODO: Write an N PHY Table with ID 15, length 4,
1902                                 offset 96, width 16, and data pointer buffer */
1903                         /* TODO: Read an N PHY Table with ID 15, length 4,
1904                                 offset 80, width 16, and data pointer buffer */
1905                         if (dev->phy.rev < 3) {
1906                                 buffer[0] = 0;
1907                                 buffer[1] = 0;
1908                                 buffer[2] = 0;
1909                                 buffer[3] = 0;
1910                         }
1911                         /* TODO: Write an N PHY Table with ID 15, length 4,
1912                                 offset 88, width 16, and data pointer buffer */
1913                         /* TODO: Read an N PHY Table with ID 15, length 2,
1914                                 offset 101, width 16, and data pointer buffer*/
1915                         /* TODO: Write an N PHY Table with ID 15, length 2,
1916                                 offset 85, width 16, and data pointer buffer */
1917                         /* TODO: Write an N PHY Table with ID 15, length 2,
1918                                 offset 93, width 16, and data pointer buffer */
1919                         length = 11;
1920                         if (dev->phy.rev < 3)
1921                                 length -= 2;
1922                         /* TODO: Read an N PHY Table with ID 15, length length,
1923                                 offset 96, width 16, and data pointer
1924                                 nphy->txiqlocal_bestc */
1925                         nphy->txiqlocal_coeffsvalid = true;
1926                         /* TODO: Set nphy->txiqlocal_chanspec to
1927                                 the current channel */
1928                 } else {
1929                         length = 11;
1930                         if (dev->phy.rev < 3)
1931                                 length -= 2;
1932                         /* TODO: Read an N PHY Table with ID 5, length length,
1933                                 offset 96, width 16, and data pointer
1934                                 nphy->mphase_txcal_bestcoeffs */
1935                 }
1936
1937                 b43_nphy_stop_playback(dev);
1938                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
1939         }
1940
1941         b43_nphy_tx_cal_phy_cleanup(dev);
1942         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1943                 width 16, and data from save */
1944
1945         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
1946                 b43_nphy_tx_iq_workaround(dev);
1947
1948         if (dev->phy.rev >= 4)
1949                 nphy->hang_avoid = avoid;
1950
1951         b43_nphy_stay_in_carrier_search(dev, false);
1952
1953         return error;
1954 }
1955
1956 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
1957 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
1958                         struct nphy_txgains target, u8 type, bool debug)
1959 {
1960         struct b43_phy_n *nphy = dev->phy.n;
1961         int i, j, index;
1962         u8 rfctl[2];
1963         u8 afectl_core;
1964         u16 tmp[6];
1965         u16 cur_hpf1, cur_hpf2, cur_lna;
1966         u32 real, imag;
1967         enum ieee80211_band band;
1968
1969         u8 use;
1970         u16 cur_hpf;
1971         u16 lna[3] = { 3, 3, 1 };
1972         u16 hpf1[3] = { 7, 2, 0 };
1973         u16 hpf2[3] = { 2, 0, 0 };
1974         u32 power[3];
1975         u16 gain_save[2];
1976         u16 cal_gain[2];
1977         struct nphy_iqcal_params cal_params[2];
1978         struct nphy_iq_est est;
1979         int ret = 0;
1980         bool playtone = true;
1981         int desired = 13;
1982
1983         b43_nphy_stay_in_carrier_search(dev, 1);
1984
1985         if (dev->phy.rev < 2)
1986                 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
1987         /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1988                 width 16, and data gain_save */
1989         for (i = 0; i < 2; i++) {
1990                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
1991                 cal_gain[i] = cal_params[i].cal_gain;
1992         }
1993         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1994                 width 16, and data from cal_gain */
1995
1996         for (i = 0; i < 2; i++) {
1997                 if (i == 0) {
1998                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
1999                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2000                         afectl_core = B43_NPHY_AFECTL_C1;
2001                 } else {
2002                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2003                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2004                         afectl_core = B43_NPHY_AFECTL_C2;
2005                 }
2006
2007                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2008                 tmp[2] = b43_phy_read(dev, afectl_core);
2009                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2010                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2011                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2012
2013                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2014                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2015                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2016                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2017                                 (1 - i));
2018                 b43_phy_set(dev, afectl_core, 0x0006);
2019                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2020
2021                 band = b43_current_band(dev->wl);
2022
2023                 if (nphy->rxcalparams & 0xFF000000) {
2024                         if (band == IEEE80211_BAND_5GHZ)
2025                                 b43_phy_write(dev, rfctl[0], 0x140);
2026                         else
2027                                 b43_phy_write(dev, rfctl[0], 0x110);
2028                 } else {
2029                         if (band == IEEE80211_BAND_5GHZ)
2030                                 b43_phy_write(dev, rfctl[0], 0x180);
2031                         else
2032                                 b43_phy_write(dev, rfctl[0], 0x120);
2033                 }
2034
2035                 if (band == IEEE80211_BAND_5GHZ)
2036                         b43_phy_write(dev, rfctl[1], 0x148);
2037                 else
2038                         b43_phy_write(dev, rfctl[1], 0x114);
2039
2040                 if (nphy->rxcalparams & 0x10000) {
2041                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2042                                         (i + 1));
2043                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2044                                         (2 - i));
2045                 }
2046
2047                 for (j = 0; i < 4; j++) {
2048                         if (j < 3) {
2049                                 cur_lna = lna[j];
2050                                 cur_hpf1 = hpf1[j];
2051                                 cur_hpf2 = hpf2[j];
2052                         } else {
2053                                 if (power[1] > 10000) {
2054                                         use = 1;
2055                                         cur_hpf = cur_hpf1;
2056                                         index = 2;
2057                                 } else {
2058                                         if (power[0] > 10000) {
2059                                                 use = 1;
2060                                                 cur_hpf = cur_hpf1;
2061                                                 index = 1;
2062                                         } else {
2063                                                 index = 0;
2064                                                 use = 2;
2065                                                 cur_hpf = cur_hpf2;
2066                                         }
2067                                 }
2068                                 cur_lna = lna[index];
2069                                 cur_hpf1 = hpf1[index];
2070                                 cur_hpf2 = hpf2[index];
2071                                 cur_hpf += desired - hweight32(power[index]);
2072                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2073                                 if (use == 1)
2074                                         cur_hpf1 = cur_hpf;
2075                                 else
2076                                         cur_hpf2 = cur_hpf;
2077                         }
2078
2079                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2080                                         (cur_lna << 2));
2081                         /* TODO:Call N PHY RF Ctrl Override with 0x400, tmp[0],
2082                                 3, 0 as arguments */
2083                         /* TODO: Call N PHY Force RF Seq with 2 as argument */
2084                         b43_nphy_stop_playback(dev);
2085
2086                         if (playtone) {
2087                                 /* TODO: Call N PHY TX Tone with 4000,
2088                                         (nphy_rxcalparams & 0xffff), 0, 0
2089                                         as arguments and save result as ret */
2090                                 playtone = false;
2091                         } else {
2092                                 /* TODO: Call N PHY Run Samples with 160,
2093                                         0xFFFF, 0, 0, 0 as arguments */
2094                         }
2095
2096                         if (ret == 0) {
2097                                 if (j < 3) {
2098                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2099                                                                         false);
2100                                         if (i == 0) {
2101                                                 real = est.i0_pwr;
2102                                                 imag = est.q0_pwr;
2103                                         } else {
2104                                                 real = est.i1_pwr;
2105                                                 imag = est.q1_pwr;
2106                                         }
2107                                         power[i] = ((real + imag) / 1024) + 1;
2108                                 } else {
2109                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2110                                 }
2111                                 b43_nphy_stop_playback(dev);
2112                         }
2113
2114                         if (ret != 0)
2115                                 break;
2116                 }
2117
2118                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2119                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2120                 b43_phy_write(dev, rfctl[1], tmp[5]);
2121                 b43_phy_write(dev, rfctl[0], tmp[4]);
2122                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2123                 b43_phy_write(dev, afectl_core, tmp[2]);
2124                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2125
2126                 if (ret != 0)
2127                         break;
2128         }
2129
2130         /* TODO: Call N PHY RF Ctrl Override with 0x400, 0, 3, 1 as arguments*/
2131         /* TODO: Call N PHY Force RF Seq with 2 as argument */
2132         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2133                 width 16, and data from gain_save */
2134
2135         b43_nphy_stay_in_carrier_search(dev, 0);
2136
2137         return ret;
2138 }
2139
2140 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2141                         struct nphy_txgains target, u8 type, bool debug)
2142 {
2143         return -1;
2144 }
2145
2146 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2147 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2148                         struct nphy_txgains target, u8 type, bool debug)
2149 {
2150         if (dev->phy.rev >= 3)
2151                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2152         else
2153                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2154 }
2155
2156 /*
2157  * Init N-PHY
2158  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2159  */
2160 int b43_phy_initn(struct b43_wldev *dev)
2161 {
2162         struct ssb_bus *bus = dev->dev->bus;
2163         struct b43_phy *phy = &dev->phy;
2164         struct b43_phy_n *nphy = phy->n;
2165         u8 tx_pwr_state;
2166         struct nphy_txgains target;
2167         u16 tmp;
2168         enum ieee80211_band tmp2;
2169         bool do_rssi_cal;
2170
2171         u16 clip[2];
2172         bool do_cal = false;
2173
2174         if ((dev->phy.rev >= 3) &&
2175            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2176            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2177                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2178         }
2179         nphy->deaf_count = 0;
2180         b43_nphy_tables_init(dev);
2181         nphy->crsminpwr_adjusted = false;
2182         nphy->noisevars_adjusted = false;
2183
2184         /* Clear all overrides */
2185         if (dev->phy.rev >= 3) {
2186                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2187                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2188                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2189                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2190         } else {
2191                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2192         }
2193         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2194         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
2195         if (dev->phy.rev < 6) {
2196                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2197                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2198         }
2199         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2200                      ~(B43_NPHY_RFSEQMODE_CAOVER |
2201                        B43_NPHY_RFSEQMODE_TROVER));
2202         if (dev->phy.rev >= 3)
2203                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
2204         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2205
2206         if (dev->phy.rev <= 2) {
2207                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2208                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2209                                 ~B43_NPHY_BPHY_CTL3_SCALE,
2210                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2211         }
2212         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2213         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2214
2215         if (bus->sprom.boardflags2_lo & 0x100 ||
2216             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2217              bus->boardinfo.type == 0x8B))
2218                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2219         else
2220                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2221         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2222         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2223         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
2224
2225         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
2226         /* TODO Update TX/RX chain */
2227
2228         if (phy->rev < 2) {
2229                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2230                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2231         }
2232
2233         tmp2 = b43_current_band(dev->wl);
2234         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2235             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2236                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2237                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2238                                 nphy->papd_epsilon_offset[0] << 7);
2239                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2240                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2241                                 nphy->papd_epsilon_offset[1] << 7);
2242                 /* TODO N PHY IPA Set TX Dig Filters */
2243         } else if (phy->rev >= 5) {
2244                 /* TODO N PHY Ext PA Set TX Dig Filters */
2245         }
2246
2247         b43_nphy_workarounds(dev);
2248
2249         /* Reset CCA, in init code it differs a little from standard way */
2250         b43_nphy_bmac_clock_fgc(dev, 1);
2251         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2252         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2253         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
2254         b43_nphy_bmac_clock_fgc(dev, 0);
2255
2256         /* TODO N PHY MAC PHY Clock Set with argument 1 */
2257
2258         b43_nphy_pa_override(dev, false);
2259         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2260         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2261         b43_nphy_pa_override(dev, true);
2262
2263         b43_nphy_classifier(dev, 0, 0);
2264         b43_nphy_read_clip_detection(dev, clip);
2265         tx_pwr_state = nphy->txpwrctrl;
2266         /* TODO N PHY TX power control with argument 0
2267                 (turning off power control) */
2268         /* TODO Fix the TX Power Settings */
2269         /* TODO N PHY TX Power Control Idle TSSI */
2270         /* TODO N PHY TX Power Control Setup */
2271
2272         if (phy->rev >= 3) {
2273                 /* TODO */
2274         } else {
2275                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2276                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2277         }
2278
2279         if (nphy->phyrxchain != 3)
2280                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2281         if (nphy->mphase_cal_phase_id > 0)
2282                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2283
2284         do_rssi_cal = false;
2285         if (phy->rev >= 3) {
2286                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2287                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2288                 else
2289                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2290
2291                 if (do_rssi_cal)
2292                         b43_nphy_rssi_cal(dev);
2293                 else
2294                         b43_nphy_restore_rssi_cal(dev);
2295         } else {
2296                 b43_nphy_rssi_cal(dev);
2297         }
2298
2299         if (!((nphy->measure_hold & 0x6) != 0)) {
2300                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2301                         do_cal = (nphy->iqcal_chanspec_2G == 0);
2302                 else
2303                         do_cal = (nphy->iqcal_chanspec_5G == 0);
2304
2305                 if (nphy->mute)
2306                         do_cal = false;
2307
2308                 if (do_cal) {
2309                         target = b43_nphy_get_tx_gains(dev);
2310
2311                         if (nphy->antsel_type == 2)
2312                                 ;/*TODO NPHY Superswitch Init with argument 1*/
2313                         if (nphy->perical != 2) {
2314                                 b43_nphy_rssi_cal(dev);
2315                                 if (phy->rev >= 3) {
2316                                         nphy->cal_orig_pwr_idx[0] =
2317                                             nphy->txpwrindex[0].index_internal;
2318                                         nphy->cal_orig_pwr_idx[1] =
2319                                             nphy->txpwrindex[1].index_internal;
2320                                         /* TODO N PHY Pre Calibrate TX Gain */
2321                                         target = b43_nphy_get_tx_gains(dev);
2322                                 }
2323                         }
2324                 }
2325         }
2326
2327         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2328                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
2329                         ;/* Call N PHY Save Cal */
2330                 else if (nphy->mphase_cal_phase_id == 0)
2331                         ;/* N PHY Periodic Calibration with argument 3 */
2332         } else {
2333                 b43_nphy_restore_cal(dev);
2334         }
2335
2336         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
2337         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2338         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2339         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2340         if (phy->rev >= 3 && phy->rev <= 6)
2341                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
2342         b43_nphy_tx_lp_fbw(dev);
2343         /* TODO N PHY Spur Workaround */
2344
2345         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
2346         return 0;
2347 }
2348
2349 static int b43_nphy_op_allocate(struct b43_wldev *dev)
2350 {
2351         struct b43_phy_n *nphy;
2352
2353         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2354         if (!nphy)
2355                 return -ENOMEM;
2356         dev->phy.n = nphy;
2357
2358         return 0;
2359 }
2360
2361 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
2362 {
2363         struct b43_phy *phy = &dev->phy;
2364         struct b43_phy_n *nphy = phy->n;
2365
2366         memset(nphy, 0, sizeof(*nphy));
2367
2368         //TODO init struct b43_phy_n
2369 }
2370
2371 static void b43_nphy_op_free(struct b43_wldev *dev)
2372 {
2373         struct b43_phy *phy = &dev->phy;
2374         struct b43_phy_n *nphy = phy->n;
2375
2376         kfree(nphy);
2377         phy->n = NULL;
2378 }
2379
2380 static int b43_nphy_op_init(struct b43_wldev *dev)
2381 {
2382         return b43_phy_initn(dev);
2383 }
2384
2385 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2386 {
2387 #if B43_DEBUG
2388         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2389                 /* OFDM registers are onnly available on A/G-PHYs */
2390                 b43err(dev->wl, "Invalid OFDM PHY access at "
2391                        "0x%04X on N-PHY\n", offset);
2392                 dump_stack();
2393         }
2394         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2395                 /* Ext-G registers are only available on G-PHYs */
2396                 b43err(dev->wl, "Invalid EXT-G PHY access at "
2397                        "0x%04X on N-PHY\n", offset);
2398                 dump_stack();
2399         }
2400 #endif /* B43_DEBUG */
2401 }
2402
2403 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2404 {
2405         check_phyreg(dev, reg);
2406         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2407         return b43_read16(dev, B43_MMIO_PHY_DATA);
2408 }
2409
2410 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2411 {
2412         check_phyreg(dev, reg);
2413         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2414         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2415 }
2416
2417 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2418 {
2419         /* Register 1 is a 32-bit register. */
2420         B43_WARN_ON(reg == 1);
2421         /* N-PHY needs 0x100 for read access */
2422         reg |= 0x100;
2423
2424         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2425         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2426 }
2427
2428 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2429 {
2430         /* Register 1 is a 32-bit register. */
2431         B43_WARN_ON(reg == 1);
2432
2433         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2434         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2435 }
2436
2437 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
2438                                         bool blocked)
2439 {//TODO
2440 }
2441
2442 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2443 {
2444         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2445                       on ? 0 : 0x7FFF);
2446 }
2447
2448 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2449                                       unsigned int new_channel)
2450 {
2451         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2452                 if ((new_channel < 1) || (new_channel > 14))
2453                         return -EINVAL;
2454         } else {
2455                 if (new_channel > 200)
2456                         return -EINVAL;
2457         }
2458
2459         return nphy_channel_switch(dev, new_channel);
2460 }
2461
2462 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2463 {
2464         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2465                 return 1;
2466         return 36;
2467 }
2468
2469 const struct b43_phy_operations b43_phyops_n = {
2470         .allocate               = b43_nphy_op_allocate,
2471         .free                   = b43_nphy_op_free,
2472         .prepare_structs        = b43_nphy_op_prepare_structs,
2473         .init                   = b43_nphy_op_init,
2474         .phy_read               = b43_nphy_op_read,
2475         .phy_write              = b43_nphy_op_write,
2476         .radio_read             = b43_nphy_op_radio_read,
2477         .radio_write            = b43_nphy_op_radio_write,
2478         .software_rfkill        = b43_nphy_op_software_rfkill,
2479         .switch_analog          = b43_nphy_op_switch_analog,
2480         .switch_channel         = b43_nphy_op_switch_channel,
2481         .get_default_chan       = b43_nphy_op_get_default_chan,
2482         .recalc_txpower         = b43_nphy_op_recalc_txpower,
2483         .adjust_txpower         = b43_nphy_op_adjust_txpower,
2484 };