drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "rc.h"
  23 #include "initvals.h"
  24
  25 #define ATH9K_CLOCK_RATE_CCK            22
  26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  28
  29 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  30 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  31 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  32                               struct ar5416_eeprom_def *pEepData,
  33                               u32 reg, u32 value);
  34
  35 MODULE_AUTHOR("Atheros Communications");
  36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  38 MODULE_LICENSE("Dual BSD/GPL");
  39
  40 static int __init ath9k_init(void)
  41 {
  42         return 0;
  43 }
  44 module_init(ath9k_init);
  45
  46 static void __exit ath9k_exit(void)
  47 {
  48         return;
  49 }
  50 module_exit(ath9k_exit);
  51
  52 /********************/
  53 /* Helper Functions */
  54 /********************/
  55
  56 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  57 {
  58         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  59
  60         if (!ah->curchan) /* should really check for CCK instead */
  61                 return usecs *ATH9K_CLOCK_RATE_CCK;
  62         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  63                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  64         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  65 }
  66
  67 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  68 {
  69         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  70
  71         if (conf_is_ht40(conf))
  72                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  73         else
  74                 return ath9k_hw_mac_clks(ah, usecs);
  75 }
  76
  77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  78 {
  79         int i;
  80
  81         BUG_ON(timeout < AH_TIME_QUANTUM);
  82
  83         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  84                 if ((REG_READ(ah, reg) & mask) == val)
  85                         return true;
  86
  87                 udelay(AH_TIME_QUANTUM);
  88         }
  89
  90         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  91                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  92                   timeout, reg, REG_READ(ah, reg), mask, val);
  93
  94         return false;
  95 }
  96 EXPORT_SYMBOL(ath9k_hw_wait);
  97
  98 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  99 {
 100         u32 retval;
 101         int i;
 102
 103         for (i = 0, retval = 0; i < n; i++) {
 104                 retval = (retval << 1) | (val & 1);
 105                 val >>= 1;
 106         }
 107         return retval;
 108 }
 109
 110 bool ath9k_get_channel_edges(struct ath_hw *ah,
 111                              u16 flags, u16 *low,
 112                              u16 *high)
 113 {
 114         struct ath9k_hw_capabilities *pCap = &ah->caps;
 115
 116         if (flags & CHANNEL_5GHZ) {
 117                 *low = pCap->low_5ghz_chan;
 118                 *high = pCap->high_5ghz_chan;
 119                 return true;
 120         }
 121         if ((flags & CHANNEL_2GHZ)) {
 122                 *low = pCap->low_2ghz_chan;
 123                 *high = pCap->high_2ghz_chan;
 124                 return true;
 125         }
 126         return false;
 127 }
 128
 129 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 130                            u8 phy, int kbps,
 131                            u32 frameLen, u16 rateix,
 132                            bool shortPreamble)
 133 {
 134         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 135
 136         if (kbps == 0)
 137                 return 0;
 138
 139         switch (phy) {
 140         case WLAN_RC_PHY_CCK:
 141                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 142                 if (shortPreamble)
 143                         phyTime >>= 1;
 144                 numBits = frameLen << 3;
 145                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 146                 break;
 147         case WLAN_RC_PHY_OFDM:
 148                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 149                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 150                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 151                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 152                         txTime = OFDM_SIFS_TIME_QUARTER
 153                                 + OFDM_PREAMBLE_TIME_QUARTER
 154                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 155                 } else if (ah->curchan &&
 156                            IS_CHAN_HALF_RATE(ah->curchan)) {
 157                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 158                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 159                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 160                         txTime = OFDM_SIFS_TIME_HALF +
 161                                 OFDM_PREAMBLE_TIME_HALF
 162                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 163                 } else {
 164                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 165                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 166                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 167                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 168                                 + (numSymbols * OFDM_SYMBOL_TIME);
 169                 }
 170                 break;
 171         default:
 172                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 173                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 174                 txTime = 0;
 175                 break;
 176         }
 177
 178         return txTime;
 179 }
 180 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 181
 182 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 183                                   struct ath9k_channel *chan,
 184                                   struct chan_centers *centers)
 185 {
 186         int8_t extoff;
 187
 188         if (!IS_CHAN_HT40(chan)) {
 189                 centers->ctl_center = centers->ext_center =
 190                         centers->synth_center = chan->channel;
 191                 return;
 192         }
 193
 194         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 195             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 196                 centers->synth_center =
 197                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 198                 extoff = 1;
 199         } else {
 200                 centers->synth_center =
 201                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 202                 extoff = -1;
 203         }
 204
 205         centers->ctl_center =
 206                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 207         /* 25 MHz spacing is supported by hw but not on upper layers */
 208         centers->ext_center =
 209                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 210 }
 211
 212 /******************/
 213 /* Chip Revisions */
 214 /******************/
 215
 216 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 217 {
 218         u32 val;
 219
 220         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 221
 222         if (val == 0xFF) {
 223                 val = REG_READ(ah, AR_SREV);
 224                 ah->hw_version.macVersion =
 225                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 226                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 227                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 228         } else {
 229                 if (!AR_SREV_9100(ah))
 230                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 231
 232                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 233
 234                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 235                         ah->is_pciexpress = true;
 236         }
 237 }
 238
 239 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 240 {
 241         u32 val;
 242         int i;
 243
 244         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 245
 246         for (i = 0; i < 8; i++)
 247                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 248         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 249         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 250
 251         return ath9k_hw_reverse_bits(val, 8);
 252 }
 253
 254 /************************************/
 255 /* HW Attach, Detach, Init Routines */
 256 /************************************/
 257
 258 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 259 {
 260         if (AR_SREV_9100(ah))
 261                 return;
 262
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 268         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 269         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 270         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 271         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 272
 273         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 274 }
 275
 276 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 277 {
 278         struct ath_common *common = ath9k_hw_common(ah);
 279         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 280         u32 regHold[2];
 281         u32 patternData[4] = { 0x55555555,
 282                                0xaaaaaaaa,
 283                                0x66666666,
 284                                0x99999999 };
 285         int i, j;
 286
 287         for (i = 0; i < 2; i++) {
 288                 u32 addr = regAddr[i];
 289                 u32 wrData, rdData;
 290
 291                 regHold[i] = REG_READ(ah, addr);
 292                 for (j = 0; j < 0x100; j++) {
 293                         wrData = (j << 16) | j;
 294                         REG_WRITE(ah, addr, wrData);
 295                         rdData = REG_READ(ah, addr);
 296                         if (rdData != wrData) {
 297                                 ath_print(common, ATH_DBG_FATAL,
 298                                           "address test failed "
 299                                           "addr: 0x%08x - wr:0x%08x != "
 300                                           "rd:0x%08x\n",
 301                                           addr, wrData, rdData);
 302                                 return false;
 303                         }
 304                 }
 305                 for (j = 0; j < 4; j++) {
 306                         wrData = patternData[j];
 307                         REG_WRITE(ah, addr, wrData);
 308                         rdData = REG_READ(ah, addr);
 309                         if (wrData != rdData) {
 310                                 ath_print(common, ATH_DBG_FATAL,
 311                                           "address test failed "
 312                                           "addr: 0x%08x - wr:0x%08x != "
 313                                           "rd:0x%08x\n",
 314                                           addr, wrData, rdData);
 315                                 return false;
 316                         }
 317                 }
 318                 REG_WRITE(ah, regAddr[i], regHold[i]);
 319         }
 320         udelay(100);
 321
 322         return true;
 323 }
 324
 325 static void ath9k_hw_init_config(struct ath_hw *ah)
 326 {
 327         int i;
 328
 329         ah->config.dma_beacon_response_time = 2;
 330         ah->config.sw_beacon_response_time = 10;
 331         ah->config.additional_swba_backoff = 0;
 332         ah->config.ack_6mb = 0x0;
 333         ah->config.cwm_ignore_extcca = 0;
 334         ah->config.pcie_powersave_enable = 0;
 335         ah->config.pcie_clock_req = 0;
 336         ah->config.pcie_waen = 0;
 337         ah->config.analog_shiftreg = 1;
 338         ah->config.ofdm_trig_low = 200;
 339         ah->config.ofdm_trig_high = 500;
 340         ah->config.cck_trig_high = 200;
 341         ah->config.cck_trig_low = 100;
 342         ah->config.enable_ani = 1;
 343
 344         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 345                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 346                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 347         }
 348
 349         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 350                 ah->config.ht_enable = 1;
 351         else
 352                 ah->config.ht_enable = 0;
 353
 354         ah->config.rx_intr_mitigation = true;
 355
 356         /*
 357          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 358          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 359          * This means we use it for all AR5416 devices, and the few
 360          * minor PCI AR9280 devices out there.
 361          *
 362          * Serialization is required because these devices do not handle
 363          * well the case of two concurrent reads/writes due to the latency
 364          * involved. During one read/write another read/write can be issued
 365          * on another CPU while the previous read/write may still be working
 366          * on our hardware, if we hit this case the hardware poops in a loop.
 367          * We prevent this by serializing reads and writes.
 368          *
 369          * This issue is not present on PCI-Express devices or pre-AR5416
 370          * devices (legacy, 802.11abg).
 371          */
 372         if (num_possible_cpus() > 1)
 373                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 374 }
 375 EXPORT_SYMBOL(ath9k_hw_init);
 376
 377 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 378 {
 379         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 380
 381         regulatory->country_code = CTRY_DEFAULT;
 382         regulatory->power_limit = MAX_RATE_POWER;
 383         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 384
 385         ah->hw_version.magic = AR5416_MAGIC;
 386         ah->hw_version.subvendorid = 0;
 387
 388         ah->ah_flags = 0;
 389         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 390                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 391         if (!AR_SREV_9100(ah))
 392                 ah->ah_flags = AH_USE_EEPROM;
 393
 394         ah->atim_window = 0;
 395         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 396         ah->beacon_interval = 100;
 397         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 398         ah->slottime = (u32) -1;
 399         ah->globaltxtimeout = (u32) -1;
 400         ah->power_mode = ATH9K_PM_UNDEFINED;
 401 }
 402
 403 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 404 {
 405         u32 val;
 406
 407         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 408
 409         val = ath9k_hw_get_radiorev(ah);
 410         switch (val & AR_RADIO_SREV_MAJOR) {
 411         case 0:
 412                 val = AR_RAD5133_SREV_MAJOR;
 413                 break;
 414         case AR_RAD5133_SREV_MAJOR:
 415         case AR_RAD5122_SREV_MAJOR:
 416         case AR_RAD2133_SREV_MAJOR:
 417         case AR_RAD2122_SREV_MAJOR:
 418                 break;
 419         default:
 420                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 421                           "Radio Chip Rev 0x%02X not supported\n",
 422                           val & AR_RADIO_SREV_MAJOR);
 423                 return -EOPNOTSUPP;
 424         }
 425
 426         ah->hw_version.analog5GhzRev = val;
 427
 428         return 0;
 429 }
 430
 431 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 432 {
 433         struct ath_common *common = ath9k_hw_common(ah);
 434         u32 sum;
 435         int i;
 436         u16 eeval;
 437
 438         sum = 0;
 439         for (i = 0; i < 3; i++) {
 440                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 441                 sum += eeval;
 442                 common->macaddr[2 * i] = eeval >> 8;
 443                 common->macaddr[2 * i + 1] = eeval & 0xff;
 444         }
 445         if (sum == 0 || sum == 0xffff * 3)
 446                 return -EADDRNOTAVAIL;
 447
 448         return 0;
 449 }
 450
 451 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 452 {
 453         u32 rxgain_type;
 454
 455         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 456                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 457
 458                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 459                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 460                         ar9280Modes_backoff_13db_rxgain_9280_2,
 461                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 462                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 463                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 464                         ar9280Modes_backoff_23db_rxgain_9280_2,
 465                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 466                 else
 467                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 468                         ar9280Modes_original_rxgain_9280_2,
 469                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 470         } else {
 471                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 472                         ar9280Modes_original_rxgain_9280_2,
 473                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 474         }
 475 }
 476
 477 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 478 {
 479         u32 txgain_type;
 480
 481         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 482                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 483
 484                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 485                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 486                         ar9280Modes_high_power_tx_gain_9280_2,
 487                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 488                 else
 489                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 490                         ar9280Modes_original_tx_gain_9280_2,
 491                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 492         } else {
 493                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 494                 ar9280Modes_original_tx_gain_9280_2,
 495                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 496         }
 497 }
 498
 499 static int ath9k_hw_post_init(struct ath_hw *ah)
 500 {
 501         int ecode;
 502
 503         if (!ath9k_hw_chip_test(ah))
 504                 return -ENODEV;
 505
 506         ecode = ath9k_hw_rf_claim(ah);
 507         if (ecode != 0)
 508                 return ecode;
 509
 510         ecode = ath9k_hw_eeprom_init(ah);
 511         if (ecode != 0)
 512                 return ecode;
 513
 514         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 515                   "Eeprom VER: %d, REV: %d\n",
 516                   ah->eep_ops->get_eeprom_ver(ah),
 517                   ah->eep_ops->get_eeprom_rev(ah));
 518
 519         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 520                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 521                 if (ecode) {
 522                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 523                                   "Failed allocating banks for "
 524                                   "external radio\n");
 525                         return ecode;
 526                 }
 527         }
 528
 529         if (!AR_SREV_9100(ah)) {
 530                 ath9k_hw_ani_setup(ah);
 531                 ath9k_hw_ani_init(ah);
 532         }
 533
 534         return 0;
 535 }
 536
 537 static bool ath9k_hw_devid_supported(u16 devid)
 538 {
 539         switch (devid) {
 540         case AR5416_DEVID_PCI:
 541         case AR5416_DEVID_PCIE:
 542         case AR5416_AR9100_DEVID:
 543         case AR9160_DEVID_PCI:
 544         case AR9280_DEVID_PCI:
 545         case AR9280_DEVID_PCIE:
 546         case AR9285_DEVID_PCIE:
 547         case AR5416_DEVID_AR9287_PCI:
 548         case AR5416_DEVID_AR9287_PCIE:
 549         case AR9271_USB:
 550         case AR2427_DEVID_PCIE:
 551                 return true;
 552         default:
 553                 break;
 554         }
 555         return false;
 556 }
 557
 558 static bool ath9k_hw_macversion_supported(u32 macversion)
 559 {
 560         switch (macversion) {
 561         case AR_SREV_VERSION_5416_PCI:
 562         case AR_SREV_VERSION_5416_PCIE:
 563         case AR_SREV_VERSION_9160:
 564         case AR_SREV_VERSION_9100:
 565         case AR_SREV_VERSION_9280:
 566         case AR_SREV_VERSION_9285:
 567         case AR_SREV_VERSION_9287:
 568         case AR_SREV_VERSION_9271:
 569                 return true;
 570         default:
 571                 break;
 572         }
 573         return false;
 574 }
 575
 576 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 577 {
 578         if (AR_SREV_9160_10_OR_LATER(ah)) {
 579                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 580                         ah->iq_caldata.calData = &iq_cal_single_sample;
 581                         ah->adcgain_caldata.calData =
 582                                 &adc_gain_cal_single_sample;
 583                         ah->adcdc_caldata.calData =
 584                                 &adc_dc_cal_single_sample;
 585                         ah->adcdc_calinitdata.calData =
 586                                 &adc_init_dc_cal;
 587                 } else {
 588                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 589                         ah->adcgain_caldata.calData =
 590                                 &adc_gain_cal_multi_sample;
 591                         ah->adcdc_caldata.calData =
 592                                 &adc_dc_cal_multi_sample;
 593                         ah->adcdc_calinitdata.calData =
 594                                 &adc_init_dc_cal;
 595                 }
 596                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 597         }
 598 }
 599
 600 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 601 {
 602         if (AR_SREV_9271(ah)) {
 603                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 604                                ARRAY_SIZE(ar9271Modes_9271), 6);
 605                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 606                                ARRAY_SIZE(ar9271Common_9271), 2);
 607                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 608                                ar9271Modes_9271_1_0_only,
 609                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 610                 return;
 611         }
 612
 613         if (AR_SREV_9287_11_OR_LATER(ah)) {
 614                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 615                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 616                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 617                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 618                 if (ah->config.pcie_clock_req)
 619                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 620                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 621                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 622                 else
 623                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 624                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 625                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 626                                         2);
 627         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 628                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 629                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 630                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 631                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 632
 633                 if (ah->config.pcie_clock_req)
 634                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 635                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 636                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 637                 else
 638                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 639                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 640                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 641                                   2);
 642         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 643
 644
 645                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 646                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 647                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 648                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 649
 650                 if (ah->config.pcie_clock_req) {
 651                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 652                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 653                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 654                 } else {
 655                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 656                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 657                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 658                                   2);
 659                 }
 660         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 661                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 662                                ARRAY_SIZE(ar9285Modes_9285), 6);
 663                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 664                                ARRAY_SIZE(ar9285Common_9285), 2);
 665
 666                 if (ah->config.pcie_clock_req) {
 667                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 668                         ar9285PciePhy_clkreq_off_L1_9285,
 669                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 670                 } else {
 671                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 672                         ar9285PciePhy_clkreq_always_on_L1_9285,
 673                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 674                 }
 675         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 676                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 677                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 678                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 679                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 680
 681                 if (ah->config.pcie_clock_req) {
 682                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 683                                ar9280PciePhy_clkreq_off_L1_9280,
 684                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 685                 } else {
 686                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 687                                ar9280PciePhy_clkreq_always_on_L1_9280,
 688                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 689                 }
 690                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 691                                ar9280Modes_fast_clock_9280_2,
 692                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 693         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 694                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 695                                ARRAY_SIZE(ar9280Modes_9280), 6);
 696                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 697                                ARRAY_SIZE(ar9280Common_9280), 2);
 698         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 699                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 700                                ARRAY_SIZE(ar5416Modes_9160), 6);
 701                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 702                                ARRAY_SIZE(ar5416Common_9160), 2);
 703                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 704                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 705                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 706                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 707                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 708                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 709                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 710                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 711                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 712                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 713                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 714                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 715                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 716                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 717                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 718                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 719                 if (AR_SREV_9160_11(ah)) {
 720                         INIT_INI_ARRAY(&ah->iniAddac,
 721                                        ar5416Addac_91601_1,
 722                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 723                 } else {
 724                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 725                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 726                 }
 727         } else if (AR_SREV_9100_OR_LATER(ah)) {
 728                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 729                                ARRAY_SIZE(ar5416Modes_9100), 6);
 730                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 731                                ARRAY_SIZE(ar5416Common_9100), 2);
 732                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 733                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 734                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 735                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 736                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 737                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 738                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 739                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 740                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 741                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 742                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 743                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 744                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 745                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 746                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 747                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 748                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 749                                ARRAY_SIZE(ar5416Addac_9100), 2);
 750         } else {
 751                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 752                                ARRAY_SIZE(ar5416Modes), 6);
 753                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 754                                ARRAY_SIZE(ar5416Common), 2);
 755                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 756                                ARRAY_SIZE(ar5416Bank0), 2);
 757                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 758                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 759                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 760                                ARRAY_SIZE(ar5416Bank1), 2);
 761                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 762                                ARRAY_SIZE(ar5416Bank2), 2);
 763                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 764                                ARRAY_SIZE(ar5416Bank3), 3);
 765                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 766                                ARRAY_SIZE(ar5416Bank6), 3);
 767                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 768                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 769                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 770                                ARRAY_SIZE(ar5416Bank7), 2);
 771                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 772                                ARRAY_SIZE(ar5416Addac), 2);
 773         }
 774 }
 775
 776 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 777 {
 778         if (AR_SREV_9287_11_OR_LATER(ah))
 779                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 780                 ar9287Modes_rx_gain_9287_1_1,
 781                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 782         else if (AR_SREV_9287_10(ah))
 783                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 784                 ar9287Modes_rx_gain_9287_1_0,
 785                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 786         else if (AR_SREV_9280_20(ah))
 787                 ath9k_hw_init_rxgain_ini(ah);
 788
 789         if (AR_SREV_9287_11_OR_LATER(ah)) {
 790                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 791                 ar9287Modes_tx_gain_9287_1_1,
 792                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 793         } else if (AR_SREV_9287_10(ah)) {
 794                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 795                 ar9287Modes_tx_gain_9287_1_0,
 796                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 797         } else if (AR_SREV_9280_20(ah)) {
 798                 ath9k_hw_init_txgain_ini(ah);
 799         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 800                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 801
 802                 /* txgain table */
 803                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 804                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 805                         ar9285Modes_high_power_tx_gain_9285_1_2,
 806                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 807                 } else {
 808                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 809                         ar9285Modes_original_tx_gain_9285_1_2,
 810                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 811                 }
 812
 813         }
 814 }
 815
 816 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 817 {
 818         u32 i, j;
 819
 820         if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 821
 822                 /* EEPROM Fixup */
 823                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 824                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 825
 826                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 827                                 u32 val = INI_RA(&ah->iniModes, i, j);
 828
 829                                 INI_RA(&ah->iniModes, i, j) =
 830                                         ath9k_hw_ini_fixup(ah,
 831                                                            &ah->eeprom.def,
 832                                                            reg, val);
 833                         }
 834                 }
 835         }
 836 }
 837
 838 int ath9k_hw_init(struct ath_hw *ah)
 839 {
 840         struct ath_common *common = ath9k_hw_common(ah);
 841         int r = 0;
 842
 843         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 844                 ath_print(common, ATH_DBG_FATAL,
 845                           "Unsupported device ID: 0x%0x\n",
 846                           ah->hw_version.devid);
 847                 return -EOPNOTSUPP;
 848         }
 849
 850         ath9k_hw_init_defaults(ah);
 851         ath9k_hw_init_config(ah);
 852
 853         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 854                 ath_print(common, ATH_DBG_FATAL,
 855                           "Couldn't reset chip\n");
 856                 return -EIO;
 857         }
 858
 859         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 860                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 861                 return -EIO;
 862         }
 863
 864         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 865                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 866                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 867                         ah->config.serialize_regmode =
 868                                 SER_REG_MODE_ON;
 869                 } else {
 870                         ah->config.serialize_regmode =
 871                                 SER_REG_MODE_OFF;
 872                 }
 873         }
 874
 875         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 876                 ah->config.serialize_regmode);
 877
 878         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 879                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 880         else
 881                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 882
 883         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 884                 ath_print(common, ATH_DBG_FATAL,
 885                           "Mac Chip Rev 0x%02x.%x is not supported by "
 886                           "this driver\n", ah->hw_version.macVersion,
 887                           ah->hw_version.macRev);
 888                 return -EOPNOTSUPP;
 889         }
 890
 891         if (AR_SREV_9100(ah)) {
 892                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 893                 ah->supp_cals = IQ_MISMATCH_CAL;
 894                 ah->is_pciexpress = false;
 895         }
 896
 897         if (AR_SREV_9271(ah))
 898                 ah->is_pciexpress = false;
 899
 900         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 901
 902         ath9k_hw_init_cal_settings(ah);
 903
 904         ah->ani_function = ATH9K_ANI_ALL;
 905         if (AR_SREV_9280_10_OR_LATER(ah)) {
 906                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 907                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 908                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 909         } else {
 910                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 911                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 912         }
 913
 914         ath9k_hw_init_mode_regs(ah);
 915
 916         if (ah->is_pciexpress)
 917                 ath9k_hw_configpcipowersave(ah, 0, 0);
 918         else
 919                 ath9k_hw_disablepcie(ah);
 920
 921         /* Support for Japan ch.14 (2484) spread */
 922         if (AR_SREV_9287_11_OR_LATER(ah)) {
 923                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 924                        ar9287Common_normal_cck_fir_coeff_92871_1,
 925                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 926                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 927                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 928                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 929         }
 930
 931         r = ath9k_hw_post_init(ah);
 932         if (r)
 933                 return r;
 934
 935         ath9k_hw_init_mode_gain_regs(ah);
 936         r = ath9k_hw_fill_cap_info(ah);
 937         if (r)
 938                 return r;
 939
 940         ath9k_hw_init_eeprom_fix(ah);
 941
 942         r = ath9k_hw_init_macaddr(ah);
 943         if (r) {
 944                 ath_print(common, ATH_DBG_FATAL,
 945                           "Failed to initialize MAC address\n");
 946                 return r;
 947         }
 948
 949         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 950                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 951         else
 952                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 953
 954         ath9k_init_nfcal_hist_buffer(ah);
 955
 956         common->state = ATH_HW_INITIALIZED;
 957
 958         return 0;
 959 }
 960
 961 static void ath9k_hw_init_bb(struct ath_hw *ah,
 962                              struct ath9k_channel *chan)
 963 {
 964         u32 synthDelay;
 965
 966         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 967         if (IS_CHAN_B(chan))
 968                 synthDelay = (4 * synthDelay) / 22;
 969         else
 970                 synthDelay /= 10;
 971
 972         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 973
 974         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 975 }
 976
 977 static void ath9k_hw_init_qos(struct ath_hw *ah)
 978 {
 979         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 980         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 981
 982         REG_WRITE(ah, AR_QOS_NO_ACK,
 983                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 984                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 985                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 986
 987         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 988         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 989         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 990         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 991         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 992 }
 993
 994 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
 995 {
 996         u32 lcr;
 997         u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
 998
 999         lcr = REG_READ(ah , 0x5100c);
1000         lcr |= 0x80;
1001
1002         REG_WRITE(ah, 0x5100c, lcr);
1003         REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1004         REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1005
1006         lcr &= ~0x80;
1007         REG_WRITE(ah, 0x5100c, lcr);
1008 }
1009
1010 static void ath9k_hw_init_pll(struct ath_hw *ah,
1011                               struct ath9k_channel *chan)
1012 {
1013         u32 pll;
1014
1015         if (AR_SREV_9100(ah)) {
1016                 if (chan && IS_CHAN_5GHZ(chan))
1017                         pll = 0x1450;
1018                 else
1019                         pll = 0x1458;
1020         } else {
1021                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1022                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1023
1024                         if (chan && IS_CHAN_HALF_RATE(chan))
1025                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1026                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1027                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1028
1029                         if (chan && IS_CHAN_5GHZ(chan)) {
1030                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1031
1032
1033                                 if (AR_SREV_9280_20(ah)) {
1034                                         if (((chan->channel % 20) == 0)
1035                                             || ((chan->channel % 10) == 0))
1036                                                 pll = 0x2850;
1037                                         else
1038                                                 pll = 0x142c;
1039                                 }
1040                         } else {
1041                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1042                         }
1043
1044                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1045
1046                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1047
1048                         if (chan && IS_CHAN_HALF_RATE(chan))
1049                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1050                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1051                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1052
1053                         if (chan && IS_CHAN_5GHZ(chan))
1054                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1055                         else
1056                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1057                 } else {
1058                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1059
1060                         if (chan && IS_CHAN_HALF_RATE(chan))
1061                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1062                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1063                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1064
1065                         if (chan && IS_CHAN_5GHZ(chan))
1066                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1067                         else
1068                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1069                 }
1070         }
1071         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1072
1073         /* Switch the core clock for ar9271 to 117Mhz */
1074         if (AR_SREV_9271(ah)) {
1075                 if ((pll == 0x142c) || (pll == 0x2850) ) {
1076                         udelay(500);
1077                         /* set CLKOBS to output AHB clock */
1078                         REG_WRITE(ah, 0x7020, 0xe);
1079                         /*
1080                          * 0x304: 117Mhz, ahb_ratio: 1x1
1081                          * 0x306: 40Mhz, ahb_ratio: 1x1
1082                          */
1083                         REG_WRITE(ah, 0x50040, 0x304);
1084                         /*
1085                          * makes adjustments for the baud dividor to keep the
1086                          * targetted baud rate based on the used core clock.
1087                          */
1088                         ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1089                                                     AR9271_TARGET_BAUD_RATE);
1090                 }
1091         }
1092
1093         udelay(RTC_PLL_SETTLE_DELAY);
1094
1095         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1096 }
1097
1098 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1099 {
1100         int rx_chainmask, tx_chainmask;
1101
1102         rx_chainmask = ah->rxchainmask;
1103         tx_chainmask = ah->txchainmask;
1104
1105         switch (rx_chainmask) {
1106         case 0x5:
1107                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108                             AR_PHY_SWAP_ALT_CHAIN);
1109         case 0x3:
1110                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1111                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113                         break;
1114                 }
1115         case 0x1:
1116         case 0x2:
1117         case 0x7:
1118                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1119                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1120                 break;
1121         default:
1122                 break;
1123         }
1124
1125         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1126         if (tx_chainmask == 0x5) {
1127                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1128                             AR_PHY_SWAP_ALT_CHAIN);
1129         }
1130         if (AR_SREV_9100(ah))
1131                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1132                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1133 }
1134
1135 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1136                                           enum nl80211_iftype opmode)
1137 {
1138         ah->mask_reg = AR_IMR_TXERR |
1139                 AR_IMR_TXURN |
1140                 AR_IMR_RXERR |
1141                 AR_IMR_RXORN |
1142                 AR_IMR_BCNMISC;
1143
1144         if (ah->config.rx_intr_mitigation)
1145                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1146         else
1147                 ah->mask_reg |= AR_IMR_RXOK;
1148
1149         ah->mask_reg |= AR_IMR_TXOK;
1150
1151         if (opmode == NL80211_IFTYPE_AP)
1152                 ah->mask_reg |= AR_IMR_MIB;
1153
1154         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1155         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1156
1157         if (!AR_SREV_9100(ah)) {
1158                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1159                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1160                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1161         }
1162 }
1163
1164 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1165 {
1166         u32 val = ath9k_hw_mac_to_clks(ah, us);
1167         val = min(val, (u32) 0xFFFF);
1168         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1169 }
1170
1171 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1172 {
1173         u32 val = ath9k_hw_mac_to_clks(ah, us);
1174         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1175         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1176 }
1177
1178 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1179 {
1180         u32 val = ath9k_hw_mac_to_clks(ah, us);
1181         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1182         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1183 }
1184
1185 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1186 {
1187         if (tu > 0xFFFF) {
1188                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1189                           "bad global tx timeout %u\n", tu);
1190                 ah->globaltxtimeout = (u32) -1;
1191                 return false;
1192         } else {
1193                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1194                 ah->globaltxtimeout = tu;
1195                 return true;
1196         }
1197 }
1198
1199 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1200 {
1201         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1202         int acktimeout;
1203         int slottime;
1204         int sifstime;
1205
1206         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1207                   ah->misc_mode);
1208
1209         if (ah->misc_mode != 0)
1210                 REG_WRITE(ah, AR_PCU_MISC,
1211                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1212
1213         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1214                 sifstime = 16;
1215         else
1216                 sifstime = 10;
1217
1218         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1219         slottime = ah->slottime + 3 * ah->coverage_class;
1220         acktimeout = slottime + sifstime;
1221
1222         /*
1223          * Workaround for early ACK timeouts, add an offset to match the
1224          * initval's 64us ack timeout value.
1225          * This was initially only meant to work around an issue with delayed
1226          * BA frames in some implementations, but it has been found to fix ACK
1227          * timeout issues in other cases as well.
1228          */
1229         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1230                 acktimeout += 64 - sifstime - ah->slottime;
1231
1232         ath9k_hw_setslottime(ah, slottime);
1233         ath9k_hw_set_ack_timeout(ah, acktimeout);
1234         ath9k_hw_set_cts_timeout(ah, acktimeout);
1235         if (ah->globaltxtimeout != (u32) -1)
1236                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1237 }
1238 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1239
1240 void ath9k_hw_deinit(struct ath_hw *ah)
1241 {
1242         struct ath_common *common = ath9k_hw_common(ah);
1243
1244         if (common->state <= ATH_HW_INITIALIZED)
1245                 goto free_hw;
1246
1247         if (!AR_SREV_9100(ah))
1248                 ath9k_hw_ani_disable(ah);
1249
1250         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1251
1252 free_hw:
1253         if (!AR_SREV_9280_10_OR_LATER(ah))
1254                 ath9k_hw_rf_free_ext_banks(ah);
1255         kfree(ah);
1256         ah = NULL;
1257 }
1258 EXPORT_SYMBOL(ath9k_hw_deinit);
1259
1260 /*******/
1261 /* INI */
1262 /*******/
1263
1264 static void ath9k_hw_override_ini(struct ath_hw *ah,
1265                                   struct ath9k_channel *chan)
1266 {
1267         u32 val;
1268
1269         if (AR_SREV_9271(ah)) {
1270                 /*
1271                  * Enable spectral scan to solution for issues with stuck
1272                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1273                  * AR9271 1.1
1274                  */
1275                 if (AR_SREV_9271_10(ah)) {
1276                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1277                               AR_PHY_SPECTRAL_SCAN_ENABLE;
1278                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1279                 }
1280                 else if (AR_SREV_9271_11(ah))
1281                         /*
1282                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1283                          * present on AR9271 1.1
1284                          */
1285                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1286                 return;
1287         }
1288
1289         /*
1290          * Set the RX_ABORT and RX_DIS and clear if off only after
1291          * RXE is set for MAC. This prevents frames with corrupted
1292          * descriptor status.
1293          */
1294         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1295
1296         if (AR_SREV_9280_10_OR_LATER(ah)) {
1297                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1298                                (~AR_PCU_MISC_MODE2_HWWAR1);
1299
1300                 if (AR_SREV_9287_10_OR_LATER(ah))
1301                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1302
1303                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1304         }
1305
1306         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1307             AR_SREV_9280_10_OR_LATER(ah))
1308                 return;
1309         /*
1310          * Disable BB clock gating
1311          * Necessary to avoid issues on AR5416 2.0
1312          */
1313         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1314
1315         /*
1316          * Disable RIFS search on some chips to avoid baseband
1317          * hang issues.
1318          */
1319         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1320                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1321                 val &= ~AR_PHY_RIFS_INIT_DELAY;
1322                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1323         }
1324 }
1325
1326 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1327                               struct ar5416_eeprom_def *pEepData,
1328                               u32 reg, u32 value)
1329 {
1330         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1331         struct ath_common *common = ath9k_hw_common(ah);
1332
1333         switch (ah->hw_version.devid) {
1334         case AR9280_DEVID_PCI:
1335                 if (reg == 0x7894) {
1336                         ath_print(common, ATH_DBG_EEPROM,
1337                                 "ini VAL: %x  EEPROM: %x\n", value,
1338                                 (pBase->version & 0xff));
1339
1340                         if ((pBase->version & 0xff) > 0x0a) {
1341                                 ath_print(common, ATH_DBG_EEPROM,
1342                                           "PWDCLKIND: %d\n",
1343                                           pBase->pwdclkind);
1344                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1345                                 value |= AR_AN_TOP2_PWDCLKIND &
1346                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1347                         } else {
1348                                 ath_print(common, ATH_DBG_EEPROM,
1349                                           "PWDCLKIND Earlier Rev\n");
1350                         }
1351
1352                         ath_print(common, ATH_DBG_EEPROM,
1353                                   "final ini VAL: %x\n", value);
1354                 }
1355                 break;
1356         }
1357
1358         return value;
1359 }
1360
1361 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1362                               struct ar5416_eeprom_def *pEepData,
1363                               u32 reg, u32 value)
1364 {
1365         if (ah->eep_map == EEP_MAP_4KBITS)
1366                 return value;
1367         else
1368                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1369 }
1370
1371 static void ath9k_olc_init(struct ath_hw *ah)
1372 {
1373         u32 i;
1374
1375         if (OLC_FOR_AR9287_10_LATER) {
1376                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1377                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1378                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1379                                 AR9287_AN_TXPC0_TXPCMODE,
1380                                 AR9287_AN_TXPC0_TXPCMODE_S,
1381                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1382                 udelay(100);
1383         } else {
1384                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1385                         ah->originalGain[i] =
1386                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1387                                                 AR_PHY_TX_GAIN);
1388                 ah->PDADCdelta = 0;
1389         }
1390 }
1391
1392 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1393                               struct ath9k_channel *chan)
1394 {
1395         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1396
1397         if (IS_CHAN_B(chan))
1398                 ctl |= CTL_11B;
1399         else if (IS_CHAN_G(chan))
1400                 ctl |= CTL_11G;
1401         else
1402                 ctl |= CTL_11A;
1403
1404         return ctl;
1405 }
1406
1407 static int ath9k_hw_process_ini(struct ath_hw *ah,
1408                                 struct ath9k_channel *chan)
1409 {
1410         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1411         int i, regWrites = 0;
1412         struct ieee80211_channel *channel = chan->chan;
1413         u32 modesIndex, freqIndex;
1414
1415         switch (chan->chanmode) {
1416         case CHANNEL_A:
1417         case CHANNEL_A_HT20:
1418                 modesIndex = 1;
1419                 freqIndex = 1;
1420                 break;
1421         case CHANNEL_A_HT40PLUS:
1422         case CHANNEL_A_HT40MINUS:
1423                 modesIndex = 2;
1424                 freqIndex = 1;
1425                 break;
1426         case CHANNEL_G:
1427         case CHANNEL_G_HT20:
1428         case CHANNEL_B:
1429                 modesIndex = 4;
1430                 freqIndex = 2;
1431                 break;
1432         case CHANNEL_G_HT40PLUS:
1433         case CHANNEL_G_HT40MINUS:
1434                 modesIndex = 3;
1435                 freqIndex = 2;
1436                 break;
1437
1438         default:
1439                 return -EINVAL;
1440         }
1441
1442         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1443         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1444         ah->eep_ops->set_addac(ah, chan);
1445
1446         if (AR_SREV_5416_22_OR_LATER(ah)) {
1447                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1448         } else {
1449                 struct ar5416IniArray temp;
1450                 u32 addacSize =
1451                         sizeof(u32) * ah->iniAddac.ia_rows *
1452                         ah->iniAddac.ia_columns;
1453
1454                 memcpy(ah->addac5416_21,
1455                        ah->iniAddac.ia_array, addacSize);
1456
1457                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1458
1459                 temp.ia_array = ah->addac5416_21;
1460                 temp.ia_columns = ah->iniAddac.ia_columns;
1461                 temp.ia_rows = ah->iniAddac.ia_rows;
1462                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1463         }
1464
1465         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1466
1467         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1468                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1469                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1470
1471                 REG_WRITE(ah, reg, val);
1472
1473                 if (reg >= 0x7800 && reg < 0x78a0
1474                     && ah->config.analog_shiftreg) {
1475                         udelay(100);
1476                 }
1477
1478                 DO_DELAY(regWrites);
1479         }
1480
1481         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1482                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1483
1484         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1485             AR_SREV_9287_10_OR_LATER(ah))
1486                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1487
1488         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1489                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1490                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1491
1492                 REG_WRITE(ah, reg, val);
1493
1494                 if (reg >= 0x7800 && reg < 0x78a0
1495                     && ah->config.analog_shiftreg) {
1496                         udelay(100);
1497                 }
1498
1499                 DO_DELAY(regWrites);
1500         }
1501
1502         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1503
1504         if (AR_SREV_9271_10(ah))
1505                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1506                                 modesIndex, regWrites);
1507
1508         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1509                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1510                                 regWrites);
1511         }
1512
1513         ath9k_hw_override_ini(ah, chan);
1514         ath9k_hw_set_regs(ah, chan);
1515         ath9k_hw_init_chain_masks(ah);
1516
1517         if (OLC_FOR_AR9280_20_LATER)
1518                 ath9k_olc_init(ah);
1519
1520         ah->eep_ops->set_txpower(ah, chan,
1521                                  ath9k_regd_get_ctl(regulatory, chan),
1522                                  channel->max_antenna_gain * 2,
1523                                  channel->max_power * 2,
1524                                  min((u32) MAX_RATE_POWER,
1525                                  (u32) regulatory->power_limit));
1526
1527         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1528                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1529                           "ar5416SetRfRegs failed\n");
1530                 return -EIO;
1531         }
1532
1533         return 0;
1534 }
1535
1536 /****************************************/
1537 /* Reset and Channel Switching Routines */
1538 /****************************************/
1539
1540 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1541 {
1542         u32 rfMode = 0;
1543
1544         if (chan == NULL)
1545                 return;
1546
1547         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1548                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1549
1550         if (!AR_SREV_9280_10_OR_LATER(ah))
1551                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1552                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1553
1554         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1555                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1556
1557         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1558 }
1559
1560 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1561 {
1562         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1563 }
1564
1565 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1566 {
1567         u32 regval;
1568
1569         /*
1570          * set AHB_MODE not to do cacheline prefetches
1571         */
1572         regval = REG_READ(ah, AR_AHB_MODE);
1573         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1574
1575         /*
1576          * let mac dma reads be in 128 byte chunks
1577          */
1578         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1579         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1580
1581         /*
1582          * Restore TX Trigger Level to its pre-reset value.
1583          * The initial value depends on whether aggregation is enabled, and is
1584          * adjusted whenever underruns are detected.
1585          */
1586         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1587
1588         /*
1589          * let mac dma writes be in 128 byte chunks
1590          */
1591         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1592         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1593
1594         /*
1595          * Setup receive FIFO threshold to hold off TX activities
1596          */
1597         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1598
1599         /*
1600          * reduce the number of usable entries in PCU TXBUF to avoid
1601          * wrap around issues.
1602          */
1603         if (AR_SREV_9285(ah)) {
1604                 /* For AR9285 the number of Fifos are reduced to half.
1605                  * So set the usable tx buf size also to half to
1606                  * avoid data/delimiter underruns
1607                  */
1608                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1609                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1610         } else if (!AR_SREV_9271(ah)) {
1611                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1612                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1613         }
1614 }
1615
1616 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1617 {
1618         u32 val;
1619
1620         val = REG_READ(ah, AR_STA_ID1);
1621         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1622         switch (opmode) {
1623         case NL80211_IFTYPE_AP:
1624                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1625                           | AR_STA_ID1_KSRCH_MODE);
1626                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1627                 break;
1628         case NL80211_IFTYPE_ADHOC:
1629         case NL80211_IFTYPE_MESH_POINT:
1630                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1631                           | AR_STA_ID1_KSRCH_MODE);
1632                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1633                 break;
1634         case NL80211_IFTYPE_STATION:
1635         case NL80211_IFTYPE_MONITOR:
1636                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1637                 break;
1638         }
1639 }
1640
1641 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1642                                                  u32 coef_scaled,
1643                                                  u32 *coef_mantissa,
1644                                                  u32 *coef_exponent)
1645 {
1646         u32 coef_exp, coef_man;
1647
1648         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1649                 if ((coef_scaled >> coef_exp) & 0x1)
1650                         break;
1651
1652         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1653
1654         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1655
1656         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1657         *coef_exponent = coef_exp - 16;
1658 }
1659
1660 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1661                                      struct ath9k_channel *chan)
1662 {
1663         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1664         u32 clockMhzScaled = 0x64000000;
1665         struct chan_centers centers;
1666
1667         if (IS_CHAN_HALF_RATE(chan))
1668                 clockMhzScaled = clockMhzScaled >> 1;
1669         else if (IS_CHAN_QUARTER_RATE(chan))
1670                 clockMhzScaled = clockMhzScaled >> 2;
1671
1672         ath9k_hw_get_channel_centers(ah, chan, &centers);
1673         coef_scaled = clockMhzScaled / centers.synth_center;
1674
1675         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1676                                       &ds_coef_exp);
1677
1678         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1679                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1680         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1681                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1682
1683         coef_scaled = (9 * coef_scaled) / 10;
1684
1685         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1686                                       &ds_coef_exp);
1687
1688         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1689                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1690         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1691                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1692 }
1693
1694 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1695 {
1696         u32 rst_flags;
1697         u32 tmpReg;
1698
1699         if (AR_SREV_9100(ah)) {
1700                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1701                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1702                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1703                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1704                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1705         }
1706
1707         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1708                   AR_RTC_FORCE_WAKE_ON_INT);
1709
1710         if (AR_SREV_9100(ah)) {
1711                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1712                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1713         } else {
1714                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1715                 if (tmpReg &
1716                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1717                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1718                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1719                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1720                 } else {
1721                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1722                 }
1723
1724                 rst_flags = AR_RTC_RC_MAC_WARM;
1725                 if (type == ATH9K_RESET_COLD)
1726                         rst_flags |= AR_RTC_RC_MAC_COLD;
1727         }
1728
1729         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1730         udelay(50);
1731
1732         REG_WRITE(ah, AR_RTC_RC, 0);
1733         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1734                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1735                           "RTC stuck in MAC reset\n");
1736                 return false;
1737         }
1738
1739         if (!AR_SREV_9100(ah))
1740                 REG_WRITE(ah, AR_RC, 0);
1741
1742         if (AR_SREV_9100(ah))
1743                 udelay(50);
1744
1745         return true;
1746 }
1747
1748 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1749 {
1750         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1751                   AR_RTC_FORCE_WAKE_ON_INT);
1752
1753         if (!AR_SREV_9100(ah))
1754                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1755
1756         REG_WRITE(ah, AR_RTC_RESET, 0);
1757         udelay(2);
1758
1759         if (!AR_SREV_9100(ah))
1760                 REG_WRITE(ah, AR_RC, 0);
1761
1762         REG_WRITE(ah, AR_RTC_RESET, 1);
1763
1764         if (!ath9k_hw_wait(ah,
1765                            AR_RTC_STATUS,
1766                            AR_RTC_STATUS_M,
1767                            AR_RTC_STATUS_ON,
1768                            AH_WAIT_TIMEOUT)) {
1769                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1770                           "RTC not waking up\n");
1771                 return false;
1772         }
1773
1774         ath9k_hw_read_revisions(ah);
1775
1776         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1777 }
1778
1779 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1780 {
1781         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1782                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1783
1784         switch (type) {
1785         case ATH9K_RESET_POWER_ON:
1786                 return ath9k_hw_set_reset_power_on(ah);
1787         case ATH9K_RESET_WARM:
1788         case ATH9K_RESET_COLD:
1789                 return ath9k_hw_set_reset(ah, type);
1790         default:
1791                 return false;
1792         }
1793 }
1794
1795 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1796 {
1797         u32 phymode;
1798         u32 enableDacFifo = 0;
1799
1800         if (AR_SREV_9285_10_OR_LATER(ah))
1801                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1802                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1803
1804         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1805                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1806
1807         if (IS_CHAN_HT40(chan)) {
1808                 phymode |= AR_PHY_FC_DYN2040_EN;
1809
1810                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1811                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1812                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1813
1814         }
1815         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1816
1817         ath9k_hw_set11nmac2040(ah);
1818
1819         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1820         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1821 }
1822
1823 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1824                                 struct ath9k_channel *chan)
1825 {
1826         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1827                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1828                         return false;
1829         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1830                 return false;
1831
1832         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1833                 return false;
1834
1835         ah->chip_fullsleep = false;
1836         ath9k_hw_init_pll(ah, chan);
1837         ath9k_hw_set_rfmode(ah, chan);
1838
1839         return true;
1840 }
1841
1842 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1843                                     struct ath9k_channel *chan)
1844 {
1845         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1846         struct ath_common *common = ath9k_hw_common(ah);
1847         struct ieee80211_channel *channel = chan->chan;
1848         u32 synthDelay, qnum;
1849         int r;
1850
1851         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1852                 if (ath9k_hw_numtxpending(ah, qnum)) {
1853                         ath_print(common, ATH_DBG_QUEUE,
1854                                   "Transmit frames pending on "
1855                                   "queue %d\n", qnum);
1856                         return false;
1857                 }
1858         }
1859
1860         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1861         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1862                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1863                 ath_print(common, ATH_DBG_FATAL,
1864                           "Could not kill baseband RX\n");
1865                 return false;
1866         }
1867
1868         ath9k_hw_set_regs(ah, chan);
1869
1870         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1871         if (r) {
1872                 ath_print(common, ATH_DBG_FATAL,
1873                           "Failed to set channel\n");
1874                 return false;
1875         }
1876
1877         ah->eep_ops->set_txpower(ah, chan,
1878                              ath9k_regd_get_ctl(regulatory, chan),
1879                              channel->max_antenna_gain * 2,
1880                              channel->max_power * 2,
1881                              min((u32) MAX_RATE_POWER,
1882                              (u32) regulatory->power_limit));
1883
1884         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1885         if (IS_CHAN_B(chan))
1886                 synthDelay = (4 * synthDelay) / 22;
1887         else
1888                 synthDelay /= 10;
1889
1890         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1891
1892         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1893
1894         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1895                 ath9k_hw_set_delta_slope(ah, chan);
1896
1897         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1898
1899         if (!chan->oneTimeCalsDone)
1900                 chan->oneTimeCalsDone = true;
1901
1902         return true;
1903 }
1904
1905 static void ath9k_enable_rfkill(struct ath_hw *ah)
1906 {
1907         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1908                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1909
1910         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1911                     AR_GPIO_INPUT_MUX2_RFSILENT);
1912
1913         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1914         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1915 }
1916
1917 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1918                     bool bChannelChange)
1919 {
1920         struct ath_common *common = ath9k_hw_common(ah);
1921         u32 saveLedState;
1922         struct ath9k_channel *curchan = ah->curchan;
1923         u32 saveDefAntenna;
1924         u32 macStaId1;
1925         u64 tsf = 0;
1926         int i, rx_chainmask, r;
1927
1928         ah->txchainmask = common->tx_chainmask;
1929         ah->rxchainmask = common->rx_chainmask;
1930
1931         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1932                 return -EIO;
1933
1934         if (curchan && !ah->chip_fullsleep)
1935                 ath9k_hw_getnf(ah, curchan);
1936
1937         if (bChannelChange &&
1938             (ah->chip_fullsleep != true) &&
1939             (ah->curchan != NULL) &&
1940             (chan->channel != ah->curchan->channel) &&
1941             ((chan->channelFlags & CHANNEL_ALL) ==
1942              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1943              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1944              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1945
1946                 if (ath9k_hw_channel_change(ah, chan)) {
1947                         ath9k_hw_loadnf(ah, ah->curchan);
1948                         ath9k_hw_start_nfcal(ah);
1949                         return 0;
1950                 }
1951         }
1952
1953         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1954         if (saveDefAntenna == 0)
1955                 saveDefAntenna = 1;
1956
1957         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1958
1959         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1960         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1961                 tsf = ath9k_hw_gettsf64(ah);
1962
1963         saveLedState = REG_READ(ah, AR_CFG_LED) &
1964                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1965                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1966
1967         ath9k_hw_mark_phy_inactive(ah);
1968
1969         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1970                 REG_WRITE(ah,
1971                           AR9271_RESET_POWER_DOWN_CONTROL,
1972                           AR9271_RADIO_RF_RST);
1973                 udelay(50);
1974         }
1975
1976         if (!ath9k_hw_chip_reset(ah, chan)) {
1977                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1978                 return -EINVAL;
1979         }
1980
1981         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1982                 ah->htc_reset_init = false;
1983                 REG_WRITE(ah,
1984                           AR9271_RESET_POWER_DOWN_CONTROL,
1985                           AR9271_GATE_MAC_CTL);
1986                 udelay(50);
1987         }
1988
1989         /* Restore TSF */
1990         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1991                 ath9k_hw_settsf64(ah, tsf);
1992
1993         if (AR_SREV_9280_10_OR_LATER(ah))
1994                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1995
1996         if (AR_SREV_9287_12_OR_LATER(ah)) {
1997                 /* Enable ASYNC FIFO */
1998                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1999                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2000                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2001                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2002                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2003                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2004                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2005         }
2006         r = ath9k_hw_process_ini(ah, chan);
2007         if (r)
2008                 return r;
2009
2010         /* Setup MFP options for CCMP */
2011         if (AR_SREV_9280_20_OR_LATER(ah)) {
2012                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2013                  * frames when constructing CCMP AAD. */
2014                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2015                               0xc7ff);
2016                 ah->sw_mgmt_crypto = false;
2017         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2018                 /* Disable hardware crypto for management frames */
2019                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2020                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2021                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2022                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2023                 ah->sw_mgmt_crypto = true;
2024         } else
2025                 ah->sw_mgmt_crypto = true;
2026
2027         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2028                 ath9k_hw_set_delta_slope(ah, chan);
2029
2030         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2031         ah->eep_ops->set_board_values(ah, chan);
2032
2033         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2034         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2035                   | macStaId1
2036                   | AR_STA_ID1_RTS_USE_DEF
2037                   | (ah->config.
2038                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2039                   | ah->sta_id1_defaults);
2040         ath9k_hw_set_operating_mode(ah, ah->opmode);
2041
2042         ath_hw_setbssidmask(common);
2043
2044         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2045
2046         ath9k_hw_write_associd(ah);
2047
2048         REG_WRITE(ah, AR_ISR, ~0);
2049
2050         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2051
2052         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2053         if (r)
2054                 return r;
2055
2056         for (i = 0; i < AR_NUM_DCU; i++)
2057                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2058
2059         ah->intr_txqs = 0;
2060         for (i = 0; i < ah->caps.total_queues; i++)
2061                 ath9k_hw_resettxqueue(ah, i);
2062
2063         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2064         ath9k_hw_init_qos(ah);
2065
2066         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2067                 ath9k_enable_rfkill(ah);
2068
2069         ath9k_hw_init_global_settings(ah);
2070
2071         if (AR_SREV_9287_12_OR_LATER(ah)) {
2072                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2073                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2074                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2075                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2076                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2077                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2078
2079                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2080                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2081
2082                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2083                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2084                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2085                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2086         }
2087         if (AR_SREV_9287_12_OR_LATER(ah)) {
2088                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2089                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2090         }
2091
2092         REG_WRITE(ah, AR_STA_ID1,
2093                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2094
2095         ath9k_hw_set_dma(ah);
2096
2097         REG_WRITE(ah, AR_OBS, 8);
2098
2099         if (ah->config.rx_intr_mitigation) {
2100                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2101                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2102         }
2103
2104         ath9k_hw_init_bb(ah, chan);
2105
2106         if (!ath9k_hw_init_cal(ah, chan))
2107                 return -EIO;
2108
2109         rx_chainmask = ah->rxchainmask;
2110         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2111                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2112                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2113         }
2114
2115         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2116
2117         /*
2118          * For big endian systems turn on swapping for descriptors
2119          */
2120         if (AR_SREV_9100(ah)) {
2121                 u32 mask;
2122                 mask = REG_READ(ah, AR_CFG);
2123                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2124                         ath_print(common, ATH_DBG_RESET,
2125                                 "CFG Byte Swap Set 0x%x\n", mask);
2126                 } else {
2127                         mask =
2128                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2129                         REG_WRITE(ah, AR_CFG, mask);
2130                         ath_print(common, ATH_DBG_RESET,
2131                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2132                 }
2133         } else {
2134                 /* Configure AR9271 target WLAN */
2135                 if (AR_SREV_9271(ah))
2136                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2137 #ifdef __BIG_ENDIAN
2138                 else
2139                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2140 #endif
2141         }
2142
2143         if (ah->btcoex_hw.enabled)
2144                 ath9k_hw_btcoex_enable(ah);
2145
2146         return 0;
2147 }
2148 EXPORT_SYMBOL(ath9k_hw_reset);
2149
2150 /************************/
2151 /* Key Cache Management */
2152 /************************/
2153
2154 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2155 {
2156         u32 keyType;
2157
2158         if (entry >= ah->caps.keycache_size) {
2159                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2160                           "keychache entry %u out of range\n", entry);
2161                 return false;
2162         }
2163
2164         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2165
2166         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2167         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2168         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2169         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2170         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2171         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2172         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2173         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2174
2175         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2176                 u16 micentry = entry + 64;
2177
2178                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2179                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2180                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2181                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2182
2183         }
2184
2185         return true;
2186 }
2187 EXPORT_SYMBOL(ath9k_hw_keyreset);
2188
2189 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2190 {
2191         u32 macHi, macLo;
2192
2193         if (entry >= ah->caps.keycache_size) {
2194                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2195                           "keychache entry %u out of range\n", entry);
2196                 return false;
2197         }
2198
2199         if (mac != NULL) {
2200                 macHi = (mac[5] << 8) | mac[4];
2201                 macLo = (mac[3] << 24) |
2202                         (mac[2] << 16) |
2203                         (mac[1] << 8) |
2204                         mac[0];
2205                 macLo >>= 1;
2206                 macLo |= (macHi & 1) << 31;
2207                 macHi >>= 1;
2208         } else {
2209                 macLo = macHi = 0;
2210         }
2211         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2212         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2213
2214         return true;
2215 }
2216 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2217
2218 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2219                                  const struct ath9k_keyval *k,
2220                                  const u8 *mac)
2221 {
2222         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2223         struct ath_common *common = ath9k_hw_common(ah);
2224         u32 key0, key1, key2, key3, key4;
2225         u32 keyType;
2226
2227         if (entry >= pCap->keycache_size) {
2228                 ath_print(common, ATH_DBG_FATAL,
2229                           "keycache entry %u out of range\n", entry);
2230                 return false;
2231         }
2232
2233         switch (k->kv_type) {
2234         case ATH9K_CIPHER_AES_OCB:
2235                 keyType = AR_KEYTABLE_TYPE_AES;
2236                 break;
2237         case ATH9K_CIPHER_AES_CCM:
2238                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2239                         ath_print(common, ATH_DBG_ANY,
2240                                   "AES-CCM not supported by mac rev 0x%x\n",
2241                                   ah->hw_version.macRev);
2242                         return false;
2243                 }
2244                 keyType = AR_KEYTABLE_TYPE_CCM;
2245                 break;
2246         case ATH9K_CIPHER_TKIP:
2247                 keyType = AR_KEYTABLE_TYPE_TKIP;
2248                 if (ATH9K_IS_MIC_ENABLED(ah)
2249                     && entry + 64 >= pCap->keycache_size) {
2250                         ath_print(common, ATH_DBG_ANY,
2251                                   "entry %u inappropriate for TKIP\n", entry);
2252                         return false;
2253                 }
2254                 break;
2255         case ATH9K_CIPHER_WEP:
2256                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2257                         ath_print(common, ATH_DBG_ANY,
2258                                   "WEP key length %u too small\n", k->kv_len);
2259                         return false;
2260                 }
2261                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2262                         keyType = AR_KEYTABLE_TYPE_40;
2263                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2264                         keyType = AR_KEYTABLE_TYPE_104;
2265                 else
2266                         keyType = AR_KEYTABLE_TYPE_128;
2267                 break;
2268         case ATH9K_CIPHER_CLR:
2269                 keyType = AR_KEYTABLE_TYPE_CLR;
2270                 break;
2271         default:
2272                 ath_print(common, ATH_DBG_FATAL,
2273                           "cipher %u not supported\n", k->kv_type);
2274                 return false;
2275         }
2276
2277         key0 = get_unaligned_le32(k->kv_val + 0);
2278         key1 = get_unaligned_le16(k->kv_val + 4);
2279         key2 = get_unaligned_le32(k->kv_val + 6);
2280         key3 = get_unaligned_le16(k->kv_val + 10);
2281         key4 = get_unaligned_le32(k->kv_val + 12);
2282         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2283                 key4 &= 0xff;
2284
2285         /*
2286          * Note: Key cache registers access special memory area that requires
2287          * two 32-bit writes to actually update the values in the internal
2288          * memory. Consequently, the exact order and pairs used here must be
2289          * maintained.
2290          */
2291
2292         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2293                 u16 micentry = entry + 64;
2294
2295                 /*
2296                  * Write inverted key[47:0] first to avoid Michael MIC errors
2297                  * on frames that could be sent or received at the same time.
2298                  * The correct key will be written in the end once everything
2299                  * else is ready.
2300                  */
2301                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2302                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2303
2304                 /* Write key[95:48] */
2305                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2306                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2307
2308                 /* Write key[127:96] and key type */
2309                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2310                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2311
2312                 /* Write MAC address for the entry */
2313                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2314
2315                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2316                         /*
2317                          * TKIP uses two key cache entries:
2318                          * Michael MIC TX/RX keys in the same key cache entry
2319                          * (idx = main index + 64):
2320                          * key0 [31:0] = RX key [31:0]
2321                          * key1 [15:0] = TX key [31:16]
2322                          * key1 [31:16] = reserved
2323                          * key2 [31:0] = RX key [63:32]
2324                          * key3 [15:0] = TX key [15:0]
2325                          * key3 [31:16] = reserved
2326                          * key4 [31:0] = TX key [63:32]
2327                          */
2328                         u32 mic0, mic1, mic2, mic3, mic4;
2329
2330                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2331                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2332                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2333                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2334                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2335
2336                         /* Write RX[31:0] and TX[31:16] */
2337                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2338                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2339
2340                         /* Write RX[63:32] and TX[15:0] */
2341                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2342                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2343
2344                         /* Write TX[63:32] and keyType(reserved) */
2345                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2346                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2347                                   AR_KEYTABLE_TYPE_CLR);
2348
2349                 } else {
2350                         /*
2351                          * TKIP uses four key cache entries (two for group
2352                          * keys):
2353                          * Michael MIC TX/RX keys are in different key cache
2354                          * entries (idx = main index + 64 for TX and
2355                          * main index + 32 + 96 for RX):
2356                          * key0 [31:0] = TX/RX MIC key [31:0]
2357                          * key1 [31:0] = reserved
2358                          * key2 [31:0] = TX/RX MIC key [63:32]
2359                          * key3 [31:0] = reserved
2360                          * key4 [31:0] = reserved
2361                          *
2362                          * Upper layer code will call this function separately
2363                          * for TX and RX keys when these registers offsets are
2364                          * used.
2365                          */
2366                         u32 mic0, mic2;
2367
2368                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2369                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2370
2371                         /* Write MIC key[31:0] */
2372                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2373                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2374
2375                         /* Write MIC key[63:32] */
2376                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2377                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2378
2379                         /* Write TX[63:32] and keyType(reserved) */
2380                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2381                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2382                                   AR_KEYTABLE_TYPE_CLR);
2383                 }
2384
2385                 /* MAC address registers are reserved for the MIC entry */
2386                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2387                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2388
2389                 /*
2390                  * Write the correct (un-inverted) key[47:0] last to enable
2391                  * TKIP now that all other registers are set with correct
2392                  * values.
2393                  */
2394                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2395                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2396         } else {
2397                 /* Write key[47:0] */
2398                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2399                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2400
2401                 /* Write key[95:48] */
2402                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2403                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2404
2405                 /* Write key[127:96] and key type */
2406                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2407                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2408
2409                 /* Write MAC address for the entry */
2410                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2411         }
2412
2413         return true;
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2416
2417 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2418 {
2419         if (entry < ah->caps.keycache_size) {
2420                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2421                 if (val & AR_KEYTABLE_VALID)
2422                         return true;
2423         }
2424         return false;
2425 }
2426 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2427
2428 /******************************/
2429 /* Power Management (Chipset) */
2430 /******************************/
2431
2432 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2433 {
2434         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2435         if (setChip) {
2436                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2437                             AR_RTC_FORCE_WAKE_EN);
2438                 if (!AR_SREV_9100(ah))
2439                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2440
2441                 if(!AR_SREV_5416(ah))
2442                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2443                                     AR_RTC_RESET_EN);
2444         }
2445 }
2446
2447 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2448 {
2449         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2450         if (setChip) {
2451                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2452
2453                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2454                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2455                                   AR_RTC_FORCE_WAKE_ON_INT);
2456                 } else {
2457                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2458                                     AR_RTC_FORCE_WAKE_EN);
2459                 }
2460         }
2461 }
2462
2463 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2464 {
2465         u32 val;
2466         int i;
2467
2468         if (setChip) {
2469                 if ((REG_READ(ah, AR_RTC_STATUS) &
2470                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2471                         if (ath9k_hw_set_reset_reg(ah,
2472                                            ATH9K_RESET_POWER_ON) != true) {
2473                                 return false;
2474                         }
2475                         ath9k_hw_init_pll(ah, NULL);
2476                 }
2477                 if (AR_SREV_9100(ah))
2478                         REG_SET_BIT(ah, AR_RTC_RESET,
2479                                     AR_RTC_RESET_EN);
2480
2481                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2482                             AR_RTC_FORCE_WAKE_EN);
2483                 udelay(50);
2484
2485                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2486                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2487                         if (val == AR_RTC_STATUS_ON)
2488                                 break;
2489                         udelay(50);
2490                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2491                                     AR_RTC_FORCE_WAKE_EN);
2492                 }
2493                 if (i == 0) {
2494                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2495                                   "Failed to wakeup in %uus\n",
2496                                   POWER_UP_TIME / 20);
2497                         return false;
2498                 }
2499         }
2500
2501         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2502
2503         return true;
2504 }
2505
2506 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2507 {
2508         struct ath_common *common = ath9k_hw_common(ah);
2509         int status = true, setChip = true;
2510         static const char *modes[] = {
2511                 "AWAKE",
2512                 "FULL-SLEEP",
2513                 "NETWORK SLEEP",
2514                 "UNDEFINED"
2515         };
2516
2517         if (ah->power_mode == mode)
2518                 return status;
2519
2520         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2521                   modes[ah->power_mode], modes[mode]);
2522
2523         switch (mode) {
2524         case ATH9K_PM_AWAKE:
2525                 status = ath9k_hw_set_power_awake(ah, setChip);
2526                 break;
2527         case ATH9K_PM_FULL_SLEEP:
2528                 ath9k_set_power_sleep(ah, setChip);
2529                 ah->chip_fullsleep = true;
2530                 break;
2531         case ATH9K_PM_NETWORK_SLEEP:
2532                 ath9k_set_power_network_sleep(ah, setChip);
2533                 break;
2534         default:
2535                 ath_print(common, ATH_DBG_FATAL,
2536                           "Unknown power mode %u\n", mode);
2537                 return false;
2538         }
2539         ah->power_mode = mode;
2540
2541         return status;
2542 }
2543 EXPORT_SYMBOL(ath9k_hw_setpower);
2544
2545 /*
2546  * Helper for ASPM support.
2547  *
2548  * Disable PLL when in L0s as well as receiver clock when in L1.
2549  * This power saving option must be enabled through the SerDes.
2550  *
2551  * Programming the SerDes must go through the same 288 bit serial shift
2552  * register as the other analog registers.  Hence the 9 writes.
2553  */
2554 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2555 {
2556         u8 i;
2557         u32 val;
2558
2559         if (ah->is_pciexpress != true)
2560                 return;
2561
2562         /* Do not touch SerDes registers */
2563         if (ah->config.pcie_powersave_enable == 2)
2564                 return;
2565
2566         /* Nothing to do on restore for 11N */
2567         if (!restore) {
2568                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2569                         /*
2570                          * AR9280 2.0 or later chips use SerDes values from the
2571                          * initvals.h initialized depending on chipset during
2572                          * ath9k_hw_init()
2573                          */
2574                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2575                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2576                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2577                         }
2578                 } else if (AR_SREV_9280(ah) &&
2579                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2580                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2581                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2582
2583                         /* RX shut off when elecidle is asserted */
2584                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2585                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2586                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2587
2588                         /* Shut off CLKREQ active in L1 */
2589                         if (ah->config.pcie_clock_req)
2590                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2591                         else
2592                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2593
2594                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2595                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2596                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2597
2598                         /* Load the new settings */
2599                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2600
2601                 } else {
2602                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2603                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2604
2605                         /* RX shut off when elecidle is asserted */
2606                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2607                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2608                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2609
2610                         /*
2611                          * Ignore ah->ah_config.pcie_clock_req setting for
2612                          * pre-AR9280 11n
2613                          */
2614                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2615
2616                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2617                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2618                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2619
2620                         /* Load the new settings */
2621                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2622                 }
2623
2624                 udelay(1000);
2625
2626                 /* set bit 19 to allow forcing of pcie core into L1 state */
2627                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2628
2629                 /* Several PCIe massages to ensure proper behaviour */
2630                 if (ah->config.pcie_waen) {
2631                         val = ah->config.pcie_waen;
2632                         if (!power_off)
2633                                 val &= (~AR_WA_D3_L1_DISABLE);
2634                 } else {
2635                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2636                             AR_SREV_9287(ah)) {
2637                                 val = AR9285_WA_DEFAULT;
2638                                 if (!power_off)
2639                                         val &= (~AR_WA_D3_L1_DISABLE);
2640                         } else if (AR_SREV_9280(ah)) {
2641                                 /*
2642                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2643                                  * set otherwise card may disappear.
2644                                  */
2645                                 val = AR9280_WA_DEFAULT;
2646                                 if (!power_off)
2647                                         val &= (~AR_WA_D3_L1_DISABLE);
2648                         } else
2649                                 val = AR_WA_DEFAULT;
2650                 }
2651
2652                 REG_WRITE(ah, AR_WA, val);
2653         }
2654
2655         if (power_off) {
2656                 /*
2657                  * Set PCIe workaround bits
2658                  * bit 14 in WA register (disable L1) should only
2659                  * be set when device enters D3 and be cleared
2660                  * when device comes back to D0.
2661                  */
2662                 if (ah->config.pcie_waen) {
2663                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2664                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2665                 } else {
2666                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2667                               AR_SREV_9287(ah)) &&
2668                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2669                             (AR_SREV_9280(ah) &&
2670                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2671                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2672                         }
2673                 }
2674         }
2675 }
2676 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2677
2678 /**********************/
2679 /* Interrupt Handling */
2680 /**********************/
2681
2682 bool ath9k_hw_intrpend(struct ath_hw *ah)
2683 {
2684         u32 host_isr;
2685
2686         if (AR_SREV_9100(ah))
2687                 return true;
2688
2689         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2690         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2691                 return true;
2692
2693         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2694         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2695             && (host_isr != AR_INTR_SPURIOUS))
2696                 return true;
2697
2698         return false;
2699 }
2700 EXPORT_SYMBOL(ath9k_hw_intrpend);
2701
2702 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2703 {
2704         u32 isr = 0;
2705         u32 mask2 = 0;
2706         struct ath9k_hw_capabilities *pCap = &ah->caps;
2707         u32 sync_cause = 0;
2708         bool fatal_int = false;
2709         struct ath_common *common = ath9k_hw_common(ah);
2710
2711         if (!AR_SREV_9100(ah)) {
2712                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2713                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2714                             == AR_RTC_STATUS_ON) {
2715                                 isr = REG_READ(ah, AR_ISR);
2716                         }
2717                 }
2718
2719                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2720                         AR_INTR_SYNC_DEFAULT;
2721
2722                 *masked = 0;
2723
2724                 if (!isr && !sync_cause)
2725                         return false;
2726         } else {
2727                 *masked = 0;
2728                 isr = REG_READ(ah, AR_ISR);
2729         }
2730
2731         if (isr) {
2732                 if (isr & AR_ISR_BCNMISC) {
2733                         u32 isr2;
2734                         isr2 = REG_READ(ah, AR_ISR_S2);
2735                         if (isr2 & AR_ISR_S2_TIM)
2736                                 mask2 |= ATH9K_INT_TIM;
2737                         if (isr2 & AR_ISR_S2_DTIM)
2738                                 mask2 |= ATH9K_INT_DTIM;
2739                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2740                                 mask2 |= ATH9K_INT_DTIMSYNC;
2741                         if (isr2 & (AR_ISR_S2_CABEND))
2742                                 mask2 |= ATH9K_INT_CABEND;
2743                         if (isr2 & AR_ISR_S2_GTT)
2744                                 mask2 |= ATH9K_INT_GTT;
2745                         if (isr2 & AR_ISR_S2_CST)
2746                                 mask2 |= ATH9K_INT_CST;
2747                         if (isr2 & AR_ISR_S2_TSFOOR)
2748                                 mask2 |= ATH9K_INT_TSFOOR;
2749                 }
2750
2751                 isr = REG_READ(ah, AR_ISR_RAC);
2752                 if (isr == 0xffffffff) {
2753                         *masked = 0;
2754                         return false;
2755                 }
2756
2757                 *masked = isr & ATH9K_INT_COMMON;
2758
2759                 if (ah->config.rx_intr_mitigation) {
2760                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2761                                 *masked |= ATH9K_INT_RX;
2762                 }
2763
2764                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2765                         *masked |= ATH9K_INT_RX;
2766                 if (isr &
2767                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2768                      AR_ISR_TXEOL)) {
2769                         u32 s0_s, s1_s;
2770
2771                         *masked |= ATH9K_INT_TX;
2772
2773                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2774                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2775                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2776
2777                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2778                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2779                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2780                 }
2781
2782                 if (isr & AR_ISR_RXORN) {
2783                         ath_print(common, ATH_DBG_INTERRUPT,
2784                                   "receive FIFO overrun interrupt\n");
2785                 }
2786
2787                 if (!AR_SREV_9100(ah)) {
2788                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2789                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2790                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2791                                         *masked |= ATH9K_INT_TIM_TIMER;
2792                         }
2793                 }
2794
2795                 *masked |= mask2;
2796         }
2797
2798         if (AR_SREV_9100(ah))
2799                 return true;
2800
2801         if (isr & AR_ISR_GENTMR) {
2802                 u32 s5_s;
2803
2804                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2805                 if (isr & AR_ISR_GENTMR) {
2806                         ah->intr_gen_timer_trigger =
2807                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2808
2809                         ah->intr_gen_timer_thresh =
2810                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2811
2812                         if (ah->intr_gen_timer_trigger)
2813                                 *masked |= ATH9K_INT_GENTIMER;
2814
2815                 }
2816         }
2817
2818         if (sync_cause) {
2819                 fatal_int =
2820                         (sync_cause &
2821                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2822                         ? true : false;
2823
2824                 if (fatal_int) {
2825                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2826                                 ath_print(common, ATH_DBG_ANY,
2827                                           "received PCI FATAL interrupt\n");
2828                         }
2829                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2830                                 ath_print(common, ATH_DBG_ANY,
2831                                           "received PCI PERR interrupt\n");
2832                         }
2833                         *masked |= ATH9K_INT_FATAL;
2834                 }
2835                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2836                         ath_print(common, ATH_DBG_INTERRUPT,
2837                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2838                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2839                         REG_WRITE(ah, AR_RC, 0);
2840                         *masked |= ATH9K_INT_FATAL;
2841                 }
2842                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2843                         ath_print(common, ATH_DBG_INTERRUPT,
2844                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2845                 }
2846
2847                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2848                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2849         }
2850
2851         return true;
2852 }
2853 EXPORT_SYMBOL(ath9k_hw_getisr);
2854
2855 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2856 {
2857         u32 omask = ah->mask_reg;
2858         u32 mask, mask2;
2859         struct ath9k_hw_capabilities *pCap = &ah->caps;
2860         struct ath_common *common = ath9k_hw_common(ah);
2861
2862         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2863
2864         if (omask & ATH9K_INT_GLOBAL) {
2865                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2866                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2867                 (void) REG_READ(ah, AR_IER);
2868                 if (!AR_SREV_9100(ah)) {
2869                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2870                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2871
2872                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2873                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2874                 }
2875         }
2876
2877         mask = ints & ATH9K_INT_COMMON;
2878         mask2 = 0;
2879
2880         if (ints & ATH9K_INT_TX) {
2881                 if (ah->txok_interrupt_mask)
2882                         mask |= AR_IMR_TXOK;
2883                 if (ah->txdesc_interrupt_mask)
2884                         mask |= AR_IMR_TXDESC;
2885                 if (ah->txerr_interrupt_mask)
2886                         mask |= AR_IMR_TXERR;
2887                 if (ah->txeol_interrupt_mask)
2888                         mask |= AR_IMR_TXEOL;
2889         }
2890         if (ints & ATH9K_INT_RX) {
2891                 mask |= AR_IMR_RXERR;
2892                 if (ah->config.rx_intr_mitigation)
2893                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2894                 else
2895                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2896                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2897                         mask |= AR_IMR_GENTMR;
2898         }
2899
2900         if (ints & (ATH9K_INT_BMISC)) {
2901                 mask |= AR_IMR_BCNMISC;
2902                 if (ints & ATH9K_INT_TIM)
2903                         mask2 |= AR_IMR_S2_TIM;
2904                 if (ints & ATH9K_INT_DTIM)
2905                         mask2 |= AR_IMR_S2_DTIM;
2906                 if (ints & ATH9K_INT_DTIMSYNC)
2907                         mask2 |= AR_IMR_S2_DTIMSYNC;
2908                 if (ints & ATH9K_INT_CABEND)
2909                         mask2 |= AR_IMR_S2_CABEND;
2910                 if (ints & ATH9K_INT_TSFOOR)
2911                         mask2 |= AR_IMR_S2_TSFOOR;
2912         }
2913
2914         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2915                 mask |= AR_IMR_BCNMISC;
2916                 if (ints & ATH9K_INT_GTT)
2917                         mask2 |= AR_IMR_S2_GTT;
2918                 if (ints & ATH9K_INT_CST)
2919                         mask2 |= AR_IMR_S2_CST;
2920         }
2921
2922         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2923         REG_WRITE(ah, AR_IMR, mask);
2924         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2925                                            AR_IMR_S2_DTIM |
2926                                            AR_IMR_S2_DTIMSYNC |
2927                                            AR_IMR_S2_CABEND |
2928                                            AR_IMR_S2_CABTO |
2929                                            AR_IMR_S2_TSFOOR |
2930                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2931         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2932         ah->mask_reg = ints;
2933
2934         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2935                 if (ints & ATH9K_INT_TIM_TIMER)
2936                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2937                 else
2938                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2939         }
2940
2941         if (ints & ATH9K_INT_GLOBAL) {
2942                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2943                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2944                 if (!AR_SREV_9100(ah)) {
2945                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2946                                   AR_INTR_MAC_IRQ);
2947                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2948
2949
2950                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2951                                   AR_INTR_SYNC_DEFAULT);
2952                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2953                                   AR_INTR_SYNC_DEFAULT);
2954                 }
2955                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2956                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2957         }
2958
2959         return omask;
2960 }
2961 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2962
2963 /*******************/
2964 /* Beacon Handling */
2965 /*******************/
2966
2967 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2968 {
2969         int flags = 0;
2970
2971         ah->beacon_interval = beacon_period;
2972
2973         switch (ah->opmode) {
2974         case NL80211_IFTYPE_STATION:
2975         case NL80211_IFTYPE_MONITOR:
2976                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2977                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2978                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2979                 flags |= AR_TBTT_TIMER_EN;
2980                 break;
2981         case NL80211_IFTYPE_ADHOC:
2982         case NL80211_IFTYPE_MESH_POINT:
2983                 REG_SET_BIT(ah, AR_TXCFG,
2984                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2985                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2986                           TU_TO_USEC(next_beacon +
2987                                      (ah->atim_window ? ah->
2988                                       atim_window : 1)));
2989                 flags |= AR_NDP_TIMER_EN;
2990         case NL80211_IFTYPE_AP:
2991                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2992                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2993                           TU_TO_USEC(next_beacon -
2994                                      ah->config.
2995                                      dma_beacon_response_time));
2996                 REG_WRITE(ah, AR_NEXT_SWBA,
2997                           TU_TO_USEC(next_beacon -
2998                                      ah->config.
2999                                      sw_beacon_response_time));
3000                 flags |=
3001                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3002                 break;
3003         default:
3004                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3005                           "%s: unsupported opmode: %d\n",
3006                           __func__, ah->opmode);
3007                 return;
3008                 break;
3009         }
3010
3011         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3012         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3013         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3014         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3015
3016         beacon_period &= ~ATH9K_BEACON_ENA;
3017         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3018                 ath9k_hw_reset_tsf(ah);
3019         }
3020
3021         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3022 }
3023 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3024
3025 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3026                                     const struct ath9k_beacon_state *bs)
3027 {
3028         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3029         struct ath9k_hw_capabilities *pCap = &ah->caps;
3030         struct ath_common *common = ath9k_hw_common(ah);
3031
3032         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3033
3034         REG_WRITE(ah, AR_BEACON_PERIOD,
3035                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3036         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3037                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3038
3039         REG_RMW_FIELD(ah, AR_RSSI_THR,
3040                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3041
3042         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3043
3044         if (bs->bs_sleepduration > beaconintval)
3045                 beaconintval = bs->bs_sleepduration;
3046
3047         dtimperiod = bs->bs_dtimperiod;
3048         if (bs->bs_sleepduration > dtimperiod)
3049                 dtimperiod = bs->bs_sleepduration;
3050
3051         if (beaconintval == dtimperiod)
3052                 nextTbtt = bs->bs_nextdtim;
3053         else
3054                 nextTbtt = bs->bs_nexttbtt;
3055
3056         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3057         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3058         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3059         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3060
3061         REG_WRITE(ah, AR_NEXT_DTIM,
3062                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3063         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3064
3065         REG_WRITE(ah, AR_SLEEP1,
3066                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3067                   | AR_SLEEP1_ASSUME_DTIM);
3068
3069         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3070                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3071         else
3072                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3073
3074         REG_WRITE(ah, AR_SLEEP2,
3075                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3076
3077         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3078         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3079
3080         REG_SET_BIT(ah, AR_TIMER_MODE,
3081                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3082                     AR_DTIM_TIMER_EN);
3083
3084         /* TSF Out of Range Threshold */
3085         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3086 }
3087 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3088
3089 /*******************/
3090 /* HW Capabilities */
3091 /*******************/
3092
3093 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3094 {
3095         struct ath9k_hw_capabilities *pCap = &ah->caps;
3096         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3097         struct ath_common *common = ath9k_hw_common(ah);
3098         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3099
3100         u16 capField = 0, eeval;
3101
3102         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3103         regulatory->current_rd = eeval;
3104
3105         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3106         if (AR_SREV_9285_10_OR_LATER(ah))
3107                 eeval |= AR9285_RDEXT_DEFAULT;
3108         regulatory->current_rd_ext = eeval;
3109
3110         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3111
3112         if (ah->opmode != NL80211_IFTYPE_AP &&
3113             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3114                 if (regulatory->current_rd == 0x64 ||
3115                     regulatory->current_rd == 0x65)
3116                         regulatory->current_rd += 5;
3117                 else if (regulatory->current_rd == 0x41)
3118                         regulatory->current_rd = 0x43;
3119                 ath_print(common, ATH_DBG_REGULATORY,
3120                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3121         }
3122
3123         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3124         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3125                 ath_print(common, ATH_DBG_FATAL,
3126                           "no band has been marked as supported in EEPROM.\n");
3127                 return -EINVAL;
3128         }
3129
3130         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3131
3132         if (eeval & AR5416_OPFLAGS_11A) {
3133                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3134                 if (ah->config.ht_enable) {
3135                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3136                                 set_bit(ATH9K_MODE_11NA_HT20,
3137                                         pCap->wireless_modes);
3138                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3139                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3140                                         pCap->wireless_modes);
3141                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3142                                         pCap->wireless_modes);
3143                         }
3144                 }
3145         }
3146
3147         if (eeval & AR5416_OPFLAGS_11G) {
3148                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3149                 if (ah->config.ht_enable) {
3150                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3151                                 set_bit(ATH9K_MODE_11NG_HT20,
3152                                         pCap->wireless_modes);
3153                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3154                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3155                                         pCap->wireless_modes);
3156                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3157                                         pCap->wireless_modes);
3158                         }
3159                 }
3160         }
3161
3162         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3163         /*
3164          * For AR9271 we will temporarilly uses the rx chainmax as read from
3165          * the EEPROM.
3166          */
3167         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3168             !(eeval & AR5416_OPFLAGS_11A) &&
3169             !(AR_SREV_9271(ah)))
3170                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3171                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3172         else
3173                 /* Use rx_chainmask from EEPROM. */
3174                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3175
3176         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3177                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3178
3179         pCap->low_2ghz_chan = 2312;
3180         pCap->high_2ghz_chan = 2732;
3181
3182         pCap->low_5ghz_chan = 4920;
3183         pCap->high_5ghz_chan = 6100;
3184
3185         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3186         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3187         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3188
3189         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3190         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3191         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3192
3193         if (ah->config.ht_enable)
3194                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3195         else
3196                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3197
3198         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3199         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3200         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3201         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3202
3203         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3204                 pCap->total_queues =
3205                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3206         else
3207                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3208
3209         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3210                 pCap->keycache_size =
3211                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3212         else
3213                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3214
3215         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3216
3217         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3218                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3219         else
3220                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3221
3222         if (AR_SREV_9285_10_OR_LATER(ah))
3223                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3224         else if (AR_SREV_9280_10_OR_LATER(ah))
3225                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3226         else
3227                 pCap->num_gpio_pins = AR_NUM_GPIO;
3228
3229         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3230                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3231                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3232         } else {
3233                 pCap->rts_aggr_limit = (8 * 1024);
3234         }
3235
3236         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3237
3238 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3239         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3240         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3241                 ah->rfkill_gpio =
3242                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3243                 ah->rfkill_polarity =
3244                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3245
3246                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3247         }
3248 #endif
3249
3250         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3251
3252         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3253                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3254         else
3255                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3256
3257         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3258                 pCap->reg_cap =
3259                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3260                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3261                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3262                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3263         } else {
3264                 pCap->reg_cap =
3265                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3266                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3267         }
3268
3269         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3270         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3271             AR_SREV_5416(ah))
3272                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3273
3274         pCap->num_antcfg_5ghz =
3275                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3276         pCap->num_antcfg_2ghz =
3277                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3278
3279         if (AR_SREV_9280_10_OR_LATER(ah) &&
3280             ath9k_hw_btcoex_supported(ah)) {
3281                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3282                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3283
3284                 if (AR_SREV_9285(ah)) {
3285                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3286                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3287                 } else {
3288                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3289                 }
3290         } else {
3291                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3292         }
3293
3294         return 0;
3295 }
3296
3297 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3298                             u32 capability, u32 *result)
3299 {
3300         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3301         switch (type) {
3302         case ATH9K_CAP_CIPHER:
3303                 switch (capability) {
3304                 case ATH9K_CIPHER_AES_CCM:
3305                 case ATH9K_CIPHER_AES_OCB:
3306                 case ATH9K_CIPHER_TKIP:
3307                 case ATH9K_CIPHER_WEP:
3308                 case ATH9K_CIPHER_MIC:
3309                 case ATH9K_CIPHER_CLR:
3310                         return true;
3311                 default:
3312                         return false;
3313                 }
3314         case ATH9K_CAP_TKIP_MIC:
3315                 switch (capability) {
3316                 case 0:
3317                         return true;
3318                 case 1:
3319                         return (ah->sta_id1_defaults &
3320                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3321                         false;
3322                 }
3323         case ATH9K_CAP_TKIP_SPLIT:
3324                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3325                         false : true;
3326         case ATH9K_CAP_DIVERSITY:
3327                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3328                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3329                         true : false;
3330         case ATH9K_CAP_MCAST_KEYSRCH:
3331                 switch (capability) {
3332                 case 0:
3333                         return true;
3334                 case 1:
3335                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3336                                 return false;
3337                         } else {
3338                                 return (ah->sta_id1_defaults &
3339                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3340                                         false;
3341                         }
3342                 }
3343                 return false;
3344         case ATH9K_CAP_TXPOW:
3345                 switch (capability) {
3346                 case 0:
3347                         return 0;
3348                 case 1:
3349                         *result = regulatory->power_limit;
3350                         return 0;
3351                 case 2:
3352                         *result = regulatory->max_power_level;
3353                         return 0;
3354                 case 3:
3355                         *result = regulatory->tp_scale;
3356                         return 0;
3357                 }
3358                 return false;
3359         case ATH9K_CAP_DS:
3360                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3361                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3362                         ? false : true;
3363         default:
3364                 return false;
3365         }
3366 }
3367 EXPORT_SYMBOL(ath9k_hw_getcapability);
3368
3369 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3370                             u32 capability, u32 setting, int *status)
3371 {
3372         u32 v;
3373
3374         switch (type) {
3375         case ATH9K_CAP_TKIP_MIC:
3376                 if (setting)
3377                         ah->sta_id1_defaults |=
3378                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3379                 else
3380                         ah->sta_id1_defaults &=
3381                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3382                 return true;
3383         case ATH9K_CAP_DIVERSITY:
3384                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3385                 if (setting)
3386                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3387                 else
3388                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3389                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3390                 return true;
3391         case ATH9K_CAP_MCAST_KEYSRCH:
3392                 if (setting)
3393                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3394                 else
3395                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3396                 return true;
3397         default:
3398                 return false;
3399         }
3400 }
3401 EXPORT_SYMBOL(ath9k_hw_setcapability);
3402
3403 /****************************/
3404 /* GPIO / RFKILL / Antennae */
3405 /****************************/
3406
3407 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3408                                          u32 gpio, u32 type)
3409 {
3410         int addr;
3411         u32 gpio_shift, tmp;
3412
3413         if (gpio > 11)
3414                 addr = AR_GPIO_OUTPUT_MUX3;
3415         else if (gpio > 5)
3416                 addr = AR_GPIO_OUTPUT_MUX2;
3417         else
3418                 addr = AR_GPIO_OUTPUT_MUX1;
3419
3420         gpio_shift = (gpio % 6) * 5;
3421
3422         if (AR_SREV_9280_20_OR_LATER(ah)
3423             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3424                 REG_RMW(ah, addr, (type << gpio_shift),
3425                         (0x1f << gpio_shift));
3426         } else {
3427                 tmp = REG_READ(ah, addr);
3428                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3429                 tmp &= ~(0x1f << gpio_shift);
3430                 tmp |= (type << gpio_shift);
3431                 REG_WRITE(ah, addr, tmp);
3432         }
3433 }
3434
3435 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3436 {
3437         u32 gpio_shift;
3438
3439         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3440
3441         gpio_shift = gpio << 1;
3442
3443         REG_RMW(ah,
3444                 AR_GPIO_OE_OUT,
3445                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3446                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3447 }
3448 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3449
3450 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3451 {
3452 #define MS_REG_READ(x, y) \
3453         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3454
3455         if (gpio >= ah->caps.num_gpio_pins)
3456                 return 0xffffffff;
3457
3458         if (AR_SREV_9287_10_OR_LATER(ah))
3459                 return MS_REG_READ(AR9287, gpio) != 0;
3460         else if (AR_SREV_9285_10_OR_LATER(ah))
3461                 return MS_REG_READ(AR9285, gpio) != 0;
3462         else if (AR_SREV_9280_10_OR_LATER(ah))
3463                 return MS_REG_READ(AR928X, gpio) != 0;
3464         else
3465                 return MS_REG_READ(AR, gpio) != 0;
3466 }
3467 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3468
3469 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3470                          u32 ah_signal_type)
3471 {
3472         u32 gpio_shift;
3473
3474         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3475
3476         gpio_shift = 2 * gpio;
3477
3478         REG_RMW(ah,
3479                 AR_GPIO_OE_OUT,
3480                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3481                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3482 }
3483 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3484
3485 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3486 {
3487         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3488                 AR_GPIO_BIT(gpio));
3489 }
3490 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3491
3492 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3493 {
3494         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3495 }
3496 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3497
3498 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3499 {
3500         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3501 }
3502 EXPORT_SYMBOL(ath9k_hw_setantenna);
3503
3504 /*********************/
3505 /* General Operation */
3506 /*********************/
3507
3508 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3509 {
3510         u32 bits = REG_READ(ah, AR_RX_FILTER);
3511         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3512
3513         if (phybits & AR_PHY_ERR_RADAR)
3514                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3515         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3516                 bits |= ATH9K_RX_FILTER_PHYERR;
3517
3518         return bits;
3519 }
3520 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3521
3522 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3523 {
3524         u32 phybits;
3525
3526         REG_WRITE(ah, AR_RX_FILTER, bits);
3527
3528         phybits = 0;
3529         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3530                 phybits |= AR_PHY_ERR_RADAR;
3531         if (bits & ATH9K_RX_FILTER_PHYERR)
3532                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3533         REG_WRITE(ah, AR_PHY_ERR, phybits);
3534
3535         if (phybits)
3536                 REG_WRITE(ah, AR_RXCFG,
3537                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3538         else
3539                 REG_WRITE(ah, AR_RXCFG,
3540                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3541 }
3542 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3543
3544 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3545 {
3546         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3547                 return false;
3548
3549         ath9k_hw_init_pll(ah, NULL);
3550         return true;
3551 }
3552 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3553
3554 bool ath9k_hw_disable(struct ath_hw *ah)
3555 {
3556         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3557                 return false;
3558
3559         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3560                 return false;
3561
3562         ath9k_hw_init_pll(ah, NULL);
3563         return true;
3564 }
3565 EXPORT_SYMBOL(ath9k_hw_disable);
3566
3567 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3568 {
3569         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3570         struct ath9k_channel *chan = ah->curchan;
3571         struct ieee80211_channel *channel = chan->chan;
3572
3573         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3574
3575         ah->eep_ops->set_txpower(ah, chan,
3576                                  ath9k_regd_get_ctl(regulatory, chan),
3577                                  channel->max_antenna_gain * 2,
3578                                  channel->max_power * 2,
3579                                  min((u32) MAX_RATE_POWER,
3580                                  (u32) regulatory->power_limit));
3581 }
3582 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3583
3584 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3585 {
3586         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3587 }
3588 EXPORT_SYMBOL(ath9k_hw_setmac);
3589
3590 void ath9k_hw_setopmode(struct ath_hw *ah)
3591 {
3592         ath9k_hw_set_operating_mode(ah, ah->opmode);
3593 }
3594 EXPORT_SYMBOL(ath9k_hw_setopmode);
3595
3596 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3597 {
3598         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3599         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3600 }
3601 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3602
3603 void ath9k_hw_write_associd(struct ath_hw *ah)
3604 {
3605         struct ath_common *common = ath9k_hw_common(ah);
3606
3607         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3608         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3609                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3610 }
3611 EXPORT_SYMBOL(ath9k_hw_write_associd);
3612
3613 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3614 {
3615         u64 tsf;
3616
3617         tsf = REG_READ(ah, AR_TSF_U32);
3618         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3619
3620         return tsf;
3621 }
3622 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3623
3624 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3625 {
3626         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3627         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3628 }
3629 EXPORT_SYMBOL(ath9k_hw_settsf64);
3630
3631 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3632 {
3633         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3634                            AH_TSF_WRITE_TIMEOUT))
3635                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3636                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3637
3638         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3639 }
3640 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3641
3642 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3643 {
3644         if (setting)
3645                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3646         else
3647                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3648 }
3649 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3650
3651 /*
3652  *  Extend 15-bit time stamp from rx descriptor to
3653  *  a full 64-bit TSF using the current h/w TSF.
3654 */
3655 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3656 {
3657         u64 tsf;
3658
3659         tsf = ath9k_hw_gettsf64(ah);
3660         if ((tsf & 0x7fff) < rstamp)
3661                 tsf -= 0x8000;
3662         return (tsf & ~0x7fff) | rstamp;
3663 }
3664 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3665
3666 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3667 {
3668         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3669         u32 macmode;
3670
3671         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3672                 macmode = AR_2040_JOINED_RX_CLEAR;
3673         else
3674                 macmode = 0;
3675
3676         REG_WRITE(ah, AR_2040_MODE, macmode);
3677 }
3678
3679 /* HW Generic timers configuration */
3680
3681 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3682 {
3683         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3684         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3685         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3686         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3687         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3688         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3689         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3690         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3691         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3692         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3693                                 AR_NDP2_TIMER_MODE, 0x0002},
3694         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3695                                 AR_NDP2_TIMER_MODE, 0x0004},
3696         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3697                                 AR_NDP2_TIMER_MODE, 0x0008},
3698         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3699                                 AR_NDP2_TIMER_MODE, 0x0010},
3700         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3701                                 AR_NDP2_TIMER_MODE, 0x0020},
3702         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3703                                 AR_NDP2_TIMER_MODE, 0x0040},
3704         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3705                                 AR_NDP2_TIMER_MODE, 0x0080}
3706 };
3707
3708 /* HW generic timer primitives */
3709
3710 /* compute and clear index of rightmost 1 */
3711 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3712 {
3713         u32 b;
3714
3715         b = *mask;
3716         b &= (0-b);
3717         *mask &= ~b;
3718         b *= debruijn32;
3719         b >>= 27;
3720
3721         return timer_table->gen_timer_index[b];
3722 }
3723
3724 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3725 {
3726         return REG_READ(ah, AR_TSF_L32);
3727 }
3728 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3729
3730 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3731                                           void (*trigger)(void *),
3732                                           void (*overflow)(void *),
3733                                           void *arg,
3734                                           u8 timer_index)
3735 {
3736         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3737         struct ath_gen_timer *timer;
3738
3739         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3740
3741         if (timer == NULL) {
3742                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3743                           "Failed to allocate memory"
3744                           "for hw timer[%d]\n", timer_index);
3745                 return NULL;
3746         }
3747
3748         /* allocate a hardware generic timer slot */
3749         timer_table->timers[timer_index] = timer;
3750         timer->index = timer_index;
3751         timer->trigger = trigger;
3752         timer->overflow = overflow;
3753         timer->arg = arg;
3754
3755         return timer;
3756 }
3757 EXPORT_SYMBOL(ath_gen_timer_alloc);
3758
3759 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3760                               struct ath_gen_timer *timer,
3761                               u32 timer_next,
3762                               u32 timer_period)
3763 {
3764         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3765         u32 tsf;
3766
3767         BUG_ON(!timer_period);
3768
3769         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3770
3771         tsf = ath9k_hw_gettsf32(ah);
3772
3773         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3774                   "curent tsf %x period %x"
3775                   "timer_next %x\n", tsf, timer_period, timer_next);
3776
3777         /*
3778          * Pull timer_next forward if the current TSF already passed it
3779          * because of software latency
3780          */
3781         if (timer_next < tsf)
3782                 timer_next = tsf + timer_period;
3783
3784         /*
3785          * Program generic timer registers
3786          */
3787         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3788                  timer_next);
3789         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3790                   timer_period);
3791         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3792                     gen_tmr_configuration[timer->index].mode_mask);
3793
3794         /* Enable both trigger and thresh interrupt masks */
3795         REG_SET_BIT(ah, AR_IMR_S5,
3796                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3797                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3798 }
3799 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3800
3801 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3802 {
3803         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3804
3805         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3806                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3807                 return;
3808         }
3809
3810         /* Clear generic timer enable bits. */
3811         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3812                         gen_tmr_configuration[timer->index].mode_mask);
3813
3814         /* Disable both trigger and thresh interrupt masks */
3815         REG_CLR_BIT(ah, AR_IMR_S5,
3816                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3817                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3818
3819         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3820 }
3821 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3822
3823 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3824 {
3825         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3826
3827         /* free the hardware generic timer slot */
3828         timer_table->timers[timer->index] = NULL;
3829         kfree(timer);
3830 }
3831 EXPORT_SYMBOL(ath_gen_timer_free);
3832
3833 /*
3834  * Generic Timer Interrupts handling
3835  */
3836 void ath_gen_timer_isr(struct ath_hw *ah)
3837 {
3838         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3839         struct ath_gen_timer *timer;
3840         struct ath_common *common = ath9k_hw_common(ah);
3841         u32 trigger_mask, thresh_mask, index;
3842
3843         /* get hardware generic timer interrupt status */
3844         trigger_mask = ah->intr_gen_timer_trigger;
3845         thresh_mask = ah->intr_gen_timer_thresh;
3846         trigger_mask &= timer_table->timer_mask.val;
3847         thresh_mask &= timer_table->timer_mask.val;
3848
3849         trigger_mask &= ~thresh_mask;
3850
3851         while (thresh_mask) {
3852                 index = rightmost_index(timer_table, &thresh_mask);
3853                 timer = timer_table->timers[index];
3854                 BUG_ON(!timer);
3855                 ath_print(common, ATH_DBG_HWTIMER,
3856                           "TSF overflow for Gen timer %d\n", index);
3857                 timer->overflow(timer->arg);
3858         }
3859
3860         while (trigger_mask) {
3861                 index = rightmost_index(timer_table, &trigger_mask);
3862                 timer = timer_table->timers[index];
3863                 BUG_ON(!timer);
3864                 ath_print(common, ATH_DBG_HWTIMER,
3865                           "Gen timer[%d] trigger\n", index);
3866                 timer->trigger(timer->arg);
3867         }
3868 }
3869 EXPORT_SYMBOL(ath_gen_timer_isr);
3870
3871 static struct {
3872         u32 version;
3873         const char * name;
3874 } ath_mac_bb_names[] = {
3875         /* Devices with external radios */
3876         { AR_SREV_VERSION_5416_PCI,     "5416" },
3877         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3878         { AR_SREV_VERSION_9100,         "9100" },
3879         { AR_SREV_VERSION_9160,         "9160" },
3880         /* Single-chip solutions */
3881         { AR_SREV_VERSION_9280,         "9280" },
3882         { AR_SREV_VERSION_9285,         "9285" },
3883         { AR_SREV_VERSION_9287,         "9287" },
3884         { AR_SREV_VERSION_9271,         "9271" },
3885 };
3886
3887 /* For devices with external radios */
3888 static struct {
3889         u16 version;
3890         const char * name;
3891 } ath_rf_names[] = {
3892         { 0,                            "5133" },
3893         { AR_RAD5133_SREV_MAJOR,        "5133" },
3894         { AR_RAD5122_SREV_MAJOR,        "5122" },
3895         { AR_RAD2133_SREV_MAJOR,        "2133" },
3896         { AR_RAD2122_SREV_MAJOR,        "2122" }
3897 };
3898
3899 /*
3900  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3901  */
3902 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3903 {
3904         int i;
3905
3906         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3907                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3908                         return ath_mac_bb_names[i].name;
3909                 }
3910         }
3911
3912         return "????";
3913 }
3914
3915 /*
3916  * Return the RF name. "????" is returned if the RF is unknown.
3917  * Used for devices with external radios.
3918  */
3919 static const char *ath9k_hw_rf_name(u16 rf_version)
3920 {
3921         int i;
3922
3923         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3924                 if (ath_rf_names[i].version == rf_version) {
3925                         return ath_rf_names[i].name;
3926                 }
3927         }
3928
3929         return "????";
3930 }
3931
3932 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3933 {
3934         int used;
3935
3936         /* chipsets >= AR9280 are single-chip */
3937         if (AR_SREV_9280_10_OR_LATER(ah)) {
3938                 used = snprintf(hw_name, len,
3939                                "Atheros AR%s Rev:%x",
3940                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3941                                ah->hw_version.macRev);
3942         }
3943         else {
3944                 used = snprintf(hw_name, len,
3945                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3946                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3947                                ah->hw_version.macRev,
3948                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3949                                                 AR_RADIO_SREV_MAJOR)),
3950                                ah->hw_version.phyRev);
3951         }
3952
3953         hw_name[used] = '\0';
3954 }
3955 EXPORT_SYMBOL(ath9k_hw_name);