drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9003_buffalo_initvals.h"
  21 #include "ar9485_initvals.h"
  22 #include "ar9340_initvals.h"
  23 #include "ar9330_1p1_initvals.h"
  24 #include "ar9330_1p2_initvals.h"
  25 #include "ar955x_1p0_initvals.h"
  26 #include "ar9580_1p0_initvals.h"
  27 #include "ar9462_2p0_initvals.h"
  28 #include "ar9462_2p1_initvals.h"
  29 #include "ar9565_1p0_initvals.h"
  30 #include "ar9565_1p1_initvals.h"
  31 #include "ar953x_initvals.h"
  32
  33 /* General hardware code for the AR9003 hadware family */
  34
  35 /*
  36  * The AR9003 family uses a new INI format (pre, core, post
  37  * arrays per subsystem). This provides support for the
  38  * AR9003 2.2 chipsets.
  39  */
  40 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  41 {
  42         if (AR_SREV_9330_11(ah)) {
  43                 /* mac */
  44                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  45                                 ar9331_1p1_mac_core);
  46                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  47                                 ar9331_1p1_mac_postamble);
  48
  49                 /* bb */
  50                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  51                                 ar9331_1p1_baseband_core);
  52                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  53                                 ar9331_1p1_baseband_postamble);
  54
  55                 /* radio */
  56                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  57                                 ar9331_1p1_radio_core);
  58
  59                 /* soc */
  60                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  61                                 ar9331_1p1_soc_preamble);
  62                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  63                                 ar9331_1p1_soc_postamble);
  64
  65                 /* rx/tx gain */
  66                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  67                                 ar9331_common_rx_gain_1p1);
  68                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  69                                 ar9331_modes_lowest_ob_db_tx_gain_1p1);
  70
  71                 /* Japan 2484 Mhz CCK */
  72                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  73                                ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
  74
  75                 /* additional clock settings */
  76                 if (ah->is_clk_25mhz)
  77                         INIT_INI_ARRAY(&ah->iniAdditional,
  78                                         ar9331_1p1_xtal_25M);
  79                 else
  80                         INIT_INI_ARRAY(&ah->iniAdditional,
  81                                         ar9331_1p1_xtal_40M);
  82         } else if (AR_SREV_9330_12(ah)) {
  83                 /* mac */
  84                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  85                                 ar9331_1p2_mac_core);
  86                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  87                                 ar9331_1p2_mac_postamble);
  88
  89                 /* bb */
  90                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  91                                 ar9331_1p2_baseband_core);
  92                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  93                                 ar9331_1p2_baseband_postamble);
  94
  95                 /* radio */
  96                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  97                                 ar9331_1p2_radio_core);
  98
  99                 /* soc */
 100                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 101                                 ar9331_1p2_soc_preamble);
 102                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 103                                 ar9331_1p2_soc_postamble);
 104
 105                 /* rx/tx gain */
 106                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 107                                 ar9331_common_rx_gain_1p2);
 108                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 109                                 ar9331_modes_lowest_ob_db_tx_gain_1p2);
 110
 111                 /* Japan 2484 Mhz CCK */
 112                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 113                                ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
 114
 115                 /* additional clock settings */
 116                 if (ah->is_clk_25mhz)
 117                         INIT_INI_ARRAY(&ah->iniAdditional,
 118                                         ar9331_1p2_xtal_25M);
 119                 else
 120                         INIT_INI_ARRAY(&ah->iniAdditional,
 121                                         ar9331_1p2_xtal_40M);
 122         } else if (AR_SREV_9340(ah)) {
 123                 /* mac */
 124                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 125                                 ar9340_1p0_mac_core);
 126                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 127                                 ar9340_1p0_mac_postamble);
 128
 129                 /* bb */
 130                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 131                                 ar9340_1p0_baseband_core);
 132                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 133                                 ar9340_1p0_baseband_postamble);
 134
 135                 /* radio */
 136                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 137                                 ar9340_1p0_radio_core);
 138                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 139                                 ar9340_1p0_radio_postamble);
 140
 141                 /* soc */
 142                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 143                                 ar9340_1p0_soc_preamble);
 144                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 145                                 ar9340_1p0_soc_postamble);
 146
 147                 /* rx/tx gain */
 148                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 149                                 ar9340Common_wo_xlna_rx_gain_table_1p0);
 150                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 151                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
 152
 153                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 154                                ar9340Modes_fast_clock_1p0);
 155                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 156                                ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
 157                 INIT_INI_ARRAY(&ah->ini_dfs,
 158                                ar9340_1p0_baseband_postamble_dfs_channel);
 159
 160                 if (!ah->is_clk_25mhz)
 161                         INIT_INI_ARRAY(&ah->iniAdditional,
 162                                        ar9340_1p0_radio_core_40M);
 163         } else if (AR_SREV_9485_11_OR_LATER(ah)) {
 164                 /* mac */
 165                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 166                                 ar9485_1_1_mac_core);
 167                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 168                                 ar9485_1_1_mac_postamble);
 169
 170                 /* bb */
 171                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
 172                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 173                                 ar9485_1_1_baseband_core);
 174                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 175                                 ar9485_1_1_baseband_postamble);
 176
 177                 /* radio */
 178                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 179                                 ar9485_1_1_radio_core);
 180                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 181                                 ar9485_1_1_radio_postamble);
 182
 183                 /* soc */
 184                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 185                                 ar9485_1_1_soc_preamble);
 186
 187                 /* rx/tx gain */
 188                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 189                                 ar9485Common_wo_xlna_rx_gain_1_1);
 190                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 191                                 ar9485_modes_lowest_ob_db_tx_gain_1_1);
 192
 193                 /* Japan 2484 Mhz CCK */
 194                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 195                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 196
 197                 if (ah->config.no_pll_pwrsave) {
 198                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 199                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 200                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 201                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 202                 } else {
 203                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 204                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 205                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 206                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 207                 }
 208         } else if (AR_SREV_9462_21(ah)) {
 209                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 210                                ar9462_2p1_mac_core);
 211                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 212                                ar9462_2p1_mac_postamble);
 213                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 214                                ar9462_2p1_baseband_core);
 215                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 216                                ar9462_2p1_baseband_postamble);
 217                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 218                                ar9462_2p1_radio_core);
 219                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 220                                ar9462_2p1_radio_postamble);
 221                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 222                                ar9462_2p1_radio_postamble_sys2ant);
 223                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 224                                ar9462_2p1_soc_preamble);
 225                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 226                                ar9462_2p1_soc_postamble);
 227                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 228                                ar9462_2p1_common_rx_gain);
 229                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 230                                ar9462_2p1_modes_fast_clock);
 231                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 232                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 233                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 234                                ar9462_2p1_pciephy_clkreq_disable_L1);
 235                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 236                                ar9462_2p1_pciephy_clkreq_disable_L1);
 237         } else if (AR_SREV_9462_20(ah)) {
 238
 239                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 240                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 241                                 ar9462_2p0_mac_postamble);
 242
 243                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 244                                 ar9462_2p0_baseband_core);
 245                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 246                                 ar9462_2p0_baseband_postamble);
 247
 248                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 249                                 ar9462_2p0_radio_core);
 250                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 251                                 ar9462_2p0_radio_postamble);
 252                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 253                                 ar9462_2p0_radio_postamble_sys2ant);
 254
 255                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 256                                 ar9462_2p0_soc_preamble);
 257                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 258                                 ar9462_2p0_soc_postamble);
 259
 260                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 261                                 ar9462_2p0_common_rx_gain);
 262
 263                 /* Awake -> Sleep Setting */
 264                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 265                                ar9462_2p0_pciephy_clkreq_disable_L1);
 266                 /* Sleep -> Awake Setting */
 267                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 268                                ar9462_2p0_pciephy_clkreq_disable_L1);
 269
 270                 /* Fast clock modal settings */
 271                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 272                                 ar9462_2p0_modes_fast_clock);
 273
 274                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 275                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 276         } else if (AR_SREV_9550(ah)) {
 277                 /* mac */
 278                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 279                                 ar955x_1p0_mac_core);
 280                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 281                                 ar955x_1p0_mac_postamble);
 282
 283                 /* bb */
 284                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 285                                 ar955x_1p0_baseband_core);
 286                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 287                                 ar955x_1p0_baseband_postamble);
 288
 289                 /* radio */
 290                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 291                                 ar955x_1p0_radio_core);
 292                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 293                                 ar955x_1p0_radio_postamble);
 294
 295                 /* soc */
 296                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 297                                 ar955x_1p0_soc_preamble);
 298                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 299                                 ar955x_1p0_soc_postamble);
 300
 301                 /* rx/tx gain */
 302                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 303                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 304                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 305                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 306                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 307                                 ar955x_1p0_modes_xpa_tx_gain_table);
 308
 309                 /* Fast clock modal settings */
 310                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 311                                 ar955x_1p0_modes_fast_clock);
 312         } else if (AR_SREV_9531(ah)) {
 313                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 314                                qca953x_1p0_mac_core);
 315                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 316                                qca953x_1p0_mac_postamble);
 317                 if (AR_SREV_9531_20(ah)) {
 318                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 319                                        qca953x_2p0_baseband_core);
 320                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 321                                        qca953x_2p0_baseband_postamble);
 322                 } else {
 323                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 324                                        qca953x_1p0_baseband_core);
 325                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 326                                        qca953x_1p0_baseband_postamble);
 327                 }
 328                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 329                                qca953x_1p0_radio_core);
 330                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 331                                qca953x_1p0_radio_postamble);
 332                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 333                                qca953x_1p0_soc_preamble);
 334                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 335                                qca953x_1p0_soc_postamble);
 336
 337                 if (AR_SREV_9531_20(ah)) {
 338                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 339                                        qca953x_2p0_common_wo_xlna_rx_gain_table);
 340                         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 341                                        qca953x_2p0_common_wo_xlna_rx_gain_bounds);
 342                 } else {
 343                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 344                                        qca953x_1p0_common_wo_xlna_rx_gain_table);
 345                         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 346                                        qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 347                 }
 348
 349                 if (AR_SREV_9531_20(ah))
 350                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 351                                        qca953x_2p0_modes_no_xpa_tx_gain_table);
 352                 else if (AR_SREV_9531_11(ah))
 353                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 354                                        qca953x_1p1_modes_no_xpa_tx_gain_table);
 355                 else
 356                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 357                                        qca953x_1p0_modes_no_xpa_tx_gain_table);
 358
 359                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 360                                qca953x_1p0_modes_fast_clock);
 361         } else if (AR_SREV_9580(ah)) {
 362                 /* mac */
 363                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 364                                 ar9580_1p0_mac_core);
 365                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 366                                 ar9580_1p0_mac_postamble);
 367
 368                 /* bb */
 369                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 370                                 ar9580_1p0_baseband_core);
 371                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 372                                 ar9580_1p0_baseband_postamble);
 373
 374                 /* radio */
 375                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 376                                 ar9580_1p0_radio_core);
 377                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 378                                 ar9580_1p0_radio_postamble);
 379
 380                 /* soc */
 381                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 382                                 ar9580_1p0_soc_preamble);
 383                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 384                                 ar9580_1p0_soc_postamble);
 385
 386                 /* rx/tx gain */
 387                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 388                                 ar9580_1p0_rx_gain_table);
 389                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 390                                 ar9580_1p0_low_ob_db_tx_gain_table);
 391
 392                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 393                                ar9580_1p0_modes_fast_clock);
 394                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 395                                ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 396                 INIT_INI_ARRAY(&ah->ini_dfs,
 397                                ar9580_1p0_baseband_postamble_dfs_channel);
 398         } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 399                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 400                                ar9565_1p1_mac_core);
 401                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 402                                ar9565_1p1_mac_postamble);
 403
 404                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 405                                ar9565_1p1_baseband_core);
 406                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 407                                ar9565_1p1_baseband_postamble);
 408
 409                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 410                                ar9565_1p1_radio_core);
 411                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 412                                ar9565_1p1_radio_postamble);
 413
 414                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 415                                ar9565_1p1_soc_preamble);
 416                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 417                                ar9565_1p1_soc_postamble);
 418
 419                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 420                                ar9565_1p1_Common_rx_gain_table);
 421                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 422                                ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 423
 424                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 425                                ar9565_1p1_pciephy_clkreq_disable_L1);
 426                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 427                                ar9565_1p1_pciephy_clkreq_disable_L1);
 428
 429                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 430                                 ar9565_1p1_modes_fast_clock);
 431                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 432                                ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 433         } else if (AR_SREV_9565(ah)) {
 434                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 435                                ar9565_1p0_mac_core);
 436                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 437                                ar9565_1p0_mac_postamble);
 438
 439                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 440                                ar9565_1p0_baseband_core);
 441                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 442                                ar9565_1p0_baseband_postamble);
 443
 444                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 445                                ar9565_1p0_radio_core);
 446                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 447                                ar9565_1p0_radio_postamble);
 448
 449                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 450                                ar9565_1p0_soc_preamble);
 451                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 452                                ar9565_1p0_soc_postamble);
 453
 454                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 455                                ar9565_1p0_Common_rx_gain_table);
 456                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 457                                ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
 458
 459                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 460                                ar9565_1p0_pciephy_clkreq_disable_L1);
 461                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 462                                ar9565_1p0_pciephy_clkreq_disable_L1);
 463
 464                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 465                                 ar9565_1p0_modes_fast_clock);
 466                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 467                                ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
 468         } else {
 469                 /* mac */
 470                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 471                                 ar9300_2p2_mac_core);
 472                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 473                                 ar9300_2p2_mac_postamble);
 474
 475                 /* bb */
 476                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 477                                 ar9300_2p2_baseband_core);
 478                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 479                                 ar9300_2p2_baseband_postamble);
 480
 481                 /* radio */
 482                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 483                                 ar9300_2p2_radio_core);
 484                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 485                                 ar9300_2p2_radio_postamble);
 486
 487                 /* soc */
 488                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 489                                 ar9300_2p2_soc_preamble);
 490                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 491                                 ar9300_2p2_soc_postamble);
 492
 493                 /* rx/tx gain */
 494                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 495                                 ar9300Common_rx_gain_table_2p2);
 496                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 497                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 498
 499                 /* Load PCIE SERDES settings from INI */
 500
 501                 /* Awake Setting */
 502
 503                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 504                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 505
 506                 /* Sleep Setting */
 507
 508                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 509                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 510
 511                 /* Fast clock modal settings */
 512                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 513                                ar9300Modes_fast_clock_2p2);
 514                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 515                                ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 516                 INIT_INI_ARRAY(&ah->ini_dfs,
 517                                ar9300_2p2_baseband_postamble_dfs_channel);
 518         }
 519 }
 520
 521 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 522 {
 523         if (AR_SREV_9330_12(ah))
 524                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 525                         ar9331_modes_lowest_ob_db_tx_gain_1p2);
 526         else if (AR_SREV_9330_11(ah))
 527                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 528                         ar9331_modes_lowest_ob_db_tx_gain_1p1);
 529         else if (AR_SREV_9340(ah))
 530                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 531                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
 532         else if (AR_SREV_9485_11_OR_LATER(ah))
 533                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 534                         ar9485_modes_lowest_ob_db_tx_gain_1_1);
 535         else if (AR_SREV_9550(ah))
 536                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 537                         ar955x_1p0_modes_xpa_tx_gain_table);
 538         else if (AR_SREV_9531_10(ah))
 539                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 540                                qca953x_1p0_modes_xpa_tx_gain_table);
 541         else if (AR_SREV_9531_11(ah))
 542                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 543                                qca953x_1p1_modes_xpa_tx_gain_table);
 544         else if (AR_SREV_9531_20(ah))
 545                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 546                                qca953x_2p0_modes_xpa_tx_gain_table);
 547         else if (AR_SREV_9580(ah))
 548                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 549                         ar9580_1p0_lowest_ob_db_tx_gain_table);
 550         else if (AR_SREV_9462_21(ah))
 551                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 552                         ar9462_2p1_modes_low_ob_db_tx_gain);
 553         else if (AR_SREV_9462_20(ah))
 554                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 555                         ar9462_2p0_modes_low_ob_db_tx_gain);
 556         else if (AR_SREV_9565_11(ah))
 557                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 558                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 559         else if (AR_SREV_9565(ah))
 560                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 561                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 562         else
 563                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 564                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 565 }
 566
 567 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 568 {
 569         if (AR_SREV_9330_12(ah))
 570                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 571                         ar9331_modes_high_ob_db_tx_gain_1p2);
 572         else if (AR_SREV_9330_11(ah))
 573                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 574                         ar9331_modes_high_ob_db_tx_gain_1p1);
 575         else if (AR_SREV_9340(ah))
 576                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 577                         ar9340Modes_high_ob_db_tx_gain_table_1p0);
 578         else if (AR_SREV_9485_11_OR_LATER(ah))
 579                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 580                         ar9485Modes_high_ob_db_tx_gain_1_1);
 581         else if (AR_SREV_9580(ah))
 582                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 583                         ar9580_1p0_high_ob_db_tx_gain_table);
 584         else if (AR_SREV_9550(ah))
 585                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 586                         ar955x_1p0_modes_no_xpa_tx_gain_table);
 587         else if (AR_SREV_9531(ah)) {
 588                 if (AR_SREV_9531_20(ah))
 589                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 590                                        qca953x_2p0_modes_no_xpa_tx_gain_table);
 591                 else if (AR_SREV_9531_11(ah))
 592                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 593                                        qca953x_1p1_modes_no_xpa_tx_gain_table);
 594                 else
 595                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 596                                        qca953x_1p0_modes_no_xpa_tx_gain_table);
 597         } else if (AR_SREV_9462_21(ah))
 598                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 599                         ar9462_2p1_modes_high_ob_db_tx_gain);
 600         else if (AR_SREV_9462_20(ah))
 601                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 602                         ar9462_2p0_modes_high_ob_db_tx_gain);
 603         else if (AR_SREV_9565_11(ah))
 604                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 605                                ar9565_1p1_modes_high_ob_db_tx_gain_table);
 606         else if (AR_SREV_9565(ah))
 607                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 608                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 609         else
 610                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 611                         ar9300Modes_high_ob_db_tx_gain_table_2p2);
 612 }
 613
 614 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 615 {
 616         if (AR_SREV_9330_12(ah))
 617                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 618                         ar9331_modes_low_ob_db_tx_gain_1p2);
 619         else if (AR_SREV_9330_11(ah))
 620                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 621                         ar9331_modes_low_ob_db_tx_gain_1p1);
 622         else if (AR_SREV_9340(ah))
 623                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 624                         ar9340Modes_low_ob_db_tx_gain_table_1p0);
 625         else if (AR_SREV_9485_11_OR_LATER(ah))
 626                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 627                         ar9485Modes_low_ob_db_tx_gain_1_1);
 628         else if (AR_SREV_9580(ah))
 629                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 630                         ar9580_1p0_low_ob_db_tx_gain_table);
 631         else if (AR_SREV_9565_11(ah))
 632                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 633                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 634         else if (AR_SREV_9565(ah))
 635                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 636                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 637         else
 638                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 639                         ar9300Modes_low_ob_db_tx_gain_table_2p2);
 640 }
 641
 642 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 643 {
 644         if (AR_SREV_9330_12(ah))
 645                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 646                         ar9331_modes_high_power_tx_gain_1p2);
 647         else if (AR_SREV_9330_11(ah))
 648                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 649                         ar9331_modes_high_power_tx_gain_1p1);
 650         else if (AR_SREV_9340(ah))
 651                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 652                         ar9340Modes_high_power_tx_gain_table_1p0);
 653         else if (AR_SREV_9485_11_OR_LATER(ah))
 654                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 655                         ar9485Modes_high_power_tx_gain_1_1);
 656         else if (AR_SREV_9580(ah))
 657                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 658                         ar9580_1p0_high_power_tx_gain_table);
 659         else if (AR_SREV_9565_11(ah))
 660                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 661                                ar9565_1p1_modes_high_power_tx_gain_table);
 662         else if (AR_SREV_9565(ah))
 663                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 664                                ar9565_1p0_modes_high_power_tx_gain_table);
 665         else {
 666                 if (ah->config.tx_gain_buffalo)
 667                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 668                                        ar9300Modes_high_power_tx_gain_table_buffalo);
 669                 else
 670                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 671                                        ar9300Modes_high_power_tx_gain_table_2p2);
 672         }
 673 }
 674
 675 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 676 {
 677         if (AR_SREV_9340(ah))
 678                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 679                         ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
 680         else if (AR_SREV_9580(ah))
 681                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 682                         ar9580_1p0_mixed_ob_db_tx_gain_table);
 683         else if (AR_SREV_9462_21(ah))
 684                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 685                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 686         else if (AR_SREV_9462_20(ah))
 687                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 688                        ar9462_2p0_modes_mix_ob_db_tx_gain);
 689         else
 690                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 691                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 692 }
 693
 694 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
 695 {
 696         if (AR_SREV_9485_11_OR_LATER(ah))
 697                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 698                         ar9485Modes_green_ob_db_tx_gain_1_1);
 699         else if (AR_SREV_9580(ah))
 700                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 701                         ar9580_1p0_type5_tx_gain_table);
 702         else if (AR_SREV_9300_22(ah))
 703                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 704                         ar9300Modes_type5_tx_gain_table_2p2);
 705 }
 706
 707 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
 708 {
 709         if (AR_SREV_9340(ah))
 710                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 711                         ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
 712         else if (AR_SREV_9485_11_OR_LATER(ah))
 713                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 714                         ar9485Modes_green_spur_ob_db_tx_gain_1_1);
 715         else if (AR_SREV_9580(ah))
 716                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 717                         ar9580_1p0_type6_tx_gain_table);
 718 }
 719
 720 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 721 {
 722         if (AR_SREV_9340(ah))
 723                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 724                                ar9340_cus227_tx_gain_table_1p0);
 725 }
 726
 727 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 728
 729 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 730 {
 731         static const ath_txgain_tab modes[] = {
 732                 ar9003_tx_gain_table_mode0,
 733                 ar9003_tx_gain_table_mode1,
 734                 ar9003_tx_gain_table_mode2,
 735                 ar9003_tx_gain_table_mode3,
 736                 ar9003_tx_gain_table_mode4,
 737                 ar9003_tx_gain_table_mode5,
 738                 ar9003_tx_gain_table_mode6,
 739                 ar9003_tx_gain_table_mode7,
 740         };
 741         int idx = ar9003_hw_get_tx_gain_idx(ah);
 742
 743         if (idx >= ARRAY_SIZE(modes))
 744                 idx = 0;
 745
 746         modes[idx](ah);
 747 }
 748
 749 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 750 {
 751         if (AR_SREV_9330_12(ah))
 752                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 753                                 ar9331_common_rx_gain_1p2);
 754         else if (AR_SREV_9330_11(ah))
 755                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 756                                 ar9331_common_rx_gain_1p1);
 757         else if (AR_SREV_9340(ah))
 758                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 759                                 ar9340Common_rx_gain_table_1p0);
 760         else if (AR_SREV_9485_11_OR_LATER(ah))
 761                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 762                                ar9485_common_rx_gain_1_1);
 763         else if (AR_SREV_9550(ah)) {
 764                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 765                                 ar955x_1p0_common_rx_gain_table);
 766                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 767                                 ar955x_1p0_common_rx_gain_bounds);
 768         } else if (AR_SREV_9531(ah)) {
 769                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 770                                qca953x_1p0_common_rx_gain_table);
 771                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 772                                qca953x_1p0_common_rx_gain_bounds);
 773         } else if (AR_SREV_9580(ah))
 774                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 775                                 ar9580_1p0_rx_gain_table);
 776         else if (AR_SREV_9462_21(ah))
 777                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 778                                 ar9462_2p1_common_rx_gain);
 779         else if (AR_SREV_9462_20(ah))
 780                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 781                                 ar9462_2p0_common_rx_gain);
 782         else if (AR_SREV_9565_11(ah))
 783                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 784                                ar9565_1p1_Common_rx_gain_table);
 785         else if (AR_SREV_9565(ah))
 786                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 787                                ar9565_1p0_Common_rx_gain_table);
 788         else
 789                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 790                                 ar9300Common_rx_gain_table_2p2);
 791 }
 792
 793 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 794 {
 795         if (AR_SREV_9330_12(ah))
 796                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 797                         ar9331_common_wo_xlna_rx_gain_1p2);
 798         else if (AR_SREV_9330_11(ah))
 799                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 800                         ar9331_common_wo_xlna_rx_gain_1p1);
 801         else if (AR_SREV_9340(ah))
 802                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 803                         ar9340Common_wo_xlna_rx_gain_table_1p0);
 804         else if (AR_SREV_9485_11_OR_LATER(ah))
 805                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 806                         ar9485Common_wo_xlna_rx_gain_1_1);
 807         else if (AR_SREV_9462_21(ah))
 808                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 809                         ar9462_2p1_common_wo_xlna_rx_gain);
 810         else if (AR_SREV_9462_20(ah))
 811                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 812                         ar9462_2p0_common_wo_xlna_rx_gain);
 813         else if (AR_SREV_9550(ah)) {
 814                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 815                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 816                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 817                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 818         } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
 819                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 820                                qca953x_1p0_common_wo_xlna_rx_gain_table);
 821                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 822                                qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 823         } else if (AR_SREV_9531_20(ah)) {
 824                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 825                                qca953x_2p0_common_wo_xlna_rx_gain_table);
 826                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 827                                qca953x_2p0_common_wo_xlna_rx_gain_bounds);
 828         } else if (AR_SREV_9580(ah))
 829                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 830                         ar9580_1p0_wo_xlna_rx_gain_table);
 831         else if (AR_SREV_9565_11(ah))
 832                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 833                                ar9565_1p1_common_wo_xlna_rx_gain_table);
 834         else if (AR_SREV_9565(ah))
 835                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 836                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 837         else
 838                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 839                         ar9300Common_wo_xlna_rx_gain_table_2p2);
 840 }
 841
 842 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 843 {
 844         if (AR_SREV_9462_21(ah)) {
 845                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 846                                ar9462_2p1_common_mixed_rx_gain);
 847                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 848                                ar9462_2p1_baseband_core_mix_rxgain);
 849                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 850                                ar9462_2p1_baseband_postamble_mix_rxgain);
 851                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 852                                ar9462_2p1_baseband_postamble_5g_xlna);
 853         } else if (AR_SREV_9462_20(ah)) {
 854                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 855                                ar9462_2p0_common_mixed_rx_gain);
 856                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 857                                ar9462_2p0_baseband_core_mix_rxgain);
 858                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 859                                ar9462_2p0_baseband_postamble_mix_rxgain);
 860                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 861                                ar9462_2p0_baseband_postamble_5g_xlna);
 862         }
 863 }
 864
 865 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
 866 {
 867         if (AR_SREV_9462_21(ah)) {
 868                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 869                                ar9462_2p1_common_5g_xlna_only_rxgain);
 870                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 871                                ar9462_2p1_baseband_postamble_5g_xlna);
 872         } else if (AR_SREV_9462_20(ah)) {
 873                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 874                                ar9462_2p0_common_5g_xlna_only_rxgain);
 875                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 876                                ar9462_2p0_baseband_postamble_5g_xlna);
 877         }
 878 }
 879
 880 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 881 {
 882         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 883         case 0:
 884         default:
 885                 ar9003_rx_gain_table_mode0(ah);
 886                 break;
 887         case 1:
 888                 ar9003_rx_gain_table_mode1(ah);
 889                 break;
 890         case 2:
 891                 ar9003_rx_gain_table_mode2(ah);
 892                 break;
 893         case 3:
 894                 ar9003_rx_gain_table_mode3(ah);
 895                 break;
 896         }
 897 }
 898
 899 /* set gain table pointers according to values read from the eeprom */
 900 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 901 {
 902         ar9003_tx_gain_table_apply(ah);
 903         ar9003_rx_gain_table_apply(ah);
 904 }
 905
 906 /*
 907  * Helper for ASPM support.
 908  *
 909  * Disable PLL when in L0s as well as receiver clock when in L1.
 910  * This power saving option must be enabled through the SerDes.
 911  *
 912  * Programming the SerDes must go through the same 288 bit serial shift
 913  * register as the other analog registers.  Hence the 9 writes.
 914  */
 915 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 916                                          bool power_off)
 917 {
 918         unsigned int i;
 919         struct ar5416IniArray *array;
 920
 921         /*
 922          * Increase L1 Entry Latency. Some WB222 boards don't have
 923          * this change in eeprom/OTP.
 924          *
 925          */
 926         if (AR_SREV_9462(ah)) {
 927                 u32 val = ah->config.aspm_l1_fix;
 928                 if ((val & 0xff000000) == 0x17000000) {
 929                         val &= 0x00ffffff;
 930                         val |= 0x27000000;
 931                         REG_WRITE(ah, 0x570c, val);
 932                 }
 933         }
 934
 935         /* Nothing to do on restore for 11N */
 936         if (!power_off /* !restore */) {
 937                 /* set bit 19 to allow forcing of pcie core into L1 state */
 938                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 939                 REG_WRITE(ah, AR_WA, ah->WARegVal);
 940         }
 941
 942         /*
 943          * Configire PCIE after Ini init. SERDES values now come from ini file
 944          * This enables PCIe low power mode.
 945          */
 946         array = power_off ? &ah->iniPcieSerdes :
 947                 &ah->iniPcieSerdesLowPower;
 948
 949         for (i = 0; i < array->ia_rows; i++) {
 950                 REG_WRITE(ah,
 951                           INI_RA(array, i, 0),
 952                           INI_RA(array, i, 1));
 953         }
 954 }
 955
 956 static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
 957 {
 958         /*
 959          * All chips support detection of BB/MAC hangs.
 960          */
 961         ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
 962         ah->config.hw_hang_checks |= HW_MAC_HANG;
 963
 964         /*
 965          * This is not required for AR9580 1.0
 966          */
 967         if (AR_SREV_9300_22(ah))
 968                 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
 969
 970         if (AR_SREV_9330(ah))
 971                 ah->bb_watchdog_timeout_ms = 85;
 972         else
 973                 ah->bb_watchdog_timeout_ms = 25;
 974 }
 975
 976 /*
 977  * MAC HW hang check
 978  * =================
 979  *
 980  * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
 981  *
 982  * The state of each DCU chain (mapped to TX queues) is available from these
 983  * DMA debug registers:
 984  *
 985  * Chain 0 state : Bits 4:0   of AR_DMADBG_4
 986  * Chain 1 state : Bits 9:5   of AR_DMADBG_4
 987  * Chain 2 state : Bits 14:10 of AR_DMADBG_4
 988  * Chain 3 state : Bits 19:15 of AR_DMADBG_4
 989  * Chain 4 state : Bits 24:20 of AR_DMADBG_4
 990  * Chain 5 state : Bits 29:25 of AR_DMADBG_4
 991  * Chain 6 state : Bits 4:0   of AR_DMADBG_5
 992  * Chain 7 state : Bits 9:5   of AR_DMADBG_5
 993  * Chain 8 state : Bits 14:10 of AR_DMADBG_5
 994  * Chain 9 state : Bits 19:15 of AR_DMADBG_5
 995  *
 996  * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
 997  */
 998
 999 #define NUM_STATUS_READS 50
1000
1001 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
1002 {
1003         u32 dma_dbg_chain, dma_dbg_complete;
1004         u8 dcu_chain_state, dcu_complete_state;
1005         int i;
1006
1007         for (i = 0; i < NUM_STATUS_READS; i++) {
1008                 if (queue < 6)
1009                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
1010                 else
1011                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
1012
1013                 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
1014
1015                 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
1016                 dcu_complete_state = dma_dbg_complete & 0x3;
1017
1018                 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
1019                         return false;
1020         }
1021
1022         ath_dbg(ath9k_hw_common(ah), RESET,
1023                 "MAC Hang signature found for queue: %d\n", queue);
1024
1025         return true;
1026 }
1027
1028 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1029 {
1030         u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
1031         u8 dcu_chain_state, dcu_complete_state;
1032         bool dcu_wait_frdone = false;
1033         unsigned long chk_dcu = 0;
1034         unsigned int i = 0;
1035
1036         dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1037         dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1038         dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1039
1040         dcu_complete_state = dma_dbg_6 & 0x3;
1041         if (dcu_complete_state != 0x1)
1042                 goto exit;
1043
1044         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1045                 if (i < 6)
1046                         chk_dbg = dma_dbg_4;
1047                 else
1048                         chk_dbg = dma_dbg_5;
1049
1050                 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1051                 if (dcu_chain_state == 0x6) {
1052                         dcu_wait_frdone = true;
1053                         chk_dcu |= BIT(i);
1054                 }
1055         }
1056
1057         if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1058                 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1059                         if (ath9k_hw_verify_hang(ah, i))
1060                                 return true;
1061                 }
1062         }
1063 exit:
1064         return false;
1065 }
1066
1067 /* Sets up the AR9003 hardware familiy callbacks */
1068 void ar9003_hw_attach_ops(struct ath_hw *ah)
1069 {
1070         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1071         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1072
1073         ar9003_hw_init_mode_regs(ah);
1074         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
1075         priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
1076         priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
1077
1078         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1079
1080         ar9003_hw_attach_phy_ops(ah);
1081         ar9003_hw_attach_calib_ops(ah);
1082         ar9003_hw_attach_mac_ops(ah);
1083 }