2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
28 #include "targaddrs.h"
37 enum ath10k_pci_reset_mode {
38 ATH10K_PCI_RESET_AUTO = 0,
39 ATH10K_PCI_RESET_WARM_ONLY = 1,
42 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
43 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
45 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
46 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
48 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
49 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
51 /* how long wait to wait for target to initialise, in ms */
52 #define ATH10K_PCI_TARGET_WAIT 3000
53 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
55 /* Maximum number of bytes that can be handled atomically by
56 * diag read and write.
58 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000
60 static const struct pci_device_id ath10k_pci_id_table[] = {
61 /* PCI-E QCA988X V2 (Ubiquiti branded) */
62 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) },
64 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
65 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
66 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
67 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
68 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
69 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
70 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
71 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
75 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
76 /* QCA988X pre 2.0 chips are not supported because they need some nasty
77 * hacks. ath10k doesn't have them and these devices crash horribly
80 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV },
81 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
83 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
84 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
85 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
86 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
89 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
90 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
91 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
92 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
95 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
97 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
99 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
101 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
102 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
104 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
107 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
108 static int ath10k_pci_cold_reset(struct ath10k *ar);
109 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
110 static int ath10k_pci_init_irq(struct ath10k *ar);
111 static int ath10k_pci_deinit_irq(struct ath10k *ar);
112 static int ath10k_pci_request_irq(struct ath10k *ar);
113 static void ath10k_pci_free_irq(struct ath10k *ar);
114 static int ath10k_pci_bmi_wait(struct ath10k *ar,
115 struct ath10k_ce_pipe *tx_pipe,
116 struct ath10k_ce_pipe *rx_pipe,
117 struct bmi_xfer *xfer);
118 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
119 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
120 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
121 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
122 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
123 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
124 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
126 static struct ce_attr host_ce_config_wlan[] = {
127 /* CE0: host->target HTC control and raw streams */
129 .flags = CE_ATTR_FLAGS,
133 .send_cb = ath10k_pci_htc_tx_cb,
136 /* CE1: target->host HTT + HTC control */
138 .flags = CE_ATTR_FLAGS,
141 .dest_nentries = 512,
142 .recv_cb = ath10k_pci_htt_htc_rx_cb,
145 /* CE2: target->host WMI */
147 .flags = CE_ATTR_FLAGS,
150 .dest_nentries = 128,
151 .recv_cb = ath10k_pci_htc_rx_cb,
154 /* CE3: host->target WMI */
156 .flags = CE_ATTR_FLAGS,
160 .send_cb = ath10k_pci_htc_tx_cb,
163 /* CE4: host->target HTT */
165 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
166 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
169 .send_cb = ath10k_pci_htt_tx_cb,
172 /* CE5: target->host HTT (HIF->HTT) */
174 .flags = CE_ATTR_FLAGS,
177 .dest_nentries = 512,
178 .recv_cb = ath10k_pci_htt_rx_cb,
181 /* CE6: target autonomous hif_memcpy */
183 .flags = CE_ATTR_FLAGS,
189 /* CE7: ce_diag, the Diagnostic Window */
191 .flags = CE_ATTR_FLAGS,
193 .src_sz_max = DIAG_TRANSFER_LIMIT,
197 /* CE8: target->host pktlog */
199 .flags = CE_ATTR_FLAGS,
202 .dest_nentries = 128,
203 .recv_cb = ath10k_pci_pktlog_rx_cb,
206 /* CE9 target autonomous qcache memcpy */
208 .flags = CE_ATTR_FLAGS,
214 /* CE10: target autonomous hif memcpy */
216 .flags = CE_ATTR_FLAGS,
222 /* CE11: target autonomous hif memcpy */
224 .flags = CE_ATTR_FLAGS,
231 /* Target firmware's Copy Engine configuration. */
232 static struct ce_pipe_config target_ce_config_wlan[] = {
233 /* CE0: host->target HTC control and raw streams */
235 .pipenum = __cpu_to_le32(0),
236 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
237 .nentries = __cpu_to_le32(32),
238 .nbytes_max = __cpu_to_le32(256),
239 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
240 .reserved = __cpu_to_le32(0),
243 /* CE1: target->host HTT + HTC control */
245 .pipenum = __cpu_to_le32(1),
246 .pipedir = __cpu_to_le32(PIPEDIR_IN),
247 .nentries = __cpu_to_le32(32),
248 .nbytes_max = __cpu_to_le32(2048),
249 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
250 .reserved = __cpu_to_le32(0),
253 /* CE2: target->host WMI */
255 .pipenum = __cpu_to_le32(2),
256 .pipedir = __cpu_to_le32(PIPEDIR_IN),
257 .nentries = __cpu_to_le32(64),
258 .nbytes_max = __cpu_to_le32(2048),
259 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
260 .reserved = __cpu_to_le32(0),
263 /* CE3: host->target WMI */
265 .pipenum = __cpu_to_le32(3),
266 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
267 .nentries = __cpu_to_le32(32),
268 .nbytes_max = __cpu_to_le32(2048),
269 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
270 .reserved = __cpu_to_le32(0),
273 /* CE4: host->target HTT */
275 .pipenum = __cpu_to_le32(4),
276 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
277 .nentries = __cpu_to_le32(256),
278 .nbytes_max = __cpu_to_le32(256),
279 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
280 .reserved = __cpu_to_le32(0),
283 /* NB: 50% of src nentries, since tx has 2 frags */
285 /* CE5: target->host HTT (HIF->HTT) */
287 .pipenum = __cpu_to_le32(5),
288 .pipedir = __cpu_to_le32(PIPEDIR_IN),
289 .nentries = __cpu_to_le32(32),
290 .nbytes_max = __cpu_to_le32(512),
291 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
292 .reserved = __cpu_to_le32(0),
295 /* CE6: Reserved for target autonomous hif_memcpy */
297 .pipenum = __cpu_to_le32(6),
298 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
299 .nentries = __cpu_to_le32(32),
300 .nbytes_max = __cpu_to_le32(4096),
301 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
302 .reserved = __cpu_to_le32(0),
305 /* CE7 used only by Host */
307 .pipenum = __cpu_to_le32(7),
308 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
309 .nentries = __cpu_to_le32(0),
310 .nbytes_max = __cpu_to_le32(0),
311 .flags = __cpu_to_le32(0),
312 .reserved = __cpu_to_le32(0),
315 /* CE8 target->host packtlog */
317 .pipenum = __cpu_to_le32(8),
318 .pipedir = __cpu_to_le32(PIPEDIR_IN),
319 .nentries = __cpu_to_le32(64),
320 .nbytes_max = __cpu_to_le32(2048),
321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
322 .reserved = __cpu_to_le32(0),
325 /* CE9 target autonomous qcache memcpy */
327 .pipenum = __cpu_to_le32(9),
328 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
329 .nentries = __cpu_to_le32(32),
330 .nbytes_max = __cpu_to_le32(2048),
331 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
332 .reserved = __cpu_to_le32(0),
335 /* It not necessary to send target wlan configuration for CE10 & CE11
336 * as these CEs are not actively used in target.
341 * Map from service/endpoint to Copy Engine.
342 * This table is derived from the CE_PCI TABLE, above.
343 * It is passed to the Target at startup for use by firmware.
345 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
348 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
353 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
358 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
363 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
368 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
373 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
378 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
383 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
387 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
388 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
392 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
393 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
397 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
398 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
402 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
403 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
407 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
412 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
417 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
418 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
422 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
423 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
427 /* (Additions here) */
436 static bool ath10k_pci_is_awake(struct ath10k *ar)
438 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
439 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
442 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
445 static void __ath10k_pci_wake(struct ath10k *ar)
447 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
449 lockdep_assert_held(&ar_pci->ps_lock);
451 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
452 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
454 iowrite32(PCIE_SOC_WAKE_V_MASK,
455 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
456 PCIE_SOC_WAKE_ADDRESS);
459 static void __ath10k_pci_sleep(struct ath10k *ar)
461 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
463 lockdep_assert_held(&ar_pci->ps_lock);
465 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
466 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
468 iowrite32(PCIE_SOC_WAKE_RESET,
469 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
470 PCIE_SOC_WAKE_ADDRESS);
471 ar_pci->ps_awake = false;
474 static int ath10k_pci_wake_wait(struct ath10k *ar)
479 while (tot_delay < PCIE_WAKE_TIMEOUT) {
480 if (ath10k_pci_is_awake(ar)) {
481 if (tot_delay > PCIE_WAKE_LATE_US)
482 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
488 tot_delay += curr_delay;
497 static int ath10k_pci_force_wake(struct ath10k *ar)
499 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
506 spin_lock_irqsave(&ar_pci->ps_lock, flags);
508 if (!ar_pci->ps_awake) {
509 iowrite32(PCIE_SOC_WAKE_V_MASK,
510 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
511 PCIE_SOC_WAKE_ADDRESS);
513 ret = ath10k_pci_wake_wait(ar);
515 ar_pci->ps_awake = true;
518 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
523 static void ath10k_pci_force_sleep(struct ath10k *ar)
525 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
528 spin_lock_irqsave(&ar_pci->ps_lock, flags);
530 iowrite32(PCIE_SOC_WAKE_RESET,
531 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
532 PCIE_SOC_WAKE_ADDRESS);
533 ar_pci->ps_awake = false;
535 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
538 static int ath10k_pci_wake(struct ath10k *ar)
540 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
544 if (ar_pci->pci_ps == 0)
547 spin_lock_irqsave(&ar_pci->ps_lock, flags);
549 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
550 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
552 /* This function can be called very frequently. To avoid excessive
553 * CPU stalls for MMIO reads use a cache var to hold the device state.
555 if (!ar_pci->ps_awake) {
556 __ath10k_pci_wake(ar);
558 ret = ath10k_pci_wake_wait(ar);
560 ar_pci->ps_awake = true;
564 ar_pci->ps_wake_refcount++;
565 WARN_ON(ar_pci->ps_wake_refcount == 0);
568 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
573 static void ath10k_pci_sleep(struct ath10k *ar)
575 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
578 if (ar_pci->pci_ps == 0)
581 spin_lock_irqsave(&ar_pci->ps_lock, flags);
583 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
584 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
586 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
589 ar_pci->ps_wake_refcount--;
591 mod_timer(&ar_pci->ps_timer, jiffies +
592 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
595 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
598 static void ath10k_pci_ps_timer(struct timer_list *t)
600 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer);
601 struct ath10k *ar = ar_pci->ar;
604 spin_lock_irqsave(&ar_pci->ps_lock, flags);
606 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
607 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
609 if (ar_pci->ps_wake_refcount > 0)
612 __ath10k_pci_sleep(ar);
615 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
618 static void ath10k_pci_sleep_sync(struct ath10k *ar)
620 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
623 if (ar_pci->pci_ps == 0) {
624 ath10k_pci_force_sleep(ar);
628 del_timer_sync(&ar_pci->ps_timer);
630 spin_lock_irqsave(&ar_pci->ps_lock, flags);
631 WARN_ON(ar_pci->ps_wake_refcount > 0);
632 __ath10k_pci_sleep(ar);
633 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
636 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
638 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
641 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
642 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
643 offset, offset + sizeof(value), ar_pci->mem_len);
647 ret = ath10k_pci_wake(ar);
649 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
654 iowrite32(value, ar_pci->mem + offset);
655 ath10k_pci_sleep(ar);
658 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
660 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
664 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
665 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
666 offset, offset + sizeof(val), ar_pci->mem_len);
670 ret = ath10k_pci_wake(ar);
672 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
677 val = ioread32(ar_pci->mem + offset);
678 ath10k_pci_sleep(ar);
683 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
685 struct ath10k_ce *ce = ath10k_ce_priv(ar);
687 ce->bus_ops->write32(ar, offset, value);
690 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
692 struct ath10k_ce *ce = ath10k_ce_priv(ar);
694 return ce->bus_ops->read32(ar, offset);
697 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
699 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
702 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
704 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
707 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
709 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
712 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
714 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
717 bool ath10k_pci_irq_pending(struct ath10k *ar)
721 /* Check if the shared legacy irq is for us */
722 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
723 PCIE_INTR_CAUSE_ADDRESS);
724 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
730 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
732 /* IMPORTANT: INTR_CLR register has to be set after
733 * INTR_ENABLE is set to 0, otherwise interrupt can not be
736 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
738 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
739 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
741 /* IMPORTANT: this extra read transaction is required to
742 * flush the posted write buffer.
744 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
745 PCIE_INTR_ENABLE_ADDRESS);
748 void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
750 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
751 PCIE_INTR_ENABLE_ADDRESS,
752 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
754 /* IMPORTANT: this extra read transaction is required to
755 * flush the posted write buffer.
757 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
758 PCIE_INTR_ENABLE_ADDRESS);
761 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
763 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
765 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
771 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
773 struct ath10k *ar = pipe->hif_ce_state;
774 struct ath10k_ce *ce = ath10k_ce_priv(ar);
775 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
780 skb = dev_alloc_skb(pipe->buf_sz);
784 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
786 paddr = dma_map_single(ar->dev, skb->data,
787 skb->len + skb_tailroom(skb),
789 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
790 ath10k_warn(ar, "failed to dma map pci rx buf\n");
791 dev_kfree_skb_any(skb);
795 ATH10K_SKB_RXCB(skb)->paddr = paddr;
797 spin_lock_bh(&ce->ce_lock);
798 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
799 spin_unlock_bh(&ce->ce_lock);
801 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
803 dev_kfree_skb_any(skb);
810 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
812 struct ath10k *ar = pipe->hif_ce_state;
813 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
814 struct ath10k_ce *ce = ath10k_ce_priv(ar);
815 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
818 if (pipe->buf_sz == 0)
821 if (!ce_pipe->dest_ring)
824 spin_lock_bh(&ce->ce_lock);
825 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
826 spin_unlock_bh(&ce->ce_lock);
829 ret = __ath10k_pci_rx_post_buf(pipe);
833 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
834 mod_timer(&ar_pci->rx_post_retry, jiffies +
835 ATH10K_PCI_RX_POST_RETRY_MS);
842 void ath10k_pci_rx_post(struct ath10k *ar)
844 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
847 for (i = 0; i < CE_COUNT; i++)
848 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
851 void ath10k_pci_rx_replenish_retry(struct timer_list *t)
853 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry);
854 struct ath10k *ar = ar_pci->ar;
856 ath10k_pci_rx_post(ar);
859 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
861 u32 val = 0, region = addr & 0xfffff;
863 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
865 val |= 0x100000 | region;
869 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
871 u32 val = 0, region = addr & 0xfffff;
873 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
874 val |= 0x100000 | region;
878 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
880 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
882 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
885 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
889 * Diagnostic read/write access is provided for startup/config/debug usage.
890 * Caller must guarantee proper alignment, when applicable, and single user
893 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
896 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
897 struct ath10k_ce *ce = ath10k_ce_priv(ar);
900 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
901 struct ath10k_ce_pipe *ce_diag;
902 /* Host buffer address in CE space */
904 dma_addr_t ce_data_base = 0;
905 void *data_buf = NULL;
908 spin_lock_bh(&ce->ce_lock);
910 ce_diag = ar_pci->ce_diag;
913 * Allocate a temporary bounce buffer to hold caller's data
914 * to be DMA'ed from Target. This guarantees
915 * 1) 4-byte alignment
916 * 2) Buffer in DMA-able space
918 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
920 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev,
930 remaining_bytes = nbytes;
931 ce_data = ce_data_base;
932 while (remaining_bytes) {
933 nbytes = min_t(unsigned int, remaining_bytes,
934 DIAG_TRANSFER_LIMIT);
936 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &ce_data, ce_data);
940 /* Request CE to send from Target(!) address to Host buffer */
942 * The address supplied by the caller is in the
943 * Target CPU virtual address space.
945 * In order to use this address with the diagnostic CE,
946 * convert it from Target CPU virtual address space
947 * to CE address space
949 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
951 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
957 while (ath10k_ce_completed_send_next_nolock(ce_diag,
960 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
967 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
973 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
979 if (nbytes != completed_nbytes) {
984 if (*buf != ce_data) {
989 remaining_bytes -= nbytes;
990 memcpy(data, data_buf, nbytes);
999 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1002 spin_unlock_bh(&ce->ce_lock);
1007 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1012 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1013 *value = __le32_to_cpu(val);
1018 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1021 u32 host_addr, addr;
1024 host_addr = host_interest_item_address(src);
1026 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1028 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1033 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1035 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1043 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1044 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1046 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1047 const void *data, int nbytes)
1049 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1050 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1053 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1054 struct ath10k_ce_pipe *ce_diag;
1055 void *data_buf = NULL;
1056 u32 ce_data; /* Host buffer address in CE space */
1057 dma_addr_t ce_data_base = 0;
1060 spin_lock_bh(&ce->ce_lock);
1062 ce_diag = ar_pci->ce_diag;
1065 * Allocate a temporary bounce buffer to hold caller's data
1066 * to be DMA'ed to Target. This guarantees
1067 * 1) 4-byte alignment
1068 * 2) Buffer in DMA-able space
1070 orig_nbytes = nbytes;
1071 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1080 /* Copy caller's data to allocated DMA buf */
1081 memcpy(data_buf, data, orig_nbytes);
1084 * The address supplied by the caller is in the
1085 * Target CPU virtual address space.
1087 * In order to use this address with the diagnostic CE,
1089 * Target CPU virtual address space
1093 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1095 remaining_bytes = orig_nbytes;
1096 ce_data = ce_data_base;
1097 while (remaining_bytes) {
1098 /* FIXME: check cast */
1099 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1101 /* Set up to receive directly into Target(!) address */
1102 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &address, address);
1107 * Request CE to send caller-supplied data that
1108 * was copied to bounce buffer to Target(!) address.
1110 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1116 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1120 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1127 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
1133 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1139 if (nbytes != completed_nbytes) {
1144 if (*buf != address) {
1149 remaining_bytes -= nbytes;
1156 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1161 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1164 spin_unlock_bh(&ce->ce_lock);
1169 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1171 __le32 val = __cpu_to_le32(value);
1173 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1176 /* Called by lower (CE) layer when a send to Target completes. */
1177 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1179 struct ath10k *ar = ce_state->ar;
1180 struct sk_buff_head list;
1181 struct sk_buff *skb;
1183 __skb_queue_head_init(&list);
1184 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1185 /* no need to call tx completion for NULL pointers */
1189 __skb_queue_tail(&list, skb);
1192 while ((skb = __skb_dequeue(&list)))
1193 ath10k_htc_tx_completion_handler(ar, skb);
1196 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1197 void (*callback)(struct ath10k *ar,
1198 struct sk_buff *skb))
1200 struct ath10k *ar = ce_state->ar;
1201 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1202 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1203 struct sk_buff *skb;
1204 struct sk_buff_head list;
1205 void *transfer_context;
1206 unsigned int nbytes, max_nbytes;
1208 __skb_queue_head_init(&list);
1209 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1211 skb = transfer_context;
1212 max_nbytes = skb->len + skb_tailroom(skb);
1213 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1214 max_nbytes, DMA_FROM_DEVICE);
1216 if (unlikely(max_nbytes < nbytes)) {
1217 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1218 nbytes, max_nbytes);
1219 dev_kfree_skb_any(skb);
1223 skb_put(skb, nbytes);
1224 __skb_queue_tail(&list, skb);
1227 while ((skb = __skb_dequeue(&list))) {
1228 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1229 ce_state->id, skb->len);
1230 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1231 skb->data, skb->len);
1236 ath10k_pci_rx_post_pipe(pipe_info);
1239 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1240 void (*callback)(struct ath10k *ar,
1241 struct sk_buff *skb))
1243 struct ath10k *ar = ce_state->ar;
1244 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1245 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1246 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1247 struct sk_buff *skb;
1248 struct sk_buff_head list;
1249 void *transfer_context;
1250 unsigned int nbytes, max_nbytes, nentries;
1253 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1254 * is processed other than init and deinit. Before releasing CE5
1255 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1257 __skb_queue_head_init(&list);
1258 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1260 skb = transfer_context;
1261 max_nbytes = skb->len + skb_tailroom(skb);
1263 if (unlikely(max_nbytes < nbytes)) {
1264 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1265 nbytes, max_nbytes);
1269 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1270 max_nbytes, DMA_FROM_DEVICE);
1271 skb_put(skb, nbytes);
1272 __skb_queue_tail(&list, skb);
1275 nentries = skb_queue_len(&list);
1276 while ((skb = __skb_dequeue(&list))) {
1277 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1278 ce_state->id, skb->len);
1279 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1280 skb->data, skb->len);
1282 orig_len = skb->len;
1284 skb_push(skb, orig_len - skb->len);
1285 skb_reset_tail_pointer(skb);
1288 /*let device gain the buffer again*/
1289 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1290 skb->len + skb_tailroom(skb),
1293 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1296 /* Called by lower (CE) layer when data is received from the Target. */
1297 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1299 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1302 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1304 /* CE4 polling needs to be done whenever CE pipe which transports
1305 * HTT Rx (target->host) is processed.
1307 ath10k_ce_per_engine_service(ce_state->ar, 4);
1309 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1312 /* Called by lower (CE) layer when data is received from the Target.
1313 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1315 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1317 ath10k_pci_process_rx_cb(ce_state,
1318 ath10k_htt_rx_pktlog_completion_handler);
1321 /* Called by lower (CE) layer when a send to HTT Target completes. */
1322 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1324 struct ath10k *ar = ce_state->ar;
1325 struct sk_buff *skb;
1327 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1328 /* no need to call tx completion for NULL pointers */
1332 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1333 skb->len, DMA_TO_DEVICE);
1334 ath10k_htt_hif_tx_complete(ar, skb);
1338 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1340 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1341 ath10k_htt_t2h_msg_handler(ar, skb);
1344 /* Called by lower (CE) layer when HTT data is received from the Target. */
1345 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1347 /* CE4 polling needs to be done whenever CE pipe which transports
1348 * HTT Rx (target->host) is processed.
1350 ath10k_ce_per_engine_service(ce_state->ar, 4);
1352 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1355 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1356 struct ath10k_hif_sg_item *items, int n_items)
1358 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1359 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1360 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1361 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1362 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1363 unsigned int nentries_mask;
1364 unsigned int sw_index;
1365 unsigned int write_index;
1368 spin_lock_bh(&ce->ce_lock);
1370 nentries_mask = src_ring->nentries_mask;
1371 sw_index = src_ring->sw_index;
1372 write_index = src_ring->write_index;
1374 if (unlikely(CE_RING_DELTA(nentries_mask,
1375 write_index, sw_index - 1) < n_items)) {
1380 for (i = 0; i < n_items - 1; i++) {
1381 ath10k_dbg(ar, ATH10K_DBG_PCI,
1382 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1383 i, items[i].paddr, items[i].len, n_items);
1384 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1385 items[i].vaddr, items[i].len);
1387 err = ath10k_ce_send_nolock(ce_pipe,
1388 items[i].transfer_context,
1391 items[i].transfer_id,
1392 CE_SEND_FLAG_GATHER);
1397 /* `i` is equal to `n_items -1` after for() */
1399 ath10k_dbg(ar, ATH10K_DBG_PCI,
1400 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1401 i, items[i].paddr, items[i].len, n_items);
1402 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1403 items[i].vaddr, items[i].len);
1405 err = ath10k_ce_send_nolock(ce_pipe,
1406 items[i].transfer_context,
1409 items[i].transfer_id,
1414 spin_unlock_bh(&ce->ce_lock);
1419 __ath10k_ce_send_revert(ce_pipe);
1421 spin_unlock_bh(&ce->ce_lock);
1425 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1428 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1431 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1433 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1435 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1437 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1440 static void ath10k_pci_dump_registers(struct ath10k *ar,
1441 struct ath10k_fw_crash_data *crash_data)
1443 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1446 lockdep_assert_held(&ar->data_lock);
1448 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1450 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1452 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1456 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1458 ath10k_err(ar, "firmware register dump:\n");
1459 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1460 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1462 __le32_to_cpu(reg_dump_values[i]),
1463 __le32_to_cpu(reg_dump_values[i + 1]),
1464 __le32_to_cpu(reg_dump_values[i + 2]),
1465 __le32_to_cpu(reg_dump_values[i + 3]));
1470 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1471 crash_data->registers[i] = reg_dump_values[i];
1474 static int ath10k_pci_dump_memory_section(struct ath10k *ar,
1475 const struct ath10k_mem_region *mem_region,
1476 u8 *buf, size_t buf_len)
1478 const struct ath10k_mem_section *cur_section, *next_section;
1479 unsigned int count, section_size, skip_size;
1482 if (!mem_region || !buf)
1485 cur_section = &mem_region->section_table.sections[0];
1487 if (mem_region->start > cur_section->start) {
1488 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
1489 mem_region->start, cur_section->start);
1493 skip_size = cur_section->start - mem_region->start;
1495 /* fill the gap between the first register section and register
1498 for (i = 0; i < skip_size; i++) {
1499 *buf = ATH10K_MAGIC_NOT_COPIED;
1505 for (i = 0; cur_section != NULL; i++) {
1506 section_size = cur_section->end - cur_section->start;
1508 if (section_size <= 0) {
1509 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
1515 if ((i + 1) == mem_region->section_table.size) {
1517 next_section = NULL;
1520 next_section = cur_section + 1;
1522 if (cur_section->end > next_section->start) {
1523 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
1524 next_section->start,
1529 skip_size = next_section->start - cur_section->end;
1532 if (buf_len < (skip_size + section_size)) {
1533 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len);
1537 buf_len -= skip_size + section_size;
1539 /* read section to dest memory */
1540 ret = ath10k_pci_diag_read_mem(ar, cur_section->start,
1543 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
1544 cur_section->start, ret);
1548 buf += section_size;
1549 count += section_size;
1551 /* fill in the gap between this section and the next */
1552 for (j = 0; j < skip_size; j++) {
1553 *buf = ATH10K_MAGIC_NOT_COPIED;
1560 /* this was the last section */
1563 cur_section = next_section;
1569 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config)
1573 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1574 FW_RAM_CONFIG_ADDRESS, config);
1576 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1577 FW_RAM_CONFIG_ADDRESS);
1578 if (val != config) {
1579 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n",
1587 static void ath10k_pci_dump_memory(struct ath10k *ar,
1588 struct ath10k_fw_crash_data *crash_data)
1590 const struct ath10k_hw_mem_layout *mem_layout;
1591 const struct ath10k_mem_region *current_region;
1592 struct ath10k_dump_ram_data_hdr *hdr;
1598 lockdep_assert_held(&ar->data_lock);
1603 mem_layout = ath10k_coredump_get_mem_layout(ar);
1607 current_region = &mem_layout->region_table.regions[0];
1609 buf = crash_data->ramdump_buf;
1610 buf_len = crash_data->ramdump_buf_len;
1612 memset(buf, 0, buf_len);
1614 for (i = 0; i < mem_layout->region_table.size; i++) {
1617 if (current_region->len > buf_len) {
1618 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n",
1619 current_region->name,
1620 current_region->len,
1625 /* To get IRAM dump, the host driver needs to switch target
1626 * ram config from DRAM to IRAM.
1628 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 ||
1629 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) {
1630 shift = current_region->start >> 20;
1632 ret = ath10k_pci_set_ram_config(ar, shift);
1634 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n",
1635 current_region->name, ret);
1640 /* Reserve space for the header. */
1642 buf += sizeof(*hdr);
1643 buf_len -= sizeof(*hdr);
1645 if (current_region->section_table.size > 0) {
1646 /* Copy each section individually. */
1647 count = ath10k_pci_dump_memory_section(ar,
1650 current_region->len);
1652 /* No individiual memory sections defined so we can
1653 * copy the entire memory region.
1655 ret = ath10k_pci_diag_read_mem(ar,
1656 current_region->start,
1658 current_region->len);
1660 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
1661 current_region->name, ret);
1665 count = current_region->len;
1668 hdr->region_type = cpu_to_le32(current_region->type);
1669 hdr->start = cpu_to_le32(current_region->start);
1670 hdr->length = cpu_to_le32(count);
1673 /* Note: the header remains, just with zero length. */
1683 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1685 struct ath10k_fw_crash_data *crash_data;
1686 char guid[UUID_STRING_LEN + 1];
1688 spin_lock_bh(&ar->data_lock);
1690 ar->stats.fw_crash_counter++;
1692 crash_data = ath10k_coredump_new(ar);
1695 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1697 scnprintf(guid, sizeof(guid), "n/a");
1699 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1700 ath10k_print_driver_info(ar);
1701 ath10k_pci_dump_registers(ar, crash_data);
1702 ath10k_ce_dump_registers(ar, crash_data);
1703 ath10k_pci_dump_memory(ar, crash_data);
1705 spin_unlock_bh(&ar->data_lock);
1707 queue_work(ar->workqueue, &ar->restart_work);
1710 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1713 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1718 * Decide whether to actually poll for completions, or just
1719 * wait for a later chance.
1720 * If there seem to be plenty of resources left, then just wait
1721 * since checking involves reading a CE register, which is a
1722 * relatively expensive operation.
1724 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1727 * If at least 50% of the total resources are still available,
1728 * don't bother checking again yet.
1730 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1733 ath10k_ce_per_engine_service(ar, pipe);
1736 static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1738 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1740 del_timer_sync(&ar_pci->rx_post_retry);
1743 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1744 u8 *ul_pipe, u8 *dl_pipe)
1746 const struct service_to_pipe *entry;
1747 bool ul_set = false, dl_set = false;
1750 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1752 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1753 entry = &target_service_to_ce_map_wlan[i];
1755 if (__le32_to_cpu(entry->service_id) != service_id)
1758 switch (__le32_to_cpu(entry->pipedir)) {
1763 *dl_pipe = __le32_to_cpu(entry->pipenum);
1768 *ul_pipe = __le32_to_cpu(entry->pipenum);
1774 *dl_pipe = __le32_to_cpu(entry->pipenum);
1775 *ul_pipe = __le32_to_cpu(entry->pipenum);
1782 if (WARN_ON(!ul_set || !dl_set))
1788 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1789 u8 *ul_pipe, u8 *dl_pipe)
1791 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1793 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1794 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1798 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1802 switch (ar->hw_rev) {
1803 case ATH10K_HW_QCA988X:
1804 case ATH10K_HW_QCA9887:
1805 case ATH10K_HW_QCA6174:
1806 case ATH10K_HW_QCA9377:
1807 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1809 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1810 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1811 CORE_CTRL_ADDRESS, val);
1813 case ATH10K_HW_QCA99X0:
1814 case ATH10K_HW_QCA9984:
1815 case ATH10K_HW_QCA9888:
1816 case ATH10K_HW_QCA4019:
1817 /* TODO: Find appropriate register configuration for QCA99X0
1821 case ATH10K_HW_WCN3990:
1826 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1830 switch (ar->hw_rev) {
1831 case ATH10K_HW_QCA988X:
1832 case ATH10K_HW_QCA9887:
1833 case ATH10K_HW_QCA6174:
1834 case ATH10K_HW_QCA9377:
1835 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1837 val |= CORE_CTRL_PCIE_REG_31_MASK;
1838 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1839 CORE_CTRL_ADDRESS, val);
1841 case ATH10K_HW_QCA99X0:
1842 case ATH10K_HW_QCA9984:
1843 case ATH10K_HW_QCA9888:
1844 case ATH10K_HW_QCA4019:
1845 /* TODO: Find appropriate register configuration for QCA99X0
1846 * to unmask irq/MSI.
1849 case ATH10K_HW_WCN3990:
1854 static void ath10k_pci_irq_disable(struct ath10k *ar)
1856 ath10k_ce_disable_interrupts(ar);
1857 ath10k_pci_disable_and_clear_legacy_irq(ar);
1858 ath10k_pci_irq_msi_fw_mask(ar);
1861 static void ath10k_pci_irq_sync(struct ath10k *ar)
1863 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1865 synchronize_irq(ar_pci->pdev->irq);
1868 static void ath10k_pci_irq_enable(struct ath10k *ar)
1870 ath10k_ce_enable_interrupts(ar);
1871 ath10k_pci_enable_legacy_irq(ar);
1872 ath10k_pci_irq_msi_fw_unmask(ar);
1875 static int ath10k_pci_hif_start(struct ath10k *ar)
1877 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1879 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1881 napi_enable(&ar->napi);
1883 ath10k_pci_irq_enable(ar);
1884 ath10k_pci_rx_post(ar);
1886 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1892 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1895 struct ath10k_ce_pipe *ce_pipe;
1896 struct ath10k_ce_ring *ce_ring;
1897 struct sk_buff *skb;
1900 ar = pci_pipe->hif_ce_state;
1901 ce_pipe = pci_pipe->ce_hdl;
1902 ce_ring = ce_pipe->dest_ring;
1907 if (!pci_pipe->buf_sz)
1910 for (i = 0; i < ce_ring->nentries; i++) {
1911 skb = ce_ring->per_transfer_context[i];
1915 ce_ring->per_transfer_context[i] = NULL;
1917 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1918 skb->len + skb_tailroom(skb),
1920 dev_kfree_skb_any(skb);
1924 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1927 struct ath10k_ce_pipe *ce_pipe;
1928 struct ath10k_ce_ring *ce_ring;
1929 struct sk_buff *skb;
1932 ar = pci_pipe->hif_ce_state;
1933 ce_pipe = pci_pipe->ce_hdl;
1934 ce_ring = ce_pipe->src_ring;
1939 if (!pci_pipe->buf_sz)
1942 for (i = 0; i < ce_ring->nentries; i++) {
1943 skb = ce_ring->per_transfer_context[i];
1947 ce_ring->per_transfer_context[i] = NULL;
1949 ath10k_htc_tx_completion_handler(ar, skb);
1954 * Cleanup residual buffers for device shutdown:
1955 * buffers that were enqueued for receive
1956 * buffers that were to be sent
1957 * Note: Buffers that had completed but which were
1958 * not yet processed are on a completion queue. They
1959 * are handled when the completion thread shuts down.
1961 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1963 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1966 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1967 struct ath10k_pci_pipe *pipe_info;
1969 pipe_info = &ar_pci->pipe_info[pipe_num];
1970 ath10k_pci_rx_pipe_cleanup(pipe_info);
1971 ath10k_pci_tx_pipe_cleanup(pipe_info);
1975 void ath10k_pci_ce_deinit(struct ath10k *ar)
1979 for (i = 0; i < CE_COUNT; i++)
1980 ath10k_ce_deinit_pipe(ar, i);
1983 void ath10k_pci_flush(struct ath10k *ar)
1985 ath10k_pci_rx_retry_sync(ar);
1986 ath10k_pci_buffer_cleanup(ar);
1989 static void ath10k_pci_hif_stop(struct ath10k *ar)
1991 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1992 unsigned long flags;
1994 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1996 /* Most likely the device has HTT Rx ring configured. The only way to
1997 * prevent the device from accessing (and possible corrupting) host
1998 * memory is to reset the chip now.
2000 * There's also no known way of masking MSI interrupts on the device.
2001 * For ranged MSI the CE-related interrupts can be masked. However
2002 * regardless how many MSI interrupts are assigned the first one
2003 * is always used for firmware indications (crashes) and cannot be
2004 * masked. To prevent the device from asserting the interrupt reset it
2005 * before proceeding with cleanup.
2007 ath10k_pci_safe_chip_reset(ar);
2009 ath10k_pci_irq_disable(ar);
2010 ath10k_pci_irq_sync(ar);
2011 ath10k_pci_flush(ar);
2012 napi_synchronize(&ar->napi);
2013 napi_disable(&ar->napi);
2015 spin_lock_irqsave(&ar_pci->ps_lock, flags);
2016 WARN_ON(ar_pci->ps_wake_refcount > 0);
2017 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
2020 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
2021 void *req, u32 req_len,
2022 void *resp, u32 *resp_len)
2024 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2025 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
2026 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
2027 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
2028 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
2029 dma_addr_t req_paddr = 0;
2030 dma_addr_t resp_paddr = 0;
2031 struct bmi_xfer xfer = {};
2032 void *treq, *tresp = NULL;
2037 if (resp && !resp_len)
2040 if (resp && resp_len && *resp_len == 0)
2043 treq = kmemdup(req, req_len, GFP_KERNEL);
2047 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
2048 ret = dma_mapping_error(ar->dev, req_paddr);
2054 if (resp && resp_len) {
2055 tresp = kzalloc(*resp_len, GFP_KERNEL);
2061 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
2063 ret = dma_mapping_error(ar->dev, resp_paddr);
2069 xfer.wait_for_resp = true;
2072 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
2075 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
2079 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
2081 dma_addr_t unused_buffer;
2082 unsigned int unused_nbytes;
2083 unsigned int unused_id;
2085 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
2086 &unused_nbytes, &unused_id);
2088 /* non-zero means we did not time out */
2094 dma_addr_t unused_buffer;
2096 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
2097 dma_unmap_single(ar->dev, resp_paddr,
2098 *resp_len, DMA_FROM_DEVICE);
2101 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
2103 if (ret == 0 && resp_len) {
2104 *resp_len = min(*resp_len, xfer.resp_len);
2105 memcpy(resp, tresp, xfer.resp_len);
2114 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
2116 struct bmi_xfer *xfer;
2118 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
2121 xfer->tx_done = true;
2124 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
2126 struct ath10k *ar = ce_state->ar;
2127 struct bmi_xfer *xfer;
2128 unsigned int nbytes;
2130 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
2134 if (WARN_ON_ONCE(!xfer))
2137 if (!xfer->wait_for_resp) {
2138 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
2142 xfer->resp_len = nbytes;
2143 xfer->rx_done = true;
2146 static int ath10k_pci_bmi_wait(struct ath10k *ar,
2147 struct ath10k_ce_pipe *tx_pipe,
2148 struct ath10k_ce_pipe *rx_pipe,
2149 struct bmi_xfer *xfer)
2151 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
2152 unsigned long started = jiffies;
2156 while (time_before_eq(jiffies, timeout)) {
2157 ath10k_pci_bmi_send_done(tx_pipe);
2158 ath10k_pci_bmi_recv_data(rx_pipe);
2160 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
2171 dur = jiffies - started;
2173 ath10k_dbg(ar, ATH10K_DBG_BMI,
2174 "bmi cmd took %lu jiffies hz %d ret %d\n",
2180 * Send an interrupt to the device to wake up the Target CPU
2181 * so it has an opportunity to notice any changed state.
2183 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
2187 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
2188 val = ath10k_pci_read32(ar, addr);
2189 val |= CORE_CTRL_CPU_INTR_MASK;
2190 ath10k_pci_write32(ar, addr, val);
2195 static int ath10k_pci_get_num_banks(struct ath10k *ar)
2197 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2199 switch (ar_pci->pdev->device) {
2200 case QCA988X_2_0_DEVICE_ID_UBNT:
2201 case QCA988X_2_0_DEVICE_ID:
2202 case QCA99X0_2_0_DEVICE_ID:
2203 case QCA9888_2_0_DEVICE_ID:
2204 case QCA9984_1_0_DEVICE_ID:
2205 case QCA9887_1_0_DEVICE_ID:
2207 case QCA6164_2_1_DEVICE_ID:
2208 case QCA6174_2_1_DEVICE_ID:
2209 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
2210 case QCA6174_HW_1_0_CHIP_ID_REV:
2211 case QCA6174_HW_1_1_CHIP_ID_REV:
2212 case QCA6174_HW_2_1_CHIP_ID_REV:
2213 case QCA6174_HW_2_2_CHIP_ID_REV:
2215 case QCA6174_HW_1_3_CHIP_ID_REV:
2217 case QCA6174_HW_3_0_CHIP_ID_REV:
2218 case QCA6174_HW_3_1_CHIP_ID_REV:
2219 case QCA6174_HW_3_2_CHIP_ID_REV:
2223 case QCA9377_1_0_DEVICE_ID:
2227 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2231 static int ath10k_bus_get_num_banks(struct ath10k *ar)
2233 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2235 return ce->bus_ops->get_num_banks(ar);
2238 int ath10k_pci_init_config(struct ath10k *ar)
2240 u32 interconnect_targ_addr;
2241 u32 pcie_state_targ_addr = 0;
2242 u32 pipe_cfg_targ_addr = 0;
2243 u32 svc_to_pipe_map = 0;
2244 u32 pcie_config_flags = 0;
2246 u32 ealloc_targ_addr;
2248 u32 flag2_targ_addr;
2251 /* Download to Target the CE Config and the service-to-CE map */
2252 interconnect_targ_addr =
2253 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2255 /* Supply Target-side CE configuration */
2256 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2257 &pcie_state_targ_addr);
2259 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2263 if (pcie_state_targ_addr == 0) {
2265 ath10k_err(ar, "Invalid pcie state addr\n");
2269 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2270 offsetof(struct pcie_state,
2272 &pipe_cfg_targ_addr);
2274 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2278 if (pipe_cfg_targ_addr == 0) {
2280 ath10k_err(ar, "Invalid pipe cfg addr\n");
2284 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2285 target_ce_config_wlan,
2286 sizeof(struct ce_pipe_config) *
2287 NUM_TARGET_CE_CONFIG_WLAN);
2290 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2294 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2295 offsetof(struct pcie_state,
2299 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2303 if (svc_to_pipe_map == 0) {
2305 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2309 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2310 target_service_to_ce_map_wlan,
2311 sizeof(target_service_to_ce_map_wlan));
2313 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2317 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2318 offsetof(struct pcie_state,
2320 &pcie_config_flags);
2322 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2326 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2328 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2329 offsetof(struct pcie_state,
2333 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2337 /* configure early allocation */
2338 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2340 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2342 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2346 /* first bank is switched to IRAM */
2347 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2348 HI_EARLY_ALLOC_MAGIC_MASK);
2349 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2350 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2351 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2353 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2355 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2359 /* Tell Target to proceed with initialization */
2360 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2362 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2364 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2368 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2370 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2372 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2379 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2381 struct ce_attr *attr;
2382 struct ce_pipe_config *config;
2384 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2385 * since it is currently used for other feature.
2388 /* Override Host's Copy Engine 5 configuration */
2389 attr = &host_ce_config_wlan[5];
2390 attr->src_sz_max = 0;
2391 attr->dest_nentries = 0;
2393 /* Override Target firmware's Copy Engine configuration */
2394 config = &target_ce_config_wlan[5];
2395 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2396 config->nbytes_max = __cpu_to_le32(2048);
2398 /* Map from service/endpoint to Copy Engine */
2399 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2402 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2404 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2405 struct ath10k_pci_pipe *pipe;
2406 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2409 for (i = 0; i < CE_COUNT; i++) {
2410 pipe = &ar_pci->pipe_info[i];
2411 pipe->ce_hdl = &ce->ce_states[i];
2413 pipe->hif_ce_state = ar;
2415 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2417 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2422 /* Last CE is Diagnostic Window */
2423 if (i == CE_DIAG_PIPE) {
2424 ar_pci->ce_diag = pipe->ce_hdl;
2428 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2434 void ath10k_pci_free_pipes(struct ath10k *ar)
2438 for (i = 0; i < CE_COUNT; i++)
2439 ath10k_ce_free_pipe(ar, i);
2442 int ath10k_pci_init_pipes(struct ath10k *ar)
2446 for (i = 0; i < CE_COUNT; i++) {
2447 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2449 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2458 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2460 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2461 FW_IND_EVENT_PENDING;
2464 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2468 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2469 val &= ~FW_IND_EVENT_PENDING;
2470 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2473 static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2477 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2478 return (val == 0xffffffff);
2481 /* this function effectively clears target memory controller assert line */
2482 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2486 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2487 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2488 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2489 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2493 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2494 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2495 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2496 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2501 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2505 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2507 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2508 SOC_RESET_CONTROL_ADDRESS);
2509 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2510 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2513 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2517 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2518 SOC_RESET_CONTROL_ADDRESS);
2520 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2521 val | SOC_RESET_CONTROL_CE_RST_MASK);
2523 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2524 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2527 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2531 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2532 SOC_LF_TIMER_CONTROL0_ADDRESS);
2533 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2534 SOC_LF_TIMER_CONTROL0_ADDRESS,
2535 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2538 static int ath10k_pci_warm_reset(struct ath10k *ar)
2542 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2544 spin_lock_bh(&ar->data_lock);
2545 ar->stats.fw_warm_reset_counter++;
2546 spin_unlock_bh(&ar->data_lock);
2548 ath10k_pci_irq_disable(ar);
2550 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2551 * were to access copy engine while host performs copy engine reset
2552 * then it is possible for the device to confuse pci-e controller to
2553 * the point of bringing host system to a complete stop (i.e. hang).
2555 ath10k_pci_warm_reset_si0(ar);
2556 ath10k_pci_warm_reset_cpu(ar);
2557 ath10k_pci_init_pipes(ar);
2558 ath10k_pci_wait_for_target_init(ar);
2560 ath10k_pci_warm_reset_clear_lf(ar);
2561 ath10k_pci_warm_reset_ce(ar);
2562 ath10k_pci_warm_reset_cpu(ar);
2563 ath10k_pci_init_pipes(ar);
2565 ret = ath10k_pci_wait_for_target_init(ar);
2567 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2571 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2576 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2578 ath10k_pci_irq_disable(ar);
2579 return ath10k_pci_qca99x0_chip_reset(ar);
2582 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2584 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2586 if (!ar_pci->pci_soft_reset)
2589 return ar_pci->pci_soft_reset(ar);
2592 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2597 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2599 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2600 * It is thus preferred to use warm reset which is safer but may not be
2601 * able to recover the device from all possible fail scenarios.
2603 * Warm reset doesn't always work on first try so attempt it a few
2604 * times before giving up.
2606 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2607 ret = ath10k_pci_warm_reset(ar);
2609 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2610 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2615 /* FIXME: Sometimes copy engine doesn't recover after warm
2616 * reset. In most cases this needs cold reset. In some of these
2617 * cases the device is in such a state that a cold reset may
2620 * Reading any host interest register via copy engine is
2621 * sufficient to verify if device is capable of booting
2624 ret = ath10k_pci_init_pipes(ar);
2626 ath10k_warn(ar, "failed to init copy engine: %d\n",
2631 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2634 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2639 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2643 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2644 ath10k_warn(ar, "refusing cold reset as requested\n");
2648 ret = ath10k_pci_cold_reset(ar);
2650 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2654 ret = ath10k_pci_wait_for_target_init(ar);
2656 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2661 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2666 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2670 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2672 /* FIXME: QCA6174 requires cold + warm reset to work. */
2674 ret = ath10k_pci_cold_reset(ar);
2676 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2680 ret = ath10k_pci_wait_for_target_init(ar);
2682 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2687 ret = ath10k_pci_warm_reset(ar);
2689 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2693 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2698 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2702 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2704 ret = ath10k_pci_cold_reset(ar);
2706 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2710 ret = ath10k_pci_wait_for_target_init(ar);
2712 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2717 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2722 static int ath10k_pci_chip_reset(struct ath10k *ar)
2724 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2726 if (WARN_ON(!ar_pci->pci_hard_reset))
2729 return ar_pci->pci_hard_reset(ar);
2732 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2734 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2737 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2739 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2741 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2742 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2745 * Bring the target up cleanly.
2747 * The target may be in an undefined state with an AUX-powered Target
2748 * and a Host in WoW mode. If the Host crashes, loses power, or is
2749 * restarted (without unloading the driver) then the Target is left
2750 * (aux) powered and running. On a subsequent driver load, the Target
2751 * is in an unexpected state. We try to catch that here in order to
2752 * reset the Target and retry the probe.
2754 ret = ath10k_pci_chip_reset(ar);
2756 if (ath10k_pci_has_fw_crashed(ar)) {
2757 ath10k_warn(ar, "firmware crashed during chip reset\n");
2758 ath10k_pci_fw_crashed_clear(ar);
2759 ath10k_pci_fw_crashed_dump(ar);
2762 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2766 ret = ath10k_pci_init_pipes(ar);
2768 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2772 ret = ath10k_pci_init_config(ar);
2774 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2778 ret = ath10k_pci_wake_target_cpu(ar);
2780 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2787 ath10k_pci_ce_deinit(ar);
2793 void ath10k_pci_hif_power_down(struct ath10k *ar)
2795 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2797 /* Currently hif_power_up performs effectively a reset and hif_stop
2798 * resets the chip as well so there's no point in resetting here.
2802 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2804 /* Nothing to do; the important stuff is in the driver suspend. */
2808 static int ath10k_pci_suspend(struct ath10k *ar)
2810 /* The grace timer can still be counting down and ar->ps_awake be true.
2811 * It is known that the device may be asleep after resuming regardless
2812 * of the SoC powersave state before suspending. Hence make sure the
2813 * device is asleep before proceeding.
2815 ath10k_pci_sleep_sync(ar);
2820 static int ath10k_pci_hif_resume(struct ath10k *ar)
2822 /* Nothing to do; the important stuff is in the driver resume. */
2826 static int ath10k_pci_resume(struct ath10k *ar)
2828 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2829 struct pci_dev *pdev = ar_pci->pdev;
2833 ret = ath10k_pci_force_wake(ar);
2835 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2839 /* Suspend/Resume resets the PCI configuration space, so we have to
2840 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2841 * from interfering with C3 CPU state. pci_restore_state won't help
2842 * here since it only restores the first 64 bytes pci config header.
2844 pci_read_config_dword(pdev, 0x40, &val);
2845 if ((val & 0x0000ff00) != 0)
2846 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2851 static bool ath10k_pci_validate_cal(void *data, size_t size)
2853 __le16 *cal_words = data;
2860 for (i = 0; i < size / 2; i++)
2861 checksum ^= le16_to_cpu(cal_words[i]);
2863 return checksum == 0xffff;
2866 static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2868 /* Enable SI clock */
2869 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2871 /* Configure GPIOs for I2C operation */
2872 ath10k_pci_write32(ar,
2873 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2874 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2875 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2877 SM(1, GPIO_PIN0_PAD_PULL));
2879 ath10k_pci_write32(ar,
2880 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2881 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2882 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2883 SM(1, GPIO_PIN0_PAD_PULL));
2885 ath10k_pci_write32(ar,
2887 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2888 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2890 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2891 ath10k_pci_write32(ar,
2892 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2893 SM(1, SI_CONFIG_ERR_INT) |
2894 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2895 SM(1, SI_CONFIG_I2C) |
2896 SM(1, SI_CONFIG_POS_SAMPLE) |
2897 SM(1, SI_CONFIG_INACTIVE_DATA) |
2898 SM(1, SI_CONFIG_INACTIVE_CLK) |
2899 SM(8, SI_CONFIG_DIVIDER));
2902 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2907 /* set device select byte and for the read operation */
2908 reg = QCA9887_EEPROM_SELECT_READ |
2909 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2910 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2911 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2913 /* write transmit data, transfer length, and START bit */
2914 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2915 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2916 SM(4, SI_CS_TX_CNT));
2918 /* wait max 1 sec */
2919 wait_limit = 100000;
2921 /* wait for SI_CS_DONE_INT */
2923 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
2924 if (MS(reg, SI_CS_DONE_INT))
2929 } while (wait_limit > 0);
2931 if (!MS(reg, SI_CS_DONE_INT)) {
2932 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
2937 /* clear SI_CS_DONE_INT */
2938 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
2940 if (MS(reg, SI_CS_DONE_ERR)) {
2941 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
2945 /* extract receive data */
2946 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
2952 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
2959 if (!QCA_REV_9887(ar))
2962 calsize = ar->hw_params.cal_data_len;
2963 caldata = kmalloc(calsize, GFP_KERNEL);
2967 ath10k_pci_enable_eeprom(ar);
2969 for (i = 0; i < calsize; i++) {
2970 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
2975 if (!ath10k_pci_validate_cal(caldata, calsize))
2979 *data_len = calsize;
2989 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2990 .tx_sg = ath10k_pci_hif_tx_sg,
2991 .diag_read = ath10k_pci_hif_diag_read,
2992 .diag_write = ath10k_pci_diag_write_mem,
2993 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2994 .start = ath10k_pci_hif_start,
2995 .stop = ath10k_pci_hif_stop,
2996 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2997 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2998 .send_complete_check = ath10k_pci_hif_send_complete_check,
2999 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
3000 .power_up = ath10k_pci_hif_power_up,
3001 .power_down = ath10k_pci_hif_power_down,
3002 .read32 = ath10k_pci_read32,
3003 .write32 = ath10k_pci_write32,
3004 .suspend = ath10k_pci_hif_suspend,
3005 .resume = ath10k_pci_hif_resume,
3006 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
3010 * Top-level interrupt handler for all PCI interrupts from a Target.
3011 * When a block of MSI interrupts is allocated, this top-level handler
3012 * is not used; instead, we directly call the correct sub-handler.
3014 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
3016 struct ath10k *ar = arg;
3017 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3020 if (ath10k_pci_has_device_gone(ar))
3023 ret = ath10k_pci_force_wake(ar);
3025 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
3029 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
3030 !ath10k_pci_irq_pending(ar))
3033 ath10k_pci_disable_and_clear_legacy_irq(ar);
3034 ath10k_pci_irq_msi_fw_mask(ar);
3035 napi_schedule(&ar->napi);
3040 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
3042 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
3045 if (ath10k_pci_has_fw_crashed(ar)) {
3046 ath10k_pci_fw_crashed_clear(ar);
3047 ath10k_pci_fw_crashed_dump(ar);
3052 ath10k_ce_per_engine_service_any(ar);
3054 done = ath10k_htt_txrx_compl_task(ar, budget);
3056 if (done < budget) {
3057 napi_complete_done(ctx, done);
3058 /* In case of MSI, it is possible that interrupts are received
3059 * while NAPI poll is inprogress. So pending interrupts that are
3060 * received after processing all copy engine pipes by NAPI poll
3061 * will not be handled again. This is causing failure to
3062 * complete boot sequence in x86 platform. So before enabling
3063 * interrupts safer to check for pending interrupts for
3064 * immediate servicing.
3066 if (ath10k_ce_interrupt_summary(ar)) {
3067 napi_reschedule(ctx);
3070 ath10k_pci_enable_legacy_irq(ar);
3071 ath10k_pci_irq_msi_fw_unmask(ar);
3078 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
3080 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3083 ret = request_irq(ar_pci->pdev->irq,
3084 ath10k_pci_interrupt_handler,
3085 IRQF_SHARED, "ath10k_pci", ar);
3087 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
3088 ar_pci->pdev->irq, ret);
3095 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
3097 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3100 ret = request_irq(ar_pci->pdev->irq,
3101 ath10k_pci_interrupt_handler,
3102 IRQF_SHARED, "ath10k_pci", ar);
3104 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
3105 ar_pci->pdev->irq, ret);
3112 static int ath10k_pci_request_irq(struct ath10k *ar)
3114 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3116 switch (ar_pci->oper_irq_mode) {
3117 case ATH10K_PCI_IRQ_LEGACY:
3118 return ath10k_pci_request_irq_legacy(ar);
3119 case ATH10K_PCI_IRQ_MSI:
3120 return ath10k_pci_request_irq_msi(ar);
3126 static void ath10k_pci_free_irq(struct ath10k *ar)
3128 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3130 free_irq(ar_pci->pdev->irq, ar);
3133 void ath10k_pci_init_napi(struct ath10k *ar)
3135 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
3136 ATH10K_NAPI_BUDGET);
3139 static int ath10k_pci_init_irq(struct ath10k *ar)
3141 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3144 ath10k_pci_init_napi(ar);
3146 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
3147 ath10k_info(ar, "limiting irq mode to: %d\n",
3148 ath10k_pci_irq_mode);
3151 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
3152 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
3153 ret = pci_enable_msi(ar_pci->pdev);
3162 * A potential race occurs here: The CORE_BASE write
3163 * depends on target correctly decoding AXI address but
3164 * host won't know when target writes BAR to CORE_CTRL.
3165 * This write might get lost if target has NOT written BAR.
3166 * For now, fix the race by repeating the write in below
3167 * synchronization checking.
3169 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
3171 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3172 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
3177 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
3179 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3183 static int ath10k_pci_deinit_irq(struct ath10k *ar)
3185 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3187 switch (ar_pci->oper_irq_mode) {
3188 case ATH10K_PCI_IRQ_LEGACY:
3189 ath10k_pci_deinit_irq_legacy(ar);
3192 pci_disable_msi(ar_pci->pdev);
3199 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
3201 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3202 unsigned long timeout;
3205 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
3207 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
3210 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3212 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
3215 /* target should never return this */
3216 if (val == 0xffffffff)
3219 /* the device has crashed so don't bother trying anymore */
3220 if (val & FW_IND_EVENT_PENDING)
3223 if (val & FW_IND_INITIALIZED)
3226 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
3227 /* Fix potential race by repeating CORE_BASE writes */
3228 ath10k_pci_enable_legacy_irq(ar);
3231 } while (time_before(jiffies, timeout));
3233 ath10k_pci_disable_and_clear_legacy_irq(ar);
3234 ath10k_pci_irq_msi_fw_mask(ar);
3236 if (val == 0xffffffff) {
3237 ath10k_err(ar, "failed to read device register, device is gone\n");
3241 if (val & FW_IND_EVENT_PENDING) {
3242 ath10k_warn(ar, "device has crashed during init\n");
3246 if (!(val & FW_IND_INITIALIZED)) {
3247 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3252 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3256 static int ath10k_pci_cold_reset(struct ath10k *ar)
3260 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3262 spin_lock_bh(&ar->data_lock);
3264 ar->stats.fw_cold_reset_counter++;
3266 spin_unlock_bh(&ar->data_lock);
3268 /* Put Target, including PCIe, into RESET. */
3269 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3271 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3273 /* After writing into SOC_GLOBAL_RESET to put device into
3274 * reset and pulling out of reset pcie may not be stable
3275 * for any immediate pcie register access and cause bus error,
3276 * add delay before any pcie access request to fix this issue.
3280 /* Pull Target, including PCIe, out of RESET. */
3282 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3286 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3291 static int ath10k_pci_claim(struct ath10k *ar)
3293 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3294 struct pci_dev *pdev = ar_pci->pdev;
3297 pci_set_drvdata(pdev, ar);
3299 ret = pci_enable_device(pdev);
3301 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3305 ret = pci_request_region(pdev, BAR_NUM, "ath");
3307 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3312 /* Target expects 32 bit DMA. Enforce it. */
3313 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3315 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3319 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3321 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3326 pci_set_master(pdev);
3328 /* Arrange for access to Target SoC registers. */
3329 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3330 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3332 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3337 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3341 pci_clear_master(pdev);
3344 pci_release_region(pdev, BAR_NUM);
3347 pci_disable_device(pdev);
3352 static void ath10k_pci_release(struct ath10k *ar)
3354 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3355 struct pci_dev *pdev = ar_pci->pdev;
3357 pci_iounmap(pdev, ar_pci->mem);
3358 pci_release_region(pdev, BAR_NUM);
3359 pci_clear_master(pdev);
3360 pci_disable_device(pdev);
3363 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3365 const struct ath10k_pci_supp_chip *supp_chip;
3367 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3369 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3370 supp_chip = &ath10k_pci_supp_chips[i];
3372 if (supp_chip->dev_id == dev_id &&
3373 supp_chip->rev_id == rev_id)
3380 int ath10k_pci_setup_resource(struct ath10k *ar)
3382 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3383 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3386 spin_lock_init(&ce->ce_lock);
3387 spin_lock_init(&ar_pci->ps_lock);
3389 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3391 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3392 ath10k_pci_override_ce_config(ar);
3394 ret = ath10k_pci_alloc_pipes(ar);
3396 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3404 void ath10k_pci_release_resource(struct ath10k *ar)
3406 ath10k_pci_rx_retry_sync(ar);
3407 netif_napi_del(&ar->napi);
3408 ath10k_pci_ce_deinit(ar);
3409 ath10k_pci_free_pipes(ar);
3412 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3413 .read32 = ath10k_bus_pci_read32,
3414 .write32 = ath10k_bus_pci_write32,
3415 .get_num_banks = ath10k_pci_get_num_banks,
3418 static int ath10k_pci_probe(struct pci_dev *pdev,
3419 const struct pci_device_id *pci_dev)
3423 struct ath10k_pci *ar_pci;
3424 enum ath10k_hw_rev hw_rev;
3427 int (*pci_soft_reset)(struct ath10k *ar);
3428 int (*pci_hard_reset)(struct ath10k *ar);
3429 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3431 switch (pci_dev->device) {
3432 case QCA988X_2_0_DEVICE_ID_UBNT:
3433 case QCA988X_2_0_DEVICE_ID:
3434 hw_rev = ATH10K_HW_QCA988X;
3436 pci_soft_reset = ath10k_pci_warm_reset;
3437 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3438 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3440 case QCA9887_1_0_DEVICE_ID:
3441 hw_rev = ATH10K_HW_QCA9887;
3443 pci_soft_reset = ath10k_pci_warm_reset;
3444 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3445 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3447 case QCA6164_2_1_DEVICE_ID:
3448 case QCA6174_2_1_DEVICE_ID:
3449 hw_rev = ATH10K_HW_QCA6174;
3451 pci_soft_reset = ath10k_pci_warm_reset;
3452 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3453 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3455 case QCA99X0_2_0_DEVICE_ID:
3456 hw_rev = ATH10K_HW_QCA99X0;
3458 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3459 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3460 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3462 case QCA9984_1_0_DEVICE_ID:
3463 hw_rev = ATH10K_HW_QCA9984;
3465 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3466 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3467 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3469 case QCA9888_2_0_DEVICE_ID:
3470 hw_rev = ATH10K_HW_QCA9888;
3472 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3473 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3474 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3476 case QCA9377_1_0_DEVICE_ID:
3477 hw_rev = ATH10K_HW_QCA9377;
3479 pci_soft_reset = NULL;
3480 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3481 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3488 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3489 hw_rev, &ath10k_pci_hif_ops);
3491 dev_err(&pdev->dev, "failed to allocate core\n");
3495 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3496 pdev->vendor, pdev->device,
3497 pdev->subsystem_vendor, pdev->subsystem_device);
3499 ar_pci = ath10k_pci_priv(ar);
3500 ar_pci->pdev = pdev;
3501 ar_pci->dev = &pdev->dev;
3503 ar->dev_id = pci_dev->device;
3504 ar_pci->pci_ps = pci_ps;
3505 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3506 ar_pci->pci_soft_reset = pci_soft_reset;
3507 ar_pci->pci_hard_reset = pci_hard_reset;
3508 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3509 ar->ce_priv = &ar_pci->ce;
3511 ar->id.vendor = pdev->vendor;
3512 ar->id.device = pdev->device;
3513 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3514 ar->id.subsystem_device = pdev->subsystem_device;
3516 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0);
3518 ret = ath10k_pci_setup_resource(ar);
3520 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3521 goto err_core_destroy;
3524 ret = ath10k_pci_claim(ar);
3526 ath10k_err(ar, "failed to claim device: %d\n", ret);
3527 goto err_free_pipes;
3530 ret = ath10k_pci_force_wake(ar);
3532 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3536 ath10k_pci_ce_deinit(ar);
3537 ath10k_pci_irq_disable(ar);
3539 ret = ath10k_pci_init_irq(ar);
3541 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3545 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3546 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3547 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3549 ret = ath10k_pci_request_irq(ar);
3551 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3552 goto err_deinit_irq;
3555 ret = ath10k_pci_chip_reset(ar);
3557 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3561 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3562 if (chip_id == 0xffffffff) {
3563 ath10k_err(ar, "failed to get chip id\n");
3567 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3568 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3569 pdev->device, chip_id);
3573 ret = ath10k_core_register(ar, chip_id);
3575 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3582 ath10k_pci_free_irq(ar);
3583 ath10k_pci_rx_retry_sync(ar);
3586 ath10k_pci_deinit_irq(ar);
3589 ath10k_pci_sleep_sync(ar);
3590 ath10k_pci_release(ar);
3593 ath10k_pci_free_pipes(ar);
3596 ath10k_core_destroy(ar);
3601 static void ath10k_pci_remove(struct pci_dev *pdev)
3603 struct ath10k *ar = pci_get_drvdata(pdev);
3604 struct ath10k_pci *ar_pci;
3606 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3611 ar_pci = ath10k_pci_priv(ar);
3616 ath10k_core_unregister(ar);
3617 ath10k_pci_free_irq(ar);
3618 ath10k_pci_deinit_irq(ar);
3619 ath10k_pci_release_resource(ar);
3620 ath10k_pci_sleep_sync(ar);
3621 ath10k_pci_release(ar);
3622 ath10k_core_destroy(ar);
3625 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3627 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3629 struct ath10k *ar = dev_get_drvdata(dev);
3632 ret = ath10k_pci_suspend(ar);
3634 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3639 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3641 struct ath10k *ar = dev_get_drvdata(dev);
3644 ret = ath10k_pci_resume(ar);
3646 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3651 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3652 ath10k_pci_pm_suspend,
3653 ath10k_pci_pm_resume);
3655 static struct pci_driver ath10k_pci_driver = {
3656 .name = "ath10k_pci",
3657 .id_table = ath10k_pci_id_table,
3658 .probe = ath10k_pci_probe,
3659 .remove = ath10k_pci_remove,
3661 .driver.pm = &ath10k_pci_pm_ops,
3665 static int __init ath10k_pci_init(void)
3669 ret = pci_register_driver(&ath10k_pci_driver);
3671 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3674 ret = ath10k_ahb_init();
3676 printk(KERN_ERR "ahb init failed: %d\n", ret);
3680 module_init(ath10k_pci_init);
3682 static void __exit ath10k_pci_exit(void)
3684 pci_unregister_driver(&ath10k_pci_driver);
3688 module_exit(ath10k_pci_exit);
3690 MODULE_AUTHOR("Qualcomm Atheros");
3691 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3692 MODULE_LICENSE("Dual BSD/GPL");
3694 /* QCA988x 2.0 firmware files */
3695 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3696 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3697 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3698 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3699 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3700 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3702 /* QCA9887 1.0 firmware files */
3703 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3704 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
3705 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3707 /* QCA6174 2.1 firmware files */
3708 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3709 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3710 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3711 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3713 /* QCA6174 3.1 firmware files */
3714 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3715 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3716 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3717 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3718 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3720 /* QCA9377 1.0 firmware files */
3721 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3722 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);