2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
42 enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
47 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
48 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
50 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
53 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
56 /* how long wait to wait for target to initialise, in ms */
57 #define ATH10K_PCI_TARGET_WAIT 3000
58 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
60 #define QCA988X_2_0_DEVICE_ID (0x003c)
62 static const struct pci_device_id ath10k_pci_id_table[] = {
63 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
67 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
68 static int ath10k_pci_cold_reset(struct ath10k *ar);
69 static int ath10k_pci_warm_reset(struct ath10k *ar);
70 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
71 static int ath10k_pci_init_irq(struct ath10k *ar);
72 static int ath10k_pci_deinit_irq(struct ath10k *ar);
73 static int ath10k_pci_request_irq(struct ath10k *ar);
74 static void ath10k_pci_free_irq(struct ath10k *ar);
75 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
76 struct ath10k_ce_pipe *rx_pipe,
77 struct bmi_xfer *xfer);
79 static const struct ce_attr host_ce_config_wlan[] = {
80 /* CE0: host->target HTC control and raw streams */
82 .flags = CE_ATTR_FLAGS,
88 /* CE1: target->host HTT + HTC control */
90 .flags = CE_ATTR_FLAGS,
96 /* CE2: target->host WMI */
98 .flags = CE_ATTR_FLAGS,
104 /* CE3: host->target WMI */
106 .flags = CE_ATTR_FLAGS,
112 /* CE4: host->target HTT */
114 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
115 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
122 .flags = CE_ATTR_FLAGS,
128 /* CE6: target autonomous hif_memcpy */
130 .flags = CE_ATTR_FLAGS,
136 /* CE7: ce_diag, the Diagnostic Window */
138 .flags = CE_ATTR_FLAGS,
140 .src_sz_max = DIAG_TRANSFER_LIMIT,
145 /* Target firmware's Copy Engine configuration. */
146 static const struct ce_pipe_config target_ce_config_wlan[] = {
147 /* CE0: host->target HTC control and raw streams */
149 .pipenum = __cpu_to_le32(0),
150 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
151 .nentries = __cpu_to_le32(32),
152 .nbytes_max = __cpu_to_le32(256),
153 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
154 .reserved = __cpu_to_le32(0),
157 /* CE1: target->host HTT + HTC control */
159 .pipenum = __cpu_to_le32(1),
160 .pipedir = __cpu_to_le32(PIPEDIR_IN),
161 .nentries = __cpu_to_le32(32),
162 .nbytes_max = __cpu_to_le32(512),
163 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
164 .reserved = __cpu_to_le32(0),
167 /* CE2: target->host WMI */
169 .pipenum = __cpu_to_le32(2),
170 .pipedir = __cpu_to_le32(PIPEDIR_IN),
171 .nentries = __cpu_to_le32(32),
172 .nbytes_max = __cpu_to_le32(2048),
173 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
174 .reserved = __cpu_to_le32(0),
177 /* CE3: host->target WMI */
179 .pipenum = __cpu_to_le32(3),
180 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
181 .nentries = __cpu_to_le32(32),
182 .nbytes_max = __cpu_to_le32(2048),
183 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
184 .reserved = __cpu_to_le32(0),
187 /* CE4: host->target HTT */
189 .pipenum = __cpu_to_le32(4),
190 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
191 .nentries = __cpu_to_le32(256),
192 .nbytes_max = __cpu_to_le32(256),
193 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
194 .reserved = __cpu_to_le32(0),
197 /* NB: 50% of src nentries, since tx has 2 frags */
201 .pipenum = __cpu_to_le32(5),
202 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
203 .nentries = __cpu_to_le32(32),
204 .nbytes_max = __cpu_to_le32(2048),
205 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
206 .reserved = __cpu_to_le32(0),
209 /* CE6: Reserved for target autonomous hif_memcpy */
211 .pipenum = __cpu_to_le32(6),
212 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
213 .nentries = __cpu_to_le32(32),
214 .nbytes_max = __cpu_to_le32(4096),
215 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
216 .reserved = __cpu_to_le32(0),
219 /* CE7 used only by Host */
223 * Map from service/endpoint to Copy Engine.
224 * This table is derived from the CE_PCI TABLE, above.
225 * It is passed to the Target at startup for use by firmware.
227 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
229 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
230 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
234 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
235 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
239 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
240 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
244 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
245 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
249 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
250 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
254 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
255 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
259 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
260 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
264 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
265 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
269 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
270 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
274 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
275 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
279 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
280 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
284 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
285 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
289 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
290 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
294 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
295 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
299 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
300 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
304 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
305 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
309 /* (Additions here) */
318 static bool ath10k_pci_irq_pending(struct ath10k *ar)
322 /* Check if the shared legacy irq is for us */
323 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
324 PCIE_INTR_CAUSE_ADDRESS);
325 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
331 static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
333 /* IMPORTANT: INTR_CLR register has to be set after
334 * INTR_ENABLE is set to 0, otherwise interrupt can not be
336 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
338 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
339 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
341 /* IMPORTANT: this extra read transaction is required to
342 * flush the posted write buffer. */
343 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
344 PCIE_INTR_ENABLE_ADDRESS);
347 static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
349 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
350 PCIE_INTR_ENABLE_ADDRESS,
351 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
353 /* IMPORTANT: this extra read transaction is required to
354 * flush the posted write buffer. */
355 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
356 PCIE_INTR_ENABLE_ADDRESS);
359 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
361 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
363 if (ar_pci->num_msi_intrs > 1)
366 if (ar_pci->num_msi_intrs == 1)
372 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
374 struct ath10k *ar = pipe->hif_ce_state;
375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
376 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
381 lockdep_assert_held(&ar_pci->ce_lock);
383 skb = dev_alloc_skb(pipe->buf_sz);
387 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
389 paddr = dma_map_single(ar->dev, skb->data,
390 skb->len + skb_tailroom(skb),
392 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
393 ath10k_warn(ar, "failed to dma map pci rx buf\n");
394 dev_kfree_skb_any(skb);
398 ATH10K_SKB_CB(skb)->paddr = paddr;
400 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
402 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
403 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
405 dev_kfree_skb_any(skb);
412 static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
414 struct ath10k *ar = pipe->hif_ce_state;
415 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
416 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
419 lockdep_assert_held(&ar_pci->ce_lock);
421 if (pipe->buf_sz == 0)
424 if (!ce_pipe->dest_ring)
427 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
429 ret = __ath10k_pci_rx_post_buf(pipe);
431 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
432 mod_timer(&ar_pci->rx_post_retry, jiffies +
433 ATH10K_PCI_RX_POST_RETRY_MS);
439 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
441 struct ath10k *ar = pipe->hif_ce_state;
442 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
444 spin_lock_bh(&ar_pci->ce_lock);
445 __ath10k_pci_rx_post_pipe(pipe);
446 spin_unlock_bh(&ar_pci->ce_lock);
449 static void ath10k_pci_rx_post(struct ath10k *ar)
451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
454 spin_lock_bh(&ar_pci->ce_lock);
455 for (i = 0; i < CE_COUNT; i++)
456 __ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
457 spin_unlock_bh(&ar_pci->ce_lock);
460 static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
462 struct ath10k *ar = (void *)ptr;
464 ath10k_pci_rx_post(ar);
468 * Diagnostic read/write access is provided for startup/config/debug usage.
469 * Caller must guarantee proper alignment, when applicable, and single user
472 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
475 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
478 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
481 struct ath10k_ce_pipe *ce_diag;
482 /* Host buffer address in CE space */
484 dma_addr_t ce_data_base = 0;
485 void *data_buf = NULL;
488 ce_diag = ar_pci->ce_diag;
491 * Allocate a temporary bounce buffer to hold caller's data
492 * to be DMA'ed from Target. This guarantees
493 * 1) 4-byte alignment
494 * 2) Buffer in DMA-able space
496 orig_nbytes = nbytes;
497 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
506 memset(data_buf, 0, orig_nbytes);
508 remaining_bytes = orig_nbytes;
509 ce_data = ce_data_base;
510 while (remaining_bytes) {
511 nbytes = min_t(unsigned int, remaining_bytes,
512 DIAG_TRANSFER_LIMIT);
514 ret = ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
518 /* Request CE to send from Target(!) address to Host buffer */
520 * The address supplied by the caller is in the
521 * Target CPU virtual address space.
523 * In order to use this address with the diagnostic CE,
524 * convert it from Target CPU virtual address space
525 * to CE address space
527 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
530 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
536 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
540 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
546 if (nbytes != completed_nbytes) {
551 if (buf != (u32)address) {
557 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
562 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
568 if (nbytes != completed_nbytes) {
573 if (buf != ce_data) {
578 remaining_bytes -= nbytes;
585 memcpy(data, data_buf, orig_nbytes);
587 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
591 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
597 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
602 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
603 *value = __le32_to_cpu(val);
608 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
614 host_addr = host_interest_item_address(src);
616 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
618 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
623 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
625 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
633 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
634 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
636 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
637 const void *data, int nbytes)
639 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
642 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
645 struct ath10k_ce_pipe *ce_diag;
646 void *data_buf = NULL;
647 u32 ce_data; /* Host buffer address in CE space */
648 dma_addr_t ce_data_base = 0;
651 ce_diag = ar_pci->ce_diag;
654 * Allocate a temporary bounce buffer to hold caller's data
655 * to be DMA'ed to Target. This guarantees
656 * 1) 4-byte alignment
657 * 2) Buffer in DMA-able space
659 orig_nbytes = nbytes;
660 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
669 /* Copy caller's data to allocated DMA buf */
670 memcpy(data_buf, data, orig_nbytes);
673 * The address supplied by the caller is in the
674 * Target CPU virtual address space.
676 * In order to use this address with the diagnostic CE,
678 * Target CPU virtual address space
682 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
684 remaining_bytes = orig_nbytes;
685 ce_data = ce_data_base;
686 while (remaining_bytes) {
687 /* FIXME: check cast */
688 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
690 /* Set up to receive directly into Target(!) address */
691 ret = ath10k_ce_rx_post_buf(ce_diag, NULL, address);
696 * Request CE to send caller-supplied data that
697 * was copied to bounce buffer to Target(!) address.
699 ret = ath10k_ce_send(ce_diag, NULL, (u32)ce_data,
705 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
710 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
716 if (nbytes != completed_nbytes) {
721 if (buf != ce_data) {
727 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
732 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
738 if (nbytes != completed_nbytes) {
743 if (buf != address) {
748 remaining_bytes -= nbytes;
755 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
760 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
766 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
768 __le32 val = __cpu_to_le32(value);
770 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
773 static bool ath10k_pci_is_awake(struct ath10k *ar)
775 u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS);
777 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
780 static int ath10k_pci_wake_wait(struct ath10k *ar)
785 while (tot_delay < PCIE_WAKE_TIMEOUT) {
786 if (ath10k_pci_is_awake(ar))
790 tot_delay += curr_delay;
799 static int ath10k_pci_wake(struct ath10k *ar)
801 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
802 PCIE_SOC_WAKE_V_MASK);
803 return ath10k_pci_wake_wait(ar);
806 static void ath10k_pci_sleep(struct ath10k *ar)
808 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
809 PCIE_SOC_WAKE_RESET);
812 /* Called by lower (CE) layer when a send to Target completes. */
813 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
815 struct ath10k *ar = ce_state->ar;
816 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
817 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
818 void *transfer_context;
821 unsigned int transfer_id;
823 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
825 &transfer_id) == 0) {
826 /* no need to call tx completion for NULL pointers */
827 if (transfer_context == NULL)
830 cb->tx_completion(ar, transfer_context, transfer_id);
834 /* Called by lower (CE) layer when data is received from the Target. */
835 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
837 struct ath10k *ar = ce_state->ar;
838 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
839 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
840 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
842 void *transfer_context;
844 unsigned int nbytes, max_nbytes;
845 unsigned int transfer_id;
848 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
849 &ce_data, &nbytes, &transfer_id,
851 skb = transfer_context;
852 max_nbytes = skb->len + skb_tailroom(skb);
853 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
854 max_nbytes, DMA_FROM_DEVICE);
856 if (unlikely(max_nbytes < nbytes)) {
857 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
859 dev_kfree_skb_any(skb);
863 skb_put(skb, nbytes);
864 cb->rx_completion(ar, skb, pipe_info->pipe_num);
867 ath10k_pci_rx_post_pipe(pipe_info);
870 static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
871 struct ath10k_hif_sg_item *items, int n_items)
873 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
874 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
875 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
876 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
877 unsigned int nentries_mask;
878 unsigned int sw_index;
879 unsigned int write_index;
882 spin_lock_bh(&ar_pci->ce_lock);
884 nentries_mask = src_ring->nentries_mask;
885 sw_index = src_ring->sw_index;
886 write_index = src_ring->write_index;
888 if (unlikely(CE_RING_DELTA(nentries_mask,
889 write_index, sw_index - 1) < n_items)) {
894 for (i = 0; i < n_items - 1; i++) {
895 ath10k_dbg(ar, ATH10K_DBG_PCI,
896 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
897 i, items[i].paddr, items[i].len, n_items);
898 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
899 items[i].vaddr, items[i].len);
901 err = ath10k_ce_send_nolock(ce_pipe,
902 items[i].transfer_context,
905 items[i].transfer_id,
906 CE_SEND_FLAG_GATHER);
911 /* `i` is equal to `n_items -1` after for() */
913 ath10k_dbg(ar, ATH10K_DBG_PCI,
914 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
915 i, items[i].paddr, items[i].len, n_items);
916 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
917 items[i].vaddr, items[i].len);
919 err = ath10k_ce_send_nolock(ce_pipe,
920 items[i].transfer_context,
923 items[i].transfer_id,
928 spin_unlock_bh(&ar_pci->ce_lock);
933 __ath10k_ce_send_revert(ce_pipe);
935 spin_unlock_bh(&ar_pci->ce_lock);
939 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
941 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
943 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
945 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
948 static void ath10k_pci_dump_registers(struct ath10k *ar,
949 struct ath10k_fw_crash_data *crash_data)
951 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
954 lockdep_assert_held(&ar->data_lock);
956 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
958 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
960 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
964 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
966 ath10k_err(ar, "firmware register dump:\n");
967 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
968 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
970 __le32_to_cpu(reg_dump_values[i]),
971 __le32_to_cpu(reg_dump_values[i + 1]),
972 __le32_to_cpu(reg_dump_values[i + 2]),
973 __le32_to_cpu(reg_dump_values[i + 3]));
978 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
979 crash_data->registers[i] = reg_dump_values[i];
982 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
984 struct ath10k_fw_crash_data *crash_data;
987 spin_lock_bh(&ar->data_lock);
989 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
992 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
994 scnprintf(uuid, sizeof(uuid), "n/a");
996 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
997 ath10k_print_driver_info(ar);
998 ath10k_pci_dump_registers(ar, crash_data);
1000 spin_unlock_bh(&ar->data_lock);
1002 queue_work(ar->workqueue, &ar->restart_work);
1005 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1008 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1013 * Decide whether to actually poll for completions, or just
1014 * wait for a later chance.
1015 * If there seem to be plenty of resources left, then just wait
1016 * since checking involves reading a CE register, which is a
1017 * relatively expensive operation.
1019 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1022 * If at least 50% of the total resources are still available,
1023 * don't bother checking again yet.
1025 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1028 ath10k_ce_per_engine_service(ar, pipe);
1031 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
1032 struct ath10k_hif_cb *callbacks)
1034 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1036 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n");
1038 memcpy(&ar_pci->msg_callbacks_current, callbacks,
1039 sizeof(ar_pci->msg_callbacks_current));
1042 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
1044 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1047 tasklet_kill(&ar_pci->intr_tq);
1048 tasklet_kill(&ar_pci->msi_fw_err);
1050 for (i = 0; i < CE_COUNT; i++)
1051 tasklet_kill(&ar_pci->pipe_info[i].intr);
1053 del_timer_sync(&ar_pci->rx_post_retry);
1056 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1057 u16 service_id, u8 *ul_pipe,
1058 u8 *dl_pipe, int *ul_is_polled,
1061 const struct service_to_pipe *entry;
1062 bool ul_set = false, dl_set = false;
1065 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1067 /* polling for received messages not supported */
1070 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1071 entry = &target_service_to_ce_map_wlan[i];
1073 if (__le32_to_cpu(entry->service_id) != service_id)
1076 switch (__le32_to_cpu(entry->pipedir)) {
1081 *dl_pipe = __le32_to_cpu(entry->pipenum);
1086 *ul_pipe = __le32_to_cpu(entry->pipenum);
1092 *dl_pipe = __le32_to_cpu(entry->pipenum);
1093 *ul_pipe = __le32_to_cpu(entry->pipenum);
1100 if (WARN_ON(!ul_set || !dl_set))
1104 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1109 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1110 u8 *ul_pipe, u8 *dl_pipe)
1112 int ul_is_polled, dl_is_polled;
1114 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1116 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1117 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1124 static void ath10k_pci_irq_disable(struct ath10k *ar)
1126 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1129 ath10k_ce_disable_interrupts(ar);
1130 ath10k_pci_disable_and_clear_legacy_irq(ar);
1131 /* FIXME: How to mask all MSI interrupts? */
1133 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1134 synchronize_irq(ar_pci->pdev->irq + i);
1137 static void ath10k_pci_irq_enable(struct ath10k *ar)
1139 ath10k_ce_enable_interrupts(ar);
1140 ath10k_pci_enable_legacy_irq(ar);
1141 /* FIXME: How to unmask all MSI interrupts? */
1144 static int ath10k_pci_hif_start(struct ath10k *ar)
1146 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1148 ath10k_pci_irq_enable(ar);
1149 ath10k_pci_rx_post(ar);
1154 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1157 struct ath10k_pci *ar_pci;
1158 struct ath10k_ce_pipe *ce_hdl;
1160 struct sk_buff *netbuf;
1163 buf_sz = pipe_info->buf_sz;
1165 /* Unused Copy Engine */
1169 ar = pipe_info->hif_ce_state;
1170 ar_pci = ath10k_pci_priv(ar);
1171 ce_hdl = pipe_info->ce_hdl;
1173 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1175 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1176 netbuf->len + skb_tailroom(netbuf),
1178 dev_kfree_skb_any(netbuf);
1182 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1185 struct ath10k_pci *ar_pci;
1186 struct ath10k_ce_pipe *ce_hdl;
1187 struct sk_buff *netbuf;
1189 unsigned int nbytes;
1193 buf_sz = pipe_info->buf_sz;
1195 /* Unused Copy Engine */
1199 ar = pipe_info->hif_ce_state;
1200 ar_pci = ath10k_pci_priv(ar);
1201 ce_hdl = pipe_info->ce_hdl;
1203 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1204 &ce_data, &nbytes, &id) == 0) {
1205 /* no need to call tx completion for NULL pointers */
1209 ar_pci->msg_callbacks_current.tx_completion(ar,
1216 * Cleanup residual buffers for device shutdown:
1217 * buffers that were enqueued for receive
1218 * buffers that were to be sent
1219 * Note: Buffers that had completed but which were
1220 * not yet processed are on a completion queue. They
1221 * are handled when the completion thread shuts down.
1223 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1225 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1228 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1229 struct ath10k_pci_pipe *pipe_info;
1231 pipe_info = &ar_pci->pipe_info[pipe_num];
1232 ath10k_pci_rx_pipe_cleanup(pipe_info);
1233 ath10k_pci_tx_pipe_cleanup(pipe_info);
1237 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1241 for (i = 0; i < CE_COUNT; i++)
1242 ath10k_ce_deinit_pipe(ar, i);
1245 static void ath10k_pci_flush(struct ath10k *ar)
1247 ath10k_pci_kill_tasklet(ar);
1248 ath10k_pci_buffer_cleanup(ar);
1251 static void ath10k_pci_hif_stop(struct ath10k *ar)
1253 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1255 /* Most likely the device has HTT Rx ring configured. The only way to
1256 * prevent the device from accessing (and possible corrupting) host
1257 * memory is to reset the chip now.
1259 * There's also no known way of masking MSI interrupts on the device.
1260 * For ranged MSI the CE-related interrupts can be masked. However
1261 * regardless how many MSI interrupts are assigned the first one
1262 * is always used for firmware indications (crashes) and cannot be
1263 * masked. To prevent the device from asserting the interrupt reset it
1264 * before proceeding with cleanup.
1266 ath10k_pci_warm_reset(ar);
1268 ath10k_pci_irq_disable(ar);
1269 ath10k_pci_flush(ar);
1272 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1273 void *req, u32 req_len,
1274 void *resp, u32 *resp_len)
1276 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1277 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1278 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1279 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1280 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1281 dma_addr_t req_paddr = 0;
1282 dma_addr_t resp_paddr = 0;
1283 struct bmi_xfer xfer = {};
1284 void *treq, *tresp = NULL;
1289 if (resp && !resp_len)
1292 if (resp && resp_len && *resp_len == 0)
1295 treq = kmemdup(req, req_len, GFP_KERNEL);
1299 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1300 ret = dma_mapping_error(ar->dev, req_paddr);
1304 if (resp && resp_len) {
1305 tresp = kzalloc(*resp_len, GFP_KERNEL);
1311 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1313 ret = dma_mapping_error(ar->dev, resp_paddr);
1317 xfer.wait_for_resp = true;
1320 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1323 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1327 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1330 unsigned int unused_nbytes;
1331 unsigned int unused_id;
1333 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1334 &unused_nbytes, &unused_id);
1336 /* non-zero means we did not time out */
1344 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1345 dma_unmap_single(ar->dev, resp_paddr,
1346 *resp_len, DMA_FROM_DEVICE);
1349 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1351 if (ret == 0 && resp_len) {
1352 *resp_len = min(*resp_len, xfer.resp_len);
1353 memcpy(resp, tresp, xfer.resp_len);
1362 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1364 struct bmi_xfer *xfer;
1366 unsigned int nbytes;
1367 unsigned int transfer_id;
1369 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1370 &nbytes, &transfer_id))
1373 xfer->tx_done = true;
1376 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1378 struct ath10k *ar = ce_state->ar;
1379 struct bmi_xfer *xfer;
1381 unsigned int nbytes;
1382 unsigned int transfer_id;
1385 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1386 &nbytes, &transfer_id, &flags))
1389 if (!xfer->wait_for_resp) {
1390 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1394 xfer->resp_len = nbytes;
1395 xfer->rx_done = true;
1398 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1399 struct ath10k_ce_pipe *rx_pipe,
1400 struct bmi_xfer *xfer)
1402 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1404 while (time_before_eq(jiffies, timeout)) {
1405 ath10k_pci_bmi_send_done(tx_pipe);
1406 ath10k_pci_bmi_recv_data(rx_pipe);
1408 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1418 * Send an interrupt to the device to wake up the Target CPU
1419 * so it has an opportunity to notice any changed state.
1421 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1425 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1426 val = ath10k_pci_read32(ar, addr);
1427 val |= CORE_CTRL_CPU_INTR_MASK;
1428 ath10k_pci_write32(ar, addr, val);
1433 static int ath10k_pci_init_config(struct ath10k *ar)
1435 u32 interconnect_targ_addr;
1436 u32 pcie_state_targ_addr = 0;
1437 u32 pipe_cfg_targ_addr = 0;
1438 u32 svc_to_pipe_map = 0;
1439 u32 pcie_config_flags = 0;
1441 u32 ealloc_targ_addr;
1443 u32 flag2_targ_addr;
1446 /* Download to Target the CE Config and the service-to-CE map */
1447 interconnect_targ_addr =
1448 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1450 /* Supply Target-side CE configuration */
1451 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
1452 &pcie_state_targ_addr);
1454 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1458 if (pcie_state_targ_addr == 0) {
1460 ath10k_err(ar, "Invalid pcie state addr\n");
1464 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1465 offsetof(struct pcie_state,
1467 &pipe_cfg_targ_addr);
1469 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1473 if (pipe_cfg_targ_addr == 0) {
1475 ath10k_err(ar, "Invalid pipe cfg addr\n");
1479 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1480 target_ce_config_wlan,
1481 sizeof(target_ce_config_wlan));
1484 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1488 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1489 offsetof(struct pcie_state,
1493 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1497 if (svc_to_pipe_map == 0) {
1499 ath10k_err(ar, "Invalid svc_to_pipe map\n");
1503 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1504 target_service_to_ce_map_wlan,
1505 sizeof(target_service_to_ce_map_wlan));
1507 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
1511 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1512 offsetof(struct pcie_state,
1514 &pcie_config_flags);
1516 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
1520 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1522 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
1523 offsetof(struct pcie_state,
1527 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
1531 /* configure early allocation */
1532 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1534 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
1536 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
1540 /* first bank is switched to IRAM */
1541 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1542 HI_EARLY_ALLOC_MAGIC_MASK);
1543 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1544 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1546 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
1548 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
1552 /* Tell Target to proceed with initialization */
1553 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1555 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
1557 ath10k_err(ar, "Failed to get option val: %d\n", ret);
1561 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1563 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
1565 ath10k_err(ar, "Failed to set option val: %d\n", ret);
1572 static int ath10k_pci_alloc_ce(struct ath10k *ar)
1576 for (i = 0; i < CE_COUNT; i++) {
1577 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1579 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1588 static void ath10k_pci_free_ce(struct ath10k *ar)
1592 for (i = 0; i < CE_COUNT; i++)
1593 ath10k_ce_free_pipe(ar, i);
1596 static int ath10k_pci_ce_init(struct ath10k *ar)
1598 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1599 struct ath10k_pci_pipe *pipe_info;
1600 const struct ce_attr *attr;
1603 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1604 pipe_info = &ar_pci->pipe_info[pipe_num];
1605 pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
1606 pipe_info->pipe_num = pipe_num;
1607 pipe_info->hif_ce_state = ar;
1608 attr = &host_ce_config_wlan[pipe_num];
1610 ret = ath10k_ce_init_pipe(ar, pipe_num, attr,
1611 ath10k_pci_ce_send_done,
1612 ath10k_pci_ce_recv_data);
1614 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
1619 if (pipe_num == CE_COUNT - 1) {
1621 * Reserve the ultimate CE for
1622 * diagnostic Window support
1624 ar_pci->ce_diag = pipe_info->ce_hdl;
1628 pipe_info->buf_sz = (size_t)(attr->src_sz_max);
1634 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
1636 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
1637 FW_IND_EVENT_PENDING;
1640 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
1644 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
1645 val &= ~FW_IND_EVENT_PENDING;
1646 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
1649 /* this function effectively clears target memory controller assert line */
1650 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
1654 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1655 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1656 val | SOC_RESET_CONTROL_SI0_RST_MASK);
1657 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1661 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1662 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1663 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
1664 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1669 static int ath10k_pci_warm_reset(struct ath10k *ar)
1673 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
1676 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1677 PCIE_INTR_CAUSE_ADDRESS);
1678 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
1681 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1683 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1686 /* disable pending irqs */
1687 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1688 PCIE_INTR_ENABLE_ADDRESS, 0);
1690 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1691 PCIE_INTR_CLR_ADDRESS, ~0);
1695 /* clear fw indicator */
1696 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
1698 /* clear target LF timer interrupts */
1699 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1700 SOC_LF_TIMER_CONTROL0_ADDRESS);
1701 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
1702 SOC_LF_TIMER_CONTROL0_ADDRESS,
1703 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
1706 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1707 SOC_RESET_CONTROL_ADDRESS);
1708 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1709 val | SOC_RESET_CONTROL_CE_RST_MASK);
1710 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1711 SOC_RESET_CONTROL_ADDRESS);
1715 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1716 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1717 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1718 SOC_RESET_CONTROL_ADDRESS);
1721 ath10k_pci_warm_reset_si0(ar);
1724 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1725 PCIE_INTR_CAUSE_ADDRESS);
1726 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
1729 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1731 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1734 /* CPU warm reset */
1735 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1736 SOC_RESET_CONTROL_ADDRESS);
1737 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1738 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
1740 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1741 SOC_RESET_CONTROL_ADDRESS);
1742 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n",
1747 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
1752 static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
1757 * Bring the target up cleanly.
1759 * The target may be in an undefined state with an AUX-powered Target
1760 * and a Host in WoW mode. If the Host crashes, loses power, or is
1761 * restarted (without unloading the driver) then the Target is left
1762 * (aux) powered and running. On a subsequent driver load, the Target
1763 * is in an unexpected state. We try to catch that here in order to
1764 * reset the Target and retry the probe.
1767 ret = ath10k_pci_cold_reset(ar);
1769 ret = ath10k_pci_warm_reset(ar);
1772 ath10k_err(ar, "failed to reset target: %d\n", ret);
1776 ret = ath10k_pci_ce_init(ar);
1778 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1782 ret = ath10k_pci_wait_for_target_init(ar);
1784 ath10k_err(ar, "failed to wait for target to init: %d\n", ret);
1788 ret = ath10k_pci_init_config(ar);
1790 ath10k_err(ar, "failed to setup init config: %d\n", ret);
1794 ret = ath10k_pci_wake_target_cpu(ar);
1796 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
1803 ath10k_pci_ce_deinit(ar);
1804 ath10k_pci_warm_reset(ar);
1809 static int ath10k_pci_hif_power_up_warm(struct ath10k *ar)
1814 * Sometime warm reset succeeds after retries.
1816 * FIXME: It might be possible to tune ath10k_pci_warm_reset() to work
1819 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
1820 ret = __ath10k_pci_hif_power_up(ar, false);
1824 ath10k_warn(ar, "failed to warm reset (attempt %d out of %d): %d\n",
1825 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret);
1831 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1835 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
1838 * Hardware CUS232 version 2 has some issues with cold reset and the
1839 * preferred (and safer) way to perform a device reset is through a
1842 * Warm reset doesn't always work though so fall back to cold reset may
1845 ret = ath10k_pci_hif_power_up_warm(ar);
1847 ath10k_warn(ar, "failed to power up target using warm reset: %d\n",
1850 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
1853 ath10k_warn(ar, "trying cold reset\n");
1855 ret = __ath10k_pci_hif_power_up(ar, true);
1857 ath10k_err(ar, "failed to power up target using cold reset too (%d)\n",
1866 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1868 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1870 ath10k_pci_warm_reset(ar);
1875 #define ATH10K_PCI_PM_CONTROL 0x44
1877 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1879 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1880 struct pci_dev *pdev = ar_pci->pdev;
1883 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1885 if ((val & 0x000000ff) != 0x3) {
1886 pci_save_state(pdev);
1887 pci_disable_device(pdev);
1888 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1889 (val & 0xffffff00) | 0x03);
1895 static int ath10k_pci_hif_resume(struct ath10k *ar)
1897 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1898 struct pci_dev *pdev = ar_pci->pdev;
1901 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1903 if ((val & 0x000000ff) != 0) {
1904 pci_restore_state(pdev);
1905 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1908 * Suspend/Resume resets the PCI configuration space,
1909 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1910 * to keep PCI Tx retries from interfering with C3 CPU state
1912 pci_read_config_dword(pdev, 0x40, &val);
1914 if ((val & 0x0000ff00) != 0)
1915 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1922 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
1923 .tx_sg = ath10k_pci_hif_tx_sg,
1924 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
1925 .start = ath10k_pci_hif_start,
1926 .stop = ath10k_pci_hif_stop,
1927 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
1928 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
1929 .send_complete_check = ath10k_pci_hif_send_complete_check,
1930 .set_callbacks = ath10k_pci_hif_set_callbacks,
1931 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
1932 .power_up = ath10k_pci_hif_power_up,
1933 .power_down = ath10k_pci_hif_power_down,
1935 .suspend = ath10k_pci_hif_suspend,
1936 .resume = ath10k_pci_hif_resume,
1940 static void ath10k_pci_ce_tasklet(unsigned long ptr)
1942 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
1943 struct ath10k_pci *ar_pci = pipe->ar_pci;
1945 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
1948 static void ath10k_msi_err_tasklet(unsigned long data)
1950 struct ath10k *ar = (struct ath10k *)data;
1952 if (!ath10k_pci_has_fw_crashed(ar)) {
1953 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
1957 ath10k_pci_fw_crashed_clear(ar);
1958 ath10k_pci_fw_crashed_dump(ar);
1962 * Handler for a per-engine interrupt on a PARTICULAR CE.
1963 * This is used in cases where each CE has a private MSI interrupt.
1965 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
1967 struct ath10k *ar = arg;
1968 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1969 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
1971 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
1972 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1978 * NOTE: We are able to derive ce_id from irq because we
1979 * use a one-to-one mapping for CE's 0..5.
1980 * CE's 6 & 7 do not use interrupts at all.
1982 * This mapping must be kept in sync with the mapping
1985 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
1989 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
1991 struct ath10k *ar = arg;
1992 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1994 tasklet_schedule(&ar_pci->msi_fw_err);
1999 * Top-level interrupt handler for all PCI interrupts from a Target.
2000 * When a block of MSI interrupts is allocated, this top-level handler
2001 * is not used; instead, we directly call the correct sub-handler.
2003 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2005 struct ath10k *ar = arg;
2006 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2008 if (ar_pci->num_msi_intrs == 0) {
2009 if (!ath10k_pci_irq_pending(ar))
2012 ath10k_pci_disable_and_clear_legacy_irq(ar);
2015 tasklet_schedule(&ar_pci->intr_tq);
2020 static void ath10k_pci_tasklet(unsigned long data)
2022 struct ath10k *ar = (struct ath10k *)data;
2023 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2025 if (ath10k_pci_has_fw_crashed(ar)) {
2026 ath10k_pci_fw_crashed_clear(ar);
2027 ath10k_pci_fw_crashed_dump(ar);
2031 ath10k_ce_per_engine_service_any(ar);
2033 /* Re-enable legacy irq that was disabled in the irq handler */
2034 if (ar_pci->num_msi_intrs == 0)
2035 ath10k_pci_enable_legacy_irq(ar);
2038 static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2040 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2043 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2044 ath10k_pci_msi_fw_handler,
2045 IRQF_SHARED, "ath10k_pci", ar);
2047 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2048 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2052 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2053 ret = request_irq(ar_pci->pdev->irq + i,
2054 ath10k_pci_per_engine_handler,
2055 IRQF_SHARED, "ath10k_pci", ar);
2057 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2058 ar_pci->pdev->irq + i, ret);
2060 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2061 free_irq(ar_pci->pdev->irq + i, ar);
2063 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2071 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2073 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2076 ret = request_irq(ar_pci->pdev->irq,
2077 ath10k_pci_interrupt_handler,
2078 IRQF_SHARED, "ath10k_pci", ar);
2080 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2081 ar_pci->pdev->irq, ret);
2088 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2090 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2093 ret = request_irq(ar_pci->pdev->irq,
2094 ath10k_pci_interrupt_handler,
2095 IRQF_SHARED, "ath10k_pci", ar);
2097 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2098 ar_pci->pdev->irq, ret);
2105 static int ath10k_pci_request_irq(struct ath10k *ar)
2107 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2109 switch (ar_pci->num_msi_intrs) {
2111 return ath10k_pci_request_irq_legacy(ar);
2113 return ath10k_pci_request_irq_msi(ar);
2114 case MSI_NUM_REQUEST:
2115 return ath10k_pci_request_irq_msix(ar);
2118 ath10k_warn(ar, "unknown irq configuration upon request\n");
2122 static void ath10k_pci_free_irq(struct ath10k *ar)
2124 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2127 /* There's at least one interrupt irregardless whether its legacy INTR
2128 * or MSI or MSI-X */
2129 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2130 free_irq(ar_pci->pdev->irq + i, ar);
2133 static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2135 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2138 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2139 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2142 for (i = 0; i < CE_COUNT; i++) {
2143 ar_pci->pipe_info[i].ar_pci = ar_pci;
2144 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2145 (unsigned long)&ar_pci->pipe_info[i]);
2149 static int ath10k_pci_init_irq(struct ath10k *ar)
2151 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2154 ath10k_pci_init_irq_tasklets(ar);
2156 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2157 ath10k_info(ar, "limiting irq mode to: %d\n",
2158 ath10k_pci_irq_mode);
2161 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2162 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
2163 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2164 ar_pci->num_msi_intrs);
2172 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2173 ar_pci->num_msi_intrs = 1;
2174 ret = pci_enable_msi(ar_pci->pdev);
2183 * A potential race occurs here: The CORE_BASE write
2184 * depends on target correctly decoding AXI address but
2185 * host won't know when target writes BAR to CORE_CTRL.
2186 * This write might get lost if target has NOT written BAR.
2187 * For now, fix the race by repeating the write in below
2188 * synchronization checking. */
2189 ar_pci->num_msi_intrs = 0;
2191 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2192 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2197 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2199 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2203 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2205 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2207 switch (ar_pci->num_msi_intrs) {
2209 ath10k_pci_deinit_irq_legacy(ar);
2213 case MSI_NUM_REQUEST:
2214 pci_disable_msi(ar_pci->pdev);
2217 pci_disable_msi(ar_pci->pdev);
2220 ath10k_warn(ar, "unknown irq configuration upon deinit\n");
2224 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2226 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2227 unsigned long timeout;
2230 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2232 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2235 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2237 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2240 /* target should never return this */
2241 if (val == 0xffffffff)
2244 /* the device has crashed so don't bother trying anymore */
2245 if (val & FW_IND_EVENT_PENDING)
2248 if (val & FW_IND_INITIALIZED)
2251 if (ar_pci->num_msi_intrs == 0)
2252 /* Fix potential race by repeating CORE_BASE writes */
2253 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
2254 PCIE_INTR_ENABLE_ADDRESS,
2255 PCIE_INTR_FIRMWARE_MASK |
2256 PCIE_INTR_CE_MASK_ALL);
2259 } while (time_before(jiffies, timeout));
2261 if (val == 0xffffffff) {
2262 ath10k_err(ar, "failed to read device register, device is gone\n");
2266 if (val & FW_IND_EVENT_PENDING) {
2267 ath10k_warn(ar, "device has crashed during init\n");
2268 ath10k_pci_fw_crashed_clear(ar);
2269 ath10k_pci_fw_crashed_dump(ar);
2273 if (!(val & FW_IND_INITIALIZED)) {
2274 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2283 static int ath10k_pci_cold_reset(struct ath10k *ar)
2288 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2290 /* Put Target, including PCIe, into RESET. */
2291 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2293 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2295 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2296 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2297 RTC_STATE_COLD_RESET_MASK)
2302 /* Pull Target, including PCIe, out of RESET. */
2304 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2306 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2307 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2308 RTC_STATE_COLD_RESET_MASK))
2313 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
2318 static int ath10k_pci_claim(struct ath10k *ar)
2320 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2321 struct pci_dev *pdev = ar_pci->pdev;
2325 pci_set_drvdata(pdev, ar);
2327 ret = pci_enable_device(pdev);
2329 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2333 ret = pci_request_region(pdev, BAR_NUM, "ath");
2335 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2340 /* Target expects 32 bit DMA. Enforce it. */
2341 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2343 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2347 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2349 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2354 pci_set_master(pdev);
2356 /* Workaround: Disable ASPM */
2357 pci_read_config_dword(pdev, 0x80, &lcr_val);
2358 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2360 /* Arrange for access to Target SoC registers. */
2361 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2363 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2368 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2372 pci_clear_master(pdev);
2375 pci_release_region(pdev, BAR_NUM);
2378 pci_disable_device(pdev);
2383 static void ath10k_pci_release(struct ath10k *ar)
2385 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2386 struct pci_dev *pdev = ar_pci->pdev;
2388 pci_iounmap(pdev, ar_pci->mem);
2389 pci_release_region(pdev, BAR_NUM);
2390 pci_clear_master(pdev);
2391 pci_disable_device(pdev);
2394 static int ath10k_pci_probe(struct pci_dev *pdev,
2395 const struct pci_device_id *pci_dev)
2399 struct ath10k_pci *ar_pci;
2402 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev,
2403 &ath10k_pci_hif_ops);
2405 dev_err(&pdev->dev, "failed to allocate core\n");
2409 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n");
2411 ar_pci = ath10k_pci_priv(ar);
2412 ar_pci->pdev = pdev;
2413 ar_pci->dev = &pdev->dev;
2416 spin_lock_init(&ar_pci->ce_lock);
2417 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
2420 ret = ath10k_pci_claim(ar);
2422 ath10k_err(ar, "failed to claim device: %d\n", ret);
2423 goto err_core_destroy;
2426 ret = ath10k_pci_wake(ar);
2428 ath10k_err(ar, "failed to wake up: %d\n", ret);
2432 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2433 if (chip_id == 0xffffffff) {
2434 ath10k_err(ar, "failed to get chip id\n");
2438 ret = ath10k_pci_alloc_ce(ar);
2440 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
2445 ath10k_pci_ce_deinit(ar);
2447 ret = ath10k_ce_disable_interrupts(ar);
2449 ath10k_err(ar, "failed to disable copy engine interrupts: %d\n",
2454 /* Workaround: There's no known way to mask all possible interrupts via
2455 * device CSR. The only way to make sure device doesn't assert
2456 * interrupts is to reset it. Interrupts are then disabled on host
2457 * after handlers are registered.
2459 ath10k_pci_warm_reset(ar);
2461 ret = ath10k_pci_init_irq(ar);
2463 ath10k_err(ar, "failed to init irqs: %d\n", ret);
2467 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
2468 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
2469 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
2471 ret = ath10k_pci_request_irq(ar);
2473 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
2474 goto err_deinit_irq;
2477 /* This shouldn't race as the device has been reset above. */
2478 ath10k_pci_irq_disable(ar);
2480 ret = ath10k_core_register(ar, chip_id);
2482 ath10k_err(ar, "failed to register driver core: %d\n", ret);
2489 ath10k_pci_free_irq(ar);
2490 ath10k_pci_kill_tasklet(ar);
2493 ath10k_pci_deinit_irq(ar);
2496 ath10k_pci_free_ce(ar);
2499 ath10k_pci_sleep(ar);
2502 ath10k_pci_release(ar);
2505 ath10k_core_destroy(ar);
2510 static void ath10k_pci_remove(struct pci_dev *pdev)
2512 struct ath10k *ar = pci_get_drvdata(pdev);
2513 struct ath10k_pci *ar_pci;
2515 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
2520 ar_pci = ath10k_pci_priv(ar);
2525 ath10k_core_unregister(ar);
2526 ath10k_pci_free_irq(ar);
2527 ath10k_pci_kill_tasklet(ar);
2528 ath10k_pci_deinit_irq(ar);
2529 ath10k_pci_ce_deinit(ar);
2530 ath10k_pci_free_ce(ar);
2531 ath10k_pci_sleep(ar);
2532 ath10k_pci_release(ar);
2533 ath10k_core_destroy(ar);
2536 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2538 static struct pci_driver ath10k_pci_driver = {
2539 .name = "ath10k_pci",
2540 .id_table = ath10k_pci_id_table,
2541 .probe = ath10k_pci_probe,
2542 .remove = ath10k_pci_remove,
2545 static int __init ath10k_pci_init(void)
2549 ret = pci_register_driver(&ath10k_pci_driver);
2551 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
2556 module_init(ath10k_pci_init);
2558 static void __exit ath10k_pci_exit(void)
2560 pci_unregister_driver(&ath10k_pci_driver);
2563 module_exit(ath10k_pci_exit);
2565 MODULE_AUTHOR("Qualcomm Atheros");
2566 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2567 MODULE_LICENSE("Dual BSD/GPL");
2568 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_3_FILE);
2569 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);