1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "11"
34 /* Information for net */
35 #define NET_VERSION "11"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PLA_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_UPHY_TIMER 0xd388
61 #define PLA_SUSPEND_FLAG 0xd38a
62 #define PLA_INDICATE_FALG 0xd38c
63 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
64 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
65 #define PLA_EXTRA_STATUS 0xd398
66 #define PLA_EFUSE_DATA 0xdd00
67 #define PLA_EFUSE_CMD 0xdd02
68 #define PLA_LEDSEL 0xdd90
69 #define PLA_LED_FEATURE 0xdd92
70 #define PLA_PHYAR 0xde00
71 #define PLA_BOOT_CTRL 0xe004
72 #define PLA_LWAKE_CTRL_REG 0xe007
73 #define PLA_GPHY_INTR_IMR 0xe022
74 #define PLA_EEE_CR 0xe040
75 #define PLA_EEEP_CR 0xe080
76 #define PLA_MAC_PWR_CTRL 0xe0c0
77 #define PLA_MAC_PWR_CTRL2 0xe0ca
78 #define PLA_MAC_PWR_CTRL3 0xe0cc
79 #define PLA_MAC_PWR_CTRL4 0xe0ce
80 #define PLA_WDT6_CTRL 0xe428
81 #define PLA_TCR0 0xe610
82 #define PLA_TCR1 0xe612
83 #define PLA_MTPS 0xe615
84 #define PLA_TXFIFO_CTRL 0xe618
85 #define PLA_RSTTALLY 0xe800
87 #define PLA_CRWECR 0xe81c
88 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
89 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
90 #define PLA_CONFIG5 0xe822
91 #define PLA_PHY_PWR 0xe84c
92 #define PLA_OOB_CTRL 0xe84f
93 #define PLA_CPCR 0xe854
94 #define PLA_MISC_0 0xe858
95 #define PLA_MISC_1 0xe85a
96 #define PLA_OCP_GPHY_BASE 0xe86c
97 #define PLA_TALLYCNT 0xe890
98 #define PLA_SFF_STS_7 0xe8de
99 #define PLA_PHYSTATUS 0xe908
100 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
101 #define PLA_BP_BA 0xfc26
102 #define PLA_BP_0 0xfc28
103 #define PLA_BP_1 0xfc2a
104 #define PLA_BP_2 0xfc2c
105 #define PLA_BP_3 0xfc2e
106 #define PLA_BP_4 0xfc30
107 #define PLA_BP_5 0xfc32
108 #define PLA_BP_6 0xfc34
109 #define PLA_BP_7 0xfc36
110 #define PLA_BP_EN 0xfc38
112 #define USB_USB2PHY 0xb41e
113 #define USB_SSPHYLINK1 0xb426
114 #define USB_SSPHYLINK2 0xb428
115 #define USB_U2P3_CTRL 0xb460
116 #define USB_CSR_DUMMY1 0xb464
117 #define USB_CSR_DUMMY2 0xb466
118 #define USB_DEV_STAT 0xb808
119 #define USB_CONNECT_TIMER 0xcbf8
120 #define USB_MSC_TIMER 0xcbfc
121 #define USB_BURST_SIZE 0xcfc0
122 #define USB_FW_FIX_EN0 0xcfca
123 #define USB_FW_FIX_EN1 0xcfcc
124 #define USB_LPM_CONFIG 0xcfd8
125 #define USB_CSTMR 0xcfef /* RTL8153A */
126 #define USB_FW_CTRL 0xd334 /* RTL8153B */
127 #define USB_FC_TIMER 0xd340
128 #define USB_USB_CTRL 0xd406
129 #define USB_PHY_CTRL 0xd408
130 #define USB_TX_AGG 0xd40a
131 #define USB_RX_BUF_TH 0xd40c
132 #define USB_USB_TIMER 0xd428
133 #define USB_RX_EARLY_TIMEOUT 0xd42c
134 #define USB_RX_EARLY_SIZE 0xd42e
135 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
136 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
137 #define USB_TX_DMA 0xd434
138 #define USB_UPT_RXDMA_OWN 0xd437
139 #define USB_TOLERANCE 0xd490
140 #define USB_LPM_CTRL 0xd41a
141 #define USB_BMU_RESET 0xd4b0
142 #define USB_U1U2_TIMER 0xd4da
143 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
144 #define USB_UPS_CTRL 0xd800
145 #define USB_POWER_CUT 0xd80a
146 #define USB_MISC_0 0xd81a
147 #define USB_MISC_1 0xd81f
148 #define USB_AFE_CTRL2 0xd824
149 #define USB_UPS_CFG 0xd842
150 #define USB_UPS_FLAGS 0xd848
151 #define USB_WDT1_CTRL 0xe404
152 #define USB_WDT11_CTRL 0xe43c
153 #define USB_BP_BA PLA_BP_BA
154 #define USB_BP_0 PLA_BP_0
155 #define USB_BP_1 PLA_BP_1
156 #define USB_BP_2 PLA_BP_2
157 #define USB_BP_3 PLA_BP_3
158 #define USB_BP_4 PLA_BP_4
159 #define USB_BP_5 PLA_BP_5
160 #define USB_BP_6 PLA_BP_6
161 #define USB_BP_7 PLA_BP_7
162 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
163 #define USB_BP_8 0xfc38 /* RTL8153B */
164 #define USB_BP_9 0xfc3a
165 #define USB_BP_10 0xfc3c
166 #define USB_BP_11 0xfc3e
167 #define USB_BP_12 0xfc40
168 #define USB_BP_13 0xfc42
169 #define USB_BP_14 0xfc44
170 #define USB_BP_15 0xfc46
171 #define USB_BP2_EN 0xfc48
174 #define OCP_ALDPS_CONFIG 0x2010
175 #define OCP_EEE_CONFIG1 0x2080
176 #define OCP_EEE_CONFIG2 0x2092
177 #define OCP_EEE_CONFIG3 0x2094
178 #define OCP_BASE_MII 0xa400
179 #define OCP_EEE_AR 0xa41a
180 #define OCP_EEE_DATA 0xa41c
181 #define OCP_PHY_STATUS 0xa420
182 #define OCP_NCTL_CFG 0xa42c
183 #define OCP_POWER_CFG 0xa430
184 #define OCP_EEE_CFG 0xa432
185 #define OCP_SRAM_ADDR 0xa436
186 #define OCP_SRAM_DATA 0xa438
187 #define OCP_DOWN_SPEED 0xa442
188 #define OCP_EEE_ABLE 0xa5c4
189 #define OCP_EEE_ADV 0xa5d0
190 #define OCP_EEE_LPABLE 0xa5d2
191 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
192 #define OCP_PHY_PATCH_STAT 0xb800
193 #define OCP_PHY_PATCH_CMD 0xb820
194 #define OCP_PHY_LOCK 0xb82e
195 #define OCP_ADC_IOFFSET 0xbcfc
196 #define OCP_ADC_CFG 0xbc06
197 #define OCP_SYSCLK_CFG 0xc416
200 #define SRAM_GREEN_CFG 0x8011
201 #define SRAM_LPF_CFG 0x8012
202 #define SRAM_10M_AMP1 0x8080
203 #define SRAM_10M_AMP2 0x8082
204 #define SRAM_IMPEDANCE 0x8084
205 #define SRAM_PHY_LOCK 0xb82e
208 #define RCR_AAP 0x00000001
209 #define RCR_APM 0x00000002
210 #define RCR_AM 0x00000004
211 #define RCR_AB 0x00000008
212 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
214 /* PLA_RXFIFO_CTRL0 */
215 #define RXFIFO_THR1_NORMAL 0x00080002
216 #define RXFIFO_THR1_OOB 0x01800003
218 /* PLA_RXFIFO_CTRL1 */
219 #define RXFIFO_THR2_FULL 0x00000060
220 #define RXFIFO_THR2_HIGH 0x00000038
221 #define RXFIFO_THR2_OOB 0x0000004a
222 #define RXFIFO_THR2_NORMAL 0x00a0
224 /* PLA_RXFIFO_CTRL2 */
225 #define RXFIFO_THR3_FULL 0x00000078
226 #define RXFIFO_THR3_HIGH 0x00000048
227 #define RXFIFO_THR3_OOB 0x0000005a
228 #define RXFIFO_THR3_NORMAL 0x0110
230 /* PLA_TXFIFO_CTRL */
231 #define TXFIFO_THR_NORMAL 0x00400008
232 #define TXFIFO_THR_NORMAL2 0x01000008
235 #define ECM_ALDPS 0x0002
238 #define FMC_FCR_MCU_EN 0x0001
241 #define EEEP_CR_EEEP_TX 0x0002
244 #define WDT6_SET_MODE 0x0010
247 #define TCR0_TX_EMPTY 0x0800
248 #define TCR0_AUTO_FIFO 0x0080
251 #define VERSION_MASK 0x7cf0
254 #define MTPS_JUMBO (12 * 1024 / 64)
255 #define MTPS_DEFAULT (6 * 1024 / 64)
258 #define TALLY_RESET 0x0001
266 #define CRWECR_NORAML 0x00
267 #define CRWECR_CONFIG 0xc0
270 #define NOW_IS_OOB 0x80
271 #define TXFIFO_EMPTY 0x20
272 #define RXFIFO_EMPTY 0x10
273 #define LINK_LIST_READY 0x02
274 #define DIS_MCU_CLROOB 0x01
275 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
278 #define RXDY_GATED_EN 0x0008
281 #define RE_INIT_LL 0x8000
282 #define MCU_BORW_EN 0x4000
285 #define CPCR_RX_VLAN 0x0040
288 #define MAGIC_EN 0x0001
291 #define TEREDO_SEL 0x8000
292 #define TEREDO_WAKE_MASK 0x7f00
293 #define TEREDO_RS_EVENT_MASK 0x00fe
294 #define OOB_TEREDO_EN 0x0001
297 #define ALDPS_PROXY_MODE 0x0001
300 #define EFUSE_READ_CMD BIT(15)
301 #define EFUSE_DATA_BIT16 BIT(7)
304 #define LINK_ON_WAKE_EN 0x0010
305 #define LINK_OFF_WAKE_EN 0x0008
308 #define LANWAKE_CLR_EN BIT(0)
311 #define BWF_EN 0x0040
312 #define MWF_EN 0x0020
313 #define UWF_EN 0x0010
314 #define LAN_WAKE_EN 0x0002
316 /* PLA_LED_FEATURE */
317 #define LED_MODE_MASK 0x0700
320 #define TX_10M_IDLE_EN 0x0080
321 #define PFM_PWM_SWITCH 0x0040
322 #define TEST_IO_OFF BIT(4)
324 /* PLA_MAC_PWR_CTRL */
325 #define D3_CLK_GATED_EN 0x00004000
326 #define MCU_CLK_RATIO 0x07010f07
327 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
328 #define ALDPS_SPDWN_RATIO 0x0f87
330 /* PLA_MAC_PWR_CTRL2 */
331 #define EEE_SPDWN_RATIO 0x8007
332 #define MAC_CLK_SPDWN_EN BIT(15)
334 /* PLA_MAC_PWR_CTRL3 */
335 #define PLA_MCU_SPDWN_EN BIT(14)
336 #define PKT_AVAIL_SPDWN_EN 0x0100
337 #define SUSPEND_SPDWN_EN 0x0004
338 #define U1U2_SPDWN_EN 0x0002
339 #define L1_SPDWN_EN 0x0001
341 /* PLA_MAC_PWR_CTRL4 */
342 #define PWRSAVE_SPDWN_EN 0x1000
343 #define RXDV_SPDWN_EN 0x0800
344 #define TX10MIDLE_EN 0x0100
345 #define TP100_SPDWN_EN 0x0020
346 #define TP500_SPDWN_EN 0x0010
347 #define TP1000_SPDWN_EN 0x0008
348 #define EEE_SPDWN_EN 0x0001
350 /* PLA_GPHY_INTR_IMR */
351 #define GPHY_STS_MSK 0x0001
352 #define SPEED_DOWN_MSK 0x0002
353 #define SPDWN_RXDV_MSK 0x0004
354 #define SPDWN_LINKCHG_MSK 0x0008
357 #define PHYAR_FLAG 0x80000000
360 #define EEE_RX_EN 0x0001
361 #define EEE_TX_EN 0x0002
364 #define AUTOLOAD_DONE 0x0002
366 /* PLA_LWAKE_CTRL_REG */
367 #define LANWAKE_PIN BIT(7)
369 /* PLA_SUSPEND_FLAG */
370 #define LINK_CHG_EVENT BIT(0)
372 /* PLA_INDICATE_FALG */
373 #define UPCOMING_RUNTIME_D3 BIT(0)
375 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
376 #define DEBUG_OE BIT(0)
377 #define DEBUG_LTSSM 0x0082
379 /* PLA_EXTRA_STATUS */
380 #define CUR_LINK_OK BIT(15)
381 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
382 #define LINK_CHANGE_FLAG BIT(8)
383 #define POLL_LINK_CHG BIT(0)
386 #define USB2PHY_SUSPEND 0x0001
387 #define USB2PHY_L1 0x0002
390 #define DELAY_PHY_PWR_CHG BIT(1)
393 #define pwd_dn_scale_mask 0x3ffe
394 #define pwd_dn_scale(x) ((x) << 1)
397 #define DYNAMIC_BURST 0x0001
400 #define EP4_FULL_FC 0x0001
403 #define STAT_SPEED_MASK 0x0006
404 #define STAT_SPEED_HIGH 0x0000
405 #define STAT_SPEED_FULL 0x0002
408 #define FW_FIX_SUSPEND BIT(14)
411 #define FW_IP_RESET_EN BIT(9)
414 #define LPM_U1U2_EN BIT(0)
417 #define TX_AGG_MAX_THRESHOLD 0x03
420 #define RX_THR_SUPPER 0x0c350180
421 #define RX_THR_HIGH 0x7a120180
422 #define RX_THR_SLOW 0xffff0180
423 #define RX_THR_B 0x00010001
426 #define TEST_MODE_DISABLE 0x00000001
427 #define TX_SIZE_ADJUST1 0x00000100
430 #define BMU_RESET_EP_IN 0x01
431 #define BMU_RESET_EP_OUT 0x02
433 /* USB_UPT_RXDMA_OWN */
434 #define OWN_UPDATE BIT(0)
435 #define OWN_CLEAR BIT(1)
438 #define FC_PATCH_TASK BIT(1)
441 #define POWER_CUT 0x0100
443 /* USB_PM_CTRL_STATUS */
444 #define RESUME_INDICATE 0x0001
447 #define FORCE_SUPER BIT(0)
450 #define FLOW_CTRL_PATCH_OPT BIT(1)
453 #define CTRL_TIMER_EN BIT(15)
456 #define RX_AGG_DISABLE 0x0010
457 #define RX_ZERO_EN 0x0080
460 #define U2P3_ENABLE 0x0001
463 #define PWR_EN 0x0001
464 #define PHASE2_EN 0x0008
465 #define UPS_EN BIT(4)
466 #define USP_PREWAKE BIT(5)
469 #define PCUT_STATUS 0x0001
471 /* USB_RX_EARLY_TIMEOUT */
472 #define COALESCE_SUPER 85000U
473 #define COALESCE_HIGH 250000U
474 #define COALESCE_SLOW 524280U
477 #define WTD1_EN BIT(0)
480 #define TIMER11_EN 0x0001
483 /* bit 4 ~ 5: fifo empty boundary */
484 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
485 /* bit 2 ~ 3: LMP timer */
486 #define LPM_TIMER_MASK 0x0c
487 #define LPM_TIMER_500MS 0x04 /* 500 ms */
488 #define LPM_TIMER_500US 0x0c /* 500 us */
489 #define ROK_EXIT_LPM 0x02
492 #define SEN_VAL_MASK 0xf800
493 #define SEN_VAL_NORMAL 0xa000
494 #define SEL_RXIDLE 0x0100
497 #define SAW_CNT_1MS_MASK 0x0fff
500 #define UPS_FLAGS_R_TUNE BIT(0)
501 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
502 #define UPS_FLAGS_250M_CKDIV BIT(2)
503 #define UPS_FLAGS_EN_ALDPS BIT(3)
504 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
505 #define ups_flags_speed(x) ((x) << 16)
506 #define UPS_FLAGS_EN_EEE BIT(20)
507 #define UPS_FLAGS_EN_500M_EEE BIT(21)
508 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
509 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
510 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
511 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
512 #define UPS_FLAGS_EN_GREEN BIT(26)
513 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
527 /* OCP_ALDPS_CONFIG */
528 #define ENPWRSAVE 0x8000
529 #define ENPDNPS 0x0200
530 #define LINKENA 0x0100
531 #define DIS_SDSAVE 0x0010
534 #define PHY_STAT_MASK 0x0007
535 #define PHY_STAT_EXT_INIT 2
536 #define PHY_STAT_LAN_ON 3
537 #define PHY_STAT_PWRDN 5
540 #define PGA_RETURN_EN BIT(1)
543 #define EEE_CLKDIV_EN 0x8000
544 #define EN_ALDPS 0x0004
545 #define EN_10M_PLLOFF 0x0001
547 /* OCP_EEE_CONFIG1 */
548 #define RG_TXLPI_MSK_HFDUP 0x8000
549 #define RG_MATCLR_EN 0x4000
550 #define EEE_10_CAP 0x2000
551 #define EEE_NWAY_EN 0x1000
552 #define TX_QUIET_EN 0x0200
553 #define RX_QUIET_EN 0x0100
554 #define sd_rise_time_mask 0x0070
555 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
556 #define RG_RXLPI_MSK_HFDUP 0x0008
557 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
559 /* OCP_EEE_CONFIG2 */
560 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
561 #define RG_DACQUIET_EN 0x0400
562 #define RG_LDVQUIET_EN 0x0200
563 #define RG_CKRSEL 0x0020
564 #define RG_EEEPRG_EN 0x0010
566 /* OCP_EEE_CONFIG3 */
567 #define fast_snr_mask 0xff80
568 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
569 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
570 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
573 /* bit[15:14] function */
574 #define FUN_ADDR 0x0000
575 #define FUN_DATA 0x4000
576 /* bit[4:0] device addr */
579 #define CTAP_SHORT_EN 0x0040
580 #define EEE10_EN 0x0010
583 #define EN_EEE_CMODE BIT(14)
584 #define EN_EEE_1000 BIT(13)
585 #define EN_EEE_100 BIT(12)
586 #define EN_10M_CLKDIV BIT(11)
587 #define EN_10M_BGOFF 0x0080
590 #define TXDIS_STATE 0x01
591 #define ABD_STATE 0x02
593 /* OCP_PHY_PATCH_STAT */
594 #define PATCH_READY BIT(6)
596 /* OCP_PHY_PATCH_CMD */
597 #define PATCH_REQUEST BIT(4)
600 #define PATCH_LOCK BIT(0)
603 #define CKADSEL_L 0x0100
604 #define ADC_EN 0x0080
605 #define EN_EMI_L 0x0040
608 #define clk_div_expo(x) (min(x, 5) << 8)
611 #define GREEN_ETH_EN BIT(15)
612 #define R_TUNE_EN BIT(11)
615 #define LPF_AUTO_TUNE 0x8000
618 #define GDAC_IB_UPALL 0x0008
621 #define AMP_DN 0x0200
624 #define RX_DRIVING_MASK 0x6000
627 #define PHY_PATCH_LOCK 0x0001
630 #define AD_MASK 0xfee0
631 #define BND_MASK 0x0004
632 #define BD_MASK 0x0001
634 #define PASS_THRU_MASK 0x1
636 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
638 enum rtl_register_content {
646 #define RTL8152_MAX_TX 4
647 #define RTL8152_MAX_RX 10
652 #define RTL8152_RX_MAX_PENDING 4096
653 #define RTL8152_RXFG_HEADSZ 256
655 #define INTR_LINK 0x0004
657 #define RTL8153_MAX_PACKET 9216 /* 9K */
658 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
660 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
661 #define RTL8153_RMS RTL8153_MAX_PACKET
662 #define RTL8152_TX_TIMEOUT (5 * HZ)
663 #define RTL8152_NAPI_WEIGHT 64
664 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
665 sizeof(struct rx_desc) + RX_ALIGN)
681 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
682 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
684 struct tally_counter {
691 __le32 tx_one_collision;
692 __le32 tx_multi_collision;
702 #define RX_LEN_MASK 0x7fff
705 #define RD_UDP_CS BIT(23)
706 #define RD_TCP_CS BIT(22)
707 #define RD_IPV6_CS BIT(20)
708 #define RD_IPV4_CS BIT(19)
711 #define IPF BIT(23) /* IP checksum fail */
712 #define UDPF BIT(22) /* UDP checksum fail */
713 #define TCPF BIT(21) /* TCP checksum fail */
714 #define RX_VLAN_TAG BIT(16)
723 #define TX_FS BIT(31) /* First segment of a packet */
724 #define TX_LS BIT(30) /* Final segment of a packet */
725 #define GTSENDV4 BIT(28)
726 #define GTSENDV6 BIT(27)
727 #define GTTCPHO_SHIFT 18
728 #define GTTCPHO_MAX 0x7fU
729 #define TX_LEN_MAX 0x3ffffU
732 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
733 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
734 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
735 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
737 #define MSS_MAX 0x7ffU
738 #define TCPHO_SHIFT 17
739 #define TCPHO_MAX 0x7ffU
740 #define TX_VLAN_TAG BIT(16)
746 struct list_head list, info_list;
748 struct r8152 *context;
754 struct list_head list;
756 struct r8152 *context;
765 struct usb_device *udev;
766 struct napi_struct napi;
767 struct usb_interface *intf;
768 struct net_device *netdev;
769 struct urb *intr_urb;
770 struct tx_agg tx_info[RTL8152_MAX_TX];
771 struct list_head rx_info, rx_used;
772 struct list_head rx_done, tx_free;
773 struct sk_buff_head tx_queue, rx_queue;
774 spinlock_t rx_lock, tx_lock;
775 struct delayed_work schedule, hw_phy_work;
776 struct mii_if_info mii;
777 struct mutex control; /* use for hw setting */
778 #ifdef CONFIG_PM_SLEEP
779 struct notifier_block pm_notifier;
781 struct tasklet_struct tx_tl;
784 void (*init)(struct r8152 *tp);
785 int (*enable)(struct r8152 *tp);
786 void (*disable)(struct r8152 *tp);
787 void (*up)(struct r8152 *tp);
788 void (*down)(struct r8152 *tp);
789 void (*unload)(struct r8152 *tp);
790 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
791 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
792 bool (*in_nway)(struct r8152 *tp);
793 void (*hw_phy_cfg)(struct r8152 *tp);
794 void (*autosuspend_en)(struct r8152 *tp, bool enable);
806 u32 eee_plloff_100:1;
807 u32 eee_plloff_giga:1;
811 u32 ctap_short_off:1;
814 #define RTL_VER_SIZE 32
818 const struct firmware *fw;
820 char version[RTL_VER_SIZE];
821 int (*pre_fw)(struct r8152 *tp);
822 int (*post_fw)(struct r8152 *tp);
850 * struct fw_block - block type and total length
851 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
852 * RTL_FW_USB and so on.
853 * @length: total length of the current block.
861 * struct fw_header - header of the firmware file
862 * @checksum: checksum of sha256 which is calculated from the whole file
863 * except the checksum field of the file. That is, calculate sha256
864 * from the version field to the end of the file.
865 * @version: version of this firmware.
866 * @blocks: the first firmware block of the file
870 char version[RTL_VER_SIZE];
871 struct fw_block blocks[];
875 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
876 * The layout of the firmware block is:
877 * <struct fw_mac> + <info> + <firmware data>.
878 * @blk_hdr: firmware descriptor (type, length)
879 * @fw_offset: offset of the firmware binary data. The start address of
880 * the data would be the address of struct fw_mac + @fw_offset.
881 * @fw_reg: the register to load the firmware. Depends on chip.
882 * @bp_ba_addr: the register to write break point base address. Depends on
884 * @bp_ba_value: break point base address. Depends on chip.
885 * @bp_en_addr: the register to write break point enabled mask. Depends
887 * @bp_en_value: break point enabled mask. Depends on the firmware.
888 * @bp_start: the start register of break points. Depends on chip.
889 * @bp_num: the break point number which needs to be set for this firmware.
890 * Depends on the firmware.
891 * @bp: break points. Depends on firmware.
892 * @reserved: reserved space (unused)
893 * @fw_ver_reg: the register to store the fw version.
894 * @fw_ver_data: the firmware version of the current type.
895 * @info: additional information for debugging, and is followed by the
896 * binary data of firmware.
899 struct fw_block blk_hdr;
908 __le16 bp[16]; /* any value determined by firmware */
916 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
917 * This is used to set patch key when loading the firmware of PHY.
918 * @blk_hdr: firmware descriptor (type, length)
919 * @key_reg: the register to write the patch key.
920 * @key_data: patch key.
921 * @reserved: reserved space (unused)
923 struct fw_phy_patch_key {
924 struct fw_block blk_hdr;
931 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
932 * The layout of the firmware block is:
933 * <struct fw_phy_nc> + <info> + <firmware data>.
934 * @blk_hdr: firmware descriptor (type, length)
935 * @fw_offset: offset of the firmware binary data. The start address of
936 * the data would be the address of struct fw_phy_nc + @fw_offset.
937 * @fw_reg: the register to load the firmware. Depends on chip.
938 * @ba_reg: the register to write the base address. Depends on chip.
939 * @ba_data: base address. Depends on chip.
940 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
941 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
942 * @mode_reg: the regitster of switching the mode.
943 * @mode_pre: the mode needing to be set before loading the firmware.
944 * @mode_post: the mode to be set when finishing to load the firmware.
945 * @reserved: reserved space (unused)
946 * @bp_start: the start register of break points. Depends on chip.
947 * @bp_num: the break point number which needs to be set for this firmware.
948 * Depends on the firmware.
949 * @bp: break points. Depends on firmware.
950 * @info: additional information for debugging, and is followed by the
951 * binary data of firmware.
954 struct fw_block blk_hdr;
959 __le16 patch_en_addr;
960 __le16 patch_en_value;
1000 #define RTL_ADVERTISED_10_HALF BIT(0)
1001 #define RTL_ADVERTISED_10_FULL BIT(1)
1002 #define RTL_ADVERTISED_100_HALF BIT(2)
1003 #define RTL_ADVERTISED_100_FULL BIT(3)
1004 #define RTL_ADVERTISED_1000_HALF BIT(4)
1005 #define RTL_ADVERTISED_1000_FULL BIT(5)
1007 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1008 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1010 static const int multicast_filter_limit = 32;
1011 static unsigned int agg_buf_sz = 16384;
1013 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
1014 VLAN_ETH_HLEN - ETH_FCS_LEN)
1017 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1022 tmp = kmalloc(size, GFP_KERNEL);
1026 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1027 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1028 value, index, tmp, size, 500);
1030 memset(data, 0xff, size);
1032 memcpy(data, tmp, size);
1040 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1045 tmp = kmemdup(data, size, GFP_KERNEL);
1049 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1050 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1051 value, index, tmp, size, 500);
1058 static void rtl_set_unplug(struct r8152 *tp)
1060 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1061 set_bit(RTL8152_UNPLUG, &tp->flags);
1062 smp_mb__after_atomic();
1066 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1067 void *data, u16 type)
1072 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1075 /* both size and indix must be 4 bytes align */
1076 if ((size & 3) || !size || (index & 3) || !data)
1079 if ((u32)index + (u32)size > 0xffff)
1084 ret = get_registers(tp, index, type, limit, data);
1092 ret = get_registers(tp, index, type, size, data);
1109 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1110 u16 size, void *data, u16 type)
1113 u16 byteen_start, byteen_end, byen;
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1119 /* both size and indix must be 4 bytes align */
1120 if ((size & 3) || !size || (index & 3) || !data)
1123 if ((u32)index + (u32)size > 0xffff)
1126 byteen_start = byteen & BYTE_EN_START_MASK;
1127 byteen_end = byteen & BYTE_EN_END_MASK;
1129 byen = byteen_start | (byteen_start << 4);
1130 ret = set_registers(tp, index, type | byen, 4, data);
1143 ret = set_registers(tp, index,
1144 type | BYTE_EN_DWORD,
1153 ret = set_registers(tp, index,
1154 type | BYTE_EN_DWORD,
1166 byen = byteen_end | (byteen_end >> 4);
1167 ret = set_registers(tp, index, type | byen, 4, data);
1180 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1182 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1186 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1188 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1192 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1194 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1197 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1201 generic_ocp_read(tp, index, sizeof(data), &data, type);
1203 return __le32_to_cpu(data);
1206 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1208 __le32 tmp = __cpu_to_le32(data);
1210 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1213 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1217 u16 byen = BYTE_EN_WORD;
1218 u8 shift = index & 2;
1223 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1225 data = __le32_to_cpu(tmp);
1226 data >>= (shift * 8);
1232 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1236 u16 byen = BYTE_EN_WORD;
1237 u8 shift = index & 2;
1243 mask <<= (shift * 8);
1244 data <<= (shift * 8);
1248 tmp = __cpu_to_le32(data);
1250 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1253 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1257 u8 shift = index & 3;
1261 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1263 data = __le32_to_cpu(tmp);
1264 data >>= (shift * 8);
1270 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1274 u16 byen = BYTE_EN_BYTE;
1275 u8 shift = index & 3;
1281 mask <<= (shift * 8);
1282 data <<= (shift * 8);
1286 tmp = __cpu_to_le32(data);
1288 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1291 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1293 u16 ocp_base, ocp_index;
1295 ocp_base = addr & 0xf000;
1296 if (ocp_base != tp->ocp_base) {
1297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1298 tp->ocp_base = ocp_base;
1301 ocp_index = (addr & 0x0fff) | 0xb000;
1302 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1305 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1307 u16 ocp_base, ocp_index;
1309 ocp_base = addr & 0xf000;
1310 if (ocp_base != tp->ocp_base) {
1311 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1312 tp->ocp_base = ocp_base;
1315 ocp_index = (addr & 0x0fff) | 0xb000;
1316 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1319 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1321 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1324 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1326 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1329 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1331 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1332 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1335 static u16 sram_read(struct r8152 *tp, u16 addr)
1337 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1338 return ocp_reg_read(tp, OCP_SRAM_DATA);
1341 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1343 struct r8152 *tp = netdev_priv(netdev);
1346 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1349 if (phy_id != R8152_PHY_ID)
1352 ret = r8152_mdio_read(tp, reg);
1358 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1360 struct r8152 *tp = netdev_priv(netdev);
1362 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1365 if (phy_id != R8152_PHY_ID)
1368 r8152_mdio_write(tp, reg, val);
1372 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1374 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1376 struct r8152 *tp = netdev_priv(netdev);
1377 struct sockaddr *addr = p;
1378 int ret = -EADDRNOTAVAIL;
1380 if (!is_valid_ether_addr(addr->sa_data))
1383 ret = usb_autopm_get_interface(tp->intf);
1387 mutex_lock(&tp->control);
1389 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1391 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1392 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1393 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1395 mutex_unlock(&tp->control);
1397 usb_autopm_put_interface(tp->intf);
1402 /* Devices containing proper chips can support a persistent
1403 * host system provided MAC address.
1404 * Examples of this are Dell TB15 and Dell WD15 docks
1406 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1409 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1410 union acpi_object *obj;
1413 unsigned char buf[6];
1415 acpi_object_type mac_obj_type;
1418 if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1419 mac_obj_name = "\\MACA";
1420 mac_obj_type = ACPI_TYPE_STRING;
1423 /* test for -AD variant of RTL8153 */
1424 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1425 if ((ocp_data & AD_MASK) == 0x1000) {
1426 /* test for MAC address pass-through bit */
1427 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1428 if ((ocp_data & PASS_THRU_MASK) != 1) {
1429 netif_dbg(tp, probe, tp->netdev,
1430 "No efuse for RTL8153-AD MAC pass through\n");
1434 /* test for RTL8153-BND and RTL8153-BD */
1435 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1436 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1437 netif_dbg(tp, probe, tp->netdev,
1438 "Invalid variant for MAC pass through\n");
1443 mac_obj_name = "\\_SB.AMAC";
1444 mac_obj_type = ACPI_TYPE_BUFFER;
1448 /* returns _AUXMAC_#AABBCCDDEEFF# */
1449 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1450 obj = (union acpi_object *)buffer.pointer;
1451 if (!ACPI_SUCCESS(status))
1453 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1454 netif_warn(tp, probe, tp->netdev,
1455 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1456 obj->type, obj->string.length);
1460 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1461 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1462 netif_warn(tp, probe, tp->netdev,
1463 "Invalid header when reading pass-thru MAC addr\n");
1466 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1467 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1468 netif_warn(tp, probe, tp->netdev,
1469 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1474 memcpy(sa->sa_data, buf, 6);
1475 netif_info(tp, probe, tp->netdev,
1476 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1483 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1485 struct net_device *dev = tp->netdev;
1488 sa->sa_family = dev->type;
1490 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1492 if (tp->version == RTL_VER_01) {
1493 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1495 /* if device doesn't support MAC pass through this will
1496 * be expected to be non-zero
1498 ret = vendor_mac_passthru_addr_read(tp, sa);
1500 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1506 netif_err(tp, probe, dev, "Get ether addr fail\n");
1507 } else if (!is_valid_ether_addr(sa->sa_data)) {
1508 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1510 eth_hw_addr_random(dev);
1511 ether_addr_copy(sa->sa_data, dev->dev_addr);
1512 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1520 static int set_ethernet_addr(struct r8152 *tp)
1522 struct net_device *dev = tp->netdev;
1526 ret = determine_ethernet_addr(tp, &sa);
1530 if (tp->version == RTL_VER_01)
1531 ether_addr_copy(dev->dev_addr, sa.sa_data);
1533 ret = rtl8152_set_mac_address(dev, &sa);
1538 static void read_bulk_callback(struct urb *urb)
1540 struct net_device *netdev;
1541 int status = urb->status;
1544 unsigned long flags;
1554 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1557 if (!test_bit(WORK_ENABLE, &tp->flags))
1560 netdev = tp->netdev;
1562 /* When link down, the driver would cancel all bulks. */
1563 /* This avoid the re-submitting bulk */
1564 if (!netif_carrier_ok(netdev))
1567 usb_mark_last_busy(tp->udev);
1571 if (urb->actual_length < ETH_ZLEN)
1574 spin_lock_irqsave(&tp->rx_lock, flags);
1575 list_add_tail(&agg->list, &tp->rx_done);
1576 spin_unlock_irqrestore(&tp->rx_lock, flags);
1577 napi_schedule(&tp->napi);
1581 netif_device_detach(tp->netdev);
1584 return; /* the urb is in unlink state */
1586 if (net_ratelimit())
1587 netdev_warn(netdev, "maybe reset is needed?\n");
1590 if (net_ratelimit())
1591 netdev_warn(netdev, "Rx status %d\n", status);
1595 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1598 static void write_bulk_callback(struct urb *urb)
1600 struct net_device_stats *stats;
1601 struct net_device *netdev;
1604 unsigned long flags;
1605 int status = urb->status;
1615 netdev = tp->netdev;
1616 stats = &netdev->stats;
1618 if (net_ratelimit())
1619 netdev_warn(netdev, "Tx status %d\n", status);
1620 stats->tx_errors += agg->skb_num;
1622 stats->tx_packets += agg->skb_num;
1623 stats->tx_bytes += agg->skb_len;
1626 spin_lock_irqsave(&tp->tx_lock, flags);
1627 list_add_tail(&agg->list, &tp->tx_free);
1628 spin_unlock_irqrestore(&tp->tx_lock, flags);
1630 usb_autopm_put_interface_async(tp->intf);
1632 if (!netif_carrier_ok(netdev))
1635 if (!test_bit(WORK_ENABLE, &tp->flags))
1638 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1641 if (!skb_queue_empty(&tp->tx_queue))
1642 tasklet_schedule(&tp->tx_tl);
1645 static void intr_callback(struct urb *urb)
1649 int status = urb->status;
1656 if (!test_bit(WORK_ENABLE, &tp->flags))
1659 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1663 case 0: /* success */
1665 case -ECONNRESET: /* unlink */
1667 netif_device_detach(tp->netdev);
1671 netif_info(tp, intr, tp->netdev,
1672 "Stop submitting intr, status %d\n", status);
1675 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1677 /* -EPIPE: should clear the halt */
1679 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1683 d = urb->transfer_buffer;
1684 if (INTR_LINK & __le16_to_cpu(d[0])) {
1685 if (!netif_carrier_ok(tp->netdev)) {
1686 set_bit(RTL8152_LINK_CHG, &tp->flags);
1687 schedule_delayed_work(&tp->schedule, 0);
1690 if (netif_carrier_ok(tp->netdev)) {
1691 netif_stop_queue(tp->netdev);
1692 set_bit(RTL8152_LINK_CHG, &tp->flags);
1693 schedule_delayed_work(&tp->schedule, 0);
1698 res = usb_submit_urb(urb, GFP_ATOMIC);
1699 if (res == -ENODEV) {
1701 netif_device_detach(tp->netdev);
1703 netif_err(tp, intr, tp->netdev,
1704 "can't resubmit intr, status %d\n", res);
1708 static inline void *rx_agg_align(void *data)
1710 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1713 static inline void *tx_agg_align(void *data)
1715 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1718 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1720 list_del(&agg->info_list);
1722 usb_free_urb(agg->urb);
1723 put_page(agg->page);
1726 atomic_dec(&tp->rx_count);
1729 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1731 struct net_device *netdev = tp->netdev;
1732 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1733 unsigned int order = get_order(tp->rx_buf_sz);
1734 struct rx_agg *rx_agg;
1735 unsigned long flags;
1737 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1741 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1745 rx_agg->buffer = page_address(rx_agg->page);
1747 rx_agg->urb = usb_alloc_urb(0, mflags);
1751 rx_agg->context = tp;
1753 INIT_LIST_HEAD(&rx_agg->list);
1754 INIT_LIST_HEAD(&rx_agg->info_list);
1755 spin_lock_irqsave(&tp->rx_lock, flags);
1756 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1757 spin_unlock_irqrestore(&tp->rx_lock, flags);
1759 atomic_inc(&tp->rx_count);
1764 __free_pages(rx_agg->page, order);
1770 static void free_all_mem(struct r8152 *tp)
1772 struct rx_agg *agg, *agg_next;
1773 unsigned long flags;
1776 spin_lock_irqsave(&tp->rx_lock, flags);
1778 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1779 free_rx_agg(tp, agg);
1781 spin_unlock_irqrestore(&tp->rx_lock, flags);
1783 WARN_ON(atomic_read(&tp->rx_count));
1785 for (i = 0; i < RTL8152_MAX_TX; i++) {
1786 usb_free_urb(tp->tx_info[i].urb);
1787 tp->tx_info[i].urb = NULL;
1789 kfree(tp->tx_info[i].buffer);
1790 tp->tx_info[i].buffer = NULL;
1791 tp->tx_info[i].head = NULL;
1794 usb_free_urb(tp->intr_urb);
1795 tp->intr_urb = NULL;
1797 kfree(tp->intr_buff);
1798 tp->intr_buff = NULL;
1801 static int alloc_all_mem(struct r8152 *tp)
1803 struct net_device *netdev = tp->netdev;
1804 struct usb_interface *intf = tp->intf;
1805 struct usb_host_interface *alt = intf->cur_altsetting;
1806 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1809 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1811 spin_lock_init(&tp->rx_lock);
1812 spin_lock_init(&tp->tx_lock);
1813 INIT_LIST_HEAD(&tp->rx_info);
1814 INIT_LIST_HEAD(&tp->tx_free);
1815 INIT_LIST_HEAD(&tp->rx_done);
1816 skb_queue_head_init(&tp->tx_queue);
1817 skb_queue_head_init(&tp->rx_queue);
1818 atomic_set(&tp->rx_count, 0);
1820 for (i = 0; i < RTL8152_MAX_RX; i++) {
1821 if (!alloc_rx_agg(tp, GFP_KERNEL))
1825 for (i = 0; i < RTL8152_MAX_TX; i++) {
1829 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1833 if (buf != tx_agg_align(buf)) {
1835 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1841 urb = usb_alloc_urb(0, GFP_KERNEL);
1847 INIT_LIST_HEAD(&tp->tx_info[i].list);
1848 tp->tx_info[i].context = tp;
1849 tp->tx_info[i].urb = urb;
1850 tp->tx_info[i].buffer = buf;
1851 tp->tx_info[i].head = tx_agg_align(buf);
1853 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1856 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1860 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1864 tp->intr_interval = (int)ep_intr->desc.bInterval;
1865 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1866 tp->intr_buff, INTBUFSIZE, intr_callback,
1867 tp, tp->intr_interval);
1876 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1878 struct tx_agg *agg = NULL;
1879 unsigned long flags;
1881 if (list_empty(&tp->tx_free))
1884 spin_lock_irqsave(&tp->tx_lock, flags);
1885 if (!list_empty(&tp->tx_free)) {
1886 struct list_head *cursor;
1888 cursor = tp->tx_free.next;
1889 list_del_init(cursor);
1890 agg = list_entry(cursor, struct tx_agg, list);
1892 spin_unlock_irqrestore(&tp->tx_lock, flags);
1897 /* r8152_csum_workaround()
1898 * The hw limits the value of the transport offset. When the offset is out of
1899 * range, calculate the checksum by sw.
1901 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1902 struct sk_buff_head *list)
1904 if (skb_shinfo(skb)->gso_size) {
1905 netdev_features_t features = tp->netdev->features;
1906 struct sk_buff *segs, *seg, *next;
1907 struct sk_buff_head seg_list;
1909 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1910 segs = skb_gso_segment(skb, features);
1911 if (IS_ERR(segs) || !segs)
1914 __skb_queue_head_init(&seg_list);
1916 skb_list_walk_safe(segs, seg, next) {
1917 skb_mark_not_on_list(seg);
1918 __skb_queue_tail(&seg_list, seg);
1921 skb_queue_splice(&seg_list, list);
1923 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1924 if (skb_checksum_help(skb) < 0)
1927 __skb_queue_head(list, skb);
1929 struct net_device_stats *stats;
1932 stats = &tp->netdev->stats;
1933 stats->tx_dropped++;
1938 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1940 if (skb_vlan_tag_present(skb)) {
1943 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1944 desc->opts2 |= cpu_to_le32(opts2);
1948 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1950 u32 opts2 = le32_to_cpu(desc->opts2);
1952 if (opts2 & RX_VLAN_TAG)
1953 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1954 swab16(opts2 & 0xffff));
1957 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1958 struct sk_buff *skb, u32 len, u32 transport_offset)
1960 u32 mss = skb_shinfo(skb)->gso_size;
1961 u32 opts1, opts2 = 0;
1962 int ret = TX_CSUM_SUCCESS;
1964 WARN_ON_ONCE(len > TX_LEN_MAX);
1966 opts1 = len | TX_FS | TX_LS;
1969 if (transport_offset > GTTCPHO_MAX) {
1970 netif_warn(tp, tx_err, tp->netdev,
1971 "Invalid transport offset 0x%x for TSO\n",
1977 switch (vlan_get_protocol(skb)) {
1978 case htons(ETH_P_IP):
1982 case htons(ETH_P_IPV6):
1983 if (skb_cow_head(skb, 0)) {
1987 tcp_v6_gso_csum_prep(skb);
1996 opts1 |= transport_offset << GTTCPHO_SHIFT;
1997 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1998 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2001 if (transport_offset > TCPHO_MAX) {
2002 netif_warn(tp, tx_err, tp->netdev,
2003 "Invalid transport offset 0x%x\n",
2009 switch (vlan_get_protocol(skb)) {
2010 case htons(ETH_P_IP):
2012 ip_protocol = ip_hdr(skb)->protocol;
2015 case htons(ETH_P_IPV6):
2017 ip_protocol = ipv6_hdr(skb)->nexthdr;
2021 ip_protocol = IPPROTO_RAW;
2025 if (ip_protocol == IPPROTO_TCP)
2027 else if (ip_protocol == IPPROTO_UDP)
2032 opts2 |= transport_offset << TCPHO_SHIFT;
2035 desc->opts2 = cpu_to_le32(opts2);
2036 desc->opts1 = cpu_to_le32(opts1);
2042 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2044 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2048 __skb_queue_head_init(&skb_head);
2049 spin_lock(&tx_queue->lock);
2050 skb_queue_splice_init(tx_queue, &skb_head);
2051 spin_unlock(&tx_queue->lock);
2053 tx_data = agg->head;
2056 remain = agg_buf_sz;
2058 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2059 struct tx_desc *tx_desc;
2060 struct sk_buff *skb;
2064 skb = __skb_dequeue(&skb_head);
2068 len = skb->len + sizeof(*tx_desc);
2071 __skb_queue_head(&skb_head, skb);
2075 tx_data = tx_agg_align(tx_data);
2076 tx_desc = (struct tx_desc *)tx_data;
2078 offset = (u32)skb_transport_offset(skb);
2080 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2081 r8152_csum_workaround(tp, skb, &skb_head);
2085 rtl_tx_vlan_tag(tx_desc, skb);
2087 tx_data += sizeof(*tx_desc);
2090 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2091 struct net_device_stats *stats = &tp->netdev->stats;
2093 stats->tx_dropped++;
2094 dev_kfree_skb_any(skb);
2095 tx_data -= sizeof(*tx_desc);
2100 agg->skb_len += len;
2101 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2103 dev_kfree_skb_any(skb);
2105 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2107 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2111 if (!skb_queue_empty(&skb_head)) {
2112 spin_lock(&tx_queue->lock);
2113 skb_queue_splice(&skb_head, tx_queue);
2114 spin_unlock(&tx_queue->lock);
2117 netif_tx_lock(tp->netdev);
2119 if (netif_queue_stopped(tp->netdev) &&
2120 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2121 netif_wake_queue(tp->netdev);
2123 netif_tx_unlock(tp->netdev);
2125 ret = usb_autopm_get_interface_async(tp->intf);
2129 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2130 agg->head, (int)(tx_data - (u8 *)agg->head),
2131 (usb_complete_t)write_bulk_callback, agg);
2133 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2135 usb_autopm_put_interface_async(tp->intf);
2141 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2143 u8 checksum = CHECKSUM_NONE;
2146 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2149 opts2 = le32_to_cpu(rx_desc->opts2);
2150 opts3 = le32_to_cpu(rx_desc->opts3);
2152 if (opts2 & RD_IPV4_CS) {
2154 checksum = CHECKSUM_NONE;
2155 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2156 checksum = CHECKSUM_UNNECESSARY;
2157 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2158 checksum = CHECKSUM_UNNECESSARY;
2159 } else if (opts2 & RD_IPV6_CS) {
2160 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2161 checksum = CHECKSUM_UNNECESSARY;
2162 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2163 checksum = CHECKSUM_UNNECESSARY;
2170 static inline bool rx_count_exceed(struct r8152 *tp)
2172 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2175 static inline int agg_offset(struct rx_agg *agg, void *addr)
2177 return (int)(addr - agg->buffer);
2180 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2182 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2183 unsigned long flags;
2185 spin_lock_irqsave(&tp->rx_lock, flags);
2187 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2188 if (page_count(agg->page) == 1) {
2190 list_del_init(&agg->list);
2194 if (rx_count_exceed(tp)) {
2195 list_del_init(&agg->list);
2196 free_rx_agg(tp, agg);
2202 spin_unlock_irqrestore(&tp->rx_lock, flags);
2204 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2205 agg_free = alloc_rx_agg(tp, mflags);
2210 static int rx_bottom(struct r8152 *tp, int budget)
2212 unsigned long flags;
2213 struct list_head *cursor, *next, rx_queue;
2214 int ret = 0, work_done = 0;
2215 struct napi_struct *napi = &tp->napi;
2217 if (!skb_queue_empty(&tp->rx_queue)) {
2218 while (work_done < budget) {
2219 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2220 struct net_device *netdev = tp->netdev;
2221 struct net_device_stats *stats = &netdev->stats;
2222 unsigned int pkt_len;
2228 napi_gro_receive(napi, skb);
2230 stats->rx_packets++;
2231 stats->rx_bytes += pkt_len;
2235 if (list_empty(&tp->rx_done))
2238 INIT_LIST_HEAD(&rx_queue);
2239 spin_lock_irqsave(&tp->rx_lock, flags);
2240 list_splice_init(&tp->rx_done, &rx_queue);
2241 spin_unlock_irqrestore(&tp->rx_lock, flags);
2243 list_for_each_safe(cursor, next, &rx_queue) {
2244 struct rx_desc *rx_desc;
2245 struct rx_agg *agg, *agg_free;
2250 list_del_init(cursor);
2252 agg = list_entry(cursor, struct rx_agg, list);
2254 if (urb->actual_length < ETH_ZLEN)
2257 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2259 rx_desc = agg->buffer;
2260 rx_data = agg->buffer;
2261 len_used += sizeof(struct rx_desc);
2263 while (urb->actual_length > len_used) {
2264 struct net_device *netdev = tp->netdev;
2265 struct net_device_stats *stats = &netdev->stats;
2266 unsigned int pkt_len, rx_frag_head_sz;
2267 struct sk_buff *skb;
2269 /* limite the skb numbers for rx_queue */
2270 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2273 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2274 if (pkt_len < ETH_ZLEN)
2277 len_used += pkt_len;
2278 if (urb->actual_length < len_used)
2281 pkt_len -= ETH_FCS_LEN;
2282 rx_data += sizeof(struct rx_desc);
2284 if (!agg_free || tp->rx_copybreak > pkt_len)
2285 rx_frag_head_sz = pkt_len;
2287 rx_frag_head_sz = tp->rx_copybreak;
2289 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2291 stats->rx_dropped++;
2295 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2296 memcpy(skb->data, rx_data, rx_frag_head_sz);
2297 skb_put(skb, rx_frag_head_sz);
2298 pkt_len -= rx_frag_head_sz;
2299 rx_data += rx_frag_head_sz;
2301 skb_add_rx_frag(skb, 0, agg->page,
2302 agg_offset(agg, rx_data),
2304 SKB_DATA_ALIGN(pkt_len));
2305 get_page(agg->page);
2308 skb->protocol = eth_type_trans(skb, netdev);
2309 rtl_rx_vlan_tag(rx_desc, skb);
2310 if (work_done < budget) {
2312 stats->rx_packets++;
2313 stats->rx_bytes += skb->len;
2314 napi_gro_receive(napi, skb);
2316 __skb_queue_tail(&tp->rx_queue, skb);
2320 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2321 rx_desc = (struct rx_desc *)rx_data;
2322 len_used = agg_offset(agg, rx_data);
2323 len_used += sizeof(struct rx_desc);
2326 WARN_ON(!agg_free && page_count(agg->page) > 1);
2329 spin_lock_irqsave(&tp->rx_lock, flags);
2330 if (page_count(agg->page) == 1) {
2331 list_add(&agg_free->list, &tp->rx_used);
2333 list_add_tail(&agg->list, &tp->rx_used);
2337 spin_unlock_irqrestore(&tp->rx_lock, flags);
2342 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2344 urb->actual_length = 0;
2345 list_add_tail(&agg->list, next);
2349 if (!list_empty(&rx_queue)) {
2350 spin_lock_irqsave(&tp->rx_lock, flags);
2351 list_splice_tail(&rx_queue, &tp->rx_done);
2352 spin_unlock_irqrestore(&tp->rx_lock, flags);
2359 static void tx_bottom(struct r8152 *tp)
2364 struct net_device *netdev = tp->netdev;
2367 if (skb_queue_empty(&tp->tx_queue))
2370 agg = r8152_get_tx_agg(tp);
2374 res = r8152_tx_agg_fill(tp, agg);
2378 if (res == -ENODEV) {
2380 netif_device_detach(netdev);
2382 struct net_device_stats *stats = &netdev->stats;
2383 unsigned long flags;
2385 netif_warn(tp, tx_err, netdev,
2386 "failed tx_urb %d\n", res);
2387 stats->tx_dropped += agg->skb_num;
2389 spin_lock_irqsave(&tp->tx_lock, flags);
2390 list_add_tail(&agg->list, &tp->tx_free);
2391 spin_unlock_irqrestore(&tp->tx_lock, flags);
2396 static void bottom_half(unsigned long data)
2400 tp = (struct r8152 *)data;
2402 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2405 if (!test_bit(WORK_ENABLE, &tp->flags))
2408 /* When link down, the driver would cancel all bulks. */
2409 /* This avoid the re-submitting bulk */
2410 if (!netif_carrier_ok(tp->netdev))
2413 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2418 static int r8152_poll(struct napi_struct *napi, int budget)
2420 struct r8152 *tp = container_of(napi, struct r8152, napi);
2423 work_done = rx_bottom(tp, budget);
2425 if (work_done < budget) {
2426 if (!napi_complete_done(napi, work_done))
2428 if (!list_empty(&tp->rx_done))
2429 napi_schedule(napi);
2437 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2441 /* The rx would be stopped, so skip submitting */
2442 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2443 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2446 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2447 agg->buffer, tp->rx_buf_sz,
2448 (usb_complete_t)read_bulk_callback, agg);
2450 ret = usb_submit_urb(agg->urb, mem_flags);
2451 if (ret == -ENODEV) {
2453 netif_device_detach(tp->netdev);
2455 struct urb *urb = agg->urb;
2456 unsigned long flags;
2458 urb->actual_length = 0;
2459 spin_lock_irqsave(&tp->rx_lock, flags);
2460 list_add_tail(&agg->list, &tp->rx_done);
2461 spin_unlock_irqrestore(&tp->rx_lock, flags);
2463 netif_err(tp, rx_err, tp->netdev,
2464 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2466 napi_schedule(&tp->napi);
2472 static void rtl_drop_queued_tx(struct r8152 *tp)
2474 struct net_device_stats *stats = &tp->netdev->stats;
2475 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2476 struct sk_buff *skb;
2478 if (skb_queue_empty(tx_queue))
2481 __skb_queue_head_init(&skb_head);
2482 spin_lock_bh(&tx_queue->lock);
2483 skb_queue_splice_init(tx_queue, &skb_head);
2484 spin_unlock_bh(&tx_queue->lock);
2486 while ((skb = __skb_dequeue(&skb_head))) {
2488 stats->tx_dropped++;
2492 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2494 struct r8152 *tp = netdev_priv(netdev);
2496 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2498 usb_queue_reset_device(tp->intf);
2501 static void rtl8152_set_rx_mode(struct net_device *netdev)
2503 struct r8152 *tp = netdev_priv(netdev);
2505 if (netif_carrier_ok(netdev)) {
2506 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2507 schedule_delayed_work(&tp->schedule, 0);
2511 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2513 struct r8152 *tp = netdev_priv(netdev);
2514 u32 mc_filter[2]; /* Multicast hash filter */
2518 netif_stop_queue(netdev);
2519 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2520 ocp_data &= ~RCR_ACPT_ALL;
2521 ocp_data |= RCR_AB | RCR_APM;
2523 if (netdev->flags & IFF_PROMISC) {
2524 /* Unconditionally log net taps. */
2525 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2526 ocp_data |= RCR_AM | RCR_AAP;
2527 mc_filter[1] = 0xffffffff;
2528 mc_filter[0] = 0xffffffff;
2529 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2530 (netdev->flags & IFF_ALLMULTI)) {
2531 /* Too many to filter perfectly -- accept all multicasts. */
2533 mc_filter[1] = 0xffffffff;
2534 mc_filter[0] = 0xffffffff;
2536 struct netdev_hw_addr *ha;
2540 netdev_for_each_mc_addr(ha, netdev) {
2541 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2543 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2548 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2549 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2551 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2552 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2553 netif_wake_queue(netdev);
2556 static netdev_features_t
2557 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2558 netdev_features_t features)
2560 u32 mss = skb_shinfo(skb)->gso_size;
2561 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2562 int offset = skb_transport_offset(skb);
2564 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2565 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2566 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2567 features &= ~NETIF_F_GSO_MASK;
2572 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2573 struct net_device *netdev)
2575 struct r8152 *tp = netdev_priv(netdev);
2577 skb_tx_timestamp(skb);
2579 skb_queue_tail(&tp->tx_queue, skb);
2581 if (!list_empty(&tp->tx_free)) {
2582 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2583 set_bit(SCHEDULE_TASKLET, &tp->flags);
2584 schedule_delayed_work(&tp->schedule, 0);
2586 usb_mark_last_busy(tp->udev);
2587 tasklet_schedule(&tp->tx_tl);
2589 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2590 netif_stop_queue(netdev);
2593 return NETDEV_TX_OK;
2596 static void r8152b_reset_packet_filter(struct r8152 *tp)
2600 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2601 ocp_data &= ~FMC_FCR_MCU_EN;
2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2603 ocp_data |= FMC_FCR_MCU_EN;
2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2607 static void rtl8152_nic_reset(struct r8152 *tp)
2611 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2613 for (i = 0; i < 1000; i++) {
2614 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2616 usleep_range(100, 400);
2620 static void set_tx_qlen(struct r8152 *tp)
2622 struct net_device *netdev = tp->netdev;
2624 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2625 sizeof(struct tx_desc));
2628 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2630 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2633 static void rtl_set_eee_plus(struct r8152 *tp)
2638 speed = rtl8152_get_speed(tp);
2639 if (speed & _10bps) {
2640 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2641 ocp_data |= EEEP_CR_EEEP_TX;
2642 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2644 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2645 ocp_data &= ~EEEP_CR_EEEP_TX;
2646 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2650 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2654 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2656 ocp_data |= RXDY_GATED_EN;
2658 ocp_data &= ~RXDY_GATED_EN;
2659 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2662 static int rtl_start_rx(struct r8152 *tp)
2664 struct rx_agg *agg, *agg_next;
2665 struct list_head tmp_list;
2666 unsigned long flags;
2669 INIT_LIST_HEAD(&tmp_list);
2671 spin_lock_irqsave(&tp->rx_lock, flags);
2673 INIT_LIST_HEAD(&tp->rx_done);
2674 INIT_LIST_HEAD(&tp->rx_used);
2676 list_splice_init(&tp->rx_info, &tmp_list);
2678 spin_unlock_irqrestore(&tp->rx_lock, flags);
2680 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2681 INIT_LIST_HEAD(&agg->list);
2683 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2684 if (++i > RTL8152_MAX_RX) {
2685 spin_lock_irqsave(&tp->rx_lock, flags);
2686 list_add_tail(&agg->list, &tp->rx_used);
2687 spin_unlock_irqrestore(&tp->rx_lock, flags);
2688 } else if (unlikely(ret < 0)) {
2689 spin_lock_irqsave(&tp->rx_lock, flags);
2690 list_add_tail(&agg->list, &tp->rx_done);
2691 spin_unlock_irqrestore(&tp->rx_lock, flags);
2693 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2697 spin_lock_irqsave(&tp->rx_lock, flags);
2698 WARN_ON(!list_empty(&tp->rx_info));
2699 list_splice(&tmp_list, &tp->rx_info);
2700 spin_unlock_irqrestore(&tp->rx_lock, flags);
2705 static int rtl_stop_rx(struct r8152 *tp)
2707 struct rx_agg *agg, *agg_next;
2708 struct list_head tmp_list;
2709 unsigned long flags;
2711 INIT_LIST_HEAD(&tmp_list);
2713 /* The usb_kill_urb() couldn't be used in atomic.
2714 * Therefore, move the list of rx_info to a tmp one.
2715 * Then, list_for_each_entry_safe could be used without
2719 spin_lock_irqsave(&tp->rx_lock, flags);
2720 list_splice_init(&tp->rx_info, &tmp_list);
2721 spin_unlock_irqrestore(&tp->rx_lock, flags);
2723 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2724 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2725 * equal to 1, so the other ones could be freed safely.
2727 if (page_count(agg->page) > 1)
2728 free_rx_agg(tp, agg);
2730 usb_kill_urb(agg->urb);
2733 /* Move back the list of temp to the rx_info */
2734 spin_lock_irqsave(&tp->rx_lock, flags);
2735 WARN_ON(!list_empty(&tp->rx_info));
2736 list_splice(&tmp_list, &tp->rx_info);
2737 spin_unlock_irqrestore(&tp->rx_lock, flags);
2739 while (!skb_queue_empty(&tp->rx_queue))
2740 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2745 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2747 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2748 OWN_UPDATE | OWN_CLEAR);
2751 static int rtl_enable(struct r8152 *tp)
2755 r8152b_reset_packet_filter(tp);
2757 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2758 ocp_data |= CR_RE | CR_TE;
2759 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2761 switch (tp->version) {
2764 r8153b_rx_agg_chg_indicate(tp);
2770 rxdy_gated_en(tp, false);
2775 static int rtl8152_enable(struct r8152 *tp)
2777 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2781 rtl_set_eee_plus(tp);
2783 return rtl_enable(tp);
2786 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2788 u32 ocp_data = tp->coalesce / 8;
2790 switch (tp->version) {
2795 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2801 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2802 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2804 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2806 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2815 static void r8153_set_rx_early_size(struct r8152 *tp)
2817 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2819 switch (tp->version) {
2824 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2829 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2838 static int rtl8153_enable(struct r8152 *tp)
2840 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2844 rtl_set_eee_plus(tp);
2845 r8153_set_rx_early_timeout(tp);
2846 r8153_set_rx_early_size(tp);
2848 if (tp->version == RTL_VER_09) {
2851 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2852 ocp_data &= ~FC_PATCH_TASK;
2853 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2854 usleep_range(1000, 2000);
2855 ocp_data |= FC_PATCH_TASK;
2856 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2859 return rtl_enable(tp);
2862 static void rtl_disable(struct r8152 *tp)
2867 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2868 rtl_drop_queued_tx(tp);
2872 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2873 ocp_data &= ~RCR_ACPT_ALL;
2874 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2876 rtl_drop_queued_tx(tp);
2878 for (i = 0; i < RTL8152_MAX_TX; i++)
2879 usb_kill_urb(tp->tx_info[i].urb);
2881 rxdy_gated_en(tp, true);
2883 for (i = 0; i < 1000; i++) {
2884 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2885 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2887 usleep_range(1000, 2000);
2890 for (i = 0; i < 1000; i++) {
2891 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2893 usleep_range(1000, 2000);
2898 rtl8152_nic_reset(tp);
2901 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2905 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2907 ocp_data |= POWER_CUT;
2909 ocp_data &= ~POWER_CUT;
2910 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2912 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2913 ocp_data &= ~RESUME_INDICATE;
2914 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2917 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2921 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2923 ocp_data |= CPCR_RX_VLAN;
2925 ocp_data &= ~CPCR_RX_VLAN;
2926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2929 static int rtl8152_set_features(struct net_device *dev,
2930 netdev_features_t features)
2932 netdev_features_t changed = features ^ dev->features;
2933 struct r8152 *tp = netdev_priv(dev);
2936 ret = usb_autopm_get_interface(tp->intf);
2940 mutex_lock(&tp->control);
2942 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2943 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2944 rtl_rx_vlan_en(tp, true);
2946 rtl_rx_vlan_en(tp, false);
2949 mutex_unlock(&tp->control);
2951 usb_autopm_put_interface(tp->intf);
2957 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2959 static u32 __rtl_get_wol(struct r8152 *tp)
2964 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2965 if (ocp_data & LINK_ON_WAKE_EN)
2966 wolopts |= WAKE_PHY;
2968 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2969 if (ocp_data & UWF_EN)
2970 wolopts |= WAKE_UCAST;
2971 if (ocp_data & BWF_EN)
2972 wolopts |= WAKE_BCAST;
2973 if (ocp_data & MWF_EN)
2974 wolopts |= WAKE_MCAST;
2976 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2977 if (ocp_data & MAGIC_EN)
2978 wolopts |= WAKE_MAGIC;
2983 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2989 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2990 ocp_data &= ~LINK_ON_WAKE_EN;
2991 if (wolopts & WAKE_PHY)
2992 ocp_data |= LINK_ON_WAKE_EN;
2993 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2995 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2996 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2997 if (wolopts & WAKE_UCAST)
2999 if (wolopts & WAKE_BCAST)
3001 if (wolopts & WAKE_MCAST)
3003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3005 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3007 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3008 ocp_data &= ~MAGIC_EN;
3009 if (wolopts & WAKE_MAGIC)
3010 ocp_data |= MAGIC_EN;
3011 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3013 if (wolopts & WAKE_ANY)
3014 device_set_wakeup_enable(&tp->udev->dev, true);
3016 device_set_wakeup_enable(&tp->udev->dev, false);
3019 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3021 /* MAC clock speed down */
3023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3028 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3029 U1U2_SPDWN_EN | L1_SPDWN_EN);
3030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3031 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3032 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3035 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3036 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3037 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3038 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3042 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3047 memset(u1u2, 0xff, sizeof(u1u2));
3049 memset(u1u2, 0x00, sizeof(u1u2));
3051 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3054 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3058 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3060 ocp_data |= LPM_U1U2_EN;
3062 ocp_data &= ~LPM_U1U2_EN;
3064 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3067 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3071 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3073 ocp_data |= U2P3_ENABLE;
3075 ocp_data &= ~U2P3_ENABLE;
3076 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3079 static void r8153b_ups_flags(struct r8152 *tp)
3083 if (tp->ups_info.green)
3084 ups_flags |= UPS_FLAGS_EN_GREEN;
3086 if (tp->ups_info.aldps)
3087 ups_flags |= UPS_FLAGS_EN_ALDPS;
3089 if (tp->ups_info.eee)
3090 ups_flags |= UPS_FLAGS_EN_EEE;
3092 if (tp->ups_info.flow_control)
3093 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3095 if (tp->ups_info.eee_ckdiv)
3096 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3098 if (tp->ups_info.eee_cmod_lv)
3099 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3101 if (tp->ups_info._10m_ckdiv)
3102 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3104 if (tp->ups_info.eee_plloff_100)
3105 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3107 if (tp->ups_info.eee_plloff_giga)
3108 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3110 if (tp->ups_info._250m_ckdiv)
3111 ups_flags |= UPS_FLAGS_250M_CKDIV;
3113 if (tp->ups_info.ctap_short_off)
3114 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3116 switch (tp->ups_info.speed_duplex) {
3118 ups_flags |= ups_flags_speed(1);
3121 ups_flags |= ups_flags_speed(2);
3123 case NWAY_100M_HALF:
3124 ups_flags |= ups_flags_speed(3);
3126 case NWAY_100M_FULL:
3127 ups_flags |= ups_flags_speed(4);
3129 case NWAY_1000M_FULL:
3130 ups_flags |= ups_flags_speed(5);
3132 case FORCE_10M_HALF:
3133 ups_flags |= ups_flags_speed(6);
3135 case FORCE_10M_FULL:
3136 ups_flags |= ups_flags_speed(7);
3138 case FORCE_100M_HALF:
3139 ups_flags |= ups_flags_speed(8);
3141 case FORCE_100M_FULL:
3142 ups_flags |= ups_flags_speed(9);
3148 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3151 static void r8153b_green_en(struct r8152 *tp, bool enable)
3156 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3157 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3158 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3160 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3161 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3162 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3165 data = sram_read(tp, SRAM_GREEN_CFG);
3166 data |= GREEN_ETH_EN;
3167 sram_write(tp, SRAM_GREEN_CFG, data);
3169 tp->ups_info.green = enable;
3172 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3177 for (i = 0; i < 500; i++) {
3178 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3179 data &= PHY_STAT_MASK;
3181 if (data == desired)
3183 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3184 data == PHY_STAT_EXT_INIT) {
3189 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3196 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3198 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3201 r8153b_ups_flags(tp);
3203 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3204 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3206 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3208 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3212 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3213 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3215 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3216 ocp_data &= ~BIT(0);
3217 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3219 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3220 ocp_data &= ~PCUT_STATUS;
3221 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3223 data = r8153_phy_status(tp, 0);
3226 case PHY_STAT_PWRDN:
3227 case PHY_STAT_EXT_INIT:
3229 test_bit(GREEN_ETHERNET, &tp->flags));
3231 data = r8152_mdio_read(tp, MII_BMCR);
3232 data &= ~BMCR_PDOWN;
3234 r8152_mdio_write(tp, MII_BMCR, data);
3236 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3240 if (data != PHY_STAT_LAN_ON)
3241 netif_warn(tp, link, tp->netdev,
3248 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3252 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3254 ocp_data |= PWR_EN | PHASE2_EN;
3256 ocp_data &= ~(PWR_EN | PHASE2_EN);
3257 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3259 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3260 ocp_data &= ~PCUT_STATUS;
3261 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3264 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3268 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3270 ocp_data |= PWR_EN | PHASE2_EN;
3272 ocp_data &= ~PWR_EN;
3273 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3275 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3276 ocp_data &= ~PCUT_STATUS;
3277 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3280 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3284 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3286 ocp_data |= UPCOMING_RUNTIME_D3;
3288 ocp_data &= ~UPCOMING_RUNTIME_D3;
3289 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3291 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3292 ocp_data &= ~LINK_CHG_EVENT;
3293 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3295 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3296 ocp_data &= ~LINK_CHANGE_FLAG;
3297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3300 static bool rtl_can_wakeup(struct r8152 *tp)
3302 struct usb_device *udev = tp->udev;
3304 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3307 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3312 __rtl_set_wol(tp, WAKE_ANY);
3314 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3316 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3317 ocp_data |= LINK_OFF_WAKE_EN;
3318 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3320 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3324 __rtl_set_wol(tp, tp->saved_wolopts);
3326 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3329 ocp_data &= ~LINK_OFF_WAKE_EN;
3330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3332 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3336 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3339 r8153_u1u2en(tp, false);
3340 r8153_u2p3en(tp, false);
3341 r8153_mac_clk_spd(tp, true);
3342 rtl_runtime_suspend_enable(tp, true);
3344 rtl_runtime_suspend_enable(tp, false);
3345 r8153_mac_clk_spd(tp, false);
3347 switch (tp->version) {
3354 r8153_u2p3en(tp, true);
3358 r8153_u1u2en(tp, true);
3362 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3365 r8153_queue_wake(tp, true);
3366 r8153b_u1u2en(tp, false);
3367 r8153_u2p3en(tp, false);
3368 rtl_runtime_suspend_enable(tp, true);
3369 r8153b_ups_en(tp, true);
3371 r8153b_ups_en(tp, false);
3372 r8153_queue_wake(tp, false);
3373 rtl_runtime_suspend_enable(tp, false);
3374 if (tp->udev->speed != USB_SPEED_HIGH)
3375 r8153b_u1u2en(tp, true);
3379 static void r8153_teredo_off(struct r8152 *tp)
3383 switch (tp->version) {
3391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3392 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3394 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3399 /* The bit 0 ~ 7 are relative with teredo settings. They are
3400 * W1C (write 1 to clear), so set all 1 to disable it.
3402 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3409 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3410 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3411 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3414 static void rtl_reset_bmu(struct r8152 *tp)
3418 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3419 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3420 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3421 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3422 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3425 /* Clear the bp to stop the firmware before loading a new one */
3426 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3428 switch (tp->version) {
3437 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3442 if (type == MCU_TYPE_USB) {
3443 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3445 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3446 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3447 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3448 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3449 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3450 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3451 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3452 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3454 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3459 ocp_write_word(tp, type, PLA_BP_0, 0);
3460 ocp_write_word(tp, type, PLA_BP_1, 0);
3461 ocp_write_word(tp, type, PLA_BP_2, 0);
3462 ocp_write_word(tp, type, PLA_BP_3, 0);
3463 ocp_write_word(tp, type, PLA_BP_4, 0);
3464 ocp_write_word(tp, type, PLA_BP_5, 0);
3465 ocp_write_word(tp, type, PLA_BP_6, 0);
3466 ocp_write_word(tp, type, PLA_BP_7, 0);
3468 /* wait 3 ms to make sure the firmware is stopped */
3469 usleep_range(3000, 6000);
3470 ocp_write_word(tp, type, PLA_BP_BA, 0);
3473 static int r8153_patch_request(struct r8152 *tp, bool request)
3478 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3480 data |= PATCH_REQUEST;
3482 data &= ~PATCH_REQUEST;
3483 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3485 for (i = 0; request && i < 5000; i++) {
3486 usleep_range(1000, 2000);
3487 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3491 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3492 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3493 r8153_patch_request(tp, false);
3500 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3502 if (r8153_patch_request(tp, true)) {
3503 dev_err(&tp->intf->dev, "patch request fail\n");
3507 sram_write(tp, key_addr, patch_key);
3508 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3513 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3517 sram_write(tp, 0x0000, 0x0000);
3519 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3520 data &= ~PATCH_LOCK;
3521 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3523 sram_write(tp, key_addr, 0x0000);
3525 r8153_patch_request(tp, false);
3527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3532 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3535 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3538 switch (tp->version) {
3544 patch_en_addr = 0xa01a;
3552 fw_offset = __le16_to_cpu(phy->fw_offset);
3553 if (fw_offset < sizeof(*phy)) {
3554 dev_err(&tp->intf->dev, "fw_offset too small\n");
3558 length = __le32_to_cpu(phy->blk_hdr.length);
3559 if (length < fw_offset) {
3560 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3564 length -= __le16_to_cpu(phy->fw_offset);
3565 if (!length || (length & 1)) {
3566 dev_err(&tp->intf->dev, "invalid block length\n");
3570 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3571 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3575 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3576 dev_err(&tp->intf->dev, "invalid base address register\n");
3580 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3581 dev_err(&tp->intf->dev,
3582 "invalid patch mode enabled register\n");
3586 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3587 dev_err(&tp->intf->dev,
3588 "invalid register to switch the mode\n");
3592 if (__le16_to_cpu(phy->bp_start) != bp_start) {
3593 dev_err(&tp->intf->dev,
3594 "invalid start register of break point\n");
3598 if (__le16_to_cpu(phy->bp_num) > 4) {
3599 dev_err(&tp->intf->dev, "invalid break point number\n");
3608 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3610 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3615 type = __le32_to_cpu(mac->blk_hdr.type);
3616 if (type == RTL_FW_PLA) {
3617 switch (tp->version) {
3622 bp_ba_addr = PLA_BP_BA;
3624 bp_start = PLA_BP_0;
3634 bp_ba_addr = PLA_BP_BA;
3635 bp_en_addr = PLA_BP_EN;
3636 bp_start = PLA_BP_0;
3642 } else if (type == RTL_FW_USB) {
3643 switch (tp->version) {
3649 bp_ba_addr = USB_BP_BA;
3650 bp_en_addr = USB_BP_EN;
3651 bp_start = USB_BP_0;
3657 bp_ba_addr = USB_BP_BA;
3658 bp_en_addr = USB_BP2_EN;
3659 bp_start = USB_BP_0;
3672 fw_offset = __le16_to_cpu(mac->fw_offset);
3673 if (fw_offset < sizeof(*mac)) {
3674 dev_err(&tp->intf->dev, "fw_offset too small\n");
3678 length = __le32_to_cpu(mac->blk_hdr.length);
3679 if (length < fw_offset) {
3680 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3684 length -= fw_offset;
3685 if (length < 4 || (length & 3)) {
3686 dev_err(&tp->intf->dev, "invalid block length\n");
3690 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3691 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3695 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3696 dev_err(&tp->intf->dev, "invalid base address register\n");
3700 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3701 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3705 if (__le16_to_cpu(mac->bp_start) != bp_start) {
3706 dev_err(&tp->intf->dev,
3707 "invalid start register of break point\n");
3711 if (__le16_to_cpu(mac->bp_num) > max_bp) {
3712 dev_err(&tp->intf->dev, "invalid break point number\n");
3716 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3718 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3728 /* Verify the checksum for the firmware file. It is calculated from the version
3729 * field to the end of the file. Compare the result with the checksum field to
3730 * make sure the file is correct.
3732 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3733 struct fw_header *fw_hdr, size_t size)
3735 unsigned char checksum[sizeof(fw_hdr->checksum)];
3736 struct crypto_shash *alg;
3737 struct shash_desc *sdesc;
3741 alg = crypto_alloc_shash("sha256", 0, 0);
3747 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3749 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3750 crypto_shash_digestsize(alg));
3754 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3755 sdesc = kmalloc(len, GFP_KERNEL);
3762 len = size - sizeof(fw_hdr->checksum);
3763 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3768 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3769 dev_err(&tp->intf->dev, "checksum fail\n");
3774 crypto_free_shash(alg);
3779 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3781 const struct firmware *fw = rtl_fw->fw;
3782 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3783 struct fw_mac *pla = NULL, *usb = NULL;
3784 struct fw_phy_patch_key *start = NULL;
3785 struct fw_phy_nc *phy_nc = NULL;
3786 struct fw_block *stop = NULL;
3790 if (fw->size < sizeof(*fw_hdr)) {
3791 dev_err(&tp->intf->dev, "file too small\n");
3795 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3801 for (i = sizeof(*fw_hdr); i < fw->size;) {
3802 struct fw_block *block = (struct fw_block *)&fw->data[i];
3805 if ((i + sizeof(*block)) > fw->size)
3808 type = __le32_to_cpu(block->type);
3811 if (__le32_to_cpu(block->length) != sizeof(*block))
3816 dev_err(&tp->intf->dev,
3817 "multiple PLA firmware encountered");
3821 pla = (struct fw_mac *)block;
3822 if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3823 dev_err(&tp->intf->dev,
3824 "check PLA firmware failed\n");
3830 dev_err(&tp->intf->dev,
3831 "multiple USB firmware encountered");
3835 usb = (struct fw_mac *)block;
3836 if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3837 dev_err(&tp->intf->dev,
3838 "check USB firmware failed\n");
3842 case RTL_FW_PHY_START:
3843 if (start || phy_nc || stop) {
3844 dev_err(&tp->intf->dev,
3845 "check PHY_START fail\n");
3849 if (__le32_to_cpu(block->length) != sizeof(*start)) {
3850 dev_err(&tp->intf->dev,
3851 "Invalid length for PHY_START\n");
3855 start = (struct fw_phy_patch_key *)block;
3857 case RTL_FW_PHY_STOP:
3858 if (stop || !start) {
3859 dev_err(&tp->intf->dev,
3860 "Check PHY_STOP fail\n");
3864 if (__le32_to_cpu(block->length) != sizeof(*block)) {
3865 dev_err(&tp->intf->dev,
3866 "Invalid length for PHY_STOP\n");
3873 if (!start || stop) {
3874 dev_err(&tp->intf->dev,
3875 "check PHY_NC fail\n");
3880 dev_err(&tp->intf->dev,
3881 "multiple PHY NC encountered\n");
3885 phy_nc = (struct fw_phy_nc *)block;
3886 if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3887 dev_err(&tp->intf->dev,
3888 "check PHY NC firmware failed\n");
3894 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3900 i += ALIGN(__le32_to_cpu(block->length), 8);
3904 if ((phy_nc || start) && !stop) {
3905 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3914 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3916 u16 mode_reg, bp_index;
3920 mode_reg = __le16_to_cpu(phy->mode_reg);
3921 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3922 sram_write(tp, __le16_to_cpu(phy->ba_reg),
3923 __le16_to_cpu(phy->ba_data));
3925 length = __le32_to_cpu(phy->blk_hdr.length);
3926 length -= __le16_to_cpu(phy->fw_offset);
3928 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3930 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3931 for (i = 0; i < num; i++)
3932 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3934 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3935 __le16_to_cpu(phy->patch_en_value));
3937 bp_index = __le16_to_cpu(phy->bp_start);
3938 num = __le16_to_cpu(phy->bp_num);
3939 for (i = 0; i < num; i++) {
3940 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3944 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3946 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3949 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3951 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3956 switch (__le32_to_cpu(mac->blk_hdr.type)) {
3958 type = MCU_TYPE_PLA;
3961 type = MCU_TYPE_USB;
3967 rtl_clear_bp(tp, type);
3969 /* Enable backup/restore of MACDBG. This is required after clearing PLA
3970 * break points and before applying the PLA firmware.
3972 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3973 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3975 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3978 length = __le32_to_cpu(mac->blk_hdr.length);
3979 length -= __le16_to_cpu(mac->fw_offset);
3982 data += __le16_to_cpu(mac->fw_offset);
3984 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3987 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3988 __le16_to_cpu(mac->bp_ba_value));
3990 bp_index = __le16_to_cpu(mac->bp_start);
3991 bp_num = __le16_to_cpu(mac->bp_num);
3992 for (i = 0; i < bp_num; i++) {
3993 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3997 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3999 ocp_write_word(tp, type, bp_en_addr,
4000 __le16_to_cpu(mac->bp_en_value));
4002 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4004 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4007 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4010 static void rtl8152_apply_firmware(struct r8152 *tp)
4012 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4013 const struct firmware *fw;
4014 struct fw_header *fw_hdr;
4015 struct fw_phy_patch_key *key;
4019 if (IS_ERR_OR_NULL(rtl_fw->fw))
4023 fw_hdr = (struct fw_header *)fw->data;
4028 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4029 struct fw_block *block = (struct fw_block *)&fw->data[i];
4031 switch (__le32_to_cpu(block->type)) {
4036 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4038 case RTL_FW_PHY_START:
4039 key = (struct fw_phy_patch_key *)block;
4040 key_addr = __le16_to_cpu(key->key_reg);
4041 r8153_pre_ram_code(tp, key_addr,
4042 __le16_to_cpu(key->key_data));
4044 case RTL_FW_PHY_STOP:
4046 r8153_post_ram_code(tp, key_addr);
4049 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4055 i += ALIGN(__le32_to_cpu(block->length), 8);
4059 if (rtl_fw->post_fw)
4060 rtl_fw->post_fw(tp);
4062 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4063 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4066 static void rtl8152_release_firmware(struct r8152 *tp)
4068 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4070 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4071 release_firmware(rtl_fw->fw);
4076 static int rtl8152_request_firmware(struct r8152 *tp)
4078 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4081 if (rtl_fw->fw || !rtl_fw->fw_name) {
4082 dev_info(&tp->intf->dev, "skip request firmware\n");
4087 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4091 rc = rtl8152_check_firmware(tp, rtl_fw);
4093 release_firmware(rtl_fw->fw);
4097 rtl_fw->fw = ERR_PTR(rc);
4099 dev_warn(&tp->intf->dev,
4100 "unable to load firmware patch %s (%ld)\n",
4101 rtl_fw->fw_name, rc);
4107 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4110 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4111 LINKENA | DIS_SDSAVE);
4113 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4119 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4121 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4122 ocp_reg_write(tp, OCP_EEE_DATA, reg);
4123 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4126 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4130 r8152_mmd_indirect(tp, dev, reg);
4131 data = ocp_reg_read(tp, OCP_EEE_DATA);
4132 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4137 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4139 r8152_mmd_indirect(tp, dev, reg);
4140 ocp_reg_write(tp, OCP_EEE_DATA, data);
4141 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4144 static void r8152_eee_en(struct r8152 *tp, bool enable)
4146 u16 config1, config2, config3;
4149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4150 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4151 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4152 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4155 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4156 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4157 config1 |= sd_rise_time(1);
4158 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4159 config3 |= fast_snr(42);
4161 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4162 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4164 config1 |= sd_rise_time(7);
4165 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4166 config3 |= fast_snr(511);
4169 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4170 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4171 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4172 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4175 static void r8153_eee_en(struct r8152 *tp, bool enable)
4180 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4181 config = ocp_reg_read(tp, OCP_EEE_CFG);
4184 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4187 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4188 config &= ~EEE10_EN;
4191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4192 ocp_reg_write(tp, OCP_EEE_CFG, config);
4194 tp->ups_info.eee = enable;
4197 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4199 switch (tp->version) {
4204 r8152_eee_en(tp, true);
4205 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4208 r8152_eee_en(tp, false);
4209 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4219 r8153_eee_en(tp, true);
4220 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4222 r8153_eee_en(tp, false);
4223 ocp_reg_write(tp, OCP_EEE_ADV, 0);
4231 static void r8152b_enable_fc(struct r8152 *tp)
4235 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4236 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4237 r8152_mdio_write(tp, MII_ADVERTISE, anar);
4239 tp->ups_info.flow_control = true;
4242 static void rtl8152_disable(struct r8152 *tp)
4244 r8152_aldps_en(tp, false);
4246 r8152_aldps_en(tp, true);
4249 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4251 rtl8152_apply_firmware(tp);
4252 rtl_eee_enable(tp, tp->eee_en);
4253 r8152_aldps_en(tp, true);
4254 r8152b_enable_fc(tp);
4256 set_bit(PHY_RESET, &tp->flags);
4259 static void wait_oob_link_list_ready(struct r8152 *tp)
4264 for (i = 0; i < 1000; i++) {
4265 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4266 if (ocp_data & LINK_LIST_READY)
4268 usleep_range(1000, 2000);
4272 static void r8152b_exit_oob(struct r8152 *tp)
4276 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4277 ocp_data &= ~RCR_ACPT_ALL;
4278 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4280 rxdy_gated_en(tp, true);
4281 r8153_teredo_off(tp);
4282 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4283 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4285 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4286 ocp_data &= ~NOW_IS_OOB;
4287 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4289 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4290 ocp_data &= ~MCU_BORW_EN;
4291 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4293 wait_oob_link_list_ready(tp);
4295 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4296 ocp_data |= RE_INIT_LL;
4297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4299 wait_oob_link_list_ready(tp);
4301 rtl8152_nic_reset(tp);
4303 /* rx share fifo credit full threshold */
4304 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4306 if (tp->udev->speed == USB_SPEED_FULL ||
4307 tp->udev->speed == USB_SPEED_LOW) {
4308 /* rx share fifo credit near full threshold */
4309 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4311 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4314 /* rx share fifo credit near full threshold */
4315 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4317 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4321 /* TX share fifo free credit full threshold */
4322 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4324 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4325 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4326 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4327 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4329 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4331 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4334 ocp_data |= TCR0_AUTO_FIFO;
4335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4338 static void r8152b_enter_oob(struct r8152 *tp)
4342 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4343 ocp_data &= ~NOW_IS_OOB;
4344 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4346 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4347 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4348 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4352 wait_oob_link_list_ready(tp);
4354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4355 ocp_data |= RE_INIT_LL;
4356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4358 wait_oob_link_list_ready(tp);
4360 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4362 rtl_rx_vlan_en(tp, true);
4364 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4365 ocp_data |= ALDPS_PROXY_MODE;
4366 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4368 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4369 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4370 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4372 rxdy_gated_en(tp, false);
4374 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4375 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4376 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4379 static int r8153_pre_firmware_1(struct r8152 *tp)
4383 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4384 for (i = 0; i < 104; i++) {
4385 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4387 if (!(ocp_data & WTD1_EN))
4389 usleep_range(1000, 2000);
4395 static int r8153_post_firmware_1(struct r8152 *tp)
4397 /* set USB_BP_4 to support USB_SPEED_SUPER only */
4398 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4399 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4401 /* reset UPHY timer to 36 ms */
4402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4407 static int r8153_pre_firmware_2(struct r8152 *tp)
4411 r8153_pre_firmware_1(tp);
4413 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4414 ocp_data &= ~FW_FIX_SUSPEND;
4415 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4420 static int r8153_post_firmware_2(struct r8152 *tp)
4424 /* enable bp0 if support USB_SPEED_SUPER only */
4425 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4426 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4428 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4431 /* reset UPHY timer to 36 ms */
4432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4434 /* enable U3P3 check, set the counter to 4 */
4435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4437 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4438 ocp_data |= FW_FIX_SUSPEND;
4439 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4441 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4442 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4443 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4448 static int r8153_post_firmware_3(struct r8152 *tp)
4452 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4453 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4454 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4456 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4457 ocp_data |= FW_IP_RESET_EN;
4458 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4463 static int r8153b_pre_firmware_1(struct r8152 *tp)
4465 /* enable fc timer and set timer to 1 second. */
4466 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4467 CTRL_TIMER_EN | (1000 / 8));
4472 static int r8153b_post_firmware_1(struct r8152 *tp)
4476 /* enable bp0 for RTL8153-BND */
4477 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4478 if (ocp_data & BND_MASK) {
4479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4481 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4484 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4485 ocp_data |= FLOW_CTRL_PATCH_OPT;
4486 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4488 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4489 ocp_data |= FC_PATCH_TASK;
4490 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4492 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4493 ocp_data |= FW_IP_RESET_EN;
4494 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4499 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4503 data = ocp_reg_read(tp, OCP_POWER_CFG);
4506 ocp_reg_write(tp, OCP_POWER_CFG, data);
4511 ocp_reg_write(tp, OCP_POWER_CFG, data);
4512 for (i = 0; i < 20; i++) {
4513 usleep_range(1000, 2000);
4514 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4519 tp->ups_info.aldps = enable;
4522 static void r8153_hw_phy_cfg(struct r8152 *tp)
4527 /* disable ALDPS before updating the PHY parameters */
4528 r8153_aldps_en(tp, false);
4530 /* disable EEE before updating the PHY parameters */
4531 rtl_eee_enable(tp, false);
4533 rtl8152_apply_firmware(tp);
4535 if (tp->version == RTL_VER_03) {
4536 data = ocp_reg_read(tp, OCP_EEE_CFG);
4537 data &= ~CTAP_SHORT_EN;
4538 ocp_reg_write(tp, OCP_EEE_CFG, data);
4541 data = ocp_reg_read(tp, OCP_POWER_CFG);
4542 data |= EEE_CLKDIV_EN;
4543 ocp_reg_write(tp, OCP_POWER_CFG, data);
4545 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4546 data |= EN_10M_BGOFF;
4547 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4548 data = ocp_reg_read(tp, OCP_POWER_CFG);
4549 data |= EN_10M_PLLOFF;
4550 ocp_reg_write(tp, OCP_POWER_CFG, data);
4551 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4553 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4554 ocp_data |= PFM_PWM_SWITCH;
4555 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4557 /* Enable LPF corner auto tune */
4558 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4560 /* Adjust 10M Amplitude */
4561 sram_write(tp, SRAM_10M_AMP1, 0x00af);
4562 sram_write(tp, SRAM_10M_AMP2, 0x0208);
4565 rtl_eee_enable(tp, true);
4567 r8153_aldps_en(tp, true);
4568 r8152b_enable_fc(tp);
4570 switch (tp->version) {
4577 r8153_u2p3en(tp, true);
4581 set_bit(PHY_RESET, &tp->flags);
4584 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4589 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4590 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
4591 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4596 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4601 /* disable ALDPS before updating the PHY parameters */
4602 r8153_aldps_en(tp, false);
4604 /* disable EEE before updating the PHY parameters */
4605 rtl_eee_enable(tp, false);
4607 rtl8152_apply_firmware(tp);
4609 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4611 data = sram_read(tp, SRAM_GREEN_CFG);
4613 sram_write(tp, SRAM_GREEN_CFG, data);
4614 data = ocp_reg_read(tp, OCP_NCTL_CFG);
4615 data |= PGA_RETURN_EN;
4616 ocp_reg_write(tp, OCP_NCTL_CFG, data);
4618 /* ADC Bias Calibration:
4619 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4620 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4623 ocp_data = r8152_efuse_read(tp, 0x7d);
4624 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4626 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4628 /* ups mode tx-link-pulse timing adjustment:
4629 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4630 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4632 ocp_data = ocp_reg_read(tp, 0xc426);
4635 u32 swr_cnt_1ms_ini;
4637 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4638 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4639 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4640 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4643 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4644 ocp_data |= PFM_PWM_SWITCH;
4645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4648 if (!r8153_patch_request(tp, true)) {
4649 data = ocp_reg_read(tp, OCP_POWER_CFG);
4650 data |= EEE_CLKDIV_EN;
4651 ocp_reg_write(tp, OCP_POWER_CFG, data);
4652 tp->ups_info.eee_ckdiv = true;
4654 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4655 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4656 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4657 tp->ups_info.eee_cmod_lv = true;
4658 tp->ups_info._10m_ckdiv = true;
4659 tp->ups_info.eee_plloff_giga = true;
4661 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4662 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4663 tp->ups_info._250m_ckdiv = true;
4665 r8153_patch_request(tp, false);
4669 rtl_eee_enable(tp, true);
4671 r8153_aldps_en(tp, true);
4672 r8152b_enable_fc(tp);
4674 set_bit(PHY_RESET, &tp->flags);
4677 static void r8153_first_init(struct r8152 *tp)
4681 r8153_mac_clk_spd(tp, false);
4682 rxdy_gated_en(tp, true);
4683 r8153_teredo_off(tp);
4685 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4686 ocp_data &= ~RCR_ACPT_ALL;
4687 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4689 rtl8152_nic_reset(tp);
4692 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4693 ocp_data &= ~NOW_IS_OOB;
4694 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4696 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4697 ocp_data &= ~MCU_BORW_EN;
4698 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4700 wait_oob_link_list_ready(tp);
4702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4703 ocp_data |= RE_INIT_LL;
4704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4706 wait_oob_link_list_ready(tp);
4708 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4710 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4711 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4712 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4714 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4715 ocp_data |= TCR0_AUTO_FIFO;
4716 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4718 rtl8152_nic_reset(tp);
4720 /* rx share fifo credit full threshold */
4721 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4722 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4723 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4724 /* TX share fifo free credit full threshold */
4725 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4728 static void r8153_enter_oob(struct r8152 *tp)
4732 r8153_mac_clk_spd(tp, true);
4734 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4735 ocp_data &= ~NOW_IS_OOB;
4736 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4741 wait_oob_link_list_ready(tp);
4743 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4744 ocp_data |= RE_INIT_LL;
4745 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4747 wait_oob_link_list_ready(tp);
4749 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4750 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4752 switch (tp->version) {
4757 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4758 ocp_data &= ~TEREDO_WAKE_MASK;
4759 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4764 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4765 * type. Set it to zero. bits[7:0] are the W1C bits about
4766 * the events. Set them to all 1 to clear them.
4768 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4775 rtl_rx_vlan_en(tp, true);
4777 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4778 ocp_data |= ALDPS_PROXY_MODE;
4779 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4781 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4782 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4783 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4785 rxdy_gated_en(tp, false);
4787 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4788 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4789 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4792 static void rtl8153_disable(struct r8152 *tp)
4794 r8153_aldps_en(tp, false);
4797 r8153_aldps_en(tp, true);
4800 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4806 if (autoneg == AUTONEG_DISABLE) {
4807 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4812 bmcr = BMCR_SPEED10;
4813 if (duplex == DUPLEX_FULL) {
4814 bmcr |= BMCR_FULLDPLX;
4815 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4817 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4821 bmcr = BMCR_SPEED100;
4822 if (duplex == DUPLEX_FULL) {
4823 bmcr |= BMCR_FULLDPLX;
4824 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4826 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4830 if (tp->mii.supports_gmii) {
4831 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4832 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4841 if (duplex == DUPLEX_FULL)
4842 tp->mii.full_duplex = 1;
4844 tp->mii.full_duplex = 0;
4846 tp->mii.force_media = 1;
4851 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4852 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4854 if (tp->mii.supports_gmii)
4855 support |= RTL_ADVERTISED_1000_FULL;
4857 if (!(advertising & support))
4860 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4861 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4862 ADVERTISE_100HALF | ADVERTISE_100FULL);
4863 if (advertising & RTL_ADVERTISED_10_HALF) {
4864 tmp1 |= ADVERTISE_10HALF;
4865 tp->ups_info.speed_duplex = NWAY_10M_HALF;
4867 if (advertising & RTL_ADVERTISED_10_FULL) {
4868 tmp1 |= ADVERTISE_10FULL;
4869 tp->ups_info.speed_duplex = NWAY_10M_FULL;
4872 if (advertising & RTL_ADVERTISED_100_HALF) {
4873 tmp1 |= ADVERTISE_100HALF;
4874 tp->ups_info.speed_duplex = NWAY_100M_HALF;
4876 if (advertising & RTL_ADVERTISED_100_FULL) {
4877 tmp1 |= ADVERTISE_100FULL;
4878 tp->ups_info.speed_duplex = NWAY_100M_FULL;
4882 r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4883 tp->mii.advertising = tmp1;
4886 if (tp->mii.supports_gmii) {
4889 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4890 tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4891 ADVERTISE_1000HALF);
4893 if (advertising & RTL_ADVERTISED_1000_FULL) {
4894 tmp1 |= ADVERTISE_1000FULL;
4895 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4899 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4902 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4904 tp->mii.force_media = 0;
4907 if (test_and_clear_bit(PHY_RESET, &tp->flags))
4910 r8152_mdio_write(tp, MII_BMCR, bmcr);
4912 if (bmcr & BMCR_RESET) {
4915 for (i = 0; i < 50; i++) {
4917 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4926 static void rtl8152_up(struct r8152 *tp)
4928 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4931 r8152_aldps_en(tp, false);
4932 r8152b_exit_oob(tp);
4933 r8152_aldps_en(tp, true);
4936 static void rtl8152_down(struct r8152 *tp)
4938 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4939 rtl_drop_queued_tx(tp);
4943 r8152_power_cut_en(tp, false);
4944 r8152_aldps_en(tp, false);
4945 r8152b_enter_oob(tp);
4946 r8152_aldps_en(tp, true);
4949 static void rtl8153_up(struct r8152 *tp)
4953 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4956 r8153_u1u2en(tp, false);
4957 r8153_u2p3en(tp, false);
4958 r8153_aldps_en(tp, false);
4959 r8153_first_init(tp);
4961 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4962 ocp_data |= LANWAKE_CLR_EN;
4963 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4965 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4966 ocp_data &= ~LANWAKE_PIN;
4967 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4969 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4970 ocp_data &= ~DELAY_PHY_PWR_CHG;
4971 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4973 r8153_aldps_en(tp, true);
4975 switch (tp->version) {
4982 r8153_u2p3en(tp, true);
4986 r8153_u1u2en(tp, true);
4989 static void rtl8153_down(struct r8152 *tp)
4993 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4994 rtl_drop_queued_tx(tp);
4998 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4999 ocp_data &= ~LANWAKE_CLR_EN;
5000 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5002 r8153_u1u2en(tp, false);
5003 r8153_u2p3en(tp, false);
5004 r8153_power_cut_en(tp, false);
5005 r8153_aldps_en(tp, false);
5006 r8153_enter_oob(tp);
5007 r8153_aldps_en(tp, true);
5010 static void rtl8153b_up(struct r8152 *tp)
5014 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5017 r8153b_u1u2en(tp, false);
5018 r8153_u2p3en(tp, false);
5019 r8153_aldps_en(tp, false);
5021 r8153_first_init(tp);
5022 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5024 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5025 ocp_data &= ~PLA_MCU_SPDWN_EN;
5026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5028 r8153_aldps_en(tp, true);
5030 if (tp->udev->speed != USB_SPEED_HIGH)
5031 r8153b_u1u2en(tp, true);
5034 static void rtl8153b_down(struct r8152 *tp)
5038 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5039 rtl_drop_queued_tx(tp);
5043 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5044 ocp_data |= PLA_MCU_SPDWN_EN;
5045 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5047 r8153b_u1u2en(tp, false);
5048 r8153_u2p3en(tp, false);
5049 r8153b_power_cut_en(tp, false);
5050 r8153_aldps_en(tp, false);
5051 r8153_enter_oob(tp);
5052 r8153_aldps_en(tp, true);
5055 static bool rtl8152_in_nway(struct r8152 *tp)
5059 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5060 tp->ocp_base = 0x2000;
5061 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
5062 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5064 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5065 if (nway_state & 0xc000)
5071 static bool rtl8153_in_nway(struct r8152 *tp)
5073 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5075 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5081 static void set_carrier(struct r8152 *tp)
5083 struct net_device *netdev = tp->netdev;
5084 struct napi_struct *napi = &tp->napi;
5087 speed = rtl8152_get_speed(tp);
5089 if (speed & LINK_STATUS) {
5090 if (!netif_carrier_ok(netdev)) {
5091 tp->rtl_ops.enable(tp);
5092 netif_stop_queue(netdev);
5094 netif_carrier_on(netdev);
5096 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5097 _rtl8152_set_rx_mode(netdev);
5098 napi_enable(&tp->napi);
5099 netif_wake_queue(netdev);
5100 netif_info(tp, link, netdev, "carrier on\n");
5101 } else if (netif_queue_stopped(netdev) &&
5102 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5103 netif_wake_queue(netdev);
5106 if (netif_carrier_ok(netdev)) {
5107 netif_carrier_off(netdev);
5108 tasklet_disable(&tp->tx_tl);
5110 tp->rtl_ops.disable(tp);
5112 tasklet_enable(&tp->tx_tl);
5113 netif_info(tp, link, netdev, "carrier off\n");
5118 static void rtl_work_func_t(struct work_struct *work)
5120 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5122 /* If the device is unplugged or !netif_running(), the workqueue
5123 * doesn't need to wake the device, and could return directly.
5125 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5128 if (usb_autopm_get_interface(tp->intf) < 0)
5131 if (!test_bit(WORK_ENABLE, &tp->flags))
5134 if (!mutex_trylock(&tp->control)) {
5135 schedule_delayed_work(&tp->schedule, 0);
5139 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5142 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5143 _rtl8152_set_rx_mode(tp->netdev);
5145 /* don't schedule tasket before linking */
5146 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5147 netif_carrier_ok(tp->netdev))
5148 tasklet_schedule(&tp->tx_tl);
5150 mutex_unlock(&tp->control);
5153 usb_autopm_put_interface(tp->intf);
5156 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5158 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5160 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5163 if (usb_autopm_get_interface(tp->intf) < 0)
5166 mutex_lock(&tp->control);
5168 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5169 tp->rtl_fw.retry = false;
5170 tp->rtl_fw.fw = NULL;
5172 /* Delay execution in case request_firmware() is not ready yet.
5174 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5178 tp->rtl_ops.hw_phy_cfg(tp);
5180 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5184 mutex_unlock(&tp->control);
5186 usb_autopm_put_interface(tp->intf);
5189 #ifdef CONFIG_PM_SLEEP
5190 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5193 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5196 case PM_HIBERNATION_PREPARE:
5197 case PM_SUSPEND_PREPARE:
5198 usb_autopm_get_interface(tp->intf);
5201 case PM_POST_HIBERNATION:
5202 case PM_POST_SUSPEND:
5203 usb_autopm_put_interface(tp->intf);
5206 case PM_POST_RESTORE:
5207 case PM_RESTORE_PREPARE:
5216 static int rtl8152_open(struct net_device *netdev)
5218 struct r8152 *tp = netdev_priv(netdev);
5221 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5222 cancel_delayed_work_sync(&tp->hw_phy_work);
5223 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5226 res = alloc_all_mem(tp);
5230 res = usb_autopm_get_interface(tp->intf);
5234 mutex_lock(&tp->control);
5238 netif_carrier_off(netdev);
5239 netif_start_queue(netdev);
5240 set_bit(WORK_ENABLE, &tp->flags);
5242 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5245 netif_device_detach(tp->netdev);
5246 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5250 napi_enable(&tp->napi);
5251 tasklet_enable(&tp->tx_tl);
5253 mutex_unlock(&tp->control);
5255 usb_autopm_put_interface(tp->intf);
5256 #ifdef CONFIG_PM_SLEEP
5257 tp->pm_notifier.notifier_call = rtl_notifier;
5258 register_pm_notifier(&tp->pm_notifier);
5263 mutex_unlock(&tp->control);
5264 usb_autopm_put_interface(tp->intf);
5271 static int rtl8152_close(struct net_device *netdev)
5273 struct r8152 *tp = netdev_priv(netdev);
5276 #ifdef CONFIG_PM_SLEEP
5277 unregister_pm_notifier(&tp->pm_notifier);
5279 tasklet_disable(&tp->tx_tl);
5280 clear_bit(WORK_ENABLE, &tp->flags);
5281 usb_kill_urb(tp->intr_urb);
5282 cancel_delayed_work_sync(&tp->schedule);
5283 napi_disable(&tp->napi);
5284 netif_stop_queue(netdev);
5286 res = usb_autopm_get_interface(tp->intf);
5287 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5288 rtl_drop_queued_tx(tp);
5291 mutex_lock(&tp->control);
5293 tp->rtl_ops.down(tp);
5295 mutex_unlock(&tp->control);
5297 usb_autopm_put_interface(tp->intf);
5305 static void rtl_tally_reset(struct r8152 *tp)
5309 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5310 ocp_data |= TALLY_RESET;
5311 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5314 static void r8152b_init(struct r8152 *tp)
5319 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5322 data = r8152_mdio_read(tp, MII_BMCR);
5323 if (data & BMCR_PDOWN) {
5324 data &= ~BMCR_PDOWN;
5325 r8152_mdio_write(tp, MII_BMCR, data);
5328 r8152_aldps_en(tp, false);
5330 if (tp->version == RTL_VER_01) {
5331 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5332 ocp_data &= ~LED_MODE_MASK;
5333 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5336 r8152_power_cut_en(tp, false);
5338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5339 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5341 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5342 ocp_data &= ~MCU_CLK_RATIO_MASK;
5343 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5344 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5345 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5346 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5349 rtl_tally_reset(tp);
5351 /* enable rx aggregation */
5352 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5353 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5354 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5357 static void r8153_init(struct r8152 *tp)
5363 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5366 r8153_u1u2en(tp, false);
5368 for (i = 0; i < 500; i++) {
5369 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5374 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5378 data = r8153_phy_status(tp, 0);
5380 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5381 tp->version == RTL_VER_05)
5382 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5384 data = r8152_mdio_read(tp, MII_BMCR);
5385 if (data & BMCR_PDOWN) {
5386 data &= ~BMCR_PDOWN;
5387 r8152_mdio_write(tp, MII_BMCR, data);
5390 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5392 r8153_u2p3en(tp, false);
5394 if (tp->version == RTL_VER_04) {
5395 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5396 ocp_data &= ~pwd_dn_scale_mask;
5397 ocp_data |= pwd_dn_scale(96);
5398 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5400 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5401 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5402 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5403 } else if (tp->version == RTL_VER_05) {
5404 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5405 ocp_data &= ~ECM_ALDPS;
5406 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5408 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5409 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5410 ocp_data &= ~DYNAMIC_BURST;
5412 ocp_data |= DYNAMIC_BURST;
5413 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5414 } else if (tp->version == RTL_VER_06) {
5415 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5416 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5417 ocp_data &= ~DYNAMIC_BURST;
5419 ocp_data |= DYNAMIC_BURST;
5420 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5422 r8153_queue_wake(tp, false);
5424 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5425 if (rtl8152_get_speed(tp) & LINK_STATUS)
5426 ocp_data |= CUR_LINK_OK;
5428 ocp_data &= ~CUR_LINK_OK;
5429 ocp_data |= POLL_LINK_CHG;
5430 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5433 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5434 ocp_data |= EP4_FULL_FC;
5435 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5437 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5438 ocp_data &= ~TIMER11_EN;
5439 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5441 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5442 ocp_data &= ~LED_MODE_MASK;
5443 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5445 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5446 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5447 ocp_data |= LPM_TIMER_500MS;
5449 ocp_data |= LPM_TIMER_500US;
5450 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5452 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5453 ocp_data &= ~SEN_VAL_MASK;
5454 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5455 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5457 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5459 r8153_power_cut_en(tp, false);
5460 rtl_runtime_suspend_enable(tp, false);
5461 r8153_u1u2en(tp, true);
5462 r8153_mac_clk_spd(tp, false);
5463 usb_enable_lpm(tp->udev);
5465 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5466 ocp_data |= LANWAKE_CLR_EN;
5467 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5469 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5470 ocp_data &= ~LANWAKE_PIN;
5471 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5473 /* rx aggregation */
5474 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5475 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5476 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5477 ocp_data |= RX_AGG_DISABLE;
5479 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5481 rtl_tally_reset(tp);
5483 switch (tp->udev->speed) {
5484 case USB_SPEED_SUPER:
5485 case USB_SPEED_SUPER_PLUS:
5486 tp->coalesce = COALESCE_SUPER;
5488 case USB_SPEED_HIGH:
5489 tp->coalesce = COALESCE_HIGH;
5492 tp->coalesce = COALESCE_SLOW;
5497 static void r8153b_init(struct r8152 *tp)
5503 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5506 r8153b_u1u2en(tp, false);
5508 for (i = 0; i < 500; i++) {
5509 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5514 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5518 data = r8153_phy_status(tp, 0);
5520 data = r8152_mdio_read(tp, MII_BMCR);
5521 if (data & BMCR_PDOWN) {
5522 data &= ~BMCR_PDOWN;
5523 r8152_mdio_write(tp, MII_BMCR, data);
5526 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5528 r8153_u2p3en(tp, false);
5530 /* MSC timer = 0xfff * 8ms = 32760 ms */
5531 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5533 /* U1/U2/L1 idle timer. 500 us */
5534 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5536 r8153b_power_cut_en(tp, false);
5537 r8153b_ups_en(tp, false);
5538 r8153_queue_wake(tp, false);
5539 rtl_runtime_suspend_enable(tp, false);
5541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5542 if (rtl8152_get_speed(tp) & LINK_STATUS)
5543 ocp_data |= CUR_LINK_OK;
5545 ocp_data &= ~CUR_LINK_OK;
5546 ocp_data |= POLL_LINK_CHG;
5547 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5549 if (tp->udev->speed != USB_SPEED_HIGH)
5550 r8153b_u1u2en(tp, true);
5551 usb_enable_lpm(tp->udev);
5553 /* MAC clock speed down */
5554 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5555 ocp_data |= MAC_CLK_SPDWN_EN;
5556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5558 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5559 ocp_data &= ~PLA_MCU_SPDWN_EN;
5560 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5562 if (tp->version == RTL_VER_09) {
5563 /* Disable Test IO for 32QFN */
5564 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5565 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5566 ocp_data |= TEST_IO_OFF;
5567 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5571 set_bit(GREEN_ETHERNET, &tp->flags);
5573 /* rx aggregation */
5574 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5575 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5576 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5578 rtl_tally_reset(tp);
5580 tp->coalesce = 15000; /* 15 us */
5583 static int rtl8152_pre_reset(struct usb_interface *intf)
5585 struct r8152 *tp = usb_get_intfdata(intf);
5586 struct net_device *netdev;
5591 netdev = tp->netdev;
5592 if (!netif_running(netdev))
5595 netif_stop_queue(netdev);
5596 tasklet_disable(&tp->tx_tl);
5597 clear_bit(WORK_ENABLE, &tp->flags);
5598 usb_kill_urb(tp->intr_urb);
5599 cancel_delayed_work_sync(&tp->schedule);
5600 napi_disable(&tp->napi);
5601 if (netif_carrier_ok(netdev)) {
5602 mutex_lock(&tp->control);
5603 tp->rtl_ops.disable(tp);
5604 mutex_unlock(&tp->control);
5610 static int rtl8152_post_reset(struct usb_interface *intf)
5612 struct r8152 *tp = usb_get_intfdata(intf);
5613 struct net_device *netdev;
5619 /* reset the MAC adddress in case of policy change */
5620 if (determine_ethernet_addr(tp, &sa) >= 0) {
5622 dev_set_mac_address (tp->netdev, &sa, NULL);
5626 netdev = tp->netdev;
5627 if (!netif_running(netdev))
5630 set_bit(WORK_ENABLE, &tp->flags);
5631 if (netif_carrier_ok(netdev)) {
5632 mutex_lock(&tp->control);
5633 tp->rtl_ops.enable(tp);
5635 _rtl8152_set_rx_mode(netdev);
5636 mutex_unlock(&tp->control);
5639 napi_enable(&tp->napi);
5640 tasklet_enable(&tp->tx_tl);
5641 netif_wake_queue(netdev);
5642 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5644 if (!list_empty(&tp->rx_done))
5645 napi_schedule(&tp->napi);
5650 static bool delay_autosuspend(struct r8152 *tp)
5652 bool sw_linking = !!netif_carrier_ok(tp->netdev);
5653 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5655 /* This means a linking change occurs and the driver doesn't detect it,
5656 * yet. If the driver has disabled tx/rx and hw is linking on, the
5657 * device wouldn't wake up by receiving any packet.
5659 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5662 /* If the linking down is occurred by nway, the device may miss the
5663 * linking change event. And it wouldn't wake when linking on.
5665 if (!sw_linking && tp->rtl_ops.in_nway(tp))
5667 else if (!skb_queue_empty(&tp->tx_queue))
5673 static int rtl8152_runtime_resume(struct r8152 *tp)
5675 struct net_device *netdev = tp->netdev;
5677 if (netif_running(netdev) && netdev->flags & IFF_UP) {
5678 struct napi_struct *napi = &tp->napi;
5680 tp->rtl_ops.autosuspend_en(tp, false);
5682 set_bit(WORK_ENABLE, &tp->flags);
5684 if (netif_carrier_ok(netdev)) {
5685 if (rtl8152_get_speed(tp) & LINK_STATUS) {
5688 netif_carrier_off(netdev);
5689 tp->rtl_ops.disable(tp);
5690 netif_info(tp, link, netdev, "linking down\n");
5695 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5696 smp_mb__after_atomic();
5698 if (!list_empty(&tp->rx_done))
5699 napi_schedule(&tp->napi);
5701 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5703 if (netdev->flags & IFF_UP)
5704 tp->rtl_ops.autosuspend_en(tp, false);
5706 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5712 static int rtl8152_system_resume(struct r8152 *tp)
5714 struct net_device *netdev = tp->netdev;
5716 netif_device_attach(netdev);
5718 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5720 netif_carrier_off(netdev);
5721 set_bit(WORK_ENABLE, &tp->flags);
5722 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5728 static int rtl8152_runtime_suspend(struct r8152 *tp)
5730 struct net_device *netdev = tp->netdev;
5733 set_bit(SELECTIVE_SUSPEND, &tp->flags);
5734 smp_mb__after_atomic();
5736 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5739 if (netif_carrier_ok(netdev)) {
5742 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5743 ocp_data = rcr & ~RCR_ACPT_ALL;
5744 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5745 rxdy_gated_en(tp, true);
5746 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5748 if (!(ocp_data & RXFIFO_EMPTY)) {
5749 rxdy_gated_en(tp, false);
5750 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5751 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5752 smp_mb__after_atomic();
5758 clear_bit(WORK_ENABLE, &tp->flags);
5759 usb_kill_urb(tp->intr_urb);
5761 tp->rtl_ops.autosuspend_en(tp, true);
5763 if (netif_carrier_ok(netdev)) {
5764 struct napi_struct *napi = &tp->napi;
5768 rxdy_gated_en(tp, false);
5769 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5773 if (delay_autosuspend(tp)) {
5774 rtl8152_runtime_resume(tp);
5783 static int rtl8152_system_suspend(struct r8152 *tp)
5785 struct net_device *netdev = tp->netdev;
5787 netif_device_detach(netdev);
5789 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5790 struct napi_struct *napi = &tp->napi;
5792 clear_bit(WORK_ENABLE, &tp->flags);
5793 usb_kill_urb(tp->intr_urb);
5794 tasklet_disable(&tp->tx_tl);
5796 cancel_delayed_work_sync(&tp->schedule);
5797 tp->rtl_ops.down(tp);
5799 tasklet_enable(&tp->tx_tl);
5805 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5807 struct r8152 *tp = usb_get_intfdata(intf);
5810 mutex_lock(&tp->control);
5812 if (PMSG_IS_AUTO(message))
5813 ret = rtl8152_runtime_suspend(tp);
5815 ret = rtl8152_system_suspend(tp);
5817 mutex_unlock(&tp->control);
5822 static int rtl8152_resume(struct usb_interface *intf)
5824 struct r8152 *tp = usb_get_intfdata(intf);
5827 mutex_lock(&tp->control);
5829 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5830 ret = rtl8152_runtime_resume(tp);
5832 ret = rtl8152_system_resume(tp);
5834 mutex_unlock(&tp->control);
5839 static int rtl8152_reset_resume(struct usb_interface *intf)
5841 struct r8152 *tp = usb_get_intfdata(intf);
5843 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5844 tp->rtl_ops.init(tp);
5845 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5846 set_ethernet_addr(tp);
5847 return rtl8152_resume(intf);
5850 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5852 struct r8152 *tp = netdev_priv(dev);
5854 if (usb_autopm_get_interface(tp->intf) < 0)
5857 if (!rtl_can_wakeup(tp)) {
5861 mutex_lock(&tp->control);
5862 wol->supported = WAKE_ANY;
5863 wol->wolopts = __rtl_get_wol(tp);
5864 mutex_unlock(&tp->control);
5867 usb_autopm_put_interface(tp->intf);
5870 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5872 struct r8152 *tp = netdev_priv(dev);
5875 if (!rtl_can_wakeup(tp))
5878 if (wol->wolopts & ~WAKE_ANY)
5881 ret = usb_autopm_get_interface(tp->intf);
5885 mutex_lock(&tp->control);
5887 __rtl_set_wol(tp, wol->wolopts);
5888 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5890 mutex_unlock(&tp->control);
5892 usb_autopm_put_interface(tp->intf);
5898 static u32 rtl8152_get_msglevel(struct net_device *dev)
5900 struct r8152 *tp = netdev_priv(dev);
5902 return tp->msg_enable;
5905 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5907 struct r8152 *tp = netdev_priv(dev);
5909 tp->msg_enable = value;
5912 static void rtl8152_get_drvinfo(struct net_device *netdev,
5913 struct ethtool_drvinfo *info)
5915 struct r8152 *tp = netdev_priv(netdev);
5917 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5918 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5919 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5920 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5921 strlcpy(info->fw_version, tp->rtl_fw.version,
5922 sizeof(info->fw_version));
5926 int rtl8152_get_link_ksettings(struct net_device *netdev,
5927 struct ethtool_link_ksettings *cmd)
5929 struct r8152 *tp = netdev_priv(netdev);
5932 if (!tp->mii.mdio_read)
5935 ret = usb_autopm_get_interface(tp->intf);
5939 mutex_lock(&tp->control);
5941 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5943 mutex_unlock(&tp->control);
5945 usb_autopm_put_interface(tp->intf);
5951 static int rtl8152_set_link_ksettings(struct net_device *dev,
5952 const struct ethtool_link_ksettings *cmd)
5954 struct r8152 *tp = netdev_priv(dev);
5955 u32 advertising = 0;
5958 ret = usb_autopm_get_interface(tp->intf);
5962 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5963 cmd->link_modes.advertising))
5964 advertising |= RTL_ADVERTISED_10_HALF;
5966 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5967 cmd->link_modes.advertising))
5968 advertising |= RTL_ADVERTISED_10_FULL;
5970 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5971 cmd->link_modes.advertising))
5972 advertising |= RTL_ADVERTISED_100_HALF;
5974 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5975 cmd->link_modes.advertising))
5976 advertising |= RTL_ADVERTISED_100_FULL;
5978 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5979 cmd->link_modes.advertising))
5980 advertising |= RTL_ADVERTISED_1000_HALF;
5982 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5983 cmd->link_modes.advertising))
5984 advertising |= RTL_ADVERTISED_1000_FULL;
5986 mutex_lock(&tp->control);
5988 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5989 cmd->base.duplex, advertising);
5991 tp->autoneg = cmd->base.autoneg;
5992 tp->speed = cmd->base.speed;
5993 tp->duplex = cmd->base.duplex;
5994 tp->advertising = advertising;
5997 mutex_unlock(&tp->control);
5999 usb_autopm_put_interface(tp->intf);
6005 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6012 "tx_single_collisions",
6013 "tx_multi_collisions",
6021 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6025 return ARRAY_SIZE(rtl8152_gstrings);
6031 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6032 struct ethtool_stats *stats, u64 *data)
6034 struct r8152 *tp = netdev_priv(dev);
6035 struct tally_counter tally;
6037 if (usb_autopm_get_interface(tp->intf) < 0)
6040 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6042 usb_autopm_put_interface(tp->intf);
6044 data[0] = le64_to_cpu(tally.tx_packets);
6045 data[1] = le64_to_cpu(tally.rx_packets);
6046 data[2] = le64_to_cpu(tally.tx_errors);
6047 data[3] = le32_to_cpu(tally.rx_errors);
6048 data[4] = le16_to_cpu(tally.rx_missed);
6049 data[5] = le16_to_cpu(tally.align_errors);
6050 data[6] = le32_to_cpu(tally.tx_one_collision);
6051 data[7] = le32_to_cpu(tally.tx_multi_collision);
6052 data[8] = le64_to_cpu(tally.rx_unicast);
6053 data[9] = le64_to_cpu(tally.rx_broadcast);
6054 data[10] = le32_to_cpu(tally.rx_multicast);
6055 data[11] = le16_to_cpu(tally.tx_aborted);
6056 data[12] = le16_to_cpu(tally.tx_underrun);
6059 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6061 switch (stringset) {
6063 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6068 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6070 u32 lp, adv, supported = 0;
6073 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6074 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6076 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6077 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6079 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6080 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6082 eee->eee_enabled = tp->eee_en;
6083 eee->eee_active = !!(supported & adv & lp);
6084 eee->supported = supported;
6085 eee->advertised = tp->eee_adv;
6086 eee->lp_advertised = lp;
6091 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6093 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6095 tp->eee_en = eee->eee_enabled;
6098 rtl_eee_enable(tp, tp->eee_en);
6103 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6105 u32 lp, adv, supported = 0;
6108 val = ocp_reg_read(tp, OCP_EEE_ABLE);
6109 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6111 val = ocp_reg_read(tp, OCP_EEE_ADV);
6112 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6114 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6115 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6117 eee->eee_enabled = tp->eee_en;
6118 eee->eee_active = !!(supported & adv & lp);
6119 eee->supported = supported;
6120 eee->advertised = tp->eee_adv;
6121 eee->lp_advertised = lp;
6127 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6129 struct r8152 *tp = netdev_priv(net);
6132 ret = usb_autopm_get_interface(tp->intf);
6136 mutex_lock(&tp->control);
6138 ret = tp->rtl_ops.eee_get(tp, edata);
6140 mutex_unlock(&tp->control);
6142 usb_autopm_put_interface(tp->intf);
6149 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6151 struct r8152 *tp = netdev_priv(net);
6154 ret = usb_autopm_get_interface(tp->intf);
6158 mutex_lock(&tp->control);
6160 ret = tp->rtl_ops.eee_set(tp, edata);
6162 ret = mii_nway_restart(&tp->mii);
6164 mutex_unlock(&tp->control);
6166 usb_autopm_put_interface(tp->intf);
6172 static int rtl8152_nway_reset(struct net_device *dev)
6174 struct r8152 *tp = netdev_priv(dev);
6177 ret = usb_autopm_get_interface(tp->intf);
6181 mutex_lock(&tp->control);
6183 ret = mii_nway_restart(&tp->mii);
6185 mutex_unlock(&tp->control);
6187 usb_autopm_put_interface(tp->intf);
6193 static int rtl8152_get_coalesce(struct net_device *netdev,
6194 struct ethtool_coalesce *coalesce)
6196 struct r8152 *tp = netdev_priv(netdev);
6198 switch (tp->version) {
6207 coalesce->rx_coalesce_usecs = tp->coalesce;
6212 static int rtl8152_set_coalesce(struct net_device *netdev,
6213 struct ethtool_coalesce *coalesce)
6215 struct r8152 *tp = netdev_priv(netdev);
6218 switch (tp->version) {
6227 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6230 ret = usb_autopm_get_interface(tp->intf);
6234 mutex_lock(&tp->control);
6236 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6237 tp->coalesce = coalesce->rx_coalesce_usecs;
6239 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6240 netif_stop_queue(netdev);
6241 napi_disable(&tp->napi);
6242 tp->rtl_ops.disable(tp);
6243 tp->rtl_ops.enable(tp);
6245 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6246 _rtl8152_set_rx_mode(netdev);
6247 napi_enable(&tp->napi);
6248 netif_wake_queue(netdev);
6252 mutex_unlock(&tp->control);
6254 usb_autopm_put_interface(tp->intf);
6259 static int rtl8152_get_tunable(struct net_device *netdev,
6260 const struct ethtool_tunable *tunable, void *d)
6262 struct r8152 *tp = netdev_priv(netdev);
6264 switch (tunable->id) {
6265 case ETHTOOL_RX_COPYBREAK:
6266 *(u32 *)d = tp->rx_copybreak;
6275 static int rtl8152_set_tunable(struct net_device *netdev,
6276 const struct ethtool_tunable *tunable,
6279 struct r8152 *tp = netdev_priv(netdev);
6282 switch (tunable->id) {
6283 case ETHTOOL_RX_COPYBREAK:
6285 if (val < ETH_ZLEN) {
6286 netif_err(tp, rx_err, netdev,
6287 "Invalid rx copy break value\n");
6291 if (tp->rx_copybreak != val) {
6292 if (netdev->flags & IFF_UP) {
6293 mutex_lock(&tp->control);
6294 napi_disable(&tp->napi);
6295 tp->rx_copybreak = val;
6296 napi_enable(&tp->napi);
6297 mutex_unlock(&tp->control);
6299 tp->rx_copybreak = val;
6310 static void rtl8152_get_ringparam(struct net_device *netdev,
6311 struct ethtool_ringparam *ring)
6313 struct r8152 *tp = netdev_priv(netdev);
6315 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6316 ring->rx_pending = tp->rx_pending;
6319 static int rtl8152_set_ringparam(struct net_device *netdev,
6320 struct ethtool_ringparam *ring)
6322 struct r8152 *tp = netdev_priv(netdev);
6324 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6327 if (tp->rx_pending != ring->rx_pending) {
6328 if (netdev->flags & IFF_UP) {
6329 mutex_lock(&tp->control);
6330 napi_disable(&tp->napi);
6331 tp->rx_pending = ring->rx_pending;
6332 napi_enable(&tp->napi);
6333 mutex_unlock(&tp->control);
6335 tp->rx_pending = ring->rx_pending;
6342 static const struct ethtool_ops ops = {
6343 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6344 .get_drvinfo = rtl8152_get_drvinfo,
6345 .get_link = ethtool_op_get_link,
6346 .nway_reset = rtl8152_nway_reset,
6347 .get_msglevel = rtl8152_get_msglevel,
6348 .set_msglevel = rtl8152_set_msglevel,
6349 .get_wol = rtl8152_get_wol,
6350 .set_wol = rtl8152_set_wol,
6351 .get_strings = rtl8152_get_strings,
6352 .get_sset_count = rtl8152_get_sset_count,
6353 .get_ethtool_stats = rtl8152_get_ethtool_stats,
6354 .get_coalesce = rtl8152_get_coalesce,
6355 .set_coalesce = rtl8152_set_coalesce,
6356 .get_eee = rtl_ethtool_get_eee,
6357 .set_eee = rtl_ethtool_set_eee,
6358 .get_link_ksettings = rtl8152_get_link_ksettings,
6359 .set_link_ksettings = rtl8152_set_link_ksettings,
6360 .get_tunable = rtl8152_get_tunable,
6361 .set_tunable = rtl8152_set_tunable,
6362 .get_ringparam = rtl8152_get_ringparam,
6363 .set_ringparam = rtl8152_set_ringparam,
6366 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6368 struct r8152 *tp = netdev_priv(netdev);
6369 struct mii_ioctl_data *data = if_mii(rq);
6372 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6375 res = usb_autopm_get_interface(tp->intf);
6381 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6385 mutex_lock(&tp->control);
6386 data->val_out = r8152_mdio_read(tp, data->reg_num);
6387 mutex_unlock(&tp->control);
6391 if (!capable(CAP_NET_ADMIN)) {
6395 mutex_lock(&tp->control);
6396 r8152_mdio_write(tp, data->reg_num, data->val_in);
6397 mutex_unlock(&tp->control);
6404 usb_autopm_put_interface(tp->intf);
6410 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6412 struct r8152 *tp = netdev_priv(dev);
6415 switch (tp->version) {
6425 ret = usb_autopm_get_interface(tp->intf);
6429 mutex_lock(&tp->control);
6433 if (netif_running(dev)) {
6434 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6438 if (netif_carrier_ok(dev))
6439 r8153_set_rx_early_size(tp);
6442 mutex_unlock(&tp->control);
6444 usb_autopm_put_interface(tp->intf);
6449 static const struct net_device_ops rtl8152_netdev_ops = {
6450 .ndo_open = rtl8152_open,
6451 .ndo_stop = rtl8152_close,
6452 .ndo_do_ioctl = rtl8152_ioctl,
6453 .ndo_start_xmit = rtl8152_start_xmit,
6454 .ndo_tx_timeout = rtl8152_tx_timeout,
6455 .ndo_set_features = rtl8152_set_features,
6456 .ndo_set_rx_mode = rtl8152_set_rx_mode,
6457 .ndo_set_mac_address = rtl8152_set_mac_address,
6458 .ndo_change_mtu = rtl8152_change_mtu,
6459 .ndo_validate_addr = eth_validate_addr,
6460 .ndo_features_check = rtl8152_features_check,
6463 static void rtl8152_unload(struct r8152 *tp)
6465 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6468 if (tp->version != RTL_VER_01)
6469 r8152_power_cut_en(tp, true);
6472 static void rtl8153_unload(struct r8152 *tp)
6474 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6477 r8153_power_cut_en(tp, false);
6480 static void rtl8153b_unload(struct r8152 *tp)
6482 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6485 r8153b_power_cut_en(tp, false);
6488 static int rtl_ops_init(struct r8152 *tp)
6490 struct rtl_ops *ops = &tp->rtl_ops;
6493 switch (tp->version) {
6497 ops->init = r8152b_init;
6498 ops->enable = rtl8152_enable;
6499 ops->disable = rtl8152_disable;
6500 ops->up = rtl8152_up;
6501 ops->down = rtl8152_down;
6502 ops->unload = rtl8152_unload;
6503 ops->eee_get = r8152_get_eee;
6504 ops->eee_set = r8152_set_eee;
6505 ops->in_nway = rtl8152_in_nway;
6506 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
6507 ops->autosuspend_en = rtl_runtime_suspend_enable;
6508 tp->rx_buf_sz = 16 * 1024;
6510 tp->eee_adv = MDIO_EEE_100TX;
6517 ops->init = r8153_init;
6518 ops->enable = rtl8153_enable;
6519 ops->disable = rtl8153_disable;
6520 ops->up = rtl8153_up;
6521 ops->down = rtl8153_down;
6522 ops->unload = rtl8153_unload;
6523 ops->eee_get = r8153_get_eee;
6524 ops->eee_set = r8152_set_eee;
6525 ops->in_nway = rtl8153_in_nway;
6526 ops->hw_phy_cfg = r8153_hw_phy_cfg;
6527 ops->autosuspend_en = rtl8153_runtime_enable;
6528 tp->rx_buf_sz = 32 * 1024;
6530 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6535 ops->init = r8153b_init;
6536 ops->enable = rtl8153_enable;
6537 ops->disable = rtl8153_disable;
6538 ops->up = rtl8153b_up;
6539 ops->down = rtl8153b_down;
6540 ops->unload = rtl8153b_unload;
6541 ops->eee_get = r8153_get_eee;
6542 ops->eee_set = r8152_set_eee;
6543 ops->in_nway = rtl8153_in_nway;
6544 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
6545 ops->autosuspend_en = rtl8153b_runtime_enable;
6546 tp->rx_buf_sz = 32 * 1024;
6548 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6553 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6560 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
6561 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
6562 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
6563 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
6565 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6566 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6567 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6568 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6570 static int rtl_fw_init(struct r8152 *tp)
6572 struct rtl_fw *rtl_fw = &tp->rtl_fw;
6574 switch (tp->version) {
6576 rtl_fw->fw_name = FIRMWARE_8153A_2;
6577 rtl_fw->pre_fw = r8153_pre_firmware_1;
6578 rtl_fw->post_fw = r8153_post_firmware_1;
6581 rtl_fw->fw_name = FIRMWARE_8153A_3;
6582 rtl_fw->pre_fw = r8153_pre_firmware_2;
6583 rtl_fw->post_fw = r8153_post_firmware_2;
6586 rtl_fw->fw_name = FIRMWARE_8153A_4;
6587 rtl_fw->post_fw = r8153_post_firmware_3;
6590 rtl_fw->fw_name = FIRMWARE_8153B_2;
6591 rtl_fw->pre_fw = r8153b_pre_firmware_1;
6592 rtl_fw->post_fw = r8153b_post_firmware_1;
6601 u8 rtl8152_get_version(struct usb_interface *intf)
6603 struct usb_device *udev = interface_to_usbdev(intf);
6609 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6613 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6614 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6615 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6617 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6623 version = RTL_VER_01;
6626 version = RTL_VER_02;
6629 version = RTL_VER_03;
6632 version = RTL_VER_04;
6635 version = RTL_VER_05;
6638 version = RTL_VER_06;
6641 version = RTL_VER_07;
6644 version = RTL_VER_08;
6647 version = RTL_VER_09;
6650 version = RTL_VER_UNKNOWN;
6651 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6655 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6659 EXPORT_SYMBOL_GPL(rtl8152_get_version);
6661 static int rtl8152_probe(struct usb_interface *intf,
6662 const struct usb_device_id *id)
6664 struct usb_device *udev = interface_to_usbdev(intf);
6665 u8 version = rtl8152_get_version(intf);
6667 struct net_device *netdev;
6670 if (version == RTL_VER_UNKNOWN)
6673 if (udev->actconfig->desc.bConfigurationValue != 1) {
6674 usb_driver_set_configuration(udev, 1);
6678 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6681 usb_reset_device(udev);
6682 netdev = alloc_etherdev(sizeof(struct r8152));
6684 dev_err(&intf->dev, "Out of memory\n");
6688 SET_NETDEV_DEV(netdev, &intf->dev);
6689 tp = netdev_priv(netdev);
6690 tp->msg_enable = 0x7FFF;
6693 tp->netdev = netdev;
6695 tp->version = version;
6701 tp->mii.supports_gmii = 0;
6704 tp->mii.supports_gmii = 1;
6708 ret = rtl_ops_init(tp);
6714 mutex_init(&tp->control);
6715 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6716 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6717 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6718 tasklet_disable(&tp->tx_tl);
6720 netdev->netdev_ops = &rtl8152_netdev_ops;
6721 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6723 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6724 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6725 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6726 NETIF_F_HW_VLAN_CTAG_TX;
6727 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6728 NETIF_F_TSO | NETIF_F_FRAGLIST |
6729 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6730 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6731 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6732 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6733 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6735 if (tp->version == RTL_VER_01) {
6736 netdev->features &= ~NETIF_F_RXCSUM;
6737 netdev->hw_features &= ~NETIF_F_RXCSUM;
6740 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6741 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6742 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6743 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6744 set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6748 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6749 (!strcmp(udev->serial, "000001000000") ||
6750 !strcmp(udev->serial, "000002000000"))) {
6751 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6752 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6755 netdev->ethtool_ops = &ops;
6756 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6758 /* MTU range: 68 - 1500 or 9194 */
6759 netdev->min_mtu = ETH_MIN_MTU;
6760 switch (tp->version) {
6763 netdev->max_mtu = ETH_DATA_LEN;
6766 netdev->max_mtu = RTL8153_MAX_MTU;
6770 tp->mii.dev = netdev;
6771 tp->mii.mdio_read = read_mii_word;
6772 tp->mii.mdio_write = write_mii_word;
6773 tp->mii.phy_id_mask = 0x3f;
6774 tp->mii.reg_num_mask = 0x1f;
6775 tp->mii.phy_id = R8152_PHY_ID;
6777 tp->autoneg = AUTONEG_ENABLE;
6778 tp->speed = SPEED_100;
6779 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6780 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6781 if (tp->mii.supports_gmii) {
6782 tp->speed = SPEED_1000;
6783 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6785 tp->duplex = DUPLEX_FULL;
6787 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6788 tp->rx_pending = 10 * RTL8152_MAX_RX;
6790 intf->needs_remote_wakeup = 1;
6792 if (!rtl_can_wakeup(tp))
6793 __rtl_set_wol(tp, 0);
6795 tp->saved_wolopts = __rtl_get_wol(tp);
6797 tp->rtl_ops.init(tp);
6798 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6799 /* Retry in case request_firmware() is not ready yet. */
6800 tp->rtl_fw.retry = true;
6802 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6803 set_ethernet_addr(tp);
6805 usb_set_intfdata(intf, tp);
6806 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6808 ret = register_netdev(netdev);
6810 netif_err(tp, probe, netdev, "couldn't register the device\n");
6814 if (tp->saved_wolopts)
6815 device_set_wakeup_enable(&udev->dev, true);
6817 device_set_wakeup_enable(&udev->dev, false);
6819 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6824 tasklet_kill(&tp->tx_tl);
6825 usb_set_intfdata(intf, NULL);
6827 free_netdev(netdev);
6831 static void rtl8152_disconnect(struct usb_interface *intf)
6833 struct r8152 *tp = usb_get_intfdata(intf);
6835 usb_set_intfdata(intf, NULL);
6839 unregister_netdev(tp->netdev);
6840 tasklet_kill(&tp->tx_tl);
6841 cancel_delayed_work_sync(&tp->hw_phy_work);
6842 tp->rtl_ops.unload(tp);
6843 rtl8152_release_firmware(tp);
6844 free_netdev(tp->netdev);
6848 #define REALTEK_USB_DEVICE(vend, prod) \
6849 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6850 USB_DEVICE_ID_MATCH_INT_CLASS, \
6851 .idVendor = (vend), \
6852 .idProduct = (prod), \
6853 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6856 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6857 USB_DEVICE_ID_MATCH_DEVICE, \
6858 .idVendor = (vend), \
6859 .idProduct = (prod), \
6860 .bInterfaceClass = USB_CLASS_COMM, \
6861 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6862 .bInterfaceProtocol = USB_CDC_PROTO_NONE
6864 /* table of devices that work with this driver */
6865 static const struct usb_device_id rtl8152_table[] = {
6866 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6867 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6868 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6869 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6870 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6871 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6872 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6873 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
6874 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
6875 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
6876 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)},
6877 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6878 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6879 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
6880 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
6881 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6882 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
6883 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
6887 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6889 static struct usb_driver rtl8152_driver = {
6891 .id_table = rtl8152_table,
6892 .probe = rtl8152_probe,
6893 .disconnect = rtl8152_disconnect,
6894 .suspend = rtl8152_suspend,
6895 .resume = rtl8152_resume,
6896 .reset_resume = rtl8152_reset_resume,
6897 .pre_reset = rtl8152_pre_reset,
6898 .post_reset = rtl8152_post_reset,
6899 .supports_autosuspend = 1,
6900 .disable_hub_initiated_lpm = 1,
6903 module_usb_driver(rtl8152_driver);
6905 MODULE_AUTHOR(DRIVER_AUTHOR);
6906 MODULE_DESCRIPTION(DRIVER_DESC);
6907 MODULE_LICENSE("GPL");
6908 MODULE_VERSION(DRIVER_VERSION);