USB: serial: drop bogus to_usb_serial_port() checks
[sfrench/cifs-2.6.git] / drivers / net / usb / r8152.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "11"
33
34 /* Information for net */
35 #define NET_VERSION             "11"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PLA_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_UPHY_TIMER          0xd388
61 #define PLA_SUSPEND_FLAG        0xd38a
62 #define PLA_INDICATE_FALG       0xd38c
63 #define PLA_MACDBG_PRE          0xd38c  /* RTL_VER_04 only */
64 #define PLA_MACDBG_POST         0xd38e  /* RTL_VER_04 only */
65 #define PLA_EXTRA_STATUS        0xd398
66 #define PLA_EFUSE_DATA          0xdd00
67 #define PLA_EFUSE_CMD           0xdd02
68 #define PLA_LEDSEL              0xdd90
69 #define PLA_LED_FEATURE         0xdd92
70 #define PLA_PHYAR               0xde00
71 #define PLA_BOOT_CTRL           0xe004
72 #define PLA_LWAKE_CTRL_REG      0xe007
73 #define PLA_GPHY_INTR_IMR       0xe022
74 #define PLA_EEE_CR              0xe040
75 #define PLA_EEEP_CR             0xe080
76 #define PLA_MAC_PWR_CTRL        0xe0c0
77 #define PLA_MAC_PWR_CTRL2       0xe0ca
78 #define PLA_MAC_PWR_CTRL3       0xe0cc
79 #define PLA_MAC_PWR_CTRL4       0xe0ce
80 #define PLA_WDT6_CTRL           0xe428
81 #define PLA_TCR0                0xe610
82 #define PLA_TCR1                0xe612
83 #define PLA_MTPS                0xe615
84 #define PLA_TXFIFO_CTRL         0xe618
85 #define PLA_RSTTALLY            0xe800
86 #define PLA_CR                  0xe813
87 #define PLA_CRWECR              0xe81c
88 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
89 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
90 #define PLA_CONFIG5             0xe822
91 #define PLA_PHY_PWR             0xe84c
92 #define PLA_OOB_CTRL            0xe84f
93 #define PLA_CPCR                0xe854
94 #define PLA_MISC_0              0xe858
95 #define PLA_MISC_1              0xe85a
96 #define PLA_OCP_GPHY_BASE       0xe86c
97 #define PLA_TALLYCNT            0xe890
98 #define PLA_SFF_STS_7           0xe8de
99 #define PLA_PHYSTATUS           0xe908
100 #define PLA_CONFIG6             0xe90a /* CONFIG6 */
101 #define PLA_BP_BA               0xfc26
102 #define PLA_BP_0                0xfc28
103 #define PLA_BP_1                0xfc2a
104 #define PLA_BP_2                0xfc2c
105 #define PLA_BP_3                0xfc2e
106 #define PLA_BP_4                0xfc30
107 #define PLA_BP_5                0xfc32
108 #define PLA_BP_6                0xfc34
109 #define PLA_BP_7                0xfc36
110 #define PLA_BP_EN               0xfc38
111
112 #define USB_USB2PHY             0xb41e
113 #define USB_SSPHYLINK1          0xb426
114 #define USB_SSPHYLINK2          0xb428
115 #define USB_U2P3_CTRL           0xb460
116 #define USB_CSR_DUMMY1          0xb464
117 #define USB_CSR_DUMMY2          0xb466
118 #define USB_DEV_STAT            0xb808
119 #define USB_CONNECT_TIMER       0xcbf8
120 #define USB_MSC_TIMER           0xcbfc
121 #define USB_BURST_SIZE          0xcfc0
122 #define USB_FW_FIX_EN0          0xcfca
123 #define USB_FW_FIX_EN1          0xcfcc
124 #define USB_LPM_CONFIG          0xcfd8
125 #define USB_CSTMR               0xcfef  /* RTL8153A */
126 #define USB_FW_CTRL             0xd334  /* RTL8153B */
127 #define USB_FC_TIMER            0xd340
128 #define USB_USB_CTRL            0xd406
129 #define USB_PHY_CTRL            0xd408
130 #define USB_TX_AGG              0xd40a
131 #define USB_RX_BUF_TH           0xd40c
132 #define USB_USB_TIMER           0xd428
133 #define USB_RX_EARLY_TIMEOUT    0xd42c
134 #define USB_RX_EARLY_SIZE       0xd42e
135 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
136 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
137 #define USB_TX_DMA              0xd434
138 #define USB_UPT_RXDMA_OWN       0xd437
139 #define USB_TOLERANCE           0xd490
140 #define USB_LPM_CTRL            0xd41a
141 #define USB_BMU_RESET           0xd4b0
142 #define USB_U1U2_TIMER          0xd4da
143 #define USB_FW_TASK             0xd4e8  /* RTL8153B */
144 #define USB_UPS_CTRL            0xd800
145 #define USB_POWER_CUT           0xd80a
146 #define USB_MISC_0              0xd81a
147 #define USB_MISC_1              0xd81f
148 #define USB_AFE_CTRL2           0xd824
149 #define USB_UPS_CFG             0xd842
150 #define USB_UPS_FLAGS           0xd848
151 #define USB_WDT1_CTRL           0xe404
152 #define USB_WDT11_CTRL          0xe43c
153 #define USB_BP_BA               PLA_BP_BA
154 #define USB_BP_0                PLA_BP_0
155 #define USB_BP_1                PLA_BP_1
156 #define USB_BP_2                PLA_BP_2
157 #define USB_BP_3                PLA_BP_3
158 #define USB_BP_4                PLA_BP_4
159 #define USB_BP_5                PLA_BP_5
160 #define USB_BP_6                PLA_BP_6
161 #define USB_BP_7                PLA_BP_7
162 #define USB_BP_EN               PLA_BP_EN       /* RTL8153A */
163 #define USB_BP_8                0xfc38          /* RTL8153B */
164 #define USB_BP_9                0xfc3a
165 #define USB_BP_10               0xfc3c
166 #define USB_BP_11               0xfc3e
167 #define USB_BP_12               0xfc40
168 #define USB_BP_13               0xfc42
169 #define USB_BP_14               0xfc44
170 #define USB_BP_15               0xfc46
171 #define USB_BP2_EN              0xfc48
172
173 /* OCP Registers */
174 #define OCP_ALDPS_CONFIG        0x2010
175 #define OCP_EEE_CONFIG1         0x2080
176 #define OCP_EEE_CONFIG2         0x2092
177 #define OCP_EEE_CONFIG3         0x2094
178 #define OCP_BASE_MII            0xa400
179 #define OCP_EEE_AR              0xa41a
180 #define OCP_EEE_DATA            0xa41c
181 #define OCP_PHY_STATUS          0xa420
182 #define OCP_NCTL_CFG            0xa42c
183 #define OCP_POWER_CFG           0xa430
184 #define OCP_EEE_CFG             0xa432
185 #define OCP_SRAM_ADDR           0xa436
186 #define OCP_SRAM_DATA           0xa438
187 #define OCP_DOWN_SPEED          0xa442
188 #define OCP_EEE_ABLE            0xa5c4
189 #define OCP_EEE_ADV             0xa5d0
190 #define OCP_EEE_LPABLE          0xa5d2
191 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
192 #define OCP_PHY_PATCH_STAT      0xb800
193 #define OCP_PHY_PATCH_CMD       0xb820
194 #define OCP_PHY_LOCK            0xb82e
195 #define OCP_ADC_IOFFSET         0xbcfc
196 #define OCP_ADC_CFG             0xbc06
197 #define OCP_SYSCLK_CFG          0xc416
198
199 /* SRAM Register */
200 #define SRAM_GREEN_CFG          0x8011
201 #define SRAM_LPF_CFG            0x8012
202 #define SRAM_10M_AMP1           0x8080
203 #define SRAM_10M_AMP2           0x8082
204 #define SRAM_IMPEDANCE          0x8084
205 #define SRAM_PHY_LOCK           0xb82e
206
207 /* PLA_RCR */
208 #define RCR_AAP                 0x00000001
209 #define RCR_APM                 0x00000002
210 #define RCR_AM                  0x00000004
211 #define RCR_AB                  0x00000008
212 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
213
214 /* PLA_RXFIFO_CTRL0 */
215 #define RXFIFO_THR1_NORMAL      0x00080002
216 #define RXFIFO_THR1_OOB         0x01800003
217
218 /* PLA_RXFIFO_CTRL1 */
219 #define RXFIFO_THR2_FULL        0x00000060
220 #define RXFIFO_THR2_HIGH        0x00000038
221 #define RXFIFO_THR2_OOB         0x0000004a
222 #define RXFIFO_THR2_NORMAL      0x00a0
223
224 /* PLA_RXFIFO_CTRL2 */
225 #define RXFIFO_THR3_FULL        0x00000078
226 #define RXFIFO_THR3_HIGH        0x00000048
227 #define RXFIFO_THR3_OOB         0x0000005a
228 #define RXFIFO_THR3_NORMAL      0x0110
229
230 /* PLA_TXFIFO_CTRL */
231 #define TXFIFO_THR_NORMAL       0x00400008
232 #define TXFIFO_THR_NORMAL2      0x01000008
233
234 /* PLA_DMY_REG0 */
235 #define ECM_ALDPS               0x0002
236
237 /* PLA_FMC */
238 #define FMC_FCR_MCU_EN          0x0001
239
240 /* PLA_EEEP_CR */
241 #define EEEP_CR_EEEP_TX         0x0002
242
243 /* PLA_WDT6_CTRL */
244 #define WDT6_SET_MODE           0x0010
245
246 /* PLA_TCR0 */
247 #define TCR0_TX_EMPTY           0x0800
248 #define TCR0_AUTO_FIFO          0x0080
249
250 /* PLA_TCR1 */
251 #define VERSION_MASK            0x7cf0
252
253 /* PLA_MTPS */
254 #define MTPS_JUMBO              (12 * 1024 / 64)
255 #define MTPS_DEFAULT            (6 * 1024 / 64)
256
257 /* PLA_RSTTALLY */
258 #define TALLY_RESET             0x0001
259
260 /* PLA_CR */
261 #define CR_RST                  0x10
262 #define CR_RE                   0x08
263 #define CR_TE                   0x04
264
265 /* PLA_CRWECR */
266 #define CRWECR_NORAML           0x00
267 #define CRWECR_CONFIG           0xc0
268
269 /* PLA_OOB_CTRL */
270 #define NOW_IS_OOB              0x80
271 #define TXFIFO_EMPTY            0x20
272 #define RXFIFO_EMPTY            0x10
273 #define LINK_LIST_READY         0x02
274 #define DIS_MCU_CLROOB          0x01
275 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
276
277 /* PLA_MISC_1 */
278 #define RXDY_GATED_EN           0x0008
279
280 /* PLA_SFF_STS_7 */
281 #define RE_INIT_LL              0x8000
282 #define MCU_BORW_EN             0x4000
283
284 /* PLA_CPCR */
285 #define CPCR_RX_VLAN            0x0040
286
287 /* PLA_CFG_WOL */
288 #define MAGIC_EN                0x0001
289
290 /* PLA_TEREDO_CFG */
291 #define TEREDO_SEL              0x8000
292 #define TEREDO_WAKE_MASK        0x7f00
293 #define TEREDO_RS_EVENT_MASK    0x00fe
294 #define OOB_TEREDO_EN           0x0001
295
296 /* PLA_BDC_CR */
297 #define ALDPS_PROXY_MODE        0x0001
298
299 /* PLA_EFUSE_CMD */
300 #define EFUSE_READ_CMD          BIT(15)
301 #define EFUSE_DATA_BIT16        BIT(7)
302
303 /* PLA_CONFIG34 */
304 #define LINK_ON_WAKE_EN         0x0010
305 #define LINK_OFF_WAKE_EN        0x0008
306
307 /* PLA_CONFIG6 */
308 #define LANWAKE_CLR_EN          BIT(0)
309
310 /* PLA_CONFIG5 */
311 #define BWF_EN                  0x0040
312 #define MWF_EN                  0x0020
313 #define UWF_EN                  0x0010
314 #define LAN_WAKE_EN             0x0002
315
316 /* PLA_LED_FEATURE */
317 #define LED_MODE_MASK           0x0700
318
319 /* PLA_PHY_PWR */
320 #define TX_10M_IDLE_EN          0x0080
321 #define PFM_PWM_SWITCH          0x0040
322 #define TEST_IO_OFF             BIT(4)
323
324 /* PLA_MAC_PWR_CTRL */
325 #define D3_CLK_GATED_EN         0x00004000
326 #define MCU_CLK_RATIO           0x07010f07
327 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
328 #define ALDPS_SPDWN_RATIO       0x0f87
329
330 /* PLA_MAC_PWR_CTRL2 */
331 #define EEE_SPDWN_RATIO         0x8007
332 #define MAC_CLK_SPDWN_EN        BIT(15)
333
334 /* PLA_MAC_PWR_CTRL3 */
335 #define PLA_MCU_SPDWN_EN        BIT(14)
336 #define PKT_AVAIL_SPDWN_EN      0x0100
337 #define SUSPEND_SPDWN_EN        0x0004
338 #define U1U2_SPDWN_EN           0x0002
339 #define L1_SPDWN_EN             0x0001
340
341 /* PLA_MAC_PWR_CTRL4 */
342 #define PWRSAVE_SPDWN_EN        0x1000
343 #define RXDV_SPDWN_EN           0x0800
344 #define TX10MIDLE_EN            0x0100
345 #define TP100_SPDWN_EN          0x0020
346 #define TP500_SPDWN_EN          0x0010
347 #define TP1000_SPDWN_EN         0x0008
348 #define EEE_SPDWN_EN            0x0001
349
350 /* PLA_GPHY_INTR_IMR */
351 #define GPHY_STS_MSK            0x0001
352 #define SPEED_DOWN_MSK          0x0002
353 #define SPDWN_RXDV_MSK          0x0004
354 #define SPDWN_LINKCHG_MSK       0x0008
355
356 /* PLA_PHYAR */
357 #define PHYAR_FLAG              0x80000000
358
359 /* PLA_EEE_CR */
360 #define EEE_RX_EN               0x0001
361 #define EEE_TX_EN               0x0002
362
363 /* PLA_BOOT_CTRL */
364 #define AUTOLOAD_DONE           0x0002
365
366 /* PLA_LWAKE_CTRL_REG */
367 #define LANWAKE_PIN             BIT(7)
368
369 /* PLA_SUSPEND_FLAG */
370 #define LINK_CHG_EVENT          BIT(0)
371
372 /* PLA_INDICATE_FALG */
373 #define UPCOMING_RUNTIME_D3     BIT(0)
374
375 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
376 #define DEBUG_OE                BIT(0)
377 #define DEBUG_LTSSM             0x0082
378
379 /* PLA_EXTRA_STATUS */
380 #define CUR_LINK_OK             BIT(15)
381 #define U3P3_CHECK_EN           BIT(7)  /* RTL_VER_05 only */
382 #define LINK_CHANGE_FLAG        BIT(8)
383 #define POLL_LINK_CHG           BIT(0)
384
385 /* USB_USB2PHY */
386 #define USB2PHY_SUSPEND         0x0001
387 #define USB2PHY_L1              0x0002
388
389 /* USB_SSPHYLINK1 */
390 #define DELAY_PHY_PWR_CHG       BIT(1)
391
392 /* USB_SSPHYLINK2 */
393 #define pwd_dn_scale_mask       0x3ffe
394 #define pwd_dn_scale(x)         ((x) << 1)
395
396 /* USB_CSR_DUMMY1 */
397 #define DYNAMIC_BURST           0x0001
398
399 /* USB_CSR_DUMMY2 */
400 #define EP4_FULL_FC             0x0001
401
402 /* USB_DEV_STAT */
403 #define STAT_SPEED_MASK         0x0006
404 #define STAT_SPEED_HIGH         0x0000
405 #define STAT_SPEED_FULL         0x0002
406
407 /* USB_FW_FIX_EN0 */
408 #define FW_FIX_SUSPEND          BIT(14)
409
410 /* USB_FW_FIX_EN1 */
411 #define FW_IP_RESET_EN          BIT(9)
412
413 /* USB_LPM_CONFIG */
414 #define LPM_U1U2_EN             BIT(0)
415
416 /* USB_TX_AGG */
417 #define TX_AGG_MAX_THRESHOLD    0x03
418
419 /* USB_RX_BUF_TH */
420 #define RX_THR_SUPPER           0x0c350180
421 #define RX_THR_HIGH             0x7a120180
422 #define RX_THR_SLOW             0xffff0180
423 #define RX_THR_B                0x00010001
424
425 /* USB_TX_DMA */
426 #define TEST_MODE_DISABLE       0x00000001
427 #define TX_SIZE_ADJUST1         0x00000100
428
429 /* USB_BMU_RESET */
430 #define BMU_RESET_EP_IN         0x01
431 #define BMU_RESET_EP_OUT        0x02
432
433 /* USB_UPT_RXDMA_OWN */
434 #define OWN_UPDATE              BIT(0)
435 #define OWN_CLEAR               BIT(1)
436
437 /* USB_FW_TASK */
438 #define FC_PATCH_TASK           BIT(1)
439
440 /* USB_UPS_CTRL */
441 #define POWER_CUT               0x0100
442
443 /* USB_PM_CTRL_STATUS */
444 #define RESUME_INDICATE         0x0001
445
446 /* USB_CSTMR */
447 #define FORCE_SUPER             BIT(0)
448
449 /* USB_FW_CTRL */
450 #define FLOW_CTRL_PATCH_OPT     BIT(1)
451
452 /* USB_FC_TIMER */
453 #define CTRL_TIMER_EN           BIT(15)
454
455 /* USB_USB_CTRL */
456 #define RX_AGG_DISABLE          0x0010
457 #define RX_ZERO_EN              0x0080
458
459 /* USB_U2P3_CTRL */
460 #define U2P3_ENABLE             0x0001
461
462 /* USB_POWER_CUT */
463 #define PWR_EN                  0x0001
464 #define PHASE2_EN               0x0008
465 #define UPS_EN                  BIT(4)
466 #define USP_PREWAKE             BIT(5)
467
468 /* USB_MISC_0 */
469 #define PCUT_STATUS             0x0001
470
471 /* USB_RX_EARLY_TIMEOUT */
472 #define COALESCE_SUPER           85000U
473 #define COALESCE_HIGH           250000U
474 #define COALESCE_SLOW           524280U
475
476 /* USB_WDT1_CTRL */
477 #define WTD1_EN                 BIT(0)
478
479 /* USB_WDT11_CTRL */
480 #define TIMER11_EN              0x0001
481
482 /* USB_LPM_CTRL */
483 /* bit 4 ~ 5: fifo empty boundary */
484 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
485 /* bit 2 ~ 3: LMP timer */
486 #define LPM_TIMER_MASK          0x0c
487 #define LPM_TIMER_500MS         0x04    /* 500 ms */
488 #define LPM_TIMER_500US         0x0c    /* 500 us */
489 #define ROK_EXIT_LPM            0x02
490
491 /* USB_AFE_CTRL2 */
492 #define SEN_VAL_MASK            0xf800
493 #define SEN_VAL_NORMAL          0xa000
494 #define SEL_RXIDLE              0x0100
495
496 /* USB_UPS_CFG */
497 #define SAW_CNT_1MS_MASK        0x0fff
498
499 /* USB_UPS_FLAGS */
500 #define UPS_FLAGS_R_TUNE                BIT(0)
501 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
502 #define UPS_FLAGS_250M_CKDIV            BIT(2)
503 #define UPS_FLAGS_EN_ALDPS              BIT(3)
504 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
505 #define ups_flags_speed(x)              ((x) << 16)
506 #define UPS_FLAGS_EN_EEE                BIT(20)
507 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
508 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
509 #define UPS_FLAGS_EEE_PLLOFF_100        BIT(23)
510 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
511 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
512 #define UPS_FLAGS_EN_GREEN              BIT(26)
513 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
514
515 enum spd_duplex {
516         NWAY_10M_HALF,
517         NWAY_10M_FULL,
518         NWAY_100M_HALF,
519         NWAY_100M_FULL,
520         NWAY_1000M_FULL,
521         FORCE_10M_HALF,
522         FORCE_10M_FULL,
523         FORCE_100M_HALF,
524         FORCE_100M_FULL,
525 };
526
527 /* OCP_ALDPS_CONFIG */
528 #define ENPWRSAVE               0x8000
529 #define ENPDNPS                 0x0200
530 #define LINKENA                 0x0100
531 #define DIS_SDSAVE              0x0010
532
533 /* OCP_PHY_STATUS */
534 #define PHY_STAT_MASK           0x0007
535 #define PHY_STAT_EXT_INIT       2
536 #define PHY_STAT_LAN_ON         3
537 #define PHY_STAT_PWRDN          5
538
539 /* OCP_NCTL_CFG */
540 #define PGA_RETURN_EN           BIT(1)
541
542 /* OCP_POWER_CFG */
543 #define EEE_CLKDIV_EN           0x8000
544 #define EN_ALDPS                0x0004
545 #define EN_10M_PLLOFF           0x0001
546
547 /* OCP_EEE_CONFIG1 */
548 #define RG_TXLPI_MSK_HFDUP      0x8000
549 #define RG_MATCLR_EN            0x4000
550 #define EEE_10_CAP              0x2000
551 #define EEE_NWAY_EN             0x1000
552 #define TX_QUIET_EN             0x0200
553 #define RX_QUIET_EN             0x0100
554 #define sd_rise_time_mask       0x0070
555 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
556 #define RG_RXLPI_MSK_HFDUP      0x0008
557 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
558
559 /* OCP_EEE_CONFIG2 */
560 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
561 #define RG_DACQUIET_EN          0x0400
562 #define RG_LDVQUIET_EN          0x0200
563 #define RG_CKRSEL               0x0020
564 #define RG_EEEPRG_EN            0x0010
565
566 /* OCP_EEE_CONFIG3 */
567 #define fast_snr_mask           0xff80
568 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
569 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
570 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
571
572 /* OCP_EEE_AR */
573 /* bit[15:14] function */
574 #define FUN_ADDR                0x0000
575 #define FUN_DATA                0x4000
576 /* bit[4:0] device addr */
577
578 /* OCP_EEE_CFG */
579 #define CTAP_SHORT_EN           0x0040
580 #define EEE10_EN                0x0010
581
582 /* OCP_DOWN_SPEED */
583 #define EN_EEE_CMODE            BIT(14)
584 #define EN_EEE_1000             BIT(13)
585 #define EN_EEE_100              BIT(12)
586 #define EN_10M_CLKDIV           BIT(11)
587 #define EN_10M_BGOFF            0x0080
588
589 /* OCP_PHY_STATE */
590 #define TXDIS_STATE             0x01
591 #define ABD_STATE               0x02
592
593 /* OCP_PHY_PATCH_STAT */
594 #define PATCH_READY             BIT(6)
595
596 /* OCP_PHY_PATCH_CMD */
597 #define PATCH_REQUEST           BIT(4)
598
599 /* OCP_PHY_LOCK */
600 #define PATCH_LOCK              BIT(0)
601
602 /* OCP_ADC_CFG */
603 #define CKADSEL_L               0x0100
604 #define ADC_EN                  0x0080
605 #define EN_EMI_L                0x0040
606
607 /* OCP_SYSCLK_CFG */
608 #define clk_div_expo(x)         (min(x, 5) << 8)
609
610 /* SRAM_GREEN_CFG */
611 #define GREEN_ETH_EN            BIT(15)
612 #define R_TUNE_EN               BIT(11)
613
614 /* SRAM_LPF_CFG */
615 #define LPF_AUTO_TUNE           0x8000
616
617 /* SRAM_10M_AMP1 */
618 #define GDAC_IB_UPALL           0x0008
619
620 /* SRAM_10M_AMP2 */
621 #define AMP_DN                  0x0200
622
623 /* SRAM_IMPEDANCE */
624 #define RX_DRIVING_MASK         0x6000
625
626 /* SRAM_PHY_LOCK */
627 #define PHY_PATCH_LOCK          0x0001
628
629 /* MAC PASSTHRU */
630 #define AD_MASK                 0xfee0
631 #define BND_MASK                0x0004
632 #define BD_MASK                 0x0001
633 #define EFUSE                   0xcfdb
634 #define PASS_THRU_MASK          0x1
635
636 #define BP4_SUPER_ONLY          0x1578  /* RTL_VER_04 only */
637
638 enum rtl_register_content {
639         _1000bps        = 0x10,
640         _100bps         = 0x08,
641         _10bps          = 0x04,
642         LINK_STATUS     = 0x02,
643         FULL_DUP        = 0x01,
644 };
645
646 #define RTL8152_MAX_TX          4
647 #define RTL8152_MAX_RX          10
648 #define INTBUFSIZE              2
649 #define TX_ALIGN                4
650 #define RX_ALIGN                8
651
652 #define RTL8152_RX_MAX_PENDING  4096
653 #define RTL8152_RXFG_HEADSZ     256
654
655 #define INTR_LINK               0x0004
656
657 #define RTL8153_MAX_PACKET      9216 /* 9K */
658 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
659                                  ETH_FCS_LEN)
660 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
661 #define RTL8153_RMS             RTL8153_MAX_PACKET
662 #define RTL8152_TX_TIMEOUT      (5 * HZ)
663 #define RTL8152_NAPI_WEIGHT     64
664 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
665                                  sizeof(struct rx_desc) + RX_ALIGN)
666
667 /* rtl8152 flags */
668 enum rtl8152_flags {
669         RTL8152_UNPLUG = 0,
670         RTL8152_SET_RX_MODE,
671         WORK_ENABLE,
672         RTL8152_LINK_CHG,
673         SELECTIVE_SUSPEND,
674         PHY_RESET,
675         SCHEDULE_TASKLET,
676         GREEN_ETHERNET,
677         DELL_TB_RX_AGG_BUG,
678         LENOVO_MACPASSTHRU,
679 };
680
681 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2       0x3082
682 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2              0xa387
683
684 struct tally_counter {
685         __le64  tx_packets;
686         __le64  rx_packets;
687         __le64  tx_errors;
688         __le32  rx_errors;
689         __le16  rx_missed;
690         __le16  align_errors;
691         __le32  tx_one_collision;
692         __le32  tx_multi_collision;
693         __le64  rx_unicast;
694         __le64  rx_broadcast;
695         __le32  rx_multicast;
696         __le16  tx_aborted;
697         __le16  tx_underrun;
698 };
699
700 struct rx_desc {
701         __le32 opts1;
702 #define RX_LEN_MASK                     0x7fff
703
704         __le32 opts2;
705 #define RD_UDP_CS                       BIT(23)
706 #define RD_TCP_CS                       BIT(22)
707 #define RD_IPV6_CS                      BIT(20)
708 #define RD_IPV4_CS                      BIT(19)
709
710         __le32 opts3;
711 #define IPF                             BIT(23) /* IP checksum fail */
712 #define UDPF                            BIT(22) /* UDP checksum fail */
713 #define TCPF                            BIT(21) /* TCP checksum fail */
714 #define RX_VLAN_TAG                     BIT(16)
715
716         __le32 opts4;
717         __le32 opts5;
718         __le32 opts6;
719 };
720
721 struct tx_desc {
722         __le32 opts1;
723 #define TX_FS                   BIT(31) /* First segment of a packet */
724 #define TX_LS                   BIT(30) /* Final segment of a packet */
725 #define GTSENDV4                BIT(28)
726 #define GTSENDV6                BIT(27)
727 #define GTTCPHO_SHIFT           18
728 #define GTTCPHO_MAX             0x7fU
729 #define TX_LEN_MAX              0x3ffffU
730
731         __le32 opts2;
732 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
733 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
734 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
735 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
736 #define MSS_SHIFT               17
737 #define MSS_MAX                 0x7ffU
738 #define TCPHO_SHIFT             17
739 #define TCPHO_MAX               0x7ffU
740 #define TX_VLAN_TAG             BIT(16)
741 };
742
743 struct r8152;
744
745 struct rx_agg {
746         struct list_head list, info_list;
747         struct urb *urb;
748         struct r8152 *context;
749         struct page *page;
750         void *buffer;
751 };
752
753 struct tx_agg {
754         struct list_head list;
755         struct urb *urb;
756         struct r8152 *context;
757         void *buffer;
758         void *head;
759         u32 skb_num;
760         u32 skb_len;
761 };
762
763 struct r8152 {
764         unsigned long flags;
765         struct usb_device *udev;
766         struct napi_struct napi;
767         struct usb_interface *intf;
768         struct net_device *netdev;
769         struct urb *intr_urb;
770         struct tx_agg tx_info[RTL8152_MAX_TX];
771         struct list_head rx_info, rx_used;
772         struct list_head rx_done, tx_free;
773         struct sk_buff_head tx_queue, rx_queue;
774         spinlock_t rx_lock, tx_lock;
775         struct delayed_work schedule, hw_phy_work;
776         struct mii_if_info mii;
777         struct mutex control;   /* use for hw setting */
778 #ifdef CONFIG_PM_SLEEP
779         struct notifier_block pm_notifier;
780 #endif
781         struct tasklet_struct tx_tl;
782
783         struct rtl_ops {
784                 void (*init)(struct r8152 *tp);
785                 int (*enable)(struct r8152 *tp);
786                 void (*disable)(struct r8152 *tp);
787                 void (*up)(struct r8152 *tp);
788                 void (*down)(struct r8152 *tp);
789                 void (*unload)(struct r8152 *tp);
790                 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
791                 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
792                 bool (*in_nway)(struct r8152 *tp);
793                 void (*hw_phy_cfg)(struct r8152 *tp);
794                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
795         } rtl_ops;
796
797         struct ups_info {
798                 u32 _10m_ckdiv:1;
799                 u32 _250m_ckdiv:1;
800                 u32 aldps:1;
801                 u32 lite_mode:2;
802                 u32 speed_duplex:4;
803                 u32 eee:1;
804                 u32 eee_lite:1;
805                 u32 eee_ckdiv:1;
806                 u32 eee_plloff_100:1;
807                 u32 eee_plloff_giga:1;
808                 u32 eee_cmod_lv:1;
809                 u32 green:1;
810                 u32 flow_control:1;
811                 u32 ctap_short_off:1;
812         } ups_info;
813
814 #define RTL_VER_SIZE            32
815
816         struct rtl_fw {
817                 const char *fw_name;
818                 const struct firmware *fw;
819
820                 char version[RTL_VER_SIZE];
821                 int (*pre_fw)(struct r8152 *tp);
822                 int (*post_fw)(struct r8152 *tp);
823
824                 bool retry;
825         } rtl_fw;
826
827         atomic_t rx_count;
828
829         bool eee_en;
830         int intr_interval;
831         u32 saved_wolopts;
832         u32 msg_enable;
833         u32 tx_qlen;
834         u32 coalesce;
835         u32 advertising;
836         u32 rx_buf_sz;
837         u32 rx_copybreak;
838         u32 rx_pending;
839
840         u16 ocp_base;
841         u16 speed;
842         u16 eee_adv;
843         u8 *intr_buff;
844         u8 version;
845         u8 duplex;
846         u8 autoneg;
847 };
848
849 /**
850  * struct fw_block - block type and total length
851  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
852  *      RTL_FW_USB and so on.
853  * @length: total length of the current block.
854  */
855 struct fw_block {
856         __le32 type;
857         __le32 length;
858 } __packed;
859
860 /**
861  * struct fw_header - header of the firmware file
862  * @checksum: checksum of sha256 which is calculated from the whole file
863  *      except the checksum field of the file. That is, calculate sha256
864  *      from the version field to the end of the file.
865  * @version: version of this firmware.
866  * @blocks: the first firmware block of the file
867  */
868 struct fw_header {
869         u8 checksum[32];
870         char version[RTL_VER_SIZE];
871         struct fw_block blocks[];
872 } __packed;
873
874 /**
875  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
876  *      The layout of the firmware block is:
877  *      <struct fw_mac> + <info> + <firmware data>.
878  * @blk_hdr: firmware descriptor (type, length)
879  * @fw_offset: offset of the firmware binary data. The start address of
880  *      the data would be the address of struct fw_mac + @fw_offset.
881  * @fw_reg: the register to load the firmware. Depends on chip.
882  * @bp_ba_addr: the register to write break point base address. Depends on
883  *      chip.
884  * @bp_ba_value: break point base address. Depends on chip.
885  * @bp_en_addr: the register to write break point enabled mask. Depends
886  *      on chip.
887  * @bp_en_value: break point enabled mask. Depends on the firmware.
888  * @bp_start: the start register of break points. Depends on chip.
889  * @bp_num: the break point number which needs to be set for this firmware.
890  *      Depends on the firmware.
891  * @bp: break points. Depends on firmware.
892  * @reserved: reserved space (unused)
893  * @fw_ver_reg: the register to store the fw version.
894  * @fw_ver_data: the firmware version of the current type.
895  * @info: additional information for debugging, and is followed by the
896  *      binary data of firmware.
897  */
898 struct fw_mac {
899         struct fw_block blk_hdr;
900         __le16 fw_offset;
901         __le16 fw_reg;
902         __le16 bp_ba_addr;
903         __le16 bp_ba_value;
904         __le16 bp_en_addr;
905         __le16 bp_en_value;
906         __le16 bp_start;
907         __le16 bp_num;
908         __le16 bp[16]; /* any value determined by firmware */
909         __le32 reserved;
910         __le16 fw_ver_reg;
911         u8 fw_ver_data;
912         char info[];
913 } __packed;
914
915 /**
916  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
917  *      This is used to set patch key when loading the firmware of PHY.
918  * @blk_hdr: firmware descriptor (type, length)
919  * @key_reg: the register to write the patch key.
920  * @key_data: patch key.
921  * @reserved: reserved space (unused)
922  */
923 struct fw_phy_patch_key {
924         struct fw_block blk_hdr;
925         __le16 key_reg;
926         __le16 key_data;
927         __le32 reserved;
928 } __packed;
929
930 /**
931  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
932  *      The layout of the firmware block is:
933  *      <struct fw_phy_nc> + <info> + <firmware data>.
934  * @blk_hdr: firmware descriptor (type, length)
935  * @fw_offset: offset of the firmware binary data. The start address of
936  *      the data would be the address of struct fw_phy_nc + @fw_offset.
937  * @fw_reg: the register to load the firmware. Depends on chip.
938  * @ba_reg: the register to write the base address. Depends on chip.
939  * @ba_data: base address. Depends on chip.
940  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
941  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
942  * @mode_reg: the regitster of switching the mode.
943  * @mode_pre: the mode needing to be set before loading the firmware.
944  * @mode_post: the mode to be set when finishing to load the firmware.
945  * @reserved: reserved space (unused)
946  * @bp_start: the start register of break points. Depends on chip.
947  * @bp_num: the break point number which needs to be set for this firmware.
948  *      Depends on the firmware.
949  * @bp: break points. Depends on firmware.
950  * @info: additional information for debugging, and is followed by the
951  *      binary data of firmware.
952  */
953 struct fw_phy_nc {
954         struct fw_block blk_hdr;
955         __le16 fw_offset;
956         __le16 fw_reg;
957         __le16 ba_reg;
958         __le16 ba_data;
959         __le16 patch_en_addr;
960         __le16 patch_en_value;
961         __le16 mode_reg;
962         __le16 mode_pre;
963         __le16 mode_post;
964         __le16 reserved;
965         __le16 bp_start;
966         __le16 bp_num;
967         __le16 bp[4];
968         char info[];
969 } __packed;
970
971 enum rtl_fw_type {
972         RTL_FW_END = 0,
973         RTL_FW_PLA,
974         RTL_FW_USB,
975         RTL_FW_PHY_START,
976         RTL_FW_PHY_STOP,
977         RTL_FW_PHY_NC,
978 };
979
980 enum rtl_version {
981         RTL_VER_UNKNOWN = 0,
982         RTL_VER_01,
983         RTL_VER_02,
984         RTL_VER_03,
985         RTL_VER_04,
986         RTL_VER_05,
987         RTL_VER_06,
988         RTL_VER_07,
989         RTL_VER_08,
990         RTL_VER_09,
991         RTL_VER_MAX
992 };
993
994 enum tx_csum_stat {
995         TX_CSUM_SUCCESS = 0,
996         TX_CSUM_TSO,
997         TX_CSUM_NONE
998 };
999
1000 #define RTL_ADVERTISED_10_HALF                  BIT(0)
1001 #define RTL_ADVERTISED_10_FULL                  BIT(1)
1002 #define RTL_ADVERTISED_100_HALF                 BIT(2)
1003 #define RTL_ADVERTISED_100_FULL                 BIT(3)
1004 #define RTL_ADVERTISED_1000_HALF                BIT(4)
1005 #define RTL_ADVERTISED_1000_FULL                BIT(5)
1006
1007 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1008  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1009  */
1010 static const int multicast_filter_limit = 32;
1011 static unsigned int agg_buf_sz = 16384;
1012
1013 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
1014                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
1015
1016 static
1017 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1018 {
1019         int ret;
1020         void *tmp;
1021
1022         tmp = kmalloc(size, GFP_KERNEL);
1023         if (!tmp)
1024                 return -ENOMEM;
1025
1026         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1027                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1028                               value, index, tmp, size, 500);
1029         if (ret < 0)
1030                 memset(data, 0xff, size);
1031         else
1032                 memcpy(data, tmp, size);
1033
1034         kfree(tmp);
1035
1036         return ret;
1037 }
1038
1039 static
1040 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1041 {
1042         int ret;
1043         void *tmp;
1044
1045         tmp = kmemdup(data, size, GFP_KERNEL);
1046         if (!tmp)
1047                 return -ENOMEM;
1048
1049         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1050                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1051                               value, index, tmp, size, 500);
1052
1053         kfree(tmp);
1054
1055         return ret;
1056 }
1057
1058 static void rtl_set_unplug(struct r8152 *tp)
1059 {
1060         if (tp->udev->state == USB_STATE_NOTATTACHED) {
1061                 set_bit(RTL8152_UNPLUG, &tp->flags);
1062                 smp_mb__after_atomic();
1063         }
1064 }
1065
1066 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1067                             void *data, u16 type)
1068 {
1069         u16 limit = 64;
1070         int ret = 0;
1071
1072         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1073                 return -ENODEV;
1074
1075         /* both size and indix must be 4 bytes align */
1076         if ((size & 3) || !size || (index & 3) || !data)
1077                 return -EPERM;
1078
1079         if ((u32)index + (u32)size > 0xffff)
1080                 return -EPERM;
1081
1082         while (size) {
1083                 if (size > limit) {
1084                         ret = get_registers(tp, index, type, limit, data);
1085                         if (ret < 0)
1086                                 break;
1087
1088                         index += limit;
1089                         data += limit;
1090                         size -= limit;
1091                 } else {
1092                         ret = get_registers(tp, index, type, size, data);
1093                         if (ret < 0)
1094                                 break;
1095
1096                         index += size;
1097                         data += size;
1098                         size = 0;
1099                         break;
1100                 }
1101         }
1102
1103         if (ret == -ENODEV)
1104                 rtl_set_unplug(tp);
1105
1106         return ret;
1107 }
1108
1109 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1110                              u16 size, void *data, u16 type)
1111 {
1112         int ret;
1113         u16 byteen_start, byteen_end, byen;
1114         u16 limit = 512;
1115
1116         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117                 return -ENODEV;
1118
1119         /* both size and indix must be 4 bytes align */
1120         if ((size & 3) || !size || (index & 3) || !data)
1121                 return -EPERM;
1122
1123         if ((u32)index + (u32)size > 0xffff)
1124                 return -EPERM;
1125
1126         byteen_start = byteen & BYTE_EN_START_MASK;
1127         byteen_end = byteen & BYTE_EN_END_MASK;
1128
1129         byen = byteen_start | (byteen_start << 4);
1130         ret = set_registers(tp, index, type | byen, 4, data);
1131         if (ret < 0)
1132                 goto error1;
1133
1134         index += 4;
1135         data += 4;
1136         size -= 4;
1137
1138         if (size) {
1139                 size -= 4;
1140
1141                 while (size) {
1142                         if (size > limit) {
1143                                 ret = set_registers(tp, index,
1144                                                     type | BYTE_EN_DWORD,
1145                                                     limit, data);
1146                                 if (ret < 0)
1147                                         goto error1;
1148
1149                                 index += limit;
1150                                 data += limit;
1151                                 size -= limit;
1152                         } else {
1153                                 ret = set_registers(tp, index,
1154                                                     type | BYTE_EN_DWORD,
1155                                                     size, data);
1156                                 if (ret < 0)
1157                                         goto error1;
1158
1159                                 index += size;
1160                                 data += size;
1161                                 size = 0;
1162                                 break;
1163                         }
1164                 }
1165
1166                 byen = byteen_end | (byteen_end >> 4);
1167                 ret = set_registers(tp, index, type | byen, 4, data);
1168                 if (ret < 0)
1169                         goto error1;
1170         }
1171
1172 error1:
1173         if (ret == -ENODEV)
1174                 rtl_set_unplug(tp);
1175
1176         return ret;
1177 }
1178
1179 static inline
1180 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1181 {
1182         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1183 }
1184
1185 static inline
1186 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1187 {
1188         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1189 }
1190
1191 static inline
1192 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1193 {
1194         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1195 }
1196
1197 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1198 {
1199         __le32 data;
1200
1201         generic_ocp_read(tp, index, sizeof(data), &data, type);
1202
1203         return __le32_to_cpu(data);
1204 }
1205
1206 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1207 {
1208         __le32 tmp = __cpu_to_le32(data);
1209
1210         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1211 }
1212
1213 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1214 {
1215         u32 data;
1216         __le32 tmp;
1217         u16 byen = BYTE_EN_WORD;
1218         u8 shift = index & 2;
1219
1220         index &= ~3;
1221         byen <<= shift;
1222
1223         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1224
1225         data = __le32_to_cpu(tmp);
1226         data >>= (shift * 8);
1227         data &= 0xffff;
1228
1229         return (u16)data;
1230 }
1231
1232 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1233 {
1234         u32 mask = 0xffff;
1235         __le32 tmp;
1236         u16 byen = BYTE_EN_WORD;
1237         u8 shift = index & 2;
1238
1239         data &= mask;
1240
1241         if (index & 2) {
1242                 byen <<= shift;
1243                 mask <<= (shift * 8);
1244                 data <<= (shift * 8);
1245                 index &= ~3;
1246         }
1247
1248         tmp = __cpu_to_le32(data);
1249
1250         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1251 }
1252
1253 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1254 {
1255         u32 data;
1256         __le32 tmp;
1257         u8 shift = index & 3;
1258
1259         index &= ~3;
1260
1261         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1262
1263         data = __le32_to_cpu(tmp);
1264         data >>= (shift * 8);
1265         data &= 0xff;
1266
1267         return (u8)data;
1268 }
1269
1270 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1271 {
1272         u32 mask = 0xff;
1273         __le32 tmp;
1274         u16 byen = BYTE_EN_BYTE;
1275         u8 shift = index & 3;
1276
1277         data &= mask;
1278
1279         if (index & 3) {
1280                 byen <<= shift;
1281                 mask <<= (shift * 8);
1282                 data <<= (shift * 8);
1283                 index &= ~3;
1284         }
1285
1286         tmp = __cpu_to_le32(data);
1287
1288         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1289 }
1290
1291 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1292 {
1293         u16 ocp_base, ocp_index;
1294
1295         ocp_base = addr & 0xf000;
1296         if (ocp_base != tp->ocp_base) {
1297                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1298                 tp->ocp_base = ocp_base;
1299         }
1300
1301         ocp_index = (addr & 0x0fff) | 0xb000;
1302         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1303 }
1304
1305 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1306 {
1307         u16 ocp_base, ocp_index;
1308
1309         ocp_base = addr & 0xf000;
1310         if (ocp_base != tp->ocp_base) {
1311                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1312                 tp->ocp_base = ocp_base;
1313         }
1314
1315         ocp_index = (addr & 0x0fff) | 0xb000;
1316         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1317 }
1318
1319 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1320 {
1321         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1322 }
1323
1324 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1325 {
1326         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1327 }
1328
1329 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1330 {
1331         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1332         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1333 }
1334
1335 static u16 sram_read(struct r8152 *tp, u16 addr)
1336 {
1337         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1338         return ocp_reg_read(tp, OCP_SRAM_DATA);
1339 }
1340
1341 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1342 {
1343         struct r8152 *tp = netdev_priv(netdev);
1344         int ret;
1345
1346         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1347                 return -ENODEV;
1348
1349         if (phy_id != R8152_PHY_ID)
1350                 return -EINVAL;
1351
1352         ret = r8152_mdio_read(tp, reg);
1353
1354         return ret;
1355 }
1356
1357 static
1358 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1359 {
1360         struct r8152 *tp = netdev_priv(netdev);
1361
1362         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1363                 return;
1364
1365         if (phy_id != R8152_PHY_ID)
1366                 return;
1367
1368         r8152_mdio_write(tp, reg, val);
1369 }
1370
1371 static int
1372 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1373
1374 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1375 {
1376         struct r8152 *tp = netdev_priv(netdev);
1377         struct sockaddr *addr = p;
1378         int ret = -EADDRNOTAVAIL;
1379
1380         if (!is_valid_ether_addr(addr->sa_data))
1381                 goto out1;
1382
1383         ret = usb_autopm_get_interface(tp->intf);
1384         if (ret < 0)
1385                 goto out1;
1386
1387         mutex_lock(&tp->control);
1388
1389         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1390
1391         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1392         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1393         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1394
1395         mutex_unlock(&tp->control);
1396
1397         usb_autopm_put_interface(tp->intf);
1398 out1:
1399         return ret;
1400 }
1401
1402 /* Devices containing proper chips can support a persistent
1403  * host system provided MAC address.
1404  * Examples of this are Dell TB15 and Dell WD15 docks
1405  */
1406 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1407 {
1408         acpi_status status;
1409         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1410         union acpi_object *obj;
1411         int ret = -EINVAL;
1412         u32 ocp_data;
1413         unsigned char buf[6];
1414         char *mac_obj_name;
1415         acpi_object_type mac_obj_type;
1416         int mac_strlen;
1417
1418         if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1419                 mac_obj_name = "\\MACA";
1420                 mac_obj_type = ACPI_TYPE_STRING;
1421                 mac_strlen = 0x16;
1422         } else {
1423                 /* test for -AD variant of RTL8153 */
1424                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1425                 if ((ocp_data & AD_MASK) == 0x1000) {
1426                         /* test for MAC address pass-through bit */
1427                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1428                         if ((ocp_data & PASS_THRU_MASK) != 1) {
1429                                 netif_dbg(tp, probe, tp->netdev,
1430                                                 "No efuse for RTL8153-AD MAC pass through\n");
1431                                 return -ENODEV;
1432                         }
1433                 } else {
1434                         /* test for RTL8153-BND and RTL8153-BD */
1435                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1436                         if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1437                                 netif_dbg(tp, probe, tp->netdev,
1438                                                 "Invalid variant for MAC pass through\n");
1439                                 return -ENODEV;
1440                         }
1441                 }
1442
1443                 mac_obj_name = "\\_SB.AMAC";
1444                 mac_obj_type = ACPI_TYPE_BUFFER;
1445                 mac_strlen = 0x17;
1446         }
1447
1448         /* returns _AUXMAC_#AABBCCDDEEFF# */
1449         status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1450         obj = (union acpi_object *)buffer.pointer;
1451         if (!ACPI_SUCCESS(status))
1452                 return -ENODEV;
1453         if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1454                 netif_warn(tp, probe, tp->netdev,
1455                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1456                            obj->type, obj->string.length);
1457                 goto amacout;
1458         }
1459
1460         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1461             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1462                 netif_warn(tp, probe, tp->netdev,
1463                            "Invalid header when reading pass-thru MAC addr\n");
1464                 goto amacout;
1465         }
1466         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1467         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1468                 netif_warn(tp, probe, tp->netdev,
1469                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1470                            ret, buf);
1471                 ret = -EINVAL;
1472                 goto amacout;
1473         }
1474         memcpy(sa->sa_data, buf, 6);
1475         netif_info(tp, probe, tp->netdev,
1476                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1477
1478 amacout:
1479         kfree(obj);
1480         return ret;
1481 }
1482
1483 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1484 {
1485         struct net_device *dev = tp->netdev;
1486         int ret;
1487
1488         sa->sa_family = dev->type;
1489
1490         ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1491         if (ret < 0) {
1492                 if (tp->version == RTL_VER_01) {
1493                         ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1494                 } else {
1495                         /* if device doesn't support MAC pass through this will
1496                          * be expected to be non-zero
1497                          */
1498                         ret = vendor_mac_passthru_addr_read(tp, sa);
1499                         if (ret < 0)
1500                                 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1501                                                    sa->sa_data);
1502                 }
1503         }
1504
1505         if (ret < 0) {
1506                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1507         } else if (!is_valid_ether_addr(sa->sa_data)) {
1508                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1509                           sa->sa_data);
1510                 eth_hw_addr_random(dev);
1511                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1512                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1513                            sa->sa_data);
1514                 return 0;
1515         }
1516
1517         return ret;
1518 }
1519
1520 static int set_ethernet_addr(struct r8152 *tp)
1521 {
1522         struct net_device *dev = tp->netdev;
1523         struct sockaddr sa;
1524         int ret;
1525
1526         ret = determine_ethernet_addr(tp, &sa);
1527         if (ret < 0)
1528                 return ret;
1529
1530         if (tp->version == RTL_VER_01)
1531                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1532         else
1533                 ret = rtl8152_set_mac_address(dev, &sa);
1534
1535         return ret;
1536 }
1537
1538 static void read_bulk_callback(struct urb *urb)
1539 {
1540         struct net_device *netdev;
1541         int status = urb->status;
1542         struct rx_agg *agg;
1543         struct r8152 *tp;
1544         unsigned long flags;
1545
1546         agg = urb->context;
1547         if (!agg)
1548                 return;
1549
1550         tp = agg->context;
1551         if (!tp)
1552                 return;
1553
1554         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1555                 return;
1556
1557         if (!test_bit(WORK_ENABLE, &tp->flags))
1558                 return;
1559
1560         netdev = tp->netdev;
1561
1562         /* When link down, the driver would cancel all bulks. */
1563         /* This avoid the re-submitting bulk */
1564         if (!netif_carrier_ok(netdev))
1565                 return;
1566
1567         usb_mark_last_busy(tp->udev);
1568
1569         switch (status) {
1570         case 0:
1571                 if (urb->actual_length < ETH_ZLEN)
1572                         break;
1573
1574                 spin_lock_irqsave(&tp->rx_lock, flags);
1575                 list_add_tail(&agg->list, &tp->rx_done);
1576                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1577                 napi_schedule(&tp->napi);
1578                 return;
1579         case -ESHUTDOWN:
1580                 rtl_set_unplug(tp);
1581                 netif_device_detach(tp->netdev);
1582                 return;
1583         case -ENOENT:
1584                 return; /* the urb is in unlink state */
1585         case -ETIME:
1586                 if (net_ratelimit())
1587                         netdev_warn(netdev, "maybe reset is needed?\n");
1588                 break;
1589         default:
1590                 if (net_ratelimit())
1591                         netdev_warn(netdev, "Rx status %d\n", status);
1592                 break;
1593         }
1594
1595         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1596 }
1597
1598 static void write_bulk_callback(struct urb *urb)
1599 {
1600         struct net_device_stats *stats;
1601         struct net_device *netdev;
1602         struct tx_agg *agg;
1603         struct r8152 *tp;
1604         unsigned long flags;
1605         int status = urb->status;
1606
1607         agg = urb->context;
1608         if (!agg)
1609                 return;
1610
1611         tp = agg->context;
1612         if (!tp)
1613                 return;
1614
1615         netdev = tp->netdev;
1616         stats = &netdev->stats;
1617         if (status) {
1618                 if (net_ratelimit())
1619                         netdev_warn(netdev, "Tx status %d\n", status);
1620                 stats->tx_errors += agg->skb_num;
1621         } else {
1622                 stats->tx_packets += agg->skb_num;
1623                 stats->tx_bytes += agg->skb_len;
1624         }
1625
1626         spin_lock_irqsave(&tp->tx_lock, flags);
1627         list_add_tail(&agg->list, &tp->tx_free);
1628         spin_unlock_irqrestore(&tp->tx_lock, flags);
1629
1630         usb_autopm_put_interface_async(tp->intf);
1631
1632         if (!netif_carrier_ok(netdev))
1633                 return;
1634
1635         if (!test_bit(WORK_ENABLE, &tp->flags))
1636                 return;
1637
1638         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1639                 return;
1640
1641         if (!skb_queue_empty(&tp->tx_queue))
1642                 tasklet_schedule(&tp->tx_tl);
1643 }
1644
1645 static void intr_callback(struct urb *urb)
1646 {
1647         struct r8152 *tp;
1648         __le16 *d;
1649         int status = urb->status;
1650         int res;
1651
1652         tp = urb->context;
1653         if (!tp)
1654                 return;
1655
1656         if (!test_bit(WORK_ENABLE, &tp->flags))
1657                 return;
1658
1659         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1660                 return;
1661
1662         switch (status) {
1663         case 0:                 /* success */
1664                 break;
1665         case -ECONNRESET:       /* unlink */
1666         case -ESHUTDOWN:
1667                 netif_device_detach(tp->netdev);
1668                 fallthrough;
1669         case -ENOENT:
1670         case -EPROTO:
1671                 netif_info(tp, intr, tp->netdev,
1672                            "Stop submitting intr, status %d\n", status);
1673                 return;
1674         case -EOVERFLOW:
1675                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1676                 goto resubmit;
1677         /* -EPIPE:  should clear the halt */
1678         default:
1679                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1680                 goto resubmit;
1681         }
1682
1683         d = urb->transfer_buffer;
1684         if (INTR_LINK & __le16_to_cpu(d[0])) {
1685                 if (!netif_carrier_ok(tp->netdev)) {
1686                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1687                         schedule_delayed_work(&tp->schedule, 0);
1688                 }
1689         } else {
1690                 if (netif_carrier_ok(tp->netdev)) {
1691                         netif_stop_queue(tp->netdev);
1692                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1693                         schedule_delayed_work(&tp->schedule, 0);
1694                 }
1695         }
1696
1697 resubmit:
1698         res = usb_submit_urb(urb, GFP_ATOMIC);
1699         if (res == -ENODEV) {
1700                 rtl_set_unplug(tp);
1701                 netif_device_detach(tp->netdev);
1702         } else if (res) {
1703                 netif_err(tp, intr, tp->netdev,
1704                           "can't resubmit intr, status %d\n", res);
1705         }
1706 }
1707
1708 static inline void *rx_agg_align(void *data)
1709 {
1710         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1711 }
1712
1713 static inline void *tx_agg_align(void *data)
1714 {
1715         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1716 }
1717
1718 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1719 {
1720         list_del(&agg->info_list);
1721
1722         usb_free_urb(agg->urb);
1723         put_page(agg->page);
1724         kfree(agg);
1725
1726         atomic_dec(&tp->rx_count);
1727 }
1728
1729 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1730 {
1731         struct net_device *netdev = tp->netdev;
1732         int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1733         unsigned int order = get_order(tp->rx_buf_sz);
1734         struct rx_agg *rx_agg;
1735         unsigned long flags;
1736
1737         rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1738         if (!rx_agg)
1739                 return NULL;
1740
1741         rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1742         if (!rx_agg->page)
1743                 goto free_rx;
1744
1745         rx_agg->buffer = page_address(rx_agg->page);
1746
1747         rx_agg->urb = usb_alloc_urb(0, mflags);
1748         if (!rx_agg->urb)
1749                 goto free_buf;
1750
1751         rx_agg->context = tp;
1752
1753         INIT_LIST_HEAD(&rx_agg->list);
1754         INIT_LIST_HEAD(&rx_agg->info_list);
1755         spin_lock_irqsave(&tp->rx_lock, flags);
1756         list_add_tail(&rx_agg->info_list, &tp->rx_info);
1757         spin_unlock_irqrestore(&tp->rx_lock, flags);
1758
1759         atomic_inc(&tp->rx_count);
1760
1761         return rx_agg;
1762
1763 free_buf:
1764         __free_pages(rx_agg->page, order);
1765 free_rx:
1766         kfree(rx_agg);
1767         return NULL;
1768 }
1769
1770 static void free_all_mem(struct r8152 *tp)
1771 {
1772         struct rx_agg *agg, *agg_next;
1773         unsigned long flags;
1774         int i;
1775
1776         spin_lock_irqsave(&tp->rx_lock, flags);
1777
1778         list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1779                 free_rx_agg(tp, agg);
1780
1781         spin_unlock_irqrestore(&tp->rx_lock, flags);
1782
1783         WARN_ON(atomic_read(&tp->rx_count));
1784
1785         for (i = 0; i < RTL8152_MAX_TX; i++) {
1786                 usb_free_urb(tp->tx_info[i].urb);
1787                 tp->tx_info[i].urb = NULL;
1788
1789                 kfree(tp->tx_info[i].buffer);
1790                 tp->tx_info[i].buffer = NULL;
1791                 tp->tx_info[i].head = NULL;
1792         }
1793
1794         usb_free_urb(tp->intr_urb);
1795         tp->intr_urb = NULL;
1796
1797         kfree(tp->intr_buff);
1798         tp->intr_buff = NULL;
1799 }
1800
1801 static int alloc_all_mem(struct r8152 *tp)
1802 {
1803         struct net_device *netdev = tp->netdev;
1804         struct usb_interface *intf = tp->intf;
1805         struct usb_host_interface *alt = intf->cur_altsetting;
1806         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1807         int node, i;
1808
1809         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1810
1811         spin_lock_init(&tp->rx_lock);
1812         spin_lock_init(&tp->tx_lock);
1813         INIT_LIST_HEAD(&tp->rx_info);
1814         INIT_LIST_HEAD(&tp->tx_free);
1815         INIT_LIST_HEAD(&tp->rx_done);
1816         skb_queue_head_init(&tp->tx_queue);
1817         skb_queue_head_init(&tp->rx_queue);
1818         atomic_set(&tp->rx_count, 0);
1819
1820         for (i = 0; i < RTL8152_MAX_RX; i++) {
1821                 if (!alloc_rx_agg(tp, GFP_KERNEL))
1822                         goto err1;
1823         }
1824
1825         for (i = 0; i < RTL8152_MAX_TX; i++) {
1826                 struct urb *urb;
1827                 u8 *buf;
1828
1829                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1830                 if (!buf)
1831                         goto err1;
1832
1833                 if (buf != tx_agg_align(buf)) {
1834                         kfree(buf);
1835                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1836                                            node);
1837                         if (!buf)
1838                                 goto err1;
1839                 }
1840
1841                 urb = usb_alloc_urb(0, GFP_KERNEL);
1842                 if (!urb) {
1843                         kfree(buf);
1844                         goto err1;
1845                 }
1846
1847                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1848                 tp->tx_info[i].context = tp;
1849                 tp->tx_info[i].urb = urb;
1850                 tp->tx_info[i].buffer = buf;
1851                 tp->tx_info[i].head = tx_agg_align(buf);
1852
1853                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1854         }
1855
1856         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1857         if (!tp->intr_urb)
1858                 goto err1;
1859
1860         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1861         if (!tp->intr_buff)
1862                 goto err1;
1863
1864         tp->intr_interval = (int)ep_intr->desc.bInterval;
1865         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1866                          tp->intr_buff, INTBUFSIZE, intr_callback,
1867                          tp, tp->intr_interval);
1868
1869         return 0;
1870
1871 err1:
1872         free_all_mem(tp);
1873         return -ENOMEM;
1874 }
1875
1876 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1877 {
1878         struct tx_agg *agg = NULL;
1879         unsigned long flags;
1880
1881         if (list_empty(&tp->tx_free))
1882                 return NULL;
1883
1884         spin_lock_irqsave(&tp->tx_lock, flags);
1885         if (!list_empty(&tp->tx_free)) {
1886                 struct list_head *cursor;
1887
1888                 cursor = tp->tx_free.next;
1889                 list_del_init(cursor);
1890                 agg = list_entry(cursor, struct tx_agg, list);
1891         }
1892         spin_unlock_irqrestore(&tp->tx_lock, flags);
1893
1894         return agg;
1895 }
1896
1897 /* r8152_csum_workaround()
1898  * The hw limits the value of the transport offset. When the offset is out of
1899  * range, calculate the checksum by sw.
1900  */
1901 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1902                                   struct sk_buff_head *list)
1903 {
1904         if (skb_shinfo(skb)->gso_size) {
1905                 netdev_features_t features = tp->netdev->features;
1906                 struct sk_buff *segs, *seg, *next;
1907                 struct sk_buff_head seg_list;
1908
1909                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1910                 segs = skb_gso_segment(skb, features);
1911                 if (IS_ERR(segs) || !segs)
1912                         goto drop;
1913
1914                 __skb_queue_head_init(&seg_list);
1915
1916                 skb_list_walk_safe(segs, seg, next) {
1917                         skb_mark_not_on_list(seg);
1918                         __skb_queue_tail(&seg_list, seg);
1919                 }
1920
1921                 skb_queue_splice(&seg_list, list);
1922                 dev_kfree_skb(skb);
1923         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1924                 if (skb_checksum_help(skb) < 0)
1925                         goto drop;
1926
1927                 __skb_queue_head(list, skb);
1928         } else {
1929                 struct net_device_stats *stats;
1930
1931 drop:
1932                 stats = &tp->netdev->stats;
1933                 stats->tx_dropped++;
1934                 dev_kfree_skb(skb);
1935         }
1936 }
1937
1938 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1939 {
1940         if (skb_vlan_tag_present(skb)) {
1941                 u32 opts2;
1942
1943                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1944                 desc->opts2 |= cpu_to_le32(opts2);
1945         }
1946 }
1947
1948 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1949 {
1950         u32 opts2 = le32_to_cpu(desc->opts2);
1951
1952         if (opts2 & RX_VLAN_TAG)
1953                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1954                                        swab16(opts2 & 0xffff));
1955 }
1956
1957 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1958                          struct sk_buff *skb, u32 len, u32 transport_offset)
1959 {
1960         u32 mss = skb_shinfo(skb)->gso_size;
1961         u32 opts1, opts2 = 0;
1962         int ret = TX_CSUM_SUCCESS;
1963
1964         WARN_ON_ONCE(len > TX_LEN_MAX);
1965
1966         opts1 = len | TX_FS | TX_LS;
1967
1968         if (mss) {
1969                 if (transport_offset > GTTCPHO_MAX) {
1970                         netif_warn(tp, tx_err, tp->netdev,
1971                                    "Invalid transport offset 0x%x for TSO\n",
1972                                    transport_offset);
1973                         ret = TX_CSUM_TSO;
1974                         goto unavailable;
1975                 }
1976
1977                 switch (vlan_get_protocol(skb)) {
1978                 case htons(ETH_P_IP):
1979                         opts1 |= GTSENDV4;
1980                         break;
1981
1982                 case htons(ETH_P_IPV6):
1983                         if (skb_cow_head(skb, 0)) {
1984                                 ret = TX_CSUM_TSO;
1985                                 goto unavailable;
1986                         }
1987                         tcp_v6_gso_csum_prep(skb);
1988                         opts1 |= GTSENDV6;
1989                         break;
1990
1991                 default:
1992                         WARN_ON_ONCE(1);
1993                         break;
1994                 }
1995
1996                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1997                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1998         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1999                 u8 ip_protocol;
2000
2001                 if (transport_offset > TCPHO_MAX) {
2002                         netif_warn(tp, tx_err, tp->netdev,
2003                                    "Invalid transport offset 0x%x\n",
2004                                    transport_offset);
2005                         ret = TX_CSUM_NONE;
2006                         goto unavailable;
2007                 }
2008
2009                 switch (vlan_get_protocol(skb)) {
2010                 case htons(ETH_P_IP):
2011                         opts2 |= IPV4_CS;
2012                         ip_protocol = ip_hdr(skb)->protocol;
2013                         break;
2014
2015                 case htons(ETH_P_IPV6):
2016                         opts2 |= IPV6_CS;
2017                         ip_protocol = ipv6_hdr(skb)->nexthdr;
2018                         break;
2019
2020                 default:
2021                         ip_protocol = IPPROTO_RAW;
2022                         break;
2023                 }
2024
2025                 if (ip_protocol == IPPROTO_TCP)
2026                         opts2 |= TCP_CS;
2027                 else if (ip_protocol == IPPROTO_UDP)
2028                         opts2 |= UDP_CS;
2029                 else
2030                         WARN_ON_ONCE(1);
2031
2032                 opts2 |= transport_offset << TCPHO_SHIFT;
2033         }
2034
2035         desc->opts2 = cpu_to_le32(opts2);
2036         desc->opts1 = cpu_to_le32(opts1);
2037
2038 unavailable:
2039         return ret;
2040 }
2041
2042 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2043 {
2044         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2045         int remain, ret;
2046         u8 *tx_data;
2047
2048         __skb_queue_head_init(&skb_head);
2049         spin_lock(&tx_queue->lock);
2050         skb_queue_splice_init(tx_queue, &skb_head);
2051         spin_unlock(&tx_queue->lock);
2052
2053         tx_data = agg->head;
2054         agg->skb_num = 0;
2055         agg->skb_len = 0;
2056         remain = agg_buf_sz;
2057
2058         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2059                 struct tx_desc *tx_desc;
2060                 struct sk_buff *skb;
2061                 unsigned int len;
2062                 u32 offset;
2063
2064                 skb = __skb_dequeue(&skb_head);
2065                 if (!skb)
2066                         break;
2067
2068                 len = skb->len + sizeof(*tx_desc);
2069
2070                 if (len > remain) {
2071                         __skb_queue_head(&skb_head, skb);
2072                         break;
2073                 }
2074
2075                 tx_data = tx_agg_align(tx_data);
2076                 tx_desc = (struct tx_desc *)tx_data;
2077
2078                 offset = (u32)skb_transport_offset(skb);
2079
2080                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2081                         r8152_csum_workaround(tp, skb, &skb_head);
2082                         continue;
2083                 }
2084
2085                 rtl_tx_vlan_tag(tx_desc, skb);
2086
2087                 tx_data += sizeof(*tx_desc);
2088
2089                 len = skb->len;
2090                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2091                         struct net_device_stats *stats = &tp->netdev->stats;
2092
2093                         stats->tx_dropped++;
2094                         dev_kfree_skb_any(skb);
2095                         tx_data -= sizeof(*tx_desc);
2096                         continue;
2097                 }
2098
2099                 tx_data += len;
2100                 agg->skb_len += len;
2101                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2102
2103                 dev_kfree_skb_any(skb);
2104
2105                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2106
2107                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2108                         break;
2109         }
2110
2111         if (!skb_queue_empty(&skb_head)) {
2112                 spin_lock(&tx_queue->lock);
2113                 skb_queue_splice(&skb_head, tx_queue);
2114                 spin_unlock(&tx_queue->lock);
2115         }
2116
2117         netif_tx_lock(tp->netdev);
2118
2119         if (netif_queue_stopped(tp->netdev) &&
2120             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2121                 netif_wake_queue(tp->netdev);
2122
2123         netif_tx_unlock(tp->netdev);
2124
2125         ret = usb_autopm_get_interface_async(tp->intf);
2126         if (ret < 0)
2127                 goto out_tx_fill;
2128
2129         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2130                           agg->head, (int)(tx_data - (u8 *)agg->head),
2131                           (usb_complete_t)write_bulk_callback, agg);
2132
2133         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2134         if (ret < 0)
2135                 usb_autopm_put_interface_async(tp->intf);
2136
2137 out_tx_fill:
2138         return ret;
2139 }
2140
2141 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2142 {
2143         u8 checksum = CHECKSUM_NONE;
2144         u32 opts2, opts3;
2145
2146         if (!(tp->netdev->features & NETIF_F_RXCSUM))
2147                 goto return_result;
2148
2149         opts2 = le32_to_cpu(rx_desc->opts2);
2150         opts3 = le32_to_cpu(rx_desc->opts3);
2151
2152         if (opts2 & RD_IPV4_CS) {
2153                 if (opts3 & IPF)
2154                         checksum = CHECKSUM_NONE;
2155                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2156                         checksum = CHECKSUM_UNNECESSARY;
2157                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2158                         checksum = CHECKSUM_UNNECESSARY;
2159         } else if (opts2 & RD_IPV6_CS) {
2160                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2161                         checksum = CHECKSUM_UNNECESSARY;
2162                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2163                         checksum = CHECKSUM_UNNECESSARY;
2164         }
2165
2166 return_result:
2167         return checksum;
2168 }
2169
2170 static inline bool rx_count_exceed(struct r8152 *tp)
2171 {
2172         return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2173 }
2174
2175 static inline int agg_offset(struct rx_agg *agg, void *addr)
2176 {
2177         return (int)(addr - agg->buffer);
2178 }
2179
2180 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2181 {
2182         struct rx_agg *agg, *agg_next, *agg_free = NULL;
2183         unsigned long flags;
2184
2185         spin_lock_irqsave(&tp->rx_lock, flags);
2186
2187         list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2188                 if (page_count(agg->page) == 1) {
2189                         if (!agg_free) {
2190                                 list_del_init(&agg->list);
2191                                 agg_free = agg;
2192                                 continue;
2193                         }
2194                         if (rx_count_exceed(tp)) {
2195                                 list_del_init(&agg->list);
2196                                 free_rx_agg(tp, agg);
2197                         }
2198                         break;
2199                 }
2200         }
2201
2202         spin_unlock_irqrestore(&tp->rx_lock, flags);
2203
2204         if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2205                 agg_free = alloc_rx_agg(tp, mflags);
2206
2207         return agg_free;
2208 }
2209
2210 static int rx_bottom(struct r8152 *tp, int budget)
2211 {
2212         unsigned long flags;
2213         struct list_head *cursor, *next, rx_queue;
2214         int ret = 0, work_done = 0;
2215         struct napi_struct *napi = &tp->napi;
2216
2217         if (!skb_queue_empty(&tp->rx_queue)) {
2218                 while (work_done < budget) {
2219                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2220                         struct net_device *netdev = tp->netdev;
2221                         struct net_device_stats *stats = &netdev->stats;
2222                         unsigned int pkt_len;
2223
2224                         if (!skb)
2225                                 break;
2226
2227                         pkt_len = skb->len;
2228                         napi_gro_receive(napi, skb);
2229                         work_done++;
2230                         stats->rx_packets++;
2231                         stats->rx_bytes += pkt_len;
2232                 }
2233         }
2234
2235         if (list_empty(&tp->rx_done))
2236                 goto out1;
2237
2238         INIT_LIST_HEAD(&rx_queue);
2239         spin_lock_irqsave(&tp->rx_lock, flags);
2240         list_splice_init(&tp->rx_done, &rx_queue);
2241         spin_unlock_irqrestore(&tp->rx_lock, flags);
2242
2243         list_for_each_safe(cursor, next, &rx_queue) {
2244                 struct rx_desc *rx_desc;
2245                 struct rx_agg *agg, *agg_free;
2246                 int len_used = 0;
2247                 struct urb *urb;
2248                 u8 *rx_data;
2249
2250                 list_del_init(cursor);
2251
2252                 agg = list_entry(cursor, struct rx_agg, list);
2253                 urb = agg->urb;
2254                 if (urb->actual_length < ETH_ZLEN)
2255                         goto submit;
2256
2257                 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2258
2259                 rx_desc = agg->buffer;
2260                 rx_data = agg->buffer;
2261                 len_used += sizeof(struct rx_desc);
2262
2263                 while (urb->actual_length > len_used) {
2264                         struct net_device *netdev = tp->netdev;
2265                         struct net_device_stats *stats = &netdev->stats;
2266                         unsigned int pkt_len, rx_frag_head_sz;
2267                         struct sk_buff *skb;
2268
2269                         /* limite the skb numbers for rx_queue */
2270                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2271                                 break;
2272
2273                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2274                         if (pkt_len < ETH_ZLEN)
2275                                 break;
2276
2277                         len_used += pkt_len;
2278                         if (urb->actual_length < len_used)
2279                                 break;
2280
2281                         pkt_len -= ETH_FCS_LEN;
2282                         rx_data += sizeof(struct rx_desc);
2283
2284                         if (!agg_free || tp->rx_copybreak > pkt_len)
2285                                 rx_frag_head_sz = pkt_len;
2286                         else
2287                                 rx_frag_head_sz = tp->rx_copybreak;
2288
2289                         skb = napi_alloc_skb(napi, rx_frag_head_sz);
2290                         if (!skb) {
2291                                 stats->rx_dropped++;
2292                                 goto find_next_rx;
2293                         }
2294
2295                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2296                         memcpy(skb->data, rx_data, rx_frag_head_sz);
2297                         skb_put(skb, rx_frag_head_sz);
2298                         pkt_len -= rx_frag_head_sz;
2299                         rx_data += rx_frag_head_sz;
2300                         if (pkt_len) {
2301                                 skb_add_rx_frag(skb, 0, agg->page,
2302                                                 agg_offset(agg, rx_data),
2303                                                 pkt_len,
2304                                                 SKB_DATA_ALIGN(pkt_len));
2305                                 get_page(agg->page);
2306                         }
2307
2308                         skb->protocol = eth_type_trans(skb, netdev);
2309                         rtl_rx_vlan_tag(rx_desc, skb);
2310                         if (work_done < budget) {
2311                                 work_done++;
2312                                 stats->rx_packets++;
2313                                 stats->rx_bytes += skb->len;
2314                                 napi_gro_receive(napi, skb);
2315                         } else {
2316                                 __skb_queue_tail(&tp->rx_queue, skb);
2317                         }
2318
2319 find_next_rx:
2320                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2321                         rx_desc = (struct rx_desc *)rx_data;
2322                         len_used = agg_offset(agg, rx_data);
2323                         len_used += sizeof(struct rx_desc);
2324                 }
2325
2326                 WARN_ON(!agg_free && page_count(agg->page) > 1);
2327
2328                 if (agg_free) {
2329                         spin_lock_irqsave(&tp->rx_lock, flags);
2330                         if (page_count(agg->page) == 1) {
2331                                 list_add(&agg_free->list, &tp->rx_used);
2332                         } else {
2333                                 list_add_tail(&agg->list, &tp->rx_used);
2334                                 agg = agg_free;
2335                                 urb = agg->urb;
2336                         }
2337                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2338                 }
2339
2340 submit:
2341                 if (!ret) {
2342                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2343                 } else {
2344                         urb->actual_length = 0;
2345                         list_add_tail(&agg->list, next);
2346                 }
2347         }
2348
2349         if (!list_empty(&rx_queue)) {
2350                 spin_lock_irqsave(&tp->rx_lock, flags);
2351                 list_splice_tail(&rx_queue, &tp->rx_done);
2352                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2353         }
2354
2355 out1:
2356         return work_done;
2357 }
2358
2359 static void tx_bottom(struct r8152 *tp)
2360 {
2361         int res;
2362
2363         do {
2364                 struct net_device *netdev = tp->netdev;
2365                 struct tx_agg *agg;
2366
2367                 if (skb_queue_empty(&tp->tx_queue))
2368                         break;
2369
2370                 agg = r8152_get_tx_agg(tp);
2371                 if (!agg)
2372                         break;
2373
2374                 res = r8152_tx_agg_fill(tp, agg);
2375                 if (!res)
2376                         continue;
2377
2378                 if (res == -ENODEV) {
2379                         rtl_set_unplug(tp);
2380                         netif_device_detach(netdev);
2381                 } else {
2382                         struct net_device_stats *stats = &netdev->stats;
2383                         unsigned long flags;
2384
2385                         netif_warn(tp, tx_err, netdev,
2386                                    "failed tx_urb %d\n", res);
2387                         stats->tx_dropped += agg->skb_num;
2388
2389                         spin_lock_irqsave(&tp->tx_lock, flags);
2390                         list_add_tail(&agg->list, &tp->tx_free);
2391                         spin_unlock_irqrestore(&tp->tx_lock, flags);
2392                 }
2393         } while (res == 0);
2394 }
2395
2396 static void bottom_half(unsigned long data)
2397 {
2398         struct r8152 *tp;
2399
2400         tp = (struct r8152 *)data;
2401
2402         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2403                 return;
2404
2405         if (!test_bit(WORK_ENABLE, &tp->flags))
2406                 return;
2407
2408         /* When link down, the driver would cancel all bulks. */
2409         /* This avoid the re-submitting bulk */
2410         if (!netif_carrier_ok(tp->netdev))
2411                 return;
2412
2413         clear_bit(SCHEDULE_TASKLET, &tp->flags);
2414
2415         tx_bottom(tp);
2416 }
2417
2418 static int r8152_poll(struct napi_struct *napi, int budget)
2419 {
2420         struct r8152 *tp = container_of(napi, struct r8152, napi);
2421         int work_done;
2422
2423         work_done = rx_bottom(tp, budget);
2424
2425         if (work_done < budget) {
2426                 if (!napi_complete_done(napi, work_done))
2427                         goto out;
2428                 if (!list_empty(&tp->rx_done))
2429                         napi_schedule(napi);
2430         }
2431
2432 out:
2433         return work_done;
2434 }
2435
2436 static
2437 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2438 {
2439         int ret;
2440
2441         /* The rx would be stopped, so skip submitting */
2442         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2443             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2444                 return 0;
2445
2446         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2447                           agg->buffer, tp->rx_buf_sz,
2448                           (usb_complete_t)read_bulk_callback, agg);
2449
2450         ret = usb_submit_urb(agg->urb, mem_flags);
2451         if (ret == -ENODEV) {
2452                 rtl_set_unplug(tp);
2453                 netif_device_detach(tp->netdev);
2454         } else if (ret) {
2455                 struct urb *urb = agg->urb;
2456                 unsigned long flags;
2457
2458                 urb->actual_length = 0;
2459                 spin_lock_irqsave(&tp->rx_lock, flags);
2460                 list_add_tail(&agg->list, &tp->rx_done);
2461                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2462
2463                 netif_err(tp, rx_err, tp->netdev,
2464                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2465
2466                 napi_schedule(&tp->napi);
2467         }
2468
2469         return ret;
2470 }
2471
2472 static void rtl_drop_queued_tx(struct r8152 *tp)
2473 {
2474         struct net_device_stats *stats = &tp->netdev->stats;
2475         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2476         struct sk_buff *skb;
2477
2478         if (skb_queue_empty(tx_queue))
2479                 return;
2480
2481         __skb_queue_head_init(&skb_head);
2482         spin_lock_bh(&tx_queue->lock);
2483         skb_queue_splice_init(tx_queue, &skb_head);
2484         spin_unlock_bh(&tx_queue->lock);
2485
2486         while ((skb = __skb_dequeue(&skb_head))) {
2487                 dev_kfree_skb(skb);
2488                 stats->tx_dropped++;
2489         }
2490 }
2491
2492 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2493 {
2494         struct r8152 *tp = netdev_priv(netdev);
2495
2496         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2497
2498         usb_queue_reset_device(tp->intf);
2499 }
2500
2501 static void rtl8152_set_rx_mode(struct net_device *netdev)
2502 {
2503         struct r8152 *tp = netdev_priv(netdev);
2504
2505         if (netif_carrier_ok(netdev)) {
2506                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2507                 schedule_delayed_work(&tp->schedule, 0);
2508         }
2509 }
2510
2511 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2512 {
2513         struct r8152 *tp = netdev_priv(netdev);
2514         u32 mc_filter[2];       /* Multicast hash filter */
2515         __le32 tmp[2];
2516         u32 ocp_data;
2517
2518         netif_stop_queue(netdev);
2519         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2520         ocp_data &= ~RCR_ACPT_ALL;
2521         ocp_data |= RCR_AB | RCR_APM;
2522
2523         if (netdev->flags & IFF_PROMISC) {
2524                 /* Unconditionally log net taps. */
2525                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2526                 ocp_data |= RCR_AM | RCR_AAP;
2527                 mc_filter[1] = 0xffffffff;
2528                 mc_filter[0] = 0xffffffff;
2529         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2530                    (netdev->flags & IFF_ALLMULTI)) {
2531                 /* Too many to filter perfectly -- accept all multicasts. */
2532                 ocp_data |= RCR_AM;
2533                 mc_filter[1] = 0xffffffff;
2534                 mc_filter[0] = 0xffffffff;
2535         } else {
2536                 struct netdev_hw_addr *ha;
2537
2538                 mc_filter[1] = 0;
2539                 mc_filter[0] = 0;
2540                 netdev_for_each_mc_addr(ha, netdev) {
2541                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2542
2543                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2544                         ocp_data |= RCR_AM;
2545                 }
2546         }
2547
2548         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2549         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2550
2551         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2552         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2553         netif_wake_queue(netdev);
2554 }
2555
2556 static netdev_features_t
2557 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2558                        netdev_features_t features)
2559 {
2560         u32 mss = skb_shinfo(skb)->gso_size;
2561         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2562         int offset = skb_transport_offset(skb);
2563
2564         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2565                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2566         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2567                 features &= ~NETIF_F_GSO_MASK;
2568
2569         return features;
2570 }
2571
2572 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2573                                       struct net_device *netdev)
2574 {
2575         struct r8152 *tp = netdev_priv(netdev);
2576
2577         skb_tx_timestamp(skb);
2578
2579         skb_queue_tail(&tp->tx_queue, skb);
2580
2581         if (!list_empty(&tp->tx_free)) {
2582                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2583                         set_bit(SCHEDULE_TASKLET, &tp->flags);
2584                         schedule_delayed_work(&tp->schedule, 0);
2585                 } else {
2586                         usb_mark_last_busy(tp->udev);
2587                         tasklet_schedule(&tp->tx_tl);
2588                 }
2589         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2590                 netif_stop_queue(netdev);
2591         }
2592
2593         return NETDEV_TX_OK;
2594 }
2595
2596 static void r8152b_reset_packet_filter(struct r8152 *tp)
2597 {
2598         u32     ocp_data;
2599
2600         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2601         ocp_data &= ~FMC_FCR_MCU_EN;
2602         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2603         ocp_data |= FMC_FCR_MCU_EN;
2604         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2605 }
2606
2607 static void rtl8152_nic_reset(struct r8152 *tp)
2608 {
2609         int     i;
2610
2611         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2612
2613         for (i = 0; i < 1000; i++) {
2614                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2615                         break;
2616                 usleep_range(100, 400);
2617         }
2618 }
2619
2620 static void set_tx_qlen(struct r8152 *tp)
2621 {
2622         struct net_device *netdev = tp->netdev;
2623
2624         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2625                                     sizeof(struct tx_desc));
2626 }
2627
2628 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2629 {
2630         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2631 }
2632
2633 static void rtl_set_eee_plus(struct r8152 *tp)
2634 {
2635         u32 ocp_data;
2636         u8 speed;
2637
2638         speed = rtl8152_get_speed(tp);
2639         if (speed & _10bps) {
2640                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2641                 ocp_data |= EEEP_CR_EEEP_TX;
2642                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2643         } else {
2644                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2645                 ocp_data &= ~EEEP_CR_EEEP_TX;
2646                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2647         }
2648 }
2649
2650 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2651 {
2652         u32 ocp_data;
2653
2654         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2655         if (enable)
2656                 ocp_data |= RXDY_GATED_EN;
2657         else
2658                 ocp_data &= ~RXDY_GATED_EN;
2659         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2660 }
2661
2662 static int rtl_start_rx(struct r8152 *tp)
2663 {
2664         struct rx_agg *agg, *agg_next;
2665         struct list_head tmp_list;
2666         unsigned long flags;
2667         int ret = 0, i = 0;
2668
2669         INIT_LIST_HEAD(&tmp_list);
2670
2671         spin_lock_irqsave(&tp->rx_lock, flags);
2672
2673         INIT_LIST_HEAD(&tp->rx_done);
2674         INIT_LIST_HEAD(&tp->rx_used);
2675
2676         list_splice_init(&tp->rx_info, &tmp_list);
2677
2678         spin_unlock_irqrestore(&tp->rx_lock, flags);
2679
2680         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2681                 INIT_LIST_HEAD(&agg->list);
2682
2683                 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2684                 if (++i > RTL8152_MAX_RX) {
2685                         spin_lock_irqsave(&tp->rx_lock, flags);
2686                         list_add_tail(&agg->list, &tp->rx_used);
2687                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2688                 } else if (unlikely(ret < 0)) {
2689                         spin_lock_irqsave(&tp->rx_lock, flags);
2690                         list_add_tail(&agg->list, &tp->rx_done);
2691                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2692                 } else {
2693                         ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2694                 }
2695         }
2696
2697         spin_lock_irqsave(&tp->rx_lock, flags);
2698         WARN_ON(!list_empty(&tp->rx_info));
2699         list_splice(&tmp_list, &tp->rx_info);
2700         spin_unlock_irqrestore(&tp->rx_lock, flags);
2701
2702         return ret;
2703 }
2704
2705 static int rtl_stop_rx(struct r8152 *tp)
2706 {
2707         struct rx_agg *agg, *agg_next;
2708         struct list_head tmp_list;
2709         unsigned long flags;
2710
2711         INIT_LIST_HEAD(&tmp_list);
2712
2713         /* The usb_kill_urb() couldn't be used in atomic.
2714          * Therefore, move the list of rx_info to a tmp one.
2715          * Then, list_for_each_entry_safe could be used without
2716          * spin lock.
2717          */
2718
2719         spin_lock_irqsave(&tp->rx_lock, flags);
2720         list_splice_init(&tp->rx_info, &tmp_list);
2721         spin_unlock_irqrestore(&tp->rx_lock, flags);
2722
2723         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2724                 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2725                  * equal to 1, so the other ones could be freed safely.
2726                  */
2727                 if (page_count(agg->page) > 1)
2728                         free_rx_agg(tp, agg);
2729                 else
2730                         usb_kill_urb(agg->urb);
2731         }
2732
2733         /* Move back the list of temp to the rx_info */
2734         spin_lock_irqsave(&tp->rx_lock, flags);
2735         WARN_ON(!list_empty(&tp->rx_info));
2736         list_splice(&tmp_list, &tp->rx_info);
2737         spin_unlock_irqrestore(&tp->rx_lock, flags);
2738
2739         while (!skb_queue_empty(&tp->rx_queue))
2740                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2741
2742         return 0;
2743 }
2744
2745 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2746 {
2747         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2748                        OWN_UPDATE | OWN_CLEAR);
2749 }
2750
2751 static int rtl_enable(struct r8152 *tp)
2752 {
2753         u32 ocp_data;
2754
2755         r8152b_reset_packet_filter(tp);
2756
2757         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2758         ocp_data |= CR_RE | CR_TE;
2759         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2760
2761         switch (tp->version) {
2762         case RTL_VER_08:
2763         case RTL_VER_09:
2764                 r8153b_rx_agg_chg_indicate(tp);
2765                 break;
2766         default:
2767                 break;
2768         }
2769
2770         rxdy_gated_en(tp, false);
2771
2772         return 0;
2773 }
2774
2775 static int rtl8152_enable(struct r8152 *tp)
2776 {
2777         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2778                 return -ENODEV;
2779
2780         set_tx_qlen(tp);
2781         rtl_set_eee_plus(tp);
2782
2783         return rtl_enable(tp);
2784 }
2785
2786 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2787 {
2788         u32 ocp_data = tp->coalesce / 8;
2789
2790         switch (tp->version) {
2791         case RTL_VER_03:
2792         case RTL_VER_04:
2793         case RTL_VER_05:
2794         case RTL_VER_06:
2795                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2796                                ocp_data);
2797                 break;
2798
2799         case RTL_VER_08:
2800         case RTL_VER_09:
2801                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2802                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2803                  */
2804                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2805                                128 / 8);
2806                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2807                                ocp_data);
2808                 break;
2809
2810         default:
2811                 break;
2812         }
2813 }
2814
2815 static void r8153_set_rx_early_size(struct r8152 *tp)
2816 {
2817         u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2818
2819         switch (tp->version) {
2820         case RTL_VER_03:
2821         case RTL_VER_04:
2822         case RTL_VER_05:
2823         case RTL_VER_06:
2824                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2825                                ocp_data / 4);
2826                 break;
2827         case RTL_VER_08:
2828         case RTL_VER_09:
2829                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2830                                ocp_data / 8);
2831                 break;
2832         default:
2833                 WARN_ON_ONCE(1);
2834                 break;
2835         }
2836 }
2837
2838 static int rtl8153_enable(struct r8152 *tp)
2839 {
2840         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2841                 return -ENODEV;
2842
2843         set_tx_qlen(tp);
2844         rtl_set_eee_plus(tp);
2845         r8153_set_rx_early_timeout(tp);
2846         r8153_set_rx_early_size(tp);
2847
2848         if (tp->version == RTL_VER_09) {
2849                 u32 ocp_data;
2850
2851                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2852                 ocp_data &= ~FC_PATCH_TASK;
2853                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2854                 usleep_range(1000, 2000);
2855                 ocp_data |= FC_PATCH_TASK;
2856                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2857         }
2858
2859         return rtl_enable(tp);
2860 }
2861
2862 static void rtl_disable(struct r8152 *tp)
2863 {
2864         u32 ocp_data;
2865         int i;
2866
2867         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2868                 rtl_drop_queued_tx(tp);
2869                 return;
2870         }
2871
2872         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2873         ocp_data &= ~RCR_ACPT_ALL;
2874         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2875
2876         rtl_drop_queued_tx(tp);
2877
2878         for (i = 0; i < RTL8152_MAX_TX; i++)
2879                 usb_kill_urb(tp->tx_info[i].urb);
2880
2881         rxdy_gated_en(tp, true);
2882
2883         for (i = 0; i < 1000; i++) {
2884                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2885                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2886                         break;
2887                 usleep_range(1000, 2000);
2888         }
2889
2890         for (i = 0; i < 1000; i++) {
2891                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2892                         break;
2893                 usleep_range(1000, 2000);
2894         }
2895
2896         rtl_stop_rx(tp);
2897
2898         rtl8152_nic_reset(tp);
2899 }
2900
2901 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2902 {
2903         u32 ocp_data;
2904
2905         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2906         if (enable)
2907                 ocp_data |= POWER_CUT;
2908         else
2909                 ocp_data &= ~POWER_CUT;
2910         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2911
2912         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2913         ocp_data &= ~RESUME_INDICATE;
2914         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2915 }
2916
2917 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2918 {
2919         u32 ocp_data;
2920
2921         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2922         if (enable)
2923                 ocp_data |= CPCR_RX_VLAN;
2924         else
2925                 ocp_data &= ~CPCR_RX_VLAN;
2926         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2927 }
2928
2929 static int rtl8152_set_features(struct net_device *dev,
2930                                 netdev_features_t features)
2931 {
2932         netdev_features_t changed = features ^ dev->features;
2933         struct r8152 *tp = netdev_priv(dev);
2934         int ret;
2935
2936         ret = usb_autopm_get_interface(tp->intf);
2937         if (ret < 0)
2938                 goto out;
2939
2940         mutex_lock(&tp->control);
2941
2942         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2943                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2944                         rtl_rx_vlan_en(tp, true);
2945                 else
2946                         rtl_rx_vlan_en(tp, false);
2947         }
2948
2949         mutex_unlock(&tp->control);
2950
2951         usb_autopm_put_interface(tp->intf);
2952
2953 out:
2954         return ret;
2955 }
2956
2957 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2958
2959 static u32 __rtl_get_wol(struct r8152 *tp)
2960 {
2961         u32 ocp_data;
2962         u32 wolopts = 0;
2963
2964         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2965         if (ocp_data & LINK_ON_WAKE_EN)
2966                 wolopts |= WAKE_PHY;
2967
2968         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2969         if (ocp_data & UWF_EN)
2970                 wolopts |= WAKE_UCAST;
2971         if (ocp_data & BWF_EN)
2972                 wolopts |= WAKE_BCAST;
2973         if (ocp_data & MWF_EN)
2974                 wolopts |= WAKE_MCAST;
2975
2976         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2977         if (ocp_data & MAGIC_EN)
2978                 wolopts |= WAKE_MAGIC;
2979
2980         return wolopts;
2981 }
2982
2983 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2984 {
2985         u32 ocp_data;
2986
2987         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2988
2989         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2990         ocp_data &= ~LINK_ON_WAKE_EN;
2991         if (wolopts & WAKE_PHY)
2992                 ocp_data |= LINK_ON_WAKE_EN;
2993         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2994
2995         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2996         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2997         if (wolopts & WAKE_UCAST)
2998                 ocp_data |= UWF_EN;
2999         if (wolopts & WAKE_BCAST)
3000                 ocp_data |= BWF_EN;
3001         if (wolopts & WAKE_MCAST)
3002                 ocp_data |= MWF_EN;
3003         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3004
3005         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3006
3007         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3008         ocp_data &= ~MAGIC_EN;
3009         if (wolopts & WAKE_MAGIC)
3010                 ocp_data |= MAGIC_EN;
3011         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3012
3013         if (wolopts & WAKE_ANY)
3014                 device_set_wakeup_enable(&tp->udev->dev, true);
3015         else
3016                 device_set_wakeup_enable(&tp->udev->dev, false);
3017 }
3018
3019 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3020 {
3021         /* MAC clock speed down */
3022         if (enable) {
3023                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3024                                ALDPS_SPDWN_RATIO);
3025                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3026                                EEE_SPDWN_RATIO);
3027                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3028                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3029                                U1U2_SPDWN_EN | L1_SPDWN_EN);
3030                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3031                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3032                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3033                                TP1000_SPDWN_EN);
3034         } else {
3035                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3036                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3037                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3038                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3039         }
3040 }
3041
3042 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3043 {
3044         u8 u1u2[8];
3045
3046         if (enable)
3047                 memset(u1u2, 0xff, sizeof(u1u2));
3048         else
3049                 memset(u1u2, 0x00, sizeof(u1u2));
3050
3051         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3052 }
3053
3054 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3055 {
3056         u32 ocp_data;
3057
3058         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3059         if (enable)
3060                 ocp_data |= LPM_U1U2_EN;
3061         else
3062                 ocp_data &= ~LPM_U1U2_EN;
3063
3064         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3065 }
3066
3067 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3068 {
3069         u32 ocp_data;
3070
3071         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3072         if (enable)
3073                 ocp_data |= U2P3_ENABLE;
3074         else
3075                 ocp_data &= ~U2P3_ENABLE;
3076         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3077 }
3078
3079 static void r8153b_ups_flags(struct r8152 *tp)
3080 {
3081         u32 ups_flags = 0;
3082
3083         if (tp->ups_info.green)
3084                 ups_flags |= UPS_FLAGS_EN_GREEN;
3085
3086         if (tp->ups_info.aldps)
3087                 ups_flags |= UPS_FLAGS_EN_ALDPS;
3088
3089         if (tp->ups_info.eee)
3090                 ups_flags |= UPS_FLAGS_EN_EEE;
3091
3092         if (tp->ups_info.flow_control)
3093                 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3094
3095         if (tp->ups_info.eee_ckdiv)
3096                 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3097
3098         if (tp->ups_info.eee_cmod_lv)
3099                 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3100
3101         if (tp->ups_info._10m_ckdiv)
3102                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3103
3104         if (tp->ups_info.eee_plloff_100)
3105                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3106
3107         if (tp->ups_info.eee_plloff_giga)
3108                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3109
3110         if (tp->ups_info._250m_ckdiv)
3111                 ups_flags |= UPS_FLAGS_250M_CKDIV;
3112
3113         if (tp->ups_info.ctap_short_off)
3114                 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3115
3116         switch (tp->ups_info.speed_duplex) {
3117         case NWAY_10M_HALF:
3118                 ups_flags |= ups_flags_speed(1);
3119                 break;
3120         case NWAY_10M_FULL:
3121                 ups_flags |= ups_flags_speed(2);
3122                 break;
3123         case NWAY_100M_HALF:
3124                 ups_flags |= ups_flags_speed(3);
3125                 break;
3126         case NWAY_100M_FULL:
3127                 ups_flags |= ups_flags_speed(4);
3128                 break;
3129         case NWAY_1000M_FULL:
3130                 ups_flags |= ups_flags_speed(5);
3131                 break;
3132         case FORCE_10M_HALF:
3133                 ups_flags |= ups_flags_speed(6);
3134                 break;
3135         case FORCE_10M_FULL:
3136                 ups_flags |= ups_flags_speed(7);
3137                 break;
3138         case FORCE_100M_HALF:
3139                 ups_flags |= ups_flags_speed(8);
3140                 break;
3141         case FORCE_100M_FULL:
3142                 ups_flags |= ups_flags_speed(9);
3143                 break;
3144         default:
3145                 break;
3146         }
3147
3148         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3149 }
3150
3151 static void r8153b_green_en(struct r8152 *tp, bool enable)
3152 {
3153         u16 data;
3154
3155         if (enable) {
3156                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
3157                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3158                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3159         } else {
3160                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3161                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3162                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3163         }
3164
3165         data = sram_read(tp, SRAM_GREEN_CFG);
3166         data |= GREEN_ETH_EN;
3167         sram_write(tp, SRAM_GREEN_CFG, data);
3168
3169         tp->ups_info.green = enable;
3170 }
3171
3172 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3173 {
3174         u16 data;
3175         int i;
3176
3177         for (i = 0; i < 500; i++) {
3178                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3179                 data &= PHY_STAT_MASK;
3180                 if (desired) {
3181                         if (data == desired)
3182                                 break;
3183                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3184                            data == PHY_STAT_EXT_INIT) {
3185                         break;
3186                 }
3187
3188                 msleep(20);
3189                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3190                         break;
3191         }
3192
3193         return data;
3194 }
3195
3196 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3197 {
3198         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3199
3200         if (enable) {
3201                 r8153b_ups_flags(tp);
3202
3203                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3204                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3205
3206                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3207                 ocp_data |= BIT(0);
3208                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3209         } else {
3210                 u16 data;
3211
3212                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3213                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3214
3215                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3216                 ocp_data &= ~BIT(0);
3217                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3218
3219                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3220                 ocp_data &= ~PCUT_STATUS;
3221                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3222
3223                 data = r8153_phy_status(tp, 0);
3224
3225                 switch (data) {
3226                 case PHY_STAT_PWRDN:
3227                 case PHY_STAT_EXT_INIT:
3228                         r8153b_green_en(tp,
3229                                         test_bit(GREEN_ETHERNET, &tp->flags));
3230
3231                         data = r8152_mdio_read(tp, MII_BMCR);
3232                         data &= ~BMCR_PDOWN;
3233                         data |= BMCR_RESET;
3234                         r8152_mdio_write(tp, MII_BMCR, data);
3235
3236                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3237                         fallthrough;
3238
3239                 default:
3240                         if (data != PHY_STAT_LAN_ON)
3241                                 netif_warn(tp, link, tp->netdev,
3242                                            "PHY not ready");
3243                         break;
3244                 }
3245         }
3246 }
3247
3248 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3249 {
3250         u32 ocp_data;
3251
3252         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3253         if (enable)
3254                 ocp_data |= PWR_EN | PHASE2_EN;
3255         else
3256                 ocp_data &= ~(PWR_EN | PHASE2_EN);
3257         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3258
3259         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3260         ocp_data &= ~PCUT_STATUS;
3261         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3262 }
3263
3264 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3265 {
3266         u32 ocp_data;
3267
3268         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3269         if (enable)
3270                 ocp_data |= PWR_EN | PHASE2_EN;
3271         else
3272                 ocp_data &= ~PWR_EN;
3273         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3274
3275         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3276         ocp_data &= ~PCUT_STATUS;
3277         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3278 }
3279
3280 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3281 {
3282         u32 ocp_data;
3283
3284         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3285         if (enable)
3286                 ocp_data |= UPCOMING_RUNTIME_D3;
3287         else
3288                 ocp_data &= ~UPCOMING_RUNTIME_D3;
3289         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3290
3291         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3292         ocp_data &= ~LINK_CHG_EVENT;
3293         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3294
3295         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3296         ocp_data &= ~LINK_CHANGE_FLAG;
3297         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3298 }
3299
3300 static bool rtl_can_wakeup(struct r8152 *tp)
3301 {
3302         struct usb_device *udev = tp->udev;
3303
3304         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3305 }
3306
3307 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3308 {
3309         if (enable) {
3310                 u32 ocp_data;
3311
3312                 __rtl_set_wol(tp, WAKE_ANY);
3313
3314                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3315
3316                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3317                 ocp_data |= LINK_OFF_WAKE_EN;
3318                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3319
3320                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3321         } else {
3322                 u32 ocp_data;
3323
3324                 __rtl_set_wol(tp, tp->saved_wolopts);
3325
3326                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3327
3328                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3329                 ocp_data &= ~LINK_OFF_WAKE_EN;
3330                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3331
3332                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3333         }
3334 }
3335
3336 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3337 {
3338         if (enable) {
3339                 r8153_u1u2en(tp, false);
3340                 r8153_u2p3en(tp, false);
3341                 r8153_mac_clk_spd(tp, true);
3342                 rtl_runtime_suspend_enable(tp, true);
3343         } else {
3344                 rtl_runtime_suspend_enable(tp, false);
3345                 r8153_mac_clk_spd(tp, false);
3346
3347                 switch (tp->version) {
3348                 case RTL_VER_03:
3349                 case RTL_VER_04:
3350                         break;
3351                 case RTL_VER_05:
3352                 case RTL_VER_06:
3353                 default:
3354                         r8153_u2p3en(tp, true);
3355                         break;
3356                 }
3357
3358                 r8153_u1u2en(tp, true);
3359         }
3360 }
3361
3362 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3363 {
3364         if (enable) {
3365                 r8153_queue_wake(tp, true);
3366                 r8153b_u1u2en(tp, false);
3367                 r8153_u2p3en(tp, false);
3368                 rtl_runtime_suspend_enable(tp, true);
3369                 r8153b_ups_en(tp, true);
3370         } else {
3371                 r8153b_ups_en(tp, false);
3372                 r8153_queue_wake(tp, false);
3373                 rtl_runtime_suspend_enable(tp, false);
3374                 if (tp->udev->speed != USB_SPEED_HIGH)
3375                         r8153b_u1u2en(tp, true);
3376         }
3377 }
3378
3379 static void r8153_teredo_off(struct r8152 *tp)
3380 {
3381         u32 ocp_data;
3382
3383         switch (tp->version) {
3384         case RTL_VER_01:
3385         case RTL_VER_02:
3386         case RTL_VER_03:
3387         case RTL_VER_04:
3388         case RTL_VER_05:
3389         case RTL_VER_06:
3390         case RTL_VER_07:
3391                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3392                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3393                               OOB_TEREDO_EN);
3394                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3395                 break;
3396
3397         case RTL_VER_08:
3398         case RTL_VER_09:
3399                 /* The bit 0 ~ 7 are relative with teredo settings. They are
3400                  * W1C (write 1 to clear), so set all 1 to disable it.
3401                  */
3402                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3403                 break;
3404
3405         default:
3406                 break;
3407         }
3408
3409         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3410         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3411         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3412 }
3413
3414 static void rtl_reset_bmu(struct r8152 *tp)
3415 {
3416         u32 ocp_data;
3417
3418         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3419         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3420         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3421         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3422         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3423 }
3424
3425 /* Clear the bp to stop the firmware before loading a new one */
3426 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3427 {
3428         switch (tp->version) {
3429         case RTL_VER_01:
3430         case RTL_VER_02:
3431         case RTL_VER_07:
3432                 break;
3433         case RTL_VER_03:
3434         case RTL_VER_04:
3435         case RTL_VER_05:
3436         case RTL_VER_06:
3437                 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3438                 break;
3439         case RTL_VER_08:
3440         case RTL_VER_09:
3441         default:
3442                 if (type == MCU_TYPE_USB) {
3443                         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3444
3445                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3446                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3447                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3448                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3449                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3450                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3451                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3452                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3453                 } else {
3454                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3455                 }
3456                 break;
3457         }
3458
3459         ocp_write_word(tp, type, PLA_BP_0, 0);
3460         ocp_write_word(tp, type, PLA_BP_1, 0);
3461         ocp_write_word(tp, type, PLA_BP_2, 0);
3462         ocp_write_word(tp, type, PLA_BP_3, 0);
3463         ocp_write_word(tp, type, PLA_BP_4, 0);
3464         ocp_write_word(tp, type, PLA_BP_5, 0);
3465         ocp_write_word(tp, type, PLA_BP_6, 0);
3466         ocp_write_word(tp, type, PLA_BP_7, 0);
3467
3468         /* wait 3 ms to make sure the firmware is stopped */
3469         usleep_range(3000, 6000);
3470         ocp_write_word(tp, type, PLA_BP_BA, 0);
3471 }
3472
3473 static int r8153_patch_request(struct r8152 *tp, bool request)
3474 {
3475         u16 data;
3476         int i;
3477
3478         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3479         if (request)
3480                 data |= PATCH_REQUEST;
3481         else
3482                 data &= ~PATCH_REQUEST;
3483         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3484
3485         for (i = 0; request && i < 5000; i++) {
3486                 usleep_range(1000, 2000);
3487                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3488                         break;
3489         }
3490
3491         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3492                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3493                 r8153_patch_request(tp, false);
3494                 return -ETIME;
3495         } else {
3496                 return 0;
3497         }
3498 }
3499
3500 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3501 {
3502         if (r8153_patch_request(tp, true)) {
3503                 dev_err(&tp->intf->dev, "patch request fail\n");
3504                 return -ETIME;
3505         }
3506
3507         sram_write(tp, key_addr, patch_key);
3508         sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3509
3510         return 0;
3511 }
3512
3513 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3514 {
3515         u16 data;
3516
3517         sram_write(tp, 0x0000, 0x0000);
3518
3519         data = ocp_reg_read(tp, OCP_PHY_LOCK);
3520         data &= ~PATCH_LOCK;
3521         ocp_reg_write(tp, OCP_PHY_LOCK, data);
3522
3523         sram_write(tp, key_addr, 0x0000);
3524
3525         r8153_patch_request(tp, false);
3526
3527         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3528
3529         return 0;
3530 }
3531
3532 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3533 {
3534         u32 length;
3535         u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3536         bool rc = false;
3537
3538         switch (tp->version) {
3539         case RTL_VER_04:
3540         case RTL_VER_05:
3541         case RTL_VER_06:
3542                 fw_reg = 0xa014;
3543                 ba_reg = 0xa012;
3544                 patch_en_addr = 0xa01a;
3545                 mode_reg = 0xb820;
3546                 bp_start = 0xa000;
3547                 break;
3548         default:
3549                 goto out;
3550         }
3551
3552         fw_offset = __le16_to_cpu(phy->fw_offset);
3553         if (fw_offset < sizeof(*phy)) {
3554                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3555                 goto out;
3556         }
3557
3558         length = __le32_to_cpu(phy->blk_hdr.length);
3559         if (length < fw_offset) {
3560                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3561                 goto out;
3562         }
3563
3564         length -= __le16_to_cpu(phy->fw_offset);
3565         if (!length || (length & 1)) {
3566                 dev_err(&tp->intf->dev, "invalid block length\n");
3567                 goto out;
3568         }
3569
3570         if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3571                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3572                 goto out;
3573         }
3574
3575         if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3576                 dev_err(&tp->intf->dev, "invalid base address register\n");
3577                 goto out;
3578         }
3579
3580         if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3581                 dev_err(&tp->intf->dev,
3582                         "invalid patch mode enabled register\n");
3583                 goto out;
3584         }
3585
3586         if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3587                 dev_err(&tp->intf->dev,
3588                         "invalid register to switch the mode\n");
3589                 goto out;
3590         }
3591
3592         if (__le16_to_cpu(phy->bp_start) != bp_start) {
3593                 dev_err(&tp->intf->dev,
3594                         "invalid start register of break point\n");
3595                 goto out;
3596         }
3597
3598         if (__le16_to_cpu(phy->bp_num) > 4) {
3599                 dev_err(&tp->intf->dev, "invalid break point number\n");
3600                 goto out;
3601         }
3602
3603         rc = true;
3604 out:
3605         return rc;
3606 }
3607
3608 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3609 {
3610         u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3611         bool rc = false;
3612         u32 length, type;
3613         int i, max_bp;
3614
3615         type = __le32_to_cpu(mac->blk_hdr.type);
3616         if (type == RTL_FW_PLA) {
3617                 switch (tp->version) {
3618                 case RTL_VER_01:
3619                 case RTL_VER_02:
3620                 case RTL_VER_07:
3621                         fw_reg = 0xf800;
3622                         bp_ba_addr = PLA_BP_BA;
3623                         bp_en_addr = 0;
3624                         bp_start = PLA_BP_0;
3625                         max_bp = 8;
3626                         break;
3627                 case RTL_VER_03:
3628                 case RTL_VER_04:
3629                 case RTL_VER_05:
3630                 case RTL_VER_06:
3631                 case RTL_VER_08:
3632                 case RTL_VER_09:
3633                         fw_reg = 0xf800;
3634                         bp_ba_addr = PLA_BP_BA;
3635                         bp_en_addr = PLA_BP_EN;
3636                         bp_start = PLA_BP_0;
3637                         max_bp = 8;
3638                         break;
3639                 default:
3640                         goto out;
3641                 }
3642         } else if (type == RTL_FW_USB) {
3643                 switch (tp->version) {
3644                 case RTL_VER_03:
3645                 case RTL_VER_04:
3646                 case RTL_VER_05:
3647                 case RTL_VER_06:
3648                         fw_reg = 0xf800;
3649                         bp_ba_addr = USB_BP_BA;
3650                         bp_en_addr = USB_BP_EN;
3651                         bp_start = USB_BP_0;
3652                         max_bp = 8;
3653                         break;
3654                 case RTL_VER_08:
3655                 case RTL_VER_09:
3656                         fw_reg = 0xe600;
3657                         bp_ba_addr = USB_BP_BA;
3658                         bp_en_addr = USB_BP2_EN;
3659                         bp_start = USB_BP_0;
3660                         max_bp = 16;
3661                         break;
3662                 case RTL_VER_01:
3663                 case RTL_VER_02:
3664                 case RTL_VER_07:
3665                 default:
3666                         goto out;
3667                 }
3668         } else {
3669                 goto out;
3670         }
3671
3672         fw_offset = __le16_to_cpu(mac->fw_offset);
3673         if (fw_offset < sizeof(*mac)) {
3674                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3675                 goto out;
3676         }
3677
3678         length = __le32_to_cpu(mac->blk_hdr.length);
3679         if (length < fw_offset) {
3680                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3681                 goto out;
3682         }
3683
3684         length -= fw_offset;
3685         if (length < 4 || (length & 3)) {
3686                 dev_err(&tp->intf->dev, "invalid block length\n");
3687                 goto out;
3688         }
3689
3690         if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3691                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3692                 goto out;
3693         }
3694
3695         if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3696                 dev_err(&tp->intf->dev, "invalid base address register\n");
3697                 goto out;
3698         }
3699
3700         if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3701                 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3702                 goto out;
3703         }
3704
3705         if (__le16_to_cpu(mac->bp_start) != bp_start) {
3706                 dev_err(&tp->intf->dev,
3707                         "invalid start register of break point\n");
3708                 goto out;
3709         }
3710
3711         if (__le16_to_cpu(mac->bp_num) > max_bp) {
3712                 dev_err(&tp->intf->dev, "invalid break point number\n");
3713                 goto out;
3714         }
3715
3716         for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3717                 if (mac->bp[i]) {
3718                         dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3719                         goto out;
3720                 }
3721         }
3722
3723         rc = true;
3724 out:
3725         return rc;
3726 }
3727
3728 /* Verify the checksum for the firmware file. It is calculated from the version
3729  * field to the end of the file. Compare the result with the checksum field to
3730  * make sure the file is correct.
3731  */
3732 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3733                                        struct fw_header *fw_hdr, size_t size)
3734 {
3735         unsigned char checksum[sizeof(fw_hdr->checksum)];
3736         struct crypto_shash *alg;
3737         struct shash_desc *sdesc;
3738         size_t len;
3739         long rc;
3740
3741         alg = crypto_alloc_shash("sha256", 0, 0);
3742         if (IS_ERR(alg)) {
3743                 rc = PTR_ERR(alg);
3744                 goto out;
3745         }
3746
3747         if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3748                 rc = -EFAULT;
3749                 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3750                         crypto_shash_digestsize(alg));
3751                 goto free_shash;
3752         }
3753
3754         len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3755         sdesc = kmalloc(len, GFP_KERNEL);
3756         if (!sdesc) {
3757                 rc = -ENOMEM;
3758                 goto free_shash;
3759         }
3760         sdesc->tfm = alg;
3761
3762         len = size - sizeof(fw_hdr->checksum);
3763         rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3764         kfree(sdesc);
3765         if (rc)
3766                 goto free_shash;
3767
3768         if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3769                 dev_err(&tp->intf->dev, "checksum fail\n");
3770                 rc = -EFAULT;
3771         }
3772
3773 free_shash:
3774         crypto_free_shash(alg);
3775 out:
3776         return rc;
3777 }
3778
3779 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3780 {
3781         const struct firmware *fw = rtl_fw->fw;
3782         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3783         struct fw_mac *pla = NULL, *usb = NULL;
3784         struct fw_phy_patch_key *start = NULL;
3785         struct fw_phy_nc *phy_nc = NULL;
3786         struct fw_block *stop = NULL;
3787         long ret = -EFAULT;
3788         int i;
3789
3790         if (fw->size < sizeof(*fw_hdr)) {
3791                 dev_err(&tp->intf->dev, "file too small\n");
3792                 goto fail;
3793         }
3794
3795         ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3796         if (ret)
3797                 goto fail;
3798
3799         ret = -EFAULT;
3800
3801         for (i = sizeof(*fw_hdr); i < fw->size;) {
3802                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3803                 u32 type;
3804
3805                 if ((i + sizeof(*block)) > fw->size)
3806                         goto fail;
3807
3808                 type = __le32_to_cpu(block->type);
3809                 switch (type) {
3810                 case RTL_FW_END:
3811                         if (__le32_to_cpu(block->length) != sizeof(*block))
3812                                 goto fail;
3813                         goto fw_end;
3814                 case RTL_FW_PLA:
3815                         if (pla) {
3816                                 dev_err(&tp->intf->dev,
3817                                         "multiple PLA firmware encountered");
3818                                 goto fail;
3819                         }
3820
3821                         pla = (struct fw_mac *)block;
3822                         if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3823                                 dev_err(&tp->intf->dev,
3824                                         "check PLA firmware failed\n");
3825                                 goto fail;
3826                         }
3827                         break;
3828                 case RTL_FW_USB:
3829                         if (usb) {
3830                                 dev_err(&tp->intf->dev,
3831                                         "multiple USB firmware encountered");
3832                                 goto fail;
3833                         }
3834
3835                         usb = (struct fw_mac *)block;
3836                         if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3837                                 dev_err(&tp->intf->dev,
3838                                         "check USB firmware failed\n");
3839                                 goto fail;
3840                         }
3841                         break;
3842                 case RTL_FW_PHY_START:
3843                         if (start || phy_nc || stop) {
3844                                 dev_err(&tp->intf->dev,
3845                                         "check PHY_START fail\n");
3846                                 goto fail;
3847                         }
3848
3849                         if (__le32_to_cpu(block->length) != sizeof(*start)) {
3850                                 dev_err(&tp->intf->dev,
3851                                         "Invalid length for PHY_START\n");
3852                                 goto fail;
3853                         }
3854
3855                         start = (struct fw_phy_patch_key *)block;
3856                         break;
3857                 case RTL_FW_PHY_STOP:
3858                         if (stop || !start) {
3859                                 dev_err(&tp->intf->dev,
3860                                         "Check PHY_STOP fail\n");
3861                                 goto fail;
3862                         }
3863
3864                         if (__le32_to_cpu(block->length) != sizeof(*block)) {
3865                                 dev_err(&tp->intf->dev,
3866                                         "Invalid length for PHY_STOP\n");
3867                                 goto fail;
3868                         }
3869
3870                         stop = block;
3871                         break;
3872                 case RTL_FW_PHY_NC:
3873                         if (!start || stop) {
3874                                 dev_err(&tp->intf->dev,
3875                                         "check PHY_NC fail\n");
3876                                 goto fail;
3877                         }
3878
3879                         if (phy_nc) {
3880                                 dev_err(&tp->intf->dev,
3881                                         "multiple PHY NC encountered\n");
3882                                 goto fail;
3883                         }
3884
3885                         phy_nc = (struct fw_phy_nc *)block;
3886                         if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3887                                 dev_err(&tp->intf->dev,
3888                                         "check PHY NC firmware failed\n");
3889                                 goto fail;
3890                         }
3891
3892                         break;
3893                 default:
3894                         dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3895                                  type);
3896                         break;
3897                 }
3898
3899                 /* next block */
3900                 i += ALIGN(__le32_to_cpu(block->length), 8);
3901         }
3902
3903 fw_end:
3904         if ((phy_nc || start) && !stop) {
3905                 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3906                 goto fail;
3907         }
3908
3909         return 0;
3910 fail:
3911         return ret;
3912 }
3913
3914 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3915 {
3916         u16 mode_reg, bp_index;
3917         u32 length, i, num;
3918         __le16 *data;
3919
3920         mode_reg = __le16_to_cpu(phy->mode_reg);
3921         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3922         sram_write(tp, __le16_to_cpu(phy->ba_reg),
3923                    __le16_to_cpu(phy->ba_data));
3924
3925         length = __le32_to_cpu(phy->blk_hdr.length);
3926         length -= __le16_to_cpu(phy->fw_offset);
3927         num = length / 2;
3928         data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3929
3930         ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3931         for (i = 0; i < num; i++)
3932                 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3933
3934         sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3935                    __le16_to_cpu(phy->patch_en_value));
3936
3937         bp_index = __le16_to_cpu(phy->bp_start);
3938         num = __le16_to_cpu(phy->bp_num);
3939         for (i = 0; i < num; i++) {
3940                 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3941                 bp_index += 2;
3942         }
3943
3944         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3945
3946         dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3947 }
3948
3949 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3950 {
3951         u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3952         u32 length;
3953         u8 *data;
3954         int i;
3955
3956         switch (__le32_to_cpu(mac->blk_hdr.type)) {
3957         case RTL_FW_PLA:
3958                 type = MCU_TYPE_PLA;
3959                 break;
3960         case RTL_FW_USB:
3961                 type = MCU_TYPE_USB;
3962                 break;
3963         default:
3964                 return;
3965         }
3966
3967         rtl_clear_bp(tp, type);
3968
3969         /* Enable backup/restore of MACDBG. This is required after clearing PLA
3970          * break points and before applying the PLA firmware.
3971          */
3972         if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3973             !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3974                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3975                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3976         }
3977
3978         length = __le32_to_cpu(mac->blk_hdr.length);
3979         length -= __le16_to_cpu(mac->fw_offset);
3980
3981         data = (u8 *)mac;
3982         data += __le16_to_cpu(mac->fw_offset);
3983
3984         generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3985                           type);
3986
3987         ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3988                        __le16_to_cpu(mac->bp_ba_value));
3989
3990         bp_index = __le16_to_cpu(mac->bp_start);
3991         bp_num = __le16_to_cpu(mac->bp_num);
3992         for (i = 0; i < bp_num; i++) {
3993                 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3994                 bp_index += 2;
3995         }
3996
3997         bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3998         if (bp_en_addr)
3999                 ocp_write_word(tp, type, bp_en_addr,
4000                                __le16_to_cpu(mac->bp_en_value));
4001
4002         fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4003         if (fw_ver_reg)
4004                 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4005                                mac->fw_ver_data);
4006
4007         dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4008 }
4009
4010 static void rtl8152_apply_firmware(struct r8152 *tp)
4011 {
4012         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4013         const struct firmware *fw;
4014         struct fw_header *fw_hdr;
4015         struct fw_phy_patch_key *key;
4016         u16 key_addr = 0;
4017         int i;
4018
4019         if (IS_ERR_OR_NULL(rtl_fw->fw))
4020                 return;
4021
4022         fw = rtl_fw->fw;
4023         fw_hdr = (struct fw_header *)fw->data;
4024
4025         if (rtl_fw->pre_fw)
4026                 rtl_fw->pre_fw(tp);
4027
4028         for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4029                 struct fw_block *block = (struct fw_block *)&fw->data[i];
4030
4031                 switch (__le32_to_cpu(block->type)) {
4032                 case RTL_FW_END:
4033                         goto post_fw;
4034                 case RTL_FW_PLA:
4035                 case RTL_FW_USB:
4036                         rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4037                         break;
4038                 case RTL_FW_PHY_START:
4039                         key = (struct fw_phy_patch_key *)block;
4040                         key_addr = __le16_to_cpu(key->key_reg);
4041                         r8153_pre_ram_code(tp, key_addr,
4042                                            __le16_to_cpu(key->key_data));
4043                         break;
4044                 case RTL_FW_PHY_STOP:
4045                         WARN_ON(!key_addr);
4046                         r8153_post_ram_code(tp, key_addr);
4047                         break;
4048                 case RTL_FW_PHY_NC:
4049                         rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4050                         break;
4051                 default:
4052                         break;
4053                 }
4054
4055                 i += ALIGN(__le32_to_cpu(block->length), 8);
4056         }
4057
4058 post_fw:
4059         if (rtl_fw->post_fw)
4060                 rtl_fw->post_fw(tp);
4061
4062         strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4063         dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4064 }
4065
4066 static void rtl8152_release_firmware(struct r8152 *tp)
4067 {
4068         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4069
4070         if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4071                 release_firmware(rtl_fw->fw);
4072                 rtl_fw->fw = NULL;
4073         }
4074 }
4075
4076 static int rtl8152_request_firmware(struct r8152 *tp)
4077 {
4078         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4079         long rc;
4080
4081         if (rtl_fw->fw || !rtl_fw->fw_name) {
4082                 dev_info(&tp->intf->dev, "skip request firmware\n");
4083                 rc = 0;
4084                 goto result;
4085         }
4086
4087         rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4088         if (rc < 0)
4089                 goto result;
4090
4091         rc = rtl8152_check_firmware(tp, rtl_fw);
4092         if (rc < 0)
4093                 release_firmware(rtl_fw->fw);
4094
4095 result:
4096         if (rc) {
4097                 rtl_fw->fw = ERR_PTR(rc);
4098
4099                 dev_warn(&tp->intf->dev,
4100                          "unable to load firmware patch %s (%ld)\n",
4101                          rtl_fw->fw_name, rc);
4102         }
4103
4104         return rc;
4105 }
4106
4107 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4108 {
4109         if (enable) {
4110                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4111                                                     LINKENA | DIS_SDSAVE);
4112         } else {
4113                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4114                                                     DIS_SDSAVE);
4115                 msleep(20);
4116         }
4117 }
4118
4119 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4120 {
4121         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4122         ocp_reg_write(tp, OCP_EEE_DATA, reg);
4123         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4124 }
4125
4126 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4127 {
4128         u16 data;
4129
4130         r8152_mmd_indirect(tp, dev, reg);
4131         data = ocp_reg_read(tp, OCP_EEE_DATA);
4132         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4133
4134         return data;
4135 }
4136
4137 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4138 {
4139         r8152_mmd_indirect(tp, dev, reg);
4140         ocp_reg_write(tp, OCP_EEE_DATA, data);
4141         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4142 }
4143
4144 static void r8152_eee_en(struct r8152 *tp, bool enable)
4145 {
4146         u16 config1, config2, config3;
4147         u32 ocp_data;
4148
4149         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4150         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4151         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4152         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4153
4154         if (enable) {
4155                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4156                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4157                 config1 |= sd_rise_time(1);
4158                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4159                 config3 |= fast_snr(42);
4160         } else {
4161                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4162                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4163                              RX_QUIET_EN);
4164                 config1 |= sd_rise_time(7);
4165                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4166                 config3 |= fast_snr(511);
4167         }
4168
4169         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4170         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4171         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4172         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4173 }
4174
4175 static void r8153_eee_en(struct r8152 *tp, bool enable)
4176 {
4177         u32 ocp_data;
4178         u16 config;
4179
4180         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4181         config = ocp_reg_read(tp, OCP_EEE_CFG);
4182
4183         if (enable) {
4184                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4185                 config |= EEE10_EN;
4186         } else {
4187                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4188                 config &= ~EEE10_EN;
4189         }
4190
4191         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4192         ocp_reg_write(tp, OCP_EEE_CFG, config);
4193
4194         tp->ups_info.eee = enable;
4195 }
4196
4197 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4198 {
4199         switch (tp->version) {
4200         case RTL_VER_01:
4201         case RTL_VER_02:
4202         case RTL_VER_07:
4203                 if (enable) {
4204                         r8152_eee_en(tp, true);
4205                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4206                                         tp->eee_adv);
4207                 } else {
4208                         r8152_eee_en(tp, false);
4209                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4210                 }
4211                 break;
4212         case RTL_VER_03:
4213         case RTL_VER_04:
4214         case RTL_VER_05:
4215         case RTL_VER_06:
4216         case RTL_VER_08:
4217         case RTL_VER_09:
4218                 if (enable) {
4219                         r8153_eee_en(tp, true);
4220                         ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4221                 } else {
4222                         r8153_eee_en(tp, false);
4223                         ocp_reg_write(tp, OCP_EEE_ADV, 0);
4224                 }
4225                 break;
4226         default:
4227                 break;
4228         }
4229 }
4230
4231 static void r8152b_enable_fc(struct r8152 *tp)
4232 {
4233         u16 anar;
4234
4235         anar = r8152_mdio_read(tp, MII_ADVERTISE);
4236         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4237         r8152_mdio_write(tp, MII_ADVERTISE, anar);
4238
4239         tp->ups_info.flow_control = true;
4240 }
4241
4242 static void rtl8152_disable(struct r8152 *tp)
4243 {
4244         r8152_aldps_en(tp, false);
4245         rtl_disable(tp);
4246         r8152_aldps_en(tp, true);
4247 }
4248
4249 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4250 {
4251         rtl8152_apply_firmware(tp);
4252         rtl_eee_enable(tp, tp->eee_en);
4253         r8152_aldps_en(tp, true);
4254         r8152b_enable_fc(tp);
4255
4256         set_bit(PHY_RESET, &tp->flags);
4257 }
4258
4259 static void wait_oob_link_list_ready(struct r8152 *tp)
4260 {
4261         u32 ocp_data;
4262         int i;
4263
4264         for (i = 0; i < 1000; i++) {
4265                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4266                 if (ocp_data & LINK_LIST_READY)
4267                         break;
4268                 usleep_range(1000, 2000);
4269         }
4270 }
4271
4272 static void r8152b_exit_oob(struct r8152 *tp)
4273 {
4274         u32 ocp_data;
4275
4276         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4277         ocp_data &= ~RCR_ACPT_ALL;
4278         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4279
4280         rxdy_gated_en(tp, true);
4281         r8153_teredo_off(tp);
4282         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4283         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4284
4285         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4286         ocp_data &= ~NOW_IS_OOB;
4287         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4288
4289         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4290         ocp_data &= ~MCU_BORW_EN;
4291         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4292
4293         wait_oob_link_list_ready(tp);
4294
4295         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4296         ocp_data |= RE_INIT_LL;
4297         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4298
4299         wait_oob_link_list_ready(tp);
4300
4301         rtl8152_nic_reset(tp);
4302
4303         /* rx share fifo credit full threshold */
4304         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4305
4306         if (tp->udev->speed == USB_SPEED_FULL ||
4307             tp->udev->speed == USB_SPEED_LOW) {
4308                 /* rx share fifo credit near full threshold */
4309                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4310                                 RXFIFO_THR2_FULL);
4311                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4312                                 RXFIFO_THR3_FULL);
4313         } else {
4314                 /* rx share fifo credit near full threshold */
4315                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4316                                 RXFIFO_THR2_HIGH);
4317                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4318                                 RXFIFO_THR3_HIGH);
4319         }
4320
4321         /* TX share fifo free credit full threshold */
4322         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4323
4324         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4325         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4326         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4327                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4328
4329         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4330
4331         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4332
4333         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4334         ocp_data |= TCR0_AUTO_FIFO;
4335         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4336 }
4337
4338 static void r8152b_enter_oob(struct r8152 *tp)
4339 {
4340         u32 ocp_data;
4341
4342         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4343         ocp_data &= ~NOW_IS_OOB;
4344         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4345
4346         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4347         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4348         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4349
4350         rtl_disable(tp);
4351
4352         wait_oob_link_list_ready(tp);
4353
4354         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4355         ocp_data |= RE_INIT_LL;
4356         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4357
4358         wait_oob_link_list_ready(tp);
4359
4360         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4361
4362         rtl_rx_vlan_en(tp, true);
4363
4364         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4365         ocp_data |= ALDPS_PROXY_MODE;
4366         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4367
4368         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4369         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4370         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4371
4372         rxdy_gated_en(tp, false);
4373
4374         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4375         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4376         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4377 }
4378
4379 static int r8153_pre_firmware_1(struct r8152 *tp)
4380 {
4381         int i;
4382
4383         /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4384         for (i = 0; i < 104; i++) {
4385                 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4386
4387                 if (!(ocp_data & WTD1_EN))
4388                         break;
4389                 usleep_range(1000, 2000);
4390         }
4391
4392         return 0;
4393 }
4394
4395 static int r8153_post_firmware_1(struct r8152 *tp)
4396 {
4397         /* set USB_BP_4 to support USB_SPEED_SUPER only */
4398         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4399                 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4400
4401         /* reset UPHY timer to 36 ms */
4402         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4403
4404         return 0;
4405 }
4406
4407 static int r8153_pre_firmware_2(struct r8152 *tp)
4408 {
4409         u32 ocp_data;
4410
4411         r8153_pre_firmware_1(tp);
4412
4413         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4414         ocp_data &= ~FW_FIX_SUSPEND;
4415         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4416
4417         return 0;
4418 }
4419
4420 static int r8153_post_firmware_2(struct r8152 *tp)
4421 {
4422         u32 ocp_data;
4423
4424         /* enable bp0 if support USB_SPEED_SUPER only */
4425         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4426                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4427                 ocp_data |= BIT(0);
4428                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4429         }
4430
4431         /* reset UPHY timer to 36 ms */
4432         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4433
4434         /* enable U3P3 check, set the counter to 4 */
4435         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4436
4437         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4438         ocp_data |= FW_FIX_SUSPEND;
4439         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4440
4441         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4442         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4443         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4444
4445         return 0;
4446 }
4447
4448 static int r8153_post_firmware_3(struct r8152 *tp)
4449 {
4450         u32 ocp_data;
4451
4452         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4453         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4454         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4455
4456         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4457         ocp_data |= FW_IP_RESET_EN;
4458         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4459
4460         return 0;
4461 }
4462
4463 static int r8153b_pre_firmware_1(struct r8152 *tp)
4464 {
4465         /* enable fc timer and set timer to 1 second. */
4466         ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4467                        CTRL_TIMER_EN | (1000 / 8));
4468
4469         return 0;
4470 }
4471
4472 static int r8153b_post_firmware_1(struct r8152 *tp)
4473 {
4474         u32 ocp_data;
4475
4476         /* enable bp0 for RTL8153-BND */
4477         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4478         if (ocp_data & BND_MASK) {
4479                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4480                 ocp_data |= BIT(0);
4481                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4482         }
4483
4484         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4485         ocp_data |= FLOW_CTRL_PATCH_OPT;
4486         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4487
4488         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4489         ocp_data |= FC_PATCH_TASK;
4490         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4491
4492         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4493         ocp_data |= FW_IP_RESET_EN;
4494         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4495
4496         return 0;
4497 }
4498
4499 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4500 {
4501         u16 data;
4502
4503         data = ocp_reg_read(tp, OCP_POWER_CFG);
4504         if (enable) {
4505                 data |= EN_ALDPS;
4506                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4507         } else {
4508                 int i;
4509
4510                 data &= ~EN_ALDPS;
4511                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4512                 for (i = 0; i < 20; i++) {
4513                         usleep_range(1000, 2000);
4514                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4515                                 break;
4516                 }
4517         }
4518
4519         tp->ups_info.aldps = enable;
4520 }
4521
4522 static void r8153_hw_phy_cfg(struct r8152 *tp)
4523 {
4524         u32 ocp_data;
4525         u16 data;
4526
4527         /* disable ALDPS before updating the PHY parameters */
4528         r8153_aldps_en(tp, false);
4529
4530         /* disable EEE before updating the PHY parameters */
4531         rtl_eee_enable(tp, false);
4532
4533         rtl8152_apply_firmware(tp);
4534
4535         if (tp->version == RTL_VER_03) {
4536                 data = ocp_reg_read(tp, OCP_EEE_CFG);
4537                 data &= ~CTAP_SHORT_EN;
4538                 ocp_reg_write(tp, OCP_EEE_CFG, data);
4539         }
4540
4541         data = ocp_reg_read(tp, OCP_POWER_CFG);
4542         data |= EEE_CLKDIV_EN;
4543         ocp_reg_write(tp, OCP_POWER_CFG, data);
4544
4545         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4546         data |= EN_10M_BGOFF;
4547         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4548         data = ocp_reg_read(tp, OCP_POWER_CFG);
4549         data |= EN_10M_PLLOFF;
4550         ocp_reg_write(tp, OCP_POWER_CFG, data);
4551         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4552
4553         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4554         ocp_data |= PFM_PWM_SWITCH;
4555         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4556
4557         /* Enable LPF corner auto tune */
4558         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4559
4560         /* Adjust 10M Amplitude */
4561         sram_write(tp, SRAM_10M_AMP1, 0x00af);
4562         sram_write(tp, SRAM_10M_AMP2, 0x0208);
4563
4564         if (tp->eee_en)
4565                 rtl_eee_enable(tp, true);
4566
4567         r8153_aldps_en(tp, true);
4568         r8152b_enable_fc(tp);
4569
4570         switch (tp->version) {
4571         case RTL_VER_03:
4572         case RTL_VER_04:
4573                 break;
4574         case RTL_VER_05:
4575         case RTL_VER_06:
4576         default:
4577                 r8153_u2p3en(tp, true);
4578                 break;
4579         }
4580
4581         set_bit(PHY_RESET, &tp->flags);
4582 }
4583
4584 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4585 {
4586         u32 ocp_data;
4587
4588         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4589         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4590         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
4591         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4592
4593         return ocp_data;
4594 }
4595
4596 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4597 {
4598         u32 ocp_data;
4599         u16 data;
4600
4601         /* disable ALDPS before updating the PHY parameters */
4602         r8153_aldps_en(tp, false);
4603
4604         /* disable EEE before updating the PHY parameters */
4605         rtl_eee_enable(tp, false);
4606
4607         rtl8152_apply_firmware(tp);
4608
4609         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4610
4611         data = sram_read(tp, SRAM_GREEN_CFG);
4612         data |= R_TUNE_EN;
4613         sram_write(tp, SRAM_GREEN_CFG, data);
4614         data = ocp_reg_read(tp, OCP_NCTL_CFG);
4615         data |= PGA_RETURN_EN;
4616         ocp_reg_write(tp, OCP_NCTL_CFG, data);
4617
4618         /* ADC Bias Calibration:
4619          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4620          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4621          * ADC ioffset.
4622          */
4623         ocp_data = r8152_efuse_read(tp, 0x7d);
4624         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4625         if (data != 0xffff)
4626                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4627
4628         /* ups mode tx-link-pulse timing adjustment:
4629          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4630          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4631          */
4632         ocp_data = ocp_reg_read(tp, 0xc426);
4633         ocp_data &= 0x3fff;
4634         if (ocp_data) {
4635                 u32 swr_cnt_1ms_ini;
4636
4637                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4638                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4639                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4640                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4641         }
4642
4643         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4644         ocp_data |= PFM_PWM_SWITCH;
4645         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4646
4647         /* Advnace EEE */
4648         if (!r8153_patch_request(tp, true)) {
4649                 data = ocp_reg_read(tp, OCP_POWER_CFG);
4650                 data |= EEE_CLKDIV_EN;
4651                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4652                 tp->ups_info.eee_ckdiv = true;
4653
4654                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4655                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4656                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4657                 tp->ups_info.eee_cmod_lv = true;
4658                 tp->ups_info._10m_ckdiv = true;
4659                 tp->ups_info.eee_plloff_giga = true;
4660
4661                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4662                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4663                 tp->ups_info._250m_ckdiv = true;
4664
4665                 r8153_patch_request(tp, false);
4666         }
4667
4668         if (tp->eee_en)
4669                 rtl_eee_enable(tp, true);
4670
4671         r8153_aldps_en(tp, true);
4672         r8152b_enable_fc(tp);
4673
4674         set_bit(PHY_RESET, &tp->flags);
4675 }
4676
4677 static void r8153_first_init(struct r8152 *tp)
4678 {
4679         u32 ocp_data;
4680
4681         r8153_mac_clk_spd(tp, false);
4682         rxdy_gated_en(tp, true);
4683         r8153_teredo_off(tp);
4684
4685         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4686         ocp_data &= ~RCR_ACPT_ALL;
4687         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4688
4689         rtl8152_nic_reset(tp);
4690         rtl_reset_bmu(tp);
4691
4692         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4693         ocp_data &= ~NOW_IS_OOB;
4694         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4695
4696         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4697         ocp_data &= ~MCU_BORW_EN;
4698         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4699
4700         wait_oob_link_list_ready(tp);
4701
4702         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4703         ocp_data |= RE_INIT_LL;
4704         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4705
4706         wait_oob_link_list_ready(tp);
4707
4708         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4709
4710         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4711         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4712         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4713
4714         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4715         ocp_data |= TCR0_AUTO_FIFO;
4716         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4717
4718         rtl8152_nic_reset(tp);
4719
4720         /* rx share fifo credit full threshold */
4721         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4722         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4723         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4724         /* TX share fifo free credit full threshold */
4725         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4726 }
4727
4728 static void r8153_enter_oob(struct r8152 *tp)
4729 {
4730         u32 ocp_data;
4731
4732         r8153_mac_clk_spd(tp, true);
4733
4734         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4735         ocp_data &= ~NOW_IS_OOB;
4736         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4737
4738         rtl_disable(tp);
4739         rtl_reset_bmu(tp);
4740
4741         wait_oob_link_list_ready(tp);
4742
4743         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4744         ocp_data |= RE_INIT_LL;
4745         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4746
4747         wait_oob_link_list_ready(tp);
4748
4749         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4750         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4751
4752         switch (tp->version) {
4753         case RTL_VER_03:
4754         case RTL_VER_04:
4755         case RTL_VER_05:
4756         case RTL_VER_06:
4757                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4758                 ocp_data &= ~TEREDO_WAKE_MASK;
4759                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4760                 break;
4761
4762         case RTL_VER_08:
4763         case RTL_VER_09:
4764                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4765                  * type. Set it to zero. bits[7:0] are the W1C bits about
4766                  * the events. Set them to all 1 to clear them.
4767                  */
4768                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4769                 break;
4770
4771         default:
4772                 break;
4773         }
4774
4775         rtl_rx_vlan_en(tp, true);
4776
4777         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4778         ocp_data |= ALDPS_PROXY_MODE;
4779         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4780
4781         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4782         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4783         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4784
4785         rxdy_gated_en(tp, false);
4786
4787         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4788         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4789         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4790 }
4791
4792 static void rtl8153_disable(struct r8152 *tp)
4793 {
4794         r8153_aldps_en(tp, false);
4795         rtl_disable(tp);
4796         rtl_reset_bmu(tp);
4797         r8153_aldps_en(tp, true);
4798 }
4799
4800 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4801                              u32 advertising)
4802 {
4803         u16 bmcr;
4804         int ret = 0;
4805
4806         if (autoneg == AUTONEG_DISABLE) {
4807                 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4808                         return -EINVAL;
4809
4810                 switch (speed) {
4811                 case SPEED_10:
4812                         bmcr = BMCR_SPEED10;
4813                         if (duplex == DUPLEX_FULL) {
4814                                 bmcr |= BMCR_FULLDPLX;
4815                                 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4816                         } else {
4817                                 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4818                         }
4819                         break;
4820                 case SPEED_100:
4821                         bmcr = BMCR_SPEED100;
4822                         if (duplex == DUPLEX_FULL) {
4823                                 bmcr |= BMCR_FULLDPLX;
4824                                 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4825                         } else {
4826                                 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4827                         }
4828                         break;
4829                 case SPEED_1000:
4830                         if (tp->mii.supports_gmii) {
4831                                 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4832                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4833                                 break;
4834                         }
4835                         fallthrough;
4836                 default:
4837                         ret = -EINVAL;
4838                         goto out;
4839                 }
4840
4841                 if (duplex == DUPLEX_FULL)
4842                         tp->mii.full_duplex = 1;
4843                 else
4844                         tp->mii.full_duplex = 0;
4845
4846                 tp->mii.force_media = 1;
4847         } else {
4848                 u16 anar, tmp1;
4849                 u32 support;
4850
4851                 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4852                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4853
4854                 if (tp->mii.supports_gmii)
4855                         support |= RTL_ADVERTISED_1000_FULL;
4856
4857                 if (!(advertising & support))
4858                         return -EINVAL;
4859
4860                 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4861                 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4862                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
4863                 if (advertising & RTL_ADVERTISED_10_HALF) {
4864                         tmp1 |= ADVERTISE_10HALF;
4865                         tp->ups_info.speed_duplex = NWAY_10M_HALF;
4866                 }
4867                 if (advertising & RTL_ADVERTISED_10_FULL) {
4868                         tmp1 |= ADVERTISE_10FULL;
4869                         tp->ups_info.speed_duplex = NWAY_10M_FULL;
4870                 }
4871
4872                 if (advertising & RTL_ADVERTISED_100_HALF) {
4873                         tmp1 |= ADVERTISE_100HALF;
4874                         tp->ups_info.speed_duplex = NWAY_100M_HALF;
4875                 }
4876                 if (advertising & RTL_ADVERTISED_100_FULL) {
4877                         tmp1 |= ADVERTISE_100FULL;
4878                         tp->ups_info.speed_duplex = NWAY_100M_FULL;
4879                 }
4880
4881                 if (anar != tmp1) {
4882                         r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4883                         tp->mii.advertising = tmp1;
4884                 }
4885
4886                 if (tp->mii.supports_gmii) {
4887                         u16 gbcr;
4888
4889                         gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4890                         tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4891                                         ADVERTISE_1000HALF);
4892
4893                         if (advertising & RTL_ADVERTISED_1000_FULL) {
4894                                 tmp1 |= ADVERTISE_1000FULL;
4895                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4896                         }
4897
4898                         if (gbcr != tmp1)
4899                                 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4900                 }
4901
4902                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4903
4904                 tp->mii.force_media = 0;
4905         }
4906
4907         if (test_and_clear_bit(PHY_RESET, &tp->flags))
4908                 bmcr |= BMCR_RESET;
4909
4910         r8152_mdio_write(tp, MII_BMCR, bmcr);
4911
4912         if (bmcr & BMCR_RESET) {
4913                 int i;
4914
4915                 for (i = 0; i < 50; i++) {
4916                         msleep(20);
4917                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4918                                 break;
4919                 }
4920         }
4921
4922 out:
4923         return ret;
4924 }
4925
4926 static void rtl8152_up(struct r8152 *tp)
4927 {
4928         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4929                 return;
4930
4931         r8152_aldps_en(tp, false);
4932         r8152b_exit_oob(tp);
4933         r8152_aldps_en(tp, true);
4934 }
4935
4936 static void rtl8152_down(struct r8152 *tp)
4937 {
4938         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4939                 rtl_drop_queued_tx(tp);
4940                 return;
4941         }
4942
4943         r8152_power_cut_en(tp, false);
4944         r8152_aldps_en(tp, false);
4945         r8152b_enter_oob(tp);
4946         r8152_aldps_en(tp, true);
4947 }
4948
4949 static void rtl8153_up(struct r8152 *tp)
4950 {
4951         u32 ocp_data;
4952
4953         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4954                 return;
4955
4956         r8153_u1u2en(tp, false);
4957         r8153_u2p3en(tp, false);
4958         r8153_aldps_en(tp, false);
4959         r8153_first_init(tp);
4960
4961         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4962         ocp_data |= LANWAKE_CLR_EN;
4963         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4964
4965         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4966         ocp_data &= ~LANWAKE_PIN;
4967         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4968
4969         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4970         ocp_data &= ~DELAY_PHY_PWR_CHG;
4971         ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4972
4973         r8153_aldps_en(tp, true);
4974
4975         switch (tp->version) {
4976         case RTL_VER_03:
4977         case RTL_VER_04:
4978                 break;
4979         case RTL_VER_05:
4980         case RTL_VER_06:
4981         default:
4982                 r8153_u2p3en(tp, true);
4983                 break;
4984         }
4985
4986         r8153_u1u2en(tp, true);
4987 }
4988
4989 static void rtl8153_down(struct r8152 *tp)
4990 {
4991         u32 ocp_data;
4992
4993         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4994                 rtl_drop_queued_tx(tp);
4995                 return;
4996         }
4997
4998         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4999         ocp_data &= ~LANWAKE_CLR_EN;
5000         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5001
5002         r8153_u1u2en(tp, false);
5003         r8153_u2p3en(tp, false);
5004         r8153_power_cut_en(tp, false);
5005         r8153_aldps_en(tp, false);
5006         r8153_enter_oob(tp);
5007         r8153_aldps_en(tp, true);
5008 }
5009
5010 static void rtl8153b_up(struct r8152 *tp)
5011 {
5012         u32 ocp_data;
5013
5014         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5015                 return;
5016
5017         r8153b_u1u2en(tp, false);
5018         r8153_u2p3en(tp, false);
5019         r8153_aldps_en(tp, false);
5020
5021         r8153_first_init(tp);
5022         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5023
5024         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5025         ocp_data &= ~PLA_MCU_SPDWN_EN;
5026         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5027
5028         r8153_aldps_en(tp, true);
5029
5030         if (tp->udev->speed != USB_SPEED_HIGH)
5031                 r8153b_u1u2en(tp, true);
5032 }
5033
5034 static void rtl8153b_down(struct r8152 *tp)
5035 {
5036         u32 ocp_data;
5037
5038         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5039                 rtl_drop_queued_tx(tp);
5040                 return;
5041         }
5042
5043         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5044         ocp_data |= PLA_MCU_SPDWN_EN;
5045         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5046
5047         r8153b_u1u2en(tp, false);
5048         r8153_u2p3en(tp, false);
5049         r8153b_power_cut_en(tp, false);
5050         r8153_aldps_en(tp, false);
5051         r8153_enter_oob(tp);
5052         r8153_aldps_en(tp, true);
5053 }
5054
5055 static bool rtl8152_in_nway(struct r8152 *tp)
5056 {
5057         u16 nway_state;
5058
5059         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5060         tp->ocp_base = 0x2000;
5061         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
5062         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5063
5064         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5065         if (nway_state & 0xc000)
5066                 return false;
5067         else
5068                 return true;
5069 }
5070
5071 static bool rtl8153_in_nway(struct r8152 *tp)
5072 {
5073         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5074
5075         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5076                 return false;
5077         else
5078                 return true;
5079 }
5080
5081 static void set_carrier(struct r8152 *tp)
5082 {
5083         struct net_device *netdev = tp->netdev;
5084         struct napi_struct *napi = &tp->napi;
5085         u8 speed;
5086
5087         speed = rtl8152_get_speed(tp);
5088
5089         if (speed & LINK_STATUS) {
5090                 if (!netif_carrier_ok(netdev)) {
5091                         tp->rtl_ops.enable(tp);
5092                         netif_stop_queue(netdev);
5093                         napi_disable(napi);
5094                         netif_carrier_on(netdev);
5095                         rtl_start_rx(tp);
5096                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5097                         _rtl8152_set_rx_mode(netdev);
5098                         napi_enable(&tp->napi);
5099                         netif_wake_queue(netdev);
5100                         netif_info(tp, link, netdev, "carrier on\n");
5101                 } else if (netif_queue_stopped(netdev) &&
5102                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5103                         netif_wake_queue(netdev);
5104                 }
5105         } else {
5106                 if (netif_carrier_ok(netdev)) {
5107                         netif_carrier_off(netdev);
5108                         tasklet_disable(&tp->tx_tl);
5109                         napi_disable(napi);
5110                         tp->rtl_ops.disable(tp);
5111                         napi_enable(napi);
5112                         tasklet_enable(&tp->tx_tl);
5113                         netif_info(tp, link, netdev, "carrier off\n");
5114                 }
5115         }
5116 }
5117
5118 static void rtl_work_func_t(struct work_struct *work)
5119 {
5120         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5121
5122         /* If the device is unplugged or !netif_running(), the workqueue
5123          * doesn't need to wake the device, and could return directly.
5124          */
5125         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5126                 return;
5127
5128         if (usb_autopm_get_interface(tp->intf) < 0)
5129                 return;
5130
5131         if (!test_bit(WORK_ENABLE, &tp->flags))
5132                 goto out1;
5133
5134         if (!mutex_trylock(&tp->control)) {
5135                 schedule_delayed_work(&tp->schedule, 0);
5136                 goto out1;
5137         }
5138
5139         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5140                 set_carrier(tp);
5141
5142         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5143                 _rtl8152_set_rx_mode(tp->netdev);
5144
5145         /* don't schedule tasket before linking */
5146         if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5147             netif_carrier_ok(tp->netdev))
5148                 tasklet_schedule(&tp->tx_tl);
5149
5150         mutex_unlock(&tp->control);
5151
5152 out1:
5153         usb_autopm_put_interface(tp->intf);
5154 }
5155
5156 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5157 {
5158         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5159
5160         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5161                 return;
5162
5163         if (usb_autopm_get_interface(tp->intf) < 0)
5164                 return;
5165
5166         mutex_lock(&tp->control);
5167
5168         if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5169                 tp->rtl_fw.retry = false;
5170                 tp->rtl_fw.fw = NULL;
5171
5172                 /* Delay execution in case request_firmware() is not ready yet.
5173                  */
5174                 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5175                 goto ignore_once;
5176         }
5177
5178         tp->rtl_ops.hw_phy_cfg(tp);
5179
5180         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5181                           tp->advertising);
5182
5183 ignore_once:
5184         mutex_unlock(&tp->control);
5185
5186         usb_autopm_put_interface(tp->intf);
5187 }
5188
5189 #ifdef CONFIG_PM_SLEEP
5190 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5191                         void *data)
5192 {
5193         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5194
5195         switch (action) {
5196         case PM_HIBERNATION_PREPARE:
5197         case PM_SUSPEND_PREPARE:
5198                 usb_autopm_get_interface(tp->intf);
5199                 break;
5200
5201         case PM_POST_HIBERNATION:
5202         case PM_POST_SUSPEND:
5203                 usb_autopm_put_interface(tp->intf);
5204                 break;
5205
5206         case PM_POST_RESTORE:
5207         case PM_RESTORE_PREPARE:
5208         default:
5209                 break;
5210         }
5211
5212         return NOTIFY_DONE;
5213 }
5214 #endif
5215
5216 static int rtl8152_open(struct net_device *netdev)
5217 {
5218         struct r8152 *tp = netdev_priv(netdev);
5219         int res = 0;
5220
5221         if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5222                 cancel_delayed_work_sync(&tp->hw_phy_work);
5223                 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5224         }
5225
5226         res = alloc_all_mem(tp);
5227         if (res)
5228                 goto out;
5229
5230         res = usb_autopm_get_interface(tp->intf);
5231         if (res < 0)
5232                 goto out_free;
5233
5234         mutex_lock(&tp->control);
5235
5236         tp->rtl_ops.up(tp);
5237
5238         netif_carrier_off(netdev);
5239         netif_start_queue(netdev);
5240         set_bit(WORK_ENABLE, &tp->flags);
5241
5242         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5243         if (res) {
5244                 if (res == -ENODEV)
5245                         netif_device_detach(tp->netdev);
5246                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5247                            res);
5248                 goto out_unlock;
5249         }
5250         napi_enable(&tp->napi);
5251         tasklet_enable(&tp->tx_tl);
5252
5253         mutex_unlock(&tp->control);
5254
5255         usb_autopm_put_interface(tp->intf);
5256 #ifdef CONFIG_PM_SLEEP
5257         tp->pm_notifier.notifier_call = rtl_notifier;
5258         register_pm_notifier(&tp->pm_notifier);
5259 #endif
5260         return 0;
5261
5262 out_unlock:
5263         mutex_unlock(&tp->control);
5264         usb_autopm_put_interface(tp->intf);
5265 out_free:
5266         free_all_mem(tp);
5267 out:
5268         return res;
5269 }
5270
5271 static int rtl8152_close(struct net_device *netdev)
5272 {
5273         struct r8152 *tp = netdev_priv(netdev);
5274         int res = 0;
5275
5276 #ifdef CONFIG_PM_SLEEP
5277         unregister_pm_notifier(&tp->pm_notifier);
5278 #endif
5279         tasklet_disable(&tp->tx_tl);
5280         clear_bit(WORK_ENABLE, &tp->flags);
5281         usb_kill_urb(tp->intr_urb);
5282         cancel_delayed_work_sync(&tp->schedule);
5283         napi_disable(&tp->napi);
5284         netif_stop_queue(netdev);
5285
5286         res = usb_autopm_get_interface(tp->intf);
5287         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5288                 rtl_drop_queued_tx(tp);
5289                 rtl_stop_rx(tp);
5290         } else {
5291                 mutex_lock(&tp->control);
5292
5293                 tp->rtl_ops.down(tp);
5294
5295                 mutex_unlock(&tp->control);
5296
5297                 usb_autopm_put_interface(tp->intf);
5298         }
5299
5300         free_all_mem(tp);
5301
5302         return res;
5303 }
5304
5305 static void rtl_tally_reset(struct r8152 *tp)
5306 {
5307         u32 ocp_data;
5308
5309         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5310         ocp_data |= TALLY_RESET;
5311         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5312 }
5313
5314 static void r8152b_init(struct r8152 *tp)
5315 {
5316         u32 ocp_data;
5317         u16 data;
5318
5319         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5320                 return;
5321
5322         data = r8152_mdio_read(tp, MII_BMCR);
5323         if (data & BMCR_PDOWN) {
5324                 data &= ~BMCR_PDOWN;
5325                 r8152_mdio_write(tp, MII_BMCR, data);
5326         }
5327
5328         r8152_aldps_en(tp, false);
5329
5330         if (tp->version == RTL_VER_01) {
5331                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5332                 ocp_data &= ~LED_MODE_MASK;
5333                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5334         }
5335
5336         r8152_power_cut_en(tp, false);
5337
5338         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5339         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5340         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5341         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5342         ocp_data &= ~MCU_CLK_RATIO_MASK;
5343         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5344         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5345         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5346                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5347         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5348
5349         rtl_tally_reset(tp);
5350
5351         /* enable rx aggregation */
5352         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5353         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5354         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5355 }
5356
5357 static void r8153_init(struct r8152 *tp)
5358 {
5359         u32 ocp_data;
5360         u16 data;
5361         int i;
5362
5363         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5364                 return;
5365
5366         r8153_u1u2en(tp, false);
5367
5368         for (i = 0; i < 500; i++) {
5369                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5370                     AUTOLOAD_DONE)
5371                         break;
5372
5373                 msleep(20);
5374                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5375                         break;
5376         }
5377
5378         data = r8153_phy_status(tp, 0);
5379
5380         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5381             tp->version == RTL_VER_05)
5382                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5383
5384         data = r8152_mdio_read(tp, MII_BMCR);
5385         if (data & BMCR_PDOWN) {
5386                 data &= ~BMCR_PDOWN;
5387                 r8152_mdio_write(tp, MII_BMCR, data);
5388         }
5389
5390         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5391
5392         r8153_u2p3en(tp, false);
5393
5394         if (tp->version == RTL_VER_04) {
5395                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5396                 ocp_data &= ~pwd_dn_scale_mask;
5397                 ocp_data |= pwd_dn_scale(96);
5398                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5399
5400                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5401                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5402                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5403         } else if (tp->version == RTL_VER_05) {
5404                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5405                 ocp_data &= ~ECM_ALDPS;
5406                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5407
5408                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5409                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5410                         ocp_data &= ~DYNAMIC_BURST;
5411                 else
5412                         ocp_data |= DYNAMIC_BURST;
5413                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5414         } else if (tp->version == RTL_VER_06) {
5415                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5416                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5417                         ocp_data &= ~DYNAMIC_BURST;
5418                 else
5419                         ocp_data |= DYNAMIC_BURST;
5420                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5421
5422                 r8153_queue_wake(tp, false);
5423
5424                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5425                 if (rtl8152_get_speed(tp) & LINK_STATUS)
5426                         ocp_data |= CUR_LINK_OK;
5427                 else
5428                         ocp_data &= ~CUR_LINK_OK;
5429                 ocp_data |= POLL_LINK_CHG;
5430                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5431         }
5432
5433         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5434         ocp_data |= EP4_FULL_FC;
5435         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5436
5437         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5438         ocp_data &= ~TIMER11_EN;
5439         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5440
5441         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5442         ocp_data &= ~LED_MODE_MASK;
5443         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5444
5445         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5446         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5447                 ocp_data |= LPM_TIMER_500MS;
5448         else
5449                 ocp_data |= LPM_TIMER_500US;
5450         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5451
5452         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5453         ocp_data &= ~SEN_VAL_MASK;
5454         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5455         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5456
5457         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5458
5459         r8153_power_cut_en(tp, false);
5460         rtl_runtime_suspend_enable(tp, false);
5461         r8153_u1u2en(tp, true);
5462         r8153_mac_clk_spd(tp, false);
5463         usb_enable_lpm(tp->udev);
5464
5465         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5466         ocp_data |= LANWAKE_CLR_EN;
5467         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5468
5469         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5470         ocp_data &= ~LANWAKE_PIN;
5471         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5472
5473         /* rx aggregation */
5474         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5475         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5476         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5477                 ocp_data |= RX_AGG_DISABLE;
5478
5479         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5480
5481         rtl_tally_reset(tp);
5482
5483         switch (tp->udev->speed) {
5484         case USB_SPEED_SUPER:
5485         case USB_SPEED_SUPER_PLUS:
5486                 tp->coalesce = COALESCE_SUPER;
5487                 break;
5488         case USB_SPEED_HIGH:
5489                 tp->coalesce = COALESCE_HIGH;
5490                 break;
5491         default:
5492                 tp->coalesce = COALESCE_SLOW;
5493                 break;
5494         }
5495 }
5496
5497 static void r8153b_init(struct r8152 *tp)
5498 {
5499         u32 ocp_data;
5500         u16 data;
5501         int i;
5502
5503         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5504                 return;
5505
5506         r8153b_u1u2en(tp, false);
5507
5508         for (i = 0; i < 500; i++) {
5509                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5510                     AUTOLOAD_DONE)
5511                         break;
5512
5513                 msleep(20);
5514                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5515                         break;
5516         }
5517
5518         data = r8153_phy_status(tp, 0);
5519
5520         data = r8152_mdio_read(tp, MII_BMCR);
5521         if (data & BMCR_PDOWN) {
5522                 data &= ~BMCR_PDOWN;
5523                 r8152_mdio_write(tp, MII_BMCR, data);
5524         }
5525
5526         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5527
5528         r8153_u2p3en(tp, false);
5529
5530         /* MSC timer = 0xfff * 8ms = 32760 ms */
5531         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5532
5533         /* U1/U2/L1 idle timer. 500 us */
5534         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5535
5536         r8153b_power_cut_en(tp, false);
5537         r8153b_ups_en(tp, false);
5538         r8153_queue_wake(tp, false);
5539         rtl_runtime_suspend_enable(tp, false);
5540
5541         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5542         if (rtl8152_get_speed(tp) & LINK_STATUS)
5543                 ocp_data |= CUR_LINK_OK;
5544         else
5545                 ocp_data &= ~CUR_LINK_OK;
5546         ocp_data |= POLL_LINK_CHG;
5547         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5548
5549         if (tp->udev->speed != USB_SPEED_HIGH)
5550                 r8153b_u1u2en(tp, true);
5551         usb_enable_lpm(tp->udev);
5552
5553         /* MAC clock speed down */
5554         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5555         ocp_data |= MAC_CLK_SPDWN_EN;
5556         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5557
5558         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5559         ocp_data &= ~PLA_MCU_SPDWN_EN;
5560         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5561
5562         if (tp->version == RTL_VER_09) {
5563                 /* Disable Test IO for 32QFN */
5564                 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5565                         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5566                         ocp_data |= TEST_IO_OFF;
5567                         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5568                 }
5569         }
5570
5571         set_bit(GREEN_ETHERNET, &tp->flags);
5572
5573         /* rx aggregation */
5574         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5575         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5576         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5577
5578         rtl_tally_reset(tp);
5579
5580         tp->coalesce = 15000;   /* 15 us */
5581 }
5582
5583 static int rtl8152_pre_reset(struct usb_interface *intf)
5584 {
5585         struct r8152 *tp = usb_get_intfdata(intf);
5586         struct net_device *netdev;
5587
5588         if (!tp)
5589                 return 0;
5590
5591         netdev = tp->netdev;
5592         if (!netif_running(netdev))
5593                 return 0;
5594
5595         netif_stop_queue(netdev);
5596         tasklet_disable(&tp->tx_tl);
5597         clear_bit(WORK_ENABLE, &tp->flags);
5598         usb_kill_urb(tp->intr_urb);
5599         cancel_delayed_work_sync(&tp->schedule);
5600         napi_disable(&tp->napi);
5601         if (netif_carrier_ok(netdev)) {
5602                 mutex_lock(&tp->control);
5603                 tp->rtl_ops.disable(tp);
5604                 mutex_unlock(&tp->control);
5605         }
5606
5607         return 0;
5608 }
5609
5610 static int rtl8152_post_reset(struct usb_interface *intf)
5611 {
5612         struct r8152 *tp = usb_get_intfdata(intf);
5613         struct net_device *netdev;
5614         struct sockaddr sa;
5615
5616         if (!tp)
5617                 return 0;
5618
5619         /* reset the MAC adddress in case of policy change */
5620         if (determine_ethernet_addr(tp, &sa) >= 0) {
5621                 rtnl_lock();
5622                 dev_set_mac_address (tp->netdev, &sa, NULL);
5623                 rtnl_unlock();
5624         }
5625
5626         netdev = tp->netdev;
5627         if (!netif_running(netdev))
5628                 return 0;
5629
5630         set_bit(WORK_ENABLE, &tp->flags);
5631         if (netif_carrier_ok(netdev)) {
5632                 mutex_lock(&tp->control);
5633                 tp->rtl_ops.enable(tp);
5634                 rtl_start_rx(tp);
5635                 _rtl8152_set_rx_mode(netdev);
5636                 mutex_unlock(&tp->control);
5637         }
5638
5639         napi_enable(&tp->napi);
5640         tasklet_enable(&tp->tx_tl);
5641         netif_wake_queue(netdev);
5642         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5643
5644         if (!list_empty(&tp->rx_done))
5645                 napi_schedule(&tp->napi);
5646
5647         return 0;
5648 }
5649
5650 static bool delay_autosuspend(struct r8152 *tp)
5651 {
5652         bool sw_linking = !!netif_carrier_ok(tp->netdev);
5653         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5654
5655         /* This means a linking change occurs and the driver doesn't detect it,
5656          * yet. If the driver has disabled tx/rx and hw is linking on, the
5657          * device wouldn't wake up by receiving any packet.
5658          */
5659         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5660                 return true;
5661
5662         /* If the linking down is occurred by nway, the device may miss the
5663          * linking change event. And it wouldn't wake when linking on.
5664          */
5665         if (!sw_linking && tp->rtl_ops.in_nway(tp))
5666                 return true;
5667         else if (!skb_queue_empty(&tp->tx_queue))
5668                 return true;
5669         else
5670                 return false;
5671 }
5672
5673 static int rtl8152_runtime_resume(struct r8152 *tp)
5674 {
5675         struct net_device *netdev = tp->netdev;
5676
5677         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5678                 struct napi_struct *napi = &tp->napi;
5679
5680                 tp->rtl_ops.autosuspend_en(tp, false);
5681                 napi_disable(napi);
5682                 set_bit(WORK_ENABLE, &tp->flags);
5683
5684                 if (netif_carrier_ok(netdev)) {
5685                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
5686                                 rtl_start_rx(tp);
5687                         } else {
5688                                 netif_carrier_off(netdev);
5689                                 tp->rtl_ops.disable(tp);
5690                                 netif_info(tp, link, netdev, "linking down\n");
5691                         }
5692                 }
5693
5694                 napi_enable(napi);
5695                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5696                 smp_mb__after_atomic();
5697
5698                 if (!list_empty(&tp->rx_done))
5699                         napi_schedule(&tp->napi);
5700
5701                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5702         } else {
5703                 if (netdev->flags & IFF_UP)
5704                         tp->rtl_ops.autosuspend_en(tp, false);
5705
5706                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5707         }
5708
5709         return 0;
5710 }
5711
5712 static int rtl8152_system_resume(struct r8152 *tp)
5713 {
5714         struct net_device *netdev = tp->netdev;
5715
5716         netif_device_attach(netdev);
5717
5718         if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5719                 tp->rtl_ops.up(tp);
5720                 netif_carrier_off(netdev);
5721                 set_bit(WORK_ENABLE, &tp->flags);
5722                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5723         }
5724
5725         return 0;
5726 }
5727
5728 static int rtl8152_runtime_suspend(struct r8152 *tp)
5729 {
5730         struct net_device *netdev = tp->netdev;
5731         int ret = 0;
5732
5733         set_bit(SELECTIVE_SUSPEND, &tp->flags);
5734         smp_mb__after_atomic();
5735
5736         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5737                 u32 rcr = 0;
5738
5739                 if (netif_carrier_ok(netdev)) {
5740                         u32 ocp_data;
5741
5742                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5743                         ocp_data = rcr & ~RCR_ACPT_ALL;
5744                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5745                         rxdy_gated_en(tp, true);
5746                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5747                                                  PLA_OOB_CTRL);
5748                         if (!(ocp_data & RXFIFO_EMPTY)) {
5749                                 rxdy_gated_en(tp, false);
5750                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5751                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5752                                 smp_mb__after_atomic();
5753                                 ret = -EBUSY;
5754                                 goto out1;
5755                         }
5756                 }
5757
5758                 clear_bit(WORK_ENABLE, &tp->flags);
5759                 usb_kill_urb(tp->intr_urb);
5760
5761                 tp->rtl_ops.autosuspend_en(tp, true);
5762
5763                 if (netif_carrier_ok(netdev)) {
5764                         struct napi_struct *napi = &tp->napi;
5765
5766                         napi_disable(napi);
5767                         rtl_stop_rx(tp);
5768                         rxdy_gated_en(tp, false);
5769                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5770                         napi_enable(napi);
5771                 }
5772
5773                 if (delay_autosuspend(tp)) {
5774                         rtl8152_runtime_resume(tp);
5775                         ret = -EBUSY;
5776                 }
5777         }
5778
5779 out1:
5780         return ret;
5781 }
5782
5783 static int rtl8152_system_suspend(struct r8152 *tp)
5784 {
5785         struct net_device *netdev = tp->netdev;
5786
5787         netif_device_detach(netdev);
5788
5789         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5790                 struct napi_struct *napi = &tp->napi;
5791
5792                 clear_bit(WORK_ENABLE, &tp->flags);
5793                 usb_kill_urb(tp->intr_urb);
5794                 tasklet_disable(&tp->tx_tl);
5795                 napi_disable(napi);
5796                 cancel_delayed_work_sync(&tp->schedule);
5797                 tp->rtl_ops.down(tp);
5798                 napi_enable(napi);
5799                 tasklet_enable(&tp->tx_tl);
5800         }
5801
5802         return 0;
5803 }
5804
5805 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5806 {
5807         struct r8152 *tp = usb_get_intfdata(intf);
5808         int ret;
5809
5810         mutex_lock(&tp->control);
5811
5812         if (PMSG_IS_AUTO(message))
5813                 ret = rtl8152_runtime_suspend(tp);
5814         else
5815                 ret = rtl8152_system_suspend(tp);
5816
5817         mutex_unlock(&tp->control);
5818
5819         return ret;
5820 }
5821
5822 static int rtl8152_resume(struct usb_interface *intf)
5823 {
5824         struct r8152 *tp = usb_get_intfdata(intf);
5825         int ret;
5826
5827         mutex_lock(&tp->control);
5828
5829         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5830                 ret = rtl8152_runtime_resume(tp);
5831         else
5832                 ret = rtl8152_system_resume(tp);
5833
5834         mutex_unlock(&tp->control);
5835
5836         return ret;
5837 }
5838
5839 static int rtl8152_reset_resume(struct usb_interface *intf)
5840 {
5841         struct r8152 *tp = usb_get_intfdata(intf);
5842
5843         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5844         tp->rtl_ops.init(tp);
5845         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5846         set_ethernet_addr(tp);
5847         return rtl8152_resume(intf);
5848 }
5849
5850 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5851 {
5852         struct r8152 *tp = netdev_priv(dev);
5853
5854         if (usb_autopm_get_interface(tp->intf) < 0)
5855                 return;
5856
5857         if (!rtl_can_wakeup(tp)) {
5858                 wol->supported = 0;
5859                 wol->wolopts = 0;
5860         } else {
5861                 mutex_lock(&tp->control);
5862                 wol->supported = WAKE_ANY;
5863                 wol->wolopts = __rtl_get_wol(tp);
5864                 mutex_unlock(&tp->control);
5865         }
5866
5867         usb_autopm_put_interface(tp->intf);
5868 }
5869
5870 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5871 {
5872         struct r8152 *tp = netdev_priv(dev);
5873         int ret;
5874
5875         if (!rtl_can_wakeup(tp))
5876                 return -EOPNOTSUPP;
5877
5878         if (wol->wolopts & ~WAKE_ANY)
5879                 return -EINVAL;
5880
5881         ret = usb_autopm_get_interface(tp->intf);
5882         if (ret < 0)
5883                 goto out_set_wol;
5884
5885         mutex_lock(&tp->control);
5886
5887         __rtl_set_wol(tp, wol->wolopts);
5888         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5889
5890         mutex_unlock(&tp->control);
5891
5892         usb_autopm_put_interface(tp->intf);
5893
5894 out_set_wol:
5895         return ret;
5896 }
5897
5898 static u32 rtl8152_get_msglevel(struct net_device *dev)
5899 {
5900         struct r8152 *tp = netdev_priv(dev);
5901
5902         return tp->msg_enable;
5903 }
5904
5905 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5906 {
5907         struct r8152 *tp = netdev_priv(dev);
5908
5909         tp->msg_enable = value;
5910 }
5911
5912 static void rtl8152_get_drvinfo(struct net_device *netdev,
5913                                 struct ethtool_drvinfo *info)
5914 {
5915         struct r8152 *tp = netdev_priv(netdev);
5916
5917         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5918         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5919         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5920         if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5921                 strlcpy(info->fw_version, tp->rtl_fw.version,
5922                         sizeof(info->fw_version));
5923 }
5924
5925 static
5926 int rtl8152_get_link_ksettings(struct net_device *netdev,
5927                                struct ethtool_link_ksettings *cmd)
5928 {
5929         struct r8152 *tp = netdev_priv(netdev);
5930         int ret;
5931
5932         if (!tp->mii.mdio_read)
5933                 return -EOPNOTSUPP;
5934
5935         ret = usb_autopm_get_interface(tp->intf);
5936         if (ret < 0)
5937                 goto out;
5938
5939         mutex_lock(&tp->control);
5940
5941         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5942
5943         mutex_unlock(&tp->control);
5944
5945         usb_autopm_put_interface(tp->intf);
5946
5947 out:
5948         return ret;
5949 }
5950
5951 static int rtl8152_set_link_ksettings(struct net_device *dev,
5952                                       const struct ethtool_link_ksettings *cmd)
5953 {
5954         struct r8152 *tp = netdev_priv(dev);
5955         u32 advertising = 0;
5956         int ret;
5957
5958         ret = usb_autopm_get_interface(tp->intf);
5959         if (ret < 0)
5960                 goto out;
5961
5962         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5963                      cmd->link_modes.advertising))
5964                 advertising |= RTL_ADVERTISED_10_HALF;
5965
5966         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5967                      cmd->link_modes.advertising))
5968                 advertising |= RTL_ADVERTISED_10_FULL;
5969
5970         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5971                      cmd->link_modes.advertising))
5972                 advertising |= RTL_ADVERTISED_100_HALF;
5973
5974         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5975                      cmd->link_modes.advertising))
5976                 advertising |= RTL_ADVERTISED_100_FULL;
5977
5978         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5979                      cmd->link_modes.advertising))
5980                 advertising |= RTL_ADVERTISED_1000_HALF;
5981
5982         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5983                      cmd->link_modes.advertising))
5984                 advertising |= RTL_ADVERTISED_1000_FULL;
5985
5986         mutex_lock(&tp->control);
5987
5988         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5989                                 cmd->base.duplex, advertising);
5990         if (!ret) {
5991                 tp->autoneg = cmd->base.autoneg;
5992                 tp->speed = cmd->base.speed;
5993                 tp->duplex = cmd->base.duplex;
5994                 tp->advertising = advertising;
5995         }
5996
5997         mutex_unlock(&tp->control);
5998
5999         usb_autopm_put_interface(tp->intf);
6000
6001 out:
6002         return ret;
6003 }
6004
6005 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6006         "tx_packets",
6007         "rx_packets",
6008         "tx_errors",
6009         "rx_errors",
6010         "rx_missed",
6011         "align_errors",
6012         "tx_single_collisions",
6013         "tx_multi_collisions",
6014         "rx_unicast",
6015         "rx_broadcast",
6016         "rx_multicast",
6017         "tx_aborted",
6018         "tx_underrun",
6019 };
6020
6021 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6022 {
6023         switch (sset) {
6024         case ETH_SS_STATS:
6025                 return ARRAY_SIZE(rtl8152_gstrings);
6026         default:
6027                 return -EOPNOTSUPP;
6028         }
6029 }
6030
6031 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6032                                       struct ethtool_stats *stats, u64 *data)
6033 {
6034         struct r8152 *tp = netdev_priv(dev);
6035         struct tally_counter tally;
6036
6037         if (usb_autopm_get_interface(tp->intf) < 0)
6038                 return;
6039
6040         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6041
6042         usb_autopm_put_interface(tp->intf);
6043
6044         data[0] = le64_to_cpu(tally.tx_packets);
6045         data[1] = le64_to_cpu(tally.rx_packets);
6046         data[2] = le64_to_cpu(tally.tx_errors);
6047         data[3] = le32_to_cpu(tally.rx_errors);
6048         data[4] = le16_to_cpu(tally.rx_missed);
6049         data[5] = le16_to_cpu(tally.align_errors);
6050         data[6] = le32_to_cpu(tally.tx_one_collision);
6051         data[7] = le32_to_cpu(tally.tx_multi_collision);
6052         data[8] = le64_to_cpu(tally.rx_unicast);
6053         data[9] = le64_to_cpu(tally.rx_broadcast);
6054         data[10] = le32_to_cpu(tally.rx_multicast);
6055         data[11] = le16_to_cpu(tally.tx_aborted);
6056         data[12] = le16_to_cpu(tally.tx_underrun);
6057 }
6058
6059 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6060 {
6061         switch (stringset) {
6062         case ETH_SS_STATS:
6063                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6064                 break;
6065         }
6066 }
6067
6068 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6069 {
6070         u32 lp, adv, supported = 0;
6071         u16 val;
6072
6073         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6074         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6075
6076         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6077         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6078
6079         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6080         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6081
6082         eee->eee_enabled = tp->eee_en;
6083         eee->eee_active = !!(supported & adv & lp);
6084         eee->supported = supported;
6085         eee->advertised = tp->eee_adv;
6086         eee->lp_advertised = lp;
6087
6088         return 0;
6089 }
6090
6091 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6092 {
6093         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6094
6095         tp->eee_en = eee->eee_enabled;
6096         tp->eee_adv = val;
6097
6098         rtl_eee_enable(tp, tp->eee_en);
6099
6100         return 0;
6101 }
6102
6103 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6104 {
6105         u32 lp, adv, supported = 0;
6106         u16 val;
6107
6108         val = ocp_reg_read(tp, OCP_EEE_ABLE);
6109         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6110
6111         val = ocp_reg_read(tp, OCP_EEE_ADV);
6112         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6113
6114         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6115         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6116
6117         eee->eee_enabled = tp->eee_en;
6118         eee->eee_active = !!(supported & adv & lp);
6119         eee->supported = supported;
6120         eee->advertised = tp->eee_adv;
6121         eee->lp_advertised = lp;
6122
6123         return 0;
6124 }
6125
6126 static int
6127 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6128 {
6129         struct r8152 *tp = netdev_priv(net);
6130         int ret;
6131
6132         ret = usb_autopm_get_interface(tp->intf);
6133         if (ret < 0)
6134                 goto out;
6135
6136         mutex_lock(&tp->control);
6137
6138         ret = tp->rtl_ops.eee_get(tp, edata);
6139
6140         mutex_unlock(&tp->control);
6141
6142         usb_autopm_put_interface(tp->intf);
6143
6144 out:
6145         return ret;
6146 }
6147
6148 static int
6149 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6150 {
6151         struct r8152 *tp = netdev_priv(net);
6152         int ret;
6153
6154         ret = usb_autopm_get_interface(tp->intf);
6155         if (ret < 0)
6156                 goto out;
6157
6158         mutex_lock(&tp->control);
6159
6160         ret = tp->rtl_ops.eee_set(tp, edata);
6161         if (!ret)
6162                 ret = mii_nway_restart(&tp->mii);
6163
6164         mutex_unlock(&tp->control);
6165
6166         usb_autopm_put_interface(tp->intf);
6167
6168 out:
6169         return ret;
6170 }
6171
6172 static int rtl8152_nway_reset(struct net_device *dev)
6173 {
6174         struct r8152 *tp = netdev_priv(dev);
6175         int ret;
6176
6177         ret = usb_autopm_get_interface(tp->intf);
6178         if (ret < 0)
6179                 goto out;
6180
6181         mutex_lock(&tp->control);
6182
6183         ret = mii_nway_restart(&tp->mii);
6184
6185         mutex_unlock(&tp->control);
6186
6187         usb_autopm_put_interface(tp->intf);
6188
6189 out:
6190         return ret;
6191 }
6192
6193 static int rtl8152_get_coalesce(struct net_device *netdev,
6194                                 struct ethtool_coalesce *coalesce)
6195 {
6196         struct r8152 *tp = netdev_priv(netdev);
6197
6198         switch (tp->version) {
6199         case RTL_VER_01:
6200         case RTL_VER_02:
6201         case RTL_VER_07:
6202                 return -EOPNOTSUPP;
6203         default:
6204                 break;
6205         }
6206
6207         coalesce->rx_coalesce_usecs = tp->coalesce;
6208
6209         return 0;
6210 }
6211
6212 static int rtl8152_set_coalesce(struct net_device *netdev,
6213                                 struct ethtool_coalesce *coalesce)
6214 {
6215         struct r8152 *tp = netdev_priv(netdev);
6216         int ret;
6217
6218         switch (tp->version) {
6219         case RTL_VER_01:
6220         case RTL_VER_02:
6221         case RTL_VER_07:
6222                 return -EOPNOTSUPP;
6223         default:
6224                 break;
6225         }
6226
6227         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6228                 return -EINVAL;
6229
6230         ret = usb_autopm_get_interface(tp->intf);
6231         if (ret < 0)
6232                 return ret;
6233
6234         mutex_lock(&tp->control);
6235
6236         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6237                 tp->coalesce = coalesce->rx_coalesce_usecs;
6238
6239                 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6240                         netif_stop_queue(netdev);
6241                         napi_disable(&tp->napi);
6242                         tp->rtl_ops.disable(tp);
6243                         tp->rtl_ops.enable(tp);
6244                         rtl_start_rx(tp);
6245                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6246                         _rtl8152_set_rx_mode(netdev);
6247                         napi_enable(&tp->napi);
6248                         netif_wake_queue(netdev);
6249                 }
6250         }
6251
6252         mutex_unlock(&tp->control);
6253
6254         usb_autopm_put_interface(tp->intf);
6255
6256         return ret;
6257 }
6258
6259 static int rtl8152_get_tunable(struct net_device *netdev,
6260                                const struct ethtool_tunable *tunable, void *d)
6261 {
6262         struct r8152 *tp = netdev_priv(netdev);
6263
6264         switch (tunable->id) {
6265         case ETHTOOL_RX_COPYBREAK:
6266                 *(u32 *)d = tp->rx_copybreak;
6267                 break;
6268         default:
6269                 return -EOPNOTSUPP;
6270         }
6271
6272         return 0;
6273 }
6274
6275 static int rtl8152_set_tunable(struct net_device *netdev,
6276                                const struct ethtool_tunable *tunable,
6277                                const void *d)
6278 {
6279         struct r8152 *tp = netdev_priv(netdev);
6280         u32 val;
6281
6282         switch (tunable->id) {
6283         case ETHTOOL_RX_COPYBREAK:
6284                 val = *(u32 *)d;
6285                 if (val < ETH_ZLEN) {
6286                         netif_err(tp, rx_err, netdev,
6287                                   "Invalid rx copy break value\n");
6288                         return -EINVAL;
6289                 }
6290
6291                 if (tp->rx_copybreak != val) {
6292                         if (netdev->flags & IFF_UP) {
6293                                 mutex_lock(&tp->control);
6294                                 napi_disable(&tp->napi);
6295                                 tp->rx_copybreak = val;
6296                                 napi_enable(&tp->napi);
6297                                 mutex_unlock(&tp->control);
6298                         } else {
6299                                 tp->rx_copybreak = val;
6300                         }
6301                 }
6302                 break;
6303         default:
6304                 return -EOPNOTSUPP;
6305         }
6306
6307         return 0;
6308 }
6309
6310 static void rtl8152_get_ringparam(struct net_device *netdev,
6311                                   struct ethtool_ringparam *ring)
6312 {
6313         struct r8152 *tp = netdev_priv(netdev);
6314
6315         ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6316         ring->rx_pending = tp->rx_pending;
6317 }
6318
6319 static int rtl8152_set_ringparam(struct net_device *netdev,
6320                                  struct ethtool_ringparam *ring)
6321 {
6322         struct r8152 *tp = netdev_priv(netdev);
6323
6324         if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6325                 return -EINVAL;
6326
6327         if (tp->rx_pending != ring->rx_pending) {
6328                 if (netdev->flags & IFF_UP) {
6329                         mutex_lock(&tp->control);
6330                         napi_disable(&tp->napi);
6331                         tp->rx_pending = ring->rx_pending;
6332                         napi_enable(&tp->napi);
6333                         mutex_unlock(&tp->control);
6334                 } else {
6335                         tp->rx_pending = ring->rx_pending;
6336                 }
6337         }
6338
6339         return 0;
6340 }
6341
6342 static const struct ethtool_ops ops = {
6343         .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6344         .get_drvinfo = rtl8152_get_drvinfo,
6345         .get_link = ethtool_op_get_link,
6346         .nway_reset = rtl8152_nway_reset,
6347         .get_msglevel = rtl8152_get_msglevel,
6348         .set_msglevel = rtl8152_set_msglevel,
6349         .get_wol = rtl8152_get_wol,
6350         .set_wol = rtl8152_set_wol,
6351         .get_strings = rtl8152_get_strings,
6352         .get_sset_count = rtl8152_get_sset_count,
6353         .get_ethtool_stats = rtl8152_get_ethtool_stats,
6354         .get_coalesce = rtl8152_get_coalesce,
6355         .set_coalesce = rtl8152_set_coalesce,
6356         .get_eee = rtl_ethtool_get_eee,
6357         .set_eee = rtl_ethtool_set_eee,
6358         .get_link_ksettings = rtl8152_get_link_ksettings,
6359         .set_link_ksettings = rtl8152_set_link_ksettings,
6360         .get_tunable = rtl8152_get_tunable,
6361         .set_tunable = rtl8152_set_tunable,
6362         .get_ringparam = rtl8152_get_ringparam,
6363         .set_ringparam = rtl8152_set_ringparam,
6364 };
6365
6366 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6367 {
6368         struct r8152 *tp = netdev_priv(netdev);
6369         struct mii_ioctl_data *data = if_mii(rq);
6370         int res;
6371
6372         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6373                 return -ENODEV;
6374
6375         res = usb_autopm_get_interface(tp->intf);
6376         if (res < 0)
6377                 goto out;
6378
6379         switch (cmd) {
6380         case SIOCGMIIPHY:
6381                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6382                 break;
6383
6384         case SIOCGMIIREG:
6385                 mutex_lock(&tp->control);
6386                 data->val_out = r8152_mdio_read(tp, data->reg_num);
6387                 mutex_unlock(&tp->control);
6388                 break;
6389
6390         case SIOCSMIIREG:
6391                 if (!capable(CAP_NET_ADMIN)) {
6392                         res = -EPERM;
6393                         break;
6394                 }
6395                 mutex_lock(&tp->control);
6396                 r8152_mdio_write(tp, data->reg_num, data->val_in);
6397                 mutex_unlock(&tp->control);
6398                 break;
6399
6400         default:
6401                 res = -EOPNOTSUPP;
6402         }
6403
6404         usb_autopm_put_interface(tp->intf);
6405
6406 out:
6407         return res;
6408 }
6409
6410 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6411 {
6412         struct r8152 *tp = netdev_priv(dev);
6413         int ret;
6414
6415         switch (tp->version) {
6416         case RTL_VER_01:
6417         case RTL_VER_02:
6418         case RTL_VER_07:
6419                 dev->mtu = new_mtu;
6420                 return 0;
6421         default:
6422                 break;
6423         }
6424
6425         ret = usb_autopm_get_interface(tp->intf);
6426         if (ret < 0)
6427                 return ret;
6428
6429         mutex_lock(&tp->control);
6430
6431         dev->mtu = new_mtu;
6432
6433         if (netif_running(dev)) {
6434                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6435
6436                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6437
6438                 if (netif_carrier_ok(dev))
6439                         r8153_set_rx_early_size(tp);
6440         }
6441
6442         mutex_unlock(&tp->control);
6443
6444         usb_autopm_put_interface(tp->intf);
6445
6446         return ret;
6447 }
6448
6449 static const struct net_device_ops rtl8152_netdev_ops = {
6450         .ndo_open               = rtl8152_open,
6451         .ndo_stop               = rtl8152_close,
6452         .ndo_do_ioctl           = rtl8152_ioctl,
6453         .ndo_start_xmit         = rtl8152_start_xmit,
6454         .ndo_tx_timeout         = rtl8152_tx_timeout,
6455         .ndo_set_features       = rtl8152_set_features,
6456         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
6457         .ndo_set_mac_address    = rtl8152_set_mac_address,
6458         .ndo_change_mtu         = rtl8152_change_mtu,
6459         .ndo_validate_addr      = eth_validate_addr,
6460         .ndo_features_check     = rtl8152_features_check,
6461 };
6462
6463 static void rtl8152_unload(struct r8152 *tp)
6464 {
6465         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6466                 return;
6467
6468         if (tp->version != RTL_VER_01)
6469                 r8152_power_cut_en(tp, true);
6470 }
6471
6472 static void rtl8153_unload(struct r8152 *tp)
6473 {
6474         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6475                 return;
6476
6477         r8153_power_cut_en(tp, false);
6478 }
6479
6480 static void rtl8153b_unload(struct r8152 *tp)
6481 {
6482         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6483                 return;
6484
6485         r8153b_power_cut_en(tp, false);
6486 }
6487
6488 static int rtl_ops_init(struct r8152 *tp)
6489 {
6490         struct rtl_ops *ops = &tp->rtl_ops;
6491         int ret = 0;
6492
6493         switch (tp->version) {
6494         case RTL_VER_01:
6495         case RTL_VER_02:
6496         case RTL_VER_07:
6497                 ops->init               = r8152b_init;
6498                 ops->enable             = rtl8152_enable;
6499                 ops->disable            = rtl8152_disable;
6500                 ops->up                 = rtl8152_up;
6501                 ops->down               = rtl8152_down;
6502                 ops->unload             = rtl8152_unload;
6503                 ops->eee_get            = r8152_get_eee;
6504                 ops->eee_set            = r8152_set_eee;
6505                 ops->in_nway            = rtl8152_in_nway;
6506                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
6507                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
6508                 tp->rx_buf_sz           = 16 * 1024;
6509                 tp->eee_en              = true;
6510                 tp->eee_adv             = MDIO_EEE_100TX;
6511                 break;
6512
6513         case RTL_VER_03:
6514         case RTL_VER_04:
6515         case RTL_VER_05:
6516         case RTL_VER_06:
6517                 ops->init               = r8153_init;
6518                 ops->enable             = rtl8153_enable;
6519                 ops->disable            = rtl8153_disable;
6520                 ops->up                 = rtl8153_up;
6521                 ops->down               = rtl8153_down;
6522                 ops->unload             = rtl8153_unload;
6523                 ops->eee_get            = r8153_get_eee;
6524                 ops->eee_set            = r8152_set_eee;
6525                 ops->in_nway            = rtl8153_in_nway;
6526                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
6527                 ops->autosuspend_en     = rtl8153_runtime_enable;
6528                 tp->rx_buf_sz           = 32 * 1024;
6529                 tp->eee_en              = true;
6530                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6531                 break;
6532
6533         case RTL_VER_08:
6534         case RTL_VER_09:
6535                 ops->init               = r8153b_init;
6536                 ops->enable             = rtl8153_enable;
6537                 ops->disable            = rtl8153_disable;
6538                 ops->up                 = rtl8153b_up;
6539                 ops->down               = rtl8153b_down;
6540                 ops->unload             = rtl8153b_unload;
6541                 ops->eee_get            = r8153_get_eee;
6542                 ops->eee_set            = r8152_set_eee;
6543                 ops->in_nway            = rtl8153_in_nway;
6544                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
6545                 ops->autosuspend_en     = rtl8153b_runtime_enable;
6546                 tp->rx_buf_sz           = 32 * 1024;
6547                 tp->eee_en              = true;
6548                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6549                 break;
6550
6551         default:
6552                 ret = -ENODEV;
6553                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6554                 break;
6555         }
6556
6557         return ret;
6558 }
6559
6560 #define FIRMWARE_8153A_2        "rtl_nic/rtl8153a-2.fw"
6561 #define FIRMWARE_8153A_3        "rtl_nic/rtl8153a-3.fw"
6562 #define FIRMWARE_8153A_4        "rtl_nic/rtl8153a-4.fw"
6563 #define FIRMWARE_8153B_2        "rtl_nic/rtl8153b-2.fw"
6564
6565 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6566 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6567 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6568 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6569
6570 static int rtl_fw_init(struct r8152 *tp)
6571 {
6572         struct rtl_fw *rtl_fw = &tp->rtl_fw;
6573
6574         switch (tp->version) {
6575         case RTL_VER_04:
6576                 rtl_fw->fw_name         = FIRMWARE_8153A_2;
6577                 rtl_fw->pre_fw          = r8153_pre_firmware_1;
6578                 rtl_fw->post_fw         = r8153_post_firmware_1;
6579                 break;
6580         case RTL_VER_05:
6581                 rtl_fw->fw_name         = FIRMWARE_8153A_3;
6582                 rtl_fw->pre_fw          = r8153_pre_firmware_2;
6583                 rtl_fw->post_fw         = r8153_post_firmware_2;
6584                 break;
6585         case RTL_VER_06:
6586                 rtl_fw->fw_name         = FIRMWARE_8153A_4;
6587                 rtl_fw->post_fw         = r8153_post_firmware_3;
6588                 break;
6589         case RTL_VER_09:
6590                 rtl_fw->fw_name         = FIRMWARE_8153B_2;
6591                 rtl_fw->pre_fw          = r8153b_pre_firmware_1;
6592                 rtl_fw->post_fw         = r8153b_post_firmware_1;
6593                 break;
6594         default:
6595                 break;
6596         }
6597
6598         return 0;
6599 }
6600
6601 u8 rtl8152_get_version(struct usb_interface *intf)
6602 {
6603         struct usb_device *udev = interface_to_usbdev(intf);
6604         u32 ocp_data = 0;
6605         __le32 *tmp;
6606         u8 version;
6607         int ret;
6608
6609         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6610         if (!tmp)
6611                 return 0;
6612
6613         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6614                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6615                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6616         if (ret > 0)
6617                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6618
6619         kfree(tmp);
6620
6621         switch (ocp_data) {
6622         case 0x4c00:
6623                 version = RTL_VER_01;
6624                 break;
6625         case 0x4c10:
6626                 version = RTL_VER_02;
6627                 break;
6628         case 0x5c00:
6629                 version = RTL_VER_03;
6630                 break;
6631         case 0x5c10:
6632                 version = RTL_VER_04;
6633                 break;
6634         case 0x5c20:
6635                 version = RTL_VER_05;
6636                 break;
6637         case 0x5c30:
6638                 version = RTL_VER_06;
6639                 break;
6640         case 0x4800:
6641                 version = RTL_VER_07;
6642                 break;
6643         case 0x6000:
6644                 version = RTL_VER_08;
6645                 break;
6646         case 0x6010:
6647                 version = RTL_VER_09;
6648                 break;
6649         default:
6650                 version = RTL_VER_UNKNOWN;
6651                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6652                 break;
6653         }
6654
6655         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6656
6657         return version;
6658 }
6659 EXPORT_SYMBOL_GPL(rtl8152_get_version);
6660
6661 static int rtl8152_probe(struct usb_interface *intf,
6662                          const struct usb_device_id *id)
6663 {
6664         struct usb_device *udev = interface_to_usbdev(intf);
6665         u8 version = rtl8152_get_version(intf);
6666         struct r8152 *tp;
6667         struct net_device *netdev;
6668         int ret;
6669
6670         if (version == RTL_VER_UNKNOWN)
6671                 return -ENODEV;
6672
6673         if (udev->actconfig->desc.bConfigurationValue != 1) {
6674                 usb_driver_set_configuration(udev, 1);
6675                 return -ENODEV;
6676         }
6677
6678         if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6679                 return -ENODEV;
6680
6681         usb_reset_device(udev);
6682         netdev = alloc_etherdev(sizeof(struct r8152));
6683         if (!netdev) {
6684                 dev_err(&intf->dev, "Out of memory\n");
6685                 return -ENOMEM;
6686         }
6687
6688         SET_NETDEV_DEV(netdev, &intf->dev);
6689         tp = netdev_priv(netdev);
6690         tp->msg_enable = 0x7FFF;
6691
6692         tp->udev = udev;
6693         tp->netdev = netdev;
6694         tp->intf = intf;
6695         tp->version = version;
6696
6697         switch (version) {
6698         case RTL_VER_01:
6699         case RTL_VER_02:
6700         case RTL_VER_07:
6701                 tp->mii.supports_gmii = 0;
6702                 break;
6703         default:
6704                 tp->mii.supports_gmii = 1;
6705                 break;
6706         }
6707
6708         ret = rtl_ops_init(tp);
6709         if (ret)
6710                 goto out;
6711
6712         rtl_fw_init(tp);
6713
6714         mutex_init(&tp->control);
6715         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6716         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6717         tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6718         tasklet_disable(&tp->tx_tl);
6719
6720         netdev->netdev_ops = &rtl8152_netdev_ops;
6721         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6722
6723         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6724                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6725                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6726                             NETIF_F_HW_VLAN_CTAG_TX;
6727         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6728                               NETIF_F_TSO | NETIF_F_FRAGLIST |
6729                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6730                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6731         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6732                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6733                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6734
6735         if (tp->version == RTL_VER_01) {
6736                 netdev->features &= ~NETIF_F_RXCSUM;
6737                 netdev->hw_features &= ~NETIF_F_RXCSUM;
6738         }
6739
6740         if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6741                 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6742                 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6743                 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6744                         set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6745                 }
6746         }
6747
6748         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6749             (!strcmp(udev->serial, "000001000000") ||
6750              !strcmp(udev->serial, "000002000000"))) {
6751                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6752                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6753         }
6754
6755         netdev->ethtool_ops = &ops;
6756         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6757
6758         /* MTU range: 68 - 1500 or 9194 */
6759         netdev->min_mtu = ETH_MIN_MTU;
6760         switch (tp->version) {
6761         case RTL_VER_01:
6762         case RTL_VER_02:
6763                 netdev->max_mtu = ETH_DATA_LEN;
6764                 break;
6765         default:
6766                 netdev->max_mtu = RTL8153_MAX_MTU;
6767                 break;
6768         }
6769
6770         tp->mii.dev = netdev;
6771         tp->mii.mdio_read = read_mii_word;
6772         tp->mii.mdio_write = write_mii_word;
6773         tp->mii.phy_id_mask = 0x3f;
6774         tp->mii.reg_num_mask = 0x1f;
6775         tp->mii.phy_id = R8152_PHY_ID;
6776
6777         tp->autoneg = AUTONEG_ENABLE;
6778         tp->speed = SPEED_100;
6779         tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6780                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6781         if (tp->mii.supports_gmii) {
6782                 tp->speed = SPEED_1000;
6783                 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6784         }
6785         tp->duplex = DUPLEX_FULL;
6786
6787         tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6788         tp->rx_pending = 10 * RTL8152_MAX_RX;
6789
6790         intf->needs_remote_wakeup = 1;
6791
6792         if (!rtl_can_wakeup(tp))
6793                 __rtl_set_wol(tp, 0);
6794         else
6795                 tp->saved_wolopts = __rtl_get_wol(tp);
6796
6797         tp->rtl_ops.init(tp);
6798 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6799         /* Retry in case request_firmware() is not ready yet. */
6800         tp->rtl_fw.retry = true;
6801 #endif
6802         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6803         set_ethernet_addr(tp);
6804
6805         usb_set_intfdata(intf, tp);
6806         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6807
6808         ret = register_netdev(netdev);
6809         if (ret != 0) {
6810                 netif_err(tp, probe, netdev, "couldn't register the device\n");
6811                 goto out1;
6812         }
6813
6814         if (tp->saved_wolopts)
6815                 device_set_wakeup_enable(&udev->dev, true);
6816         else
6817                 device_set_wakeup_enable(&udev->dev, false);
6818
6819         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6820
6821         return 0;
6822
6823 out1:
6824         tasklet_kill(&tp->tx_tl);
6825         usb_set_intfdata(intf, NULL);
6826 out:
6827         free_netdev(netdev);
6828         return ret;
6829 }
6830
6831 static void rtl8152_disconnect(struct usb_interface *intf)
6832 {
6833         struct r8152 *tp = usb_get_intfdata(intf);
6834
6835         usb_set_intfdata(intf, NULL);
6836         if (tp) {
6837                 rtl_set_unplug(tp);
6838
6839                 unregister_netdev(tp->netdev);
6840                 tasklet_kill(&tp->tx_tl);
6841                 cancel_delayed_work_sync(&tp->hw_phy_work);
6842                 tp->rtl_ops.unload(tp);
6843                 rtl8152_release_firmware(tp);
6844                 free_netdev(tp->netdev);
6845         }
6846 }
6847
6848 #define REALTEK_USB_DEVICE(vend, prod)  \
6849         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6850                        USB_DEVICE_ID_MATCH_INT_CLASS, \
6851         .idVendor = (vend), \
6852         .idProduct = (prod), \
6853         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6854 }, \
6855 { \
6856         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6857                        USB_DEVICE_ID_MATCH_DEVICE, \
6858         .idVendor = (vend), \
6859         .idProduct = (prod), \
6860         .bInterfaceClass = USB_CLASS_COMM, \
6861         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6862         .bInterfaceProtocol = USB_CDC_PROTO_NONE
6863
6864 /* table of devices that work with this driver */
6865 static const struct usb_device_id rtl8152_table[] = {
6866         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6867         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6868         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6869         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6870         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6871         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6872         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6873         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6874         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6875         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6876         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6877         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6878         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6879         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6880         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6881         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6882         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6883         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6884         {}
6885 };
6886
6887 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6888
6889 static struct usb_driver rtl8152_driver = {
6890         .name =         MODULENAME,
6891         .id_table =     rtl8152_table,
6892         .probe =        rtl8152_probe,
6893         .disconnect =   rtl8152_disconnect,
6894         .suspend =      rtl8152_suspend,
6895         .resume =       rtl8152_resume,
6896         .reset_resume = rtl8152_reset_resume,
6897         .pre_reset =    rtl8152_pre_reset,
6898         .post_reset =   rtl8152_post_reset,
6899         .supports_autosuspend = 1,
6900         .disable_hub_initiated_lpm = 1,
6901 };
6902
6903 module_usb_driver(rtl8152_driver);
6904
6905 MODULE_AUTHOR(DRIVER_AUTHOR);
6906 MODULE_DESCRIPTION(DRIVER_DESC);
6907 MODULE_LICENSE("GPL");
6908 MODULE_VERSION(DRIVER_VERSION);