drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2 and 3.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  * napi: This parameter used to enable/disable NAPI (polling Rx)
  46  *     Possible values '1' for enable and '0' for disable. Default is '1'
  47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48  *      Possible values '1' for enable and '0' for disable. Default is '0'
  49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50  *                 Possible values '1' for enable , '0' for disable.
  51  *                 Default is '2' - which means disable in promisc mode
  52  *                 and enable in non-promiscuous mode.
  53  ************************************************************************/
  54
  55 #include <linux/module.h>
  56 #include <linux/types.h>
  57 #include <linux/errno.h>
  58 #include <linux/ioport.h>
  59 #include <linux/pci.h>
  60 #include <linux/dma-mapping.h>
  61 #include <linux/kernel.h>
  62 #include <linux/netdevice.h>
  63 #include <linux/etherdevice.h>
  64 #include <linux/skbuff.h>
  65 #include <linux/init.h>
  66 #include <linux/delay.h>
  67 #include <linux/stddef.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/timex.h>
  70 #include <linux/ethtool.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/if_vlan.h>
  73 #include <linux/ip.h>
  74 #include <linux/tcp.h>
  75 #include <net/tcp.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/uaccess.h>
  79 #include <asm/io.h>
  80 #include <asm/div64.h>
  81 #include <asm/irq.h>
  82
  83 /* local include */
  84 #include "s2io.h"
  85 #include "s2io-regs.h"
  86
  87 #define DRV_VERSION "2.0.23.1"
  88
  89 /* S2io Driver name & version. */
  90 static char s2io_driver_name[] = "Neterion";
  91 static char s2io_driver_version[] = DRV_VERSION;
  92
  93 static int rxd_size[4] = {32,48,48,64};
  94 static int rxd_count[4] = {127,85,85,63};
  95
  96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  97 {
  98         int ret;
  99
 100         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 101                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 102
 103         return ret;
 104 }
 105
 106 /*
 107  * Cards with following subsystem_id have a link state indication
 108  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 109  * macro below identifies these cards given the subsystem_id.
 110  */
 111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 112         (dev_type == XFRAME_I_DEVICE) ?                 \
 113                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 114                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 115
 116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 117                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 119 #define PANIC   1
 120 #define LOW     2
 121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
 122 {
 123         struct mac_info *mac_control;
 124
 125         mac_control = &sp->mac_control;
 126         if (rxb_size <= rxd_count[sp->rxd_mode])
 127                 return PANIC;
 128         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 129                 return  LOW;
 130         return 0;
 131 }
 132
 133 /* Ethtool related variables and Macros. */
 134 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 135         "Register test\t(offline)",
 136         "Eeprom test\t(offline)",
 137         "Link test\t(online)",
 138         "RLDRAM test\t(offline)",
 139         "BIST Test\t(offline)"
 140 };
 141
 142 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 143         {"tmac_frms"},
 144         {"tmac_data_octets"},
 145         {"tmac_drop_frms"},
 146         {"tmac_mcst_frms"},
 147         {"tmac_bcst_frms"},
 148         {"tmac_pause_ctrl_frms"},
 149         {"tmac_ttl_octets"},
 150         {"tmac_ucst_frms"},
 151         {"tmac_nucst_frms"},
 152         {"tmac_any_err_frms"},
 153         {"tmac_ttl_less_fb_octets"},
 154         {"tmac_vld_ip_octets"},
 155         {"tmac_vld_ip"},
 156         {"tmac_drop_ip"},
 157         {"tmac_icmp"},
 158         {"tmac_rst_tcp"},
 159         {"tmac_tcp"},
 160         {"tmac_udp"},
 161         {"rmac_vld_frms"},
 162         {"rmac_data_octets"},
 163         {"rmac_fcs_err_frms"},
 164         {"rmac_drop_frms"},
 165         {"rmac_vld_mcst_frms"},
 166         {"rmac_vld_bcst_frms"},
 167         {"rmac_in_rng_len_err_frms"},
 168         {"rmac_out_rng_len_err_frms"},
 169         {"rmac_long_frms"},
 170         {"rmac_pause_ctrl_frms"},
 171         {"rmac_unsup_ctrl_frms"},
 172         {"rmac_ttl_octets"},
 173         {"rmac_accepted_ucst_frms"},
 174         {"rmac_accepted_nucst_frms"},
 175         {"rmac_discarded_frms"},
 176         {"rmac_drop_events"},
 177         {"rmac_ttl_less_fb_octets"},
 178         {"rmac_ttl_frms"},
 179         {"rmac_usized_frms"},
 180         {"rmac_osized_frms"},
 181         {"rmac_frag_frms"},
 182         {"rmac_jabber_frms"},
 183         {"rmac_ttl_64_frms"},
 184         {"rmac_ttl_65_127_frms"},
 185         {"rmac_ttl_128_255_frms"},
 186         {"rmac_ttl_256_511_frms"},
 187         {"rmac_ttl_512_1023_frms"},
 188         {"rmac_ttl_1024_1518_frms"},
 189         {"rmac_ip"},
 190         {"rmac_ip_octets"},
 191         {"rmac_hdr_err_ip"},
 192         {"rmac_drop_ip"},
 193         {"rmac_icmp"},
 194         {"rmac_tcp"},
 195         {"rmac_udp"},
 196         {"rmac_err_drp_udp"},
 197         {"rmac_xgmii_err_sym"},
 198         {"rmac_frms_q0"},
 199         {"rmac_frms_q1"},
 200         {"rmac_frms_q2"},
 201         {"rmac_frms_q3"},
 202         {"rmac_frms_q4"},
 203         {"rmac_frms_q5"},
 204         {"rmac_frms_q6"},
 205         {"rmac_frms_q7"},
 206         {"rmac_full_q0"},
 207         {"rmac_full_q1"},
 208         {"rmac_full_q2"},
 209         {"rmac_full_q3"},
 210         {"rmac_full_q4"},
 211         {"rmac_full_q5"},
 212         {"rmac_full_q6"},
 213         {"rmac_full_q7"},
 214         {"rmac_pause_cnt"},
 215         {"rmac_xgmii_data_err_cnt"},
 216         {"rmac_xgmii_ctrl_err_cnt"},
 217         {"rmac_accepted_ip"},
 218         {"rmac_err_tcp"},
 219         {"rd_req_cnt"},
 220         {"new_rd_req_cnt"},
 221         {"new_rd_req_rtry_cnt"},
 222         {"rd_rtry_cnt"},
 223         {"wr_rtry_rd_ack_cnt"},
 224         {"wr_req_cnt"},
 225         {"new_wr_req_cnt"},
 226         {"new_wr_req_rtry_cnt"},
 227         {"wr_rtry_cnt"},
 228         {"wr_disc_cnt"},
 229         {"rd_rtry_wr_ack_cnt"},
 230         {"txp_wr_cnt"},
 231         {"txd_rd_cnt"},
 232         {"txd_wr_cnt"},
 233         {"rxd_rd_cnt"},
 234         {"rxd_wr_cnt"},
 235         {"txf_rd_cnt"},
 236         {"rxf_wr_cnt"}
 237 };
 238
 239 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 240         {"rmac_ttl_1519_4095_frms"},
 241         {"rmac_ttl_4096_8191_frms"},
 242         {"rmac_ttl_8192_max_frms"},
 243         {"rmac_ttl_gt_max_frms"},
 244         {"rmac_osized_alt_frms"},
 245         {"rmac_jabber_alt_frms"},
 246         {"rmac_gt_max_alt_frms"},
 247         {"rmac_vlan_frms"},
 248         {"rmac_len_discard"},
 249         {"rmac_fcs_discard"},
 250         {"rmac_pf_discard"},
 251         {"rmac_da_discard"},
 252         {"rmac_red_discard"},
 253         {"rmac_rts_discard"},
 254         {"rmac_ingm_full_discard"},
 255         {"link_fault_cnt"}
 256 };
 257
 258 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 259         {"\n DRIVER STATISTICS"},
 260         {"single_bit_ecc_errs"},
 261         {"double_bit_ecc_errs"},
 262         {"parity_err_cnt"},
 263         {"serious_err_cnt"},
 264         {"soft_reset_cnt"},
 265         {"fifo_full_cnt"},
 266         {"ring_full_cnt"},
 267         ("alarm_transceiver_temp_high"),
 268         ("alarm_transceiver_temp_low"),
 269         ("alarm_laser_bias_current_high"),
 270         ("alarm_laser_bias_current_low"),
 271         ("alarm_laser_output_power_high"),
 272         ("alarm_laser_output_power_low"),
 273         ("warn_transceiver_temp_high"),
 274         ("warn_transceiver_temp_low"),
 275         ("warn_laser_bias_current_high"),
 276         ("warn_laser_bias_current_low"),
 277         ("warn_laser_output_power_high"),
 278         ("warn_laser_output_power_low"),
 279         ("lro_aggregated_pkts"),
 280         ("lro_flush_both_count"),
 281         ("lro_out_of_sequence_pkts"),
 282         ("lro_flush_due_to_max_pkts"),
 283         ("lro_avg_aggr_pkts"),
 284         ("mem_alloc_fail_cnt"),
 285         ("watchdog_timer_cnt"),
 286         ("mem_allocated"),
 287         ("mem_freed"),
 288         ("link_up_cnt"),
 289         ("link_down_cnt"),
 290         ("link_up_time"),
 291         ("link_down_time"),
 292         ("tx_tcode_buf_abort_cnt"),
 293         ("tx_tcode_desc_abort_cnt"),
 294         ("tx_tcode_parity_err_cnt"),
 295         ("tx_tcode_link_loss_cnt"),
 296         ("tx_tcode_list_proc_err_cnt"),
 297         ("rx_tcode_parity_err_cnt"),
 298         ("rx_tcode_abort_cnt"),
 299         ("rx_tcode_parity_abort_cnt"),
 300         ("rx_tcode_rda_fail_cnt"),
 301         ("rx_tcode_unkn_prot_cnt"),
 302         ("rx_tcode_fcs_err_cnt"),
 303         ("rx_tcode_buf_size_err_cnt"),
 304         ("rx_tcode_rxd_corrupt_cnt"),
 305         ("rx_tcode_unkn_err_cnt")
 306 };
 307
 308 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
 309 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
 310                                         ETH_GSTRING_LEN
 311 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
 312
 313 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
 314 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
 315
 316 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
 317 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
 318
 319 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 320 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 321
 322 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 323                         init_timer(&timer);                     \
 324                         timer.function = handle;                \
 325                         timer.data = (unsigned long) arg;       \
 326                         mod_timer(&timer, (jiffies + exp))      \
 327
 328 /* Add the vlan */
 329 static void s2io_vlan_rx_register(struct net_device *dev,
 330                                         struct vlan_group *grp)
 331 {
 332         struct s2io_nic *nic = dev->priv;
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&nic->tx_lock, flags);
 336         nic->vlgrp = grp;
 337         spin_unlock_irqrestore(&nic->tx_lock, flags);
 338 }
 339
 340 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
 341 static int vlan_strip_flag;
 342
 343 /*
 344  * Constants to be programmed into the Xena's registers, to configure
 345  * the XAUI.
 346  */
 347
 348 #define END_SIGN        0x0
 349 static const u64 herc_act_dtx_cfg[] = {
 350         /* Set address */
 351         0x8000051536750000ULL, 0x80000515367500E0ULL,
 352         /* Write data */
 353         0x8000051536750004ULL, 0x80000515367500E4ULL,
 354         /* Set address */
 355         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 356         /* Write data */
 357         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 358         /* Set address */
 359         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 360         /* Write data */
 361         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 362         /* Set address */
 363         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 364         /* Write data */
 365         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 366         /* Done */
 367         END_SIGN
 368 };
 369
 370 static const u64 xena_dtx_cfg[] = {
 371         /* Set address */
 372         0x8000051500000000ULL, 0x80000515000000E0ULL,
 373         /* Write data */
 374         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 375         /* Set address */
 376         0x8001051500000000ULL, 0x80010515000000E0ULL,
 377         /* Write data */
 378         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 379         /* Set address */
 380         0x8002051500000000ULL, 0x80020515000000E0ULL,
 381         /* Write data */
 382         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 383         END_SIGN
 384 };
 385
 386 /*
 387  * Constants for Fixing the MacAddress problem seen mostly on
 388  * Alpha machines.
 389  */
 390 static const u64 fix_mac[] = {
 391         0x0060000000000000ULL, 0x0060600000000000ULL,
 392         0x0040600000000000ULL, 0x0000600000000000ULL,
 393         0x0020600000000000ULL, 0x0060600000000000ULL,
 394         0x0020600000000000ULL, 0x0060600000000000ULL,
 395         0x0020600000000000ULL, 0x0060600000000000ULL,
 396         0x0020600000000000ULL, 0x0060600000000000ULL,
 397         0x0020600000000000ULL, 0x0060600000000000ULL,
 398         0x0020600000000000ULL, 0x0060600000000000ULL,
 399         0x0020600000000000ULL, 0x0060600000000000ULL,
 400         0x0020600000000000ULL, 0x0060600000000000ULL,
 401         0x0020600000000000ULL, 0x0060600000000000ULL,
 402         0x0020600000000000ULL, 0x0060600000000000ULL,
 403         0x0020600000000000ULL, 0x0000600000000000ULL,
 404         0x0040600000000000ULL, 0x0060600000000000ULL,
 405         END_SIGN
 406 };
 407
 408 MODULE_LICENSE("GPL");
 409 MODULE_VERSION(DRV_VERSION);
 410
 411
 412 /* Module Loadable parameters. */
 413 S2IO_PARM_INT(tx_fifo_num, 1);
 414 S2IO_PARM_INT(rx_ring_num, 1);
 415
 416
 417 S2IO_PARM_INT(rx_ring_mode, 1);
 418 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 419 S2IO_PARM_INT(rmac_pause_time, 0x100);
 420 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 421 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 422 S2IO_PARM_INT(shared_splits, 0);
 423 S2IO_PARM_INT(tmac_util_period, 5);
 424 S2IO_PARM_INT(rmac_util_period, 5);
 425 S2IO_PARM_INT(bimodal, 0);
 426 S2IO_PARM_INT(l3l4hdr_size, 128);
 427 /* Frequency of Rx desc syncs expressed as power of 2 */
 428 S2IO_PARM_INT(rxsync_frequency, 3);
 429 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 430 S2IO_PARM_INT(intr_type, 0);
 431 /* Large receive offload feature */
 432 S2IO_PARM_INT(lro, 0);
 433 /* Max pkts to be aggregated by LRO at one time. If not specified,
 434  * aggregation happens until we hit max IP pkt size(64K)
 435  */
 436 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 437 S2IO_PARM_INT(indicate_max_pkts, 0);
 438
 439 S2IO_PARM_INT(napi, 1);
 440 S2IO_PARM_INT(ufo, 0);
 441 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 442
 443 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 444     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 445 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 446     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 447 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 448     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 449
 450 module_param_array(tx_fifo_len, uint, NULL, 0);
 451 module_param_array(rx_ring_sz, uint, NULL, 0);
 452 module_param_array(rts_frm_len, uint, NULL, 0);
 453
 454 /*
 455  * S2IO device table.
 456  * This table lists all the devices that this driver supports.
 457  */
 458 static struct pci_device_id s2io_tbl[] __devinitdata = {
 459         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 460          PCI_ANY_ID, PCI_ANY_ID},
 461         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 462          PCI_ANY_ID, PCI_ANY_ID},
 463         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 464          PCI_ANY_ID, PCI_ANY_ID},
 465         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 466          PCI_ANY_ID, PCI_ANY_ID},
 467         {0,}
 468 };
 469
 470 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 471
 472 static struct pci_driver s2io_driver = {
 473       .name = "S2IO",
 474       .id_table = s2io_tbl,
 475       .probe = s2io_init_nic,
 476       .remove = __devexit_p(s2io_rem_nic),
 477 };
 478
 479 /* A simplifier macro used both by init and free shared_mem Fns(). */
 480 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 481
 482 /**
 483  * init_shared_mem - Allocation and Initialization of Memory
 484  * @nic: Device private variable.
 485  * Description: The function allocates all the memory areas shared
 486  * between the NIC and the driver. This includes Tx descriptors,
 487  * Rx descriptors and the statistics block.
 488  */
 489
 490 static int init_shared_mem(struct s2io_nic *nic)
 491 {
 492         u32 size;
 493         void *tmp_v_addr, *tmp_v_addr_next;
 494         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 495         struct RxD_block *pre_rxd_blk = NULL;
 496         int i, j, blk_cnt;
 497         int lst_size, lst_per_page;
 498         struct net_device *dev = nic->dev;
 499         unsigned long tmp;
 500         struct buffAdd *ba;
 501
 502         struct mac_info *mac_control;
 503         struct config_param *config;
 504         unsigned long long mem_allocated = 0;
 505
 506         mac_control = &nic->mac_control;
 507         config = &nic->config;
 508
 509
 510         /* Allocation and initialization of TXDLs in FIOFs */
 511         size = 0;
 512         for (i = 0; i < config->tx_fifo_num; i++) {
 513                 size += config->tx_cfg[i].fifo_len;
 514         }
 515         if (size > MAX_AVAILABLE_TXDS) {
 516                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 517                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 518                 return -EINVAL;
 519         }
 520
 521         lst_size = (sizeof(struct TxD) * config->max_txds);
 522         lst_per_page = PAGE_SIZE / lst_size;
 523
 524         for (i = 0; i < config->tx_fifo_num; i++) {
 525                 int fifo_len = config->tx_cfg[i].fifo_len;
 526                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 527                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 528                                                           GFP_KERNEL);
 529                 if (!mac_control->fifos[i].list_info) {
 530                         DBG_PRINT(INFO_DBG,
 531                                   "Malloc failed for list_info\n");
 532                         return -ENOMEM;
 533                 }
 534                 mem_allocated += list_holder_size;
 535                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 536         }
 537         for (i = 0; i < config->tx_fifo_num; i++) {
 538                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 539                                                 lst_per_page);
 540                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 541                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 542                     config->tx_cfg[i].fifo_len - 1;
 543                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 544                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 545                     config->tx_cfg[i].fifo_len - 1;
 546                 mac_control->fifos[i].fifo_no = i;
 547                 mac_control->fifos[i].nic = nic;
 548                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 549
 550                 for (j = 0; j < page_num; j++) {
 551                         int k = 0;
 552                         dma_addr_t tmp_p;
 553                         void *tmp_v;
 554                         tmp_v = pci_alloc_consistent(nic->pdev,
 555                                                      PAGE_SIZE, &tmp_p);
 556                         if (!tmp_v) {
 557                                 DBG_PRINT(INFO_DBG,
 558                                           "pci_alloc_consistent ");
 559                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 560                                 return -ENOMEM;
 561                         }
 562                         /* If we got a zero DMA address(can happen on
 563                          * certain platforms like PPC), reallocate.
 564                          * Store virtual address of page we don't want,
 565                          * to be freed later.
 566                          */
 567                         if (!tmp_p) {
 568                                 mac_control->zerodma_virt_addr = tmp_v;
 569                                 DBG_PRINT(INIT_DBG,
 570                                 "%s: Zero DMA address for TxDL. ", dev->name);
 571                                 DBG_PRINT(INIT_DBG,
 572                                 "Virtual address %p\n", tmp_v);
 573                                 tmp_v = pci_alloc_consistent(nic->pdev,
 574                                                      PAGE_SIZE, &tmp_p);
 575                                 if (!tmp_v) {
 576                                         DBG_PRINT(INFO_DBG,
 577                                           "pci_alloc_consistent ");
 578                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 579                                         return -ENOMEM;
 580                                 }
 581                                 mem_allocated += PAGE_SIZE;
 582                         }
 583                         while (k < lst_per_page) {
 584                                 int l = (j * lst_per_page) + k;
 585                                 if (l == config->tx_cfg[i].fifo_len)
 586                                         break;
 587                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 588                                     tmp_v + (k * lst_size);
 589                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 590                                     tmp_p + (k * lst_size);
 591                                 k++;
 592                         }
 593                 }
 594         }
 595
 596         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 597         if (!nic->ufo_in_band_v)
 598                 return -ENOMEM;
 599          mem_allocated += (size * sizeof(u64));
 600
 601         /* Allocation and initialization of RXDs in Rings */
 602         size = 0;
 603         for (i = 0; i < config->rx_ring_num; i++) {
 604                 if (config->rx_cfg[i].num_rxd %
 605                     (rxd_count[nic->rxd_mode] + 1)) {
 606                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 607                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 608                                   i);
 609                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 610                         return FAILURE;
 611                 }
 612                 size += config->rx_cfg[i].num_rxd;
 613                 mac_control->rings[i].block_count =
 614                         config->rx_cfg[i].num_rxd /
 615                         (rxd_count[nic->rxd_mode] + 1 );
 616                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 617                         mac_control->rings[i].block_count;
 618         }
 619         if (nic->rxd_mode == RXD_MODE_1)
 620                 size = (size * (sizeof(struct RxD1)));
 621         else
 622                 size = (size * (sizeof(struct RxD3)));
 623
 624         for (i = 0; i < config->rx_ring_num; i++) {
 625                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 626                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 627                 mac_control->rings[i].rx_curr_get_info.ring_len =
 628                     config->rx_cfg[i].num_rxd - 1;
 629                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 630                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 631                 mac_control->rings[i].rx_curr_put_info.ring_len =
 632                     config->rx_cfg[i].num_rxd - 1;
 633                 mac_control->rings[i].nic = nic;
 634                 mac_control->rings[i].ring_no = i;
 635
 636                 blk_cnt = config->rx_cfg[i].num_rxd /
 637                                 (rxd_count[nic->rxd_mode] + 1);
 638                 /*  Allocating all the Rx blocks */
 639                 for (j = 0; j < blk_cnt; j++) {
 640                         struct rx_block_info *rx_blocks;
 641                         int l;
 642
 643                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 644                         size = SIZE_OF_BLOCK; //size is always page size
 645                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 646                                                           &tmp_p_addr);
 647                         if (tmp_v_addr == NULL) {
 648                                 /*
 649                                  * In case of failure, free_shared_mem()
 650                                  * is called, which should free any
 651                                  * memory that was alloced till the
 652                                  * failure happened.
 653                                  */
 654                                 rx_blocks->block_virt_addr = tmp_v_addr;
 655                                 return -ENOMEM;
 656                         }
 657                         mem_allocated += size;
 658                         memset(tmp_v_addr, 0, size);
 659                         rx_blocks->block_virt_addr = tmp_v_addr;
 660                         rx_blocks->block_dma_addr = tmp_p_addr;
 661                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
 662                                                   rxd_count[nic->rxd_mode],
 663                                                   GFP_KERNEL);
 664                         if (!rx_blocks->rxds)
 665                                 return -ENOMEM;
 666                         mem_allocated +=
 667                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 668                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 669                                 rx_blocks->rxds[l].virt_addr =
 670                                         rx_blocks->block_virt_addr +
 671                                         (rxd_size[nic->rxd_mode] * l);
 672                                 rx_blocks->rxds[l].dma_addr =
 673                                         rx_blocks->block_dma_addr +
 674                                         (rxd_size[nic->rxd_mode] * l);
 675                         }
 676                 }
 677                 /* Interlinking all Rx Blocks */
 678                 for (j = 0; j < blk_cnt; j++) {
 679                         tmp_v_addr =
 680                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 681                         tmp_v_addr_next =
 682                                 mac_control->rings[i].rx_blocks[(j + 1) %
 683                                               blk_cnt].block_virt_addr;
 684                         tmp_p_addr =
 685                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 686                         tmp_p_addr_next =
 687                                 mac_control->rings[i].rx_blocks[(j + 1) %
 688                                               blk_cnt].block_dma_addr;
 689
 690                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
 691                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 692                             (unsigned long) tmp_v_addr_next;
 693                         pre_rxd_blk->pNext_RxD_Blk_physical =
 694                             (u64) tmp_p_addr_next;
 695                 }
 696         }
 697         if (nic->rxd_mode >= RXD_MODE_3A) {
 698                 /*
 699                  * Allocation of Storages for buffer addresses in 2BUFF mode
 700                  * and the buffers as well.
 701                  */
 702                 for (i = 0; i < config->rx_ring_num; i++) {
 703                         blk_cnt = config->rx_cfg[i].num_rxd /
 704                            (rxd_count[nic->rxd_mode]+ 1);
 705                         mac_control->rings[i].ba =
 706                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
 707                                      GFP_KERNEL);
 708                         if (!mac_control->rings[i].ba)
 709                                 return -ENOMEM;
 710                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
 711                         for (j = 0; j < blk_cnt; j++) {
 712                                 int k = 0;
 713                                 mac_control->rings[i].ba[j] =
 714                                         kmalloc((sizeof(struct buffAdd) *
 715                                                 (rxd_count[nic->rxd_mode] + 1)),
 716                                                 GFP_KERNEL);
 717                                 if (!mac_control->rings[i].ba[j])
 718                                         return -ENOMEM;
 719                                 mem_allocated += (sizeof(struct buffAdd) *  \
 720                                         (rxd_count[nic->rxd_mode] + 1));
 721                                 while (k != rxd_count[nic->rxd_mode]) {
 722                                         ba = &mac_control->rings[i].ba[j][k];
 723
 724                                         ba->ba_0_org = (void *) kmalloc
 725                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 726                                         if (!ba->ba_0_org)
 727                                                 return -ENOMEM;
 728                                         mem_allocated +=
 729                                                 (BUF0_LEN + ALIGN_SIZE);
 730                                         tmp = (unsigned long)ba->ba_0_org;
 731                                         tmp += ALIGN_SIZE;
 732                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 733                                         ba->ba_0 = (void *) tmp;
 734
 735                                         ba->ba_1_org = (void *) kmalloc
 736                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 737                                         if (!ba->ba_1_org)
 738                                                 return -ENOMEM;
 739                                         mem_allocated
 740                                                 += (BUF1_LEN + ALIGN_SIZE);
 741                                         tmp = (unsigned long) ba->ba_1_org;
 742                                         tmp += ALIGN_SIZE;
 743                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 744                                         ba->ba_1 = (void *) tmp;
 745                                         k++;
 746                                 }
 747                         }
 748                 }
 749         }
 750
 751         /* Allocation and initialization of Statistics block */
 752         size = sizeof(struct stat_block);
 753         mac_control->stats_mem = pci_alloc_consistent
 754             (nic->pdev, size, &mac_control->stats_mem_phy);
 755
 756         if (!mac_control->stats_mem) {
 757                 /*
 758                  * In case of failure, free_shared_mem() is called, which
 759                  * should free any memory that was alloced till the
 760                  * failure happened.
 761                  */
 762                 return -ENOMEM;
 763         }
 764         mem_allocated += size;
 765         mac_control->stats_mem_sz = size;
 766
 767         tmp_v_addr = mac_control->stats_mem;
 768         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
 769         memset(tmp_v_addr, 0, size);
 770         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 771                   (unsigned long long) tmp_p_addr);
 772         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 773         return SUCCESS;
 774 }
 775
 776 /**
 777  * free_shared_mem - Free the allocated Memory
 778  * @nic:  Device private variable.
 779  * Description: This function is to free all memory locations allocated by
 780  * the init_shared_mem() function and return it to the kernel.
 781  */
 782
 783 static void free_shared_mem(struct s2io_nic *nic)
 784 {
 785         int i, j, blk_cnt, size;
 786         u32 ufo_size = 0;
 787         void *tmp_v_addr;
 788         dma_addr_t tmp_p_addr;
 789         struct mac_info *mac_control;
 790         struct config_param *config;
 791         int lst_size, lst_per_page;
 792         struct net_device *dev = nic->dev;
 793         int page_num = 0;
 794
 795         if (!nic)
 796                 return;
 797
 798         mac_control = &nic->mac_control;
 799         config = &nic->config;
 800
 801         lst_size = (sizeof(struct TxD) * config->max_txds);
 802         lst_per_page = PAGE_SIZE / lst_size;
 803
 804         for (i = 0; i < config->tx_fifo_num; i++) {
 805                 ufo_size += config->tx_cfg[i].fifo_len;
 806                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 807                                                         lst_per_page);
 808                 for (j = 0; j < page_num; j++) {
 809                         int mem_blks = (j * lst_per_page);
 810                         if (!mac_control->fifos[i].list_info)
 811                                 return;
 812                         if (!mac_control->fifos[i].list_info[mem_blks].
 813                                  list_virt_addr)
 814                                 break;
 815                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 816                                             mac_control->fifos[i].
 817                                             list_info[mem_blks].
 818                                             list_virt_addr,
 819                                             mac_control->fifos[i].
 820                                             list_info[mem_blks].
 821                                             list_phy_addr);
 822                         nic->mac_control.stats_info->sw_stat.mem_freed
 823                                                 += PAGE_SIZE;
 824                 }
 825                 /* If we got a zero DMA address during allocation,
 826                  * free the page now
 827                  */
 828                 if (mac_control->zerodma_virt_addr) {
 829                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 830                                             mac_control->zerodma_virt_addr,
 831                                             (dma_addr_t)0);
 832                         DBG_PRINT(INIT_DBG,
 833                                 "%s: Freeing TxDL with zero DMA addr. ",
 834                                 dev->name);
 835                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 836                                 mac_control->zerodma_virt_addr);
 837                         nic->mac_control.stats_info->sw_stat.mem_freed
 838                                                 += PAGE_SIZE;
 839                 }
 840                 kfree(mac_control->fifos[i].list_info);
 841                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 842                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
 843         }
 844
 845         size = SIZE_OF_BLOCK;
 846         for (i = 0; i < config->rx_ring_num; i++) {
 847                 blk_cnt = mac_control->rings[i].block_count;
 848                 for (j = 0; j < blk_cnt; j++) {
 849                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 850                                 block_virt_addr;
 851                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 852                                 block_dma_addr;
 853                         if (tmp_v_addr == NULL)
 854                                 break;
 855                         pci_free_consistent(nic->pdev, size,
 856                                             tmp_v_addr, tmp_p_addr);
 857                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
 858                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 859                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 860                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 861                 }
 862         }
 863
 864         if (nic->rxd_mode >= RXD_MODE_3A) {
 865                 /* Freeing buffer storage addresses in 2BUFF mode. */
 866                 for (i = 0; i < config->rx_ring_num; i++) {
 867                         blk_cnt = config->rx_cfg[i].num_rxd /
 868                             (rxd_count[nic->rxd_mode] + 1);
 869                         for (j = 0; j < blk_cnt; j++) {
 870                                 int k = 0;
 871                                 if (!mac_control->rings[i].ba[j])
 872                                         continue;
 873                                 while (k != rxd_count[nic->rxd_mode]) {
 874                                         struct buffAdd *ba =
 875                                                 &mac_control->rings[i].ba[j][k];
 876                                         kfree(ba->ba_0_org);
 877                                         nic->mac_control.stats_info->sw_stat.\
 878                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
 879                                         kfree(ba->ba_1_org);
 880                                         nic->mac_control.stats_info->sw_stat.\
 881                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
 882                                         k++;
 883                                 }
 884                                 kfree(mac_control->rings[i].ba[j]);
 885                                 nic->mac_control.stats_info->sw_stat.mem_freed                          += (sizeof(struct buffAdd) *
 886                                 (rxd_count[nic->rxd_mode] + 1));
 887                         }
 888                         kfree(mac_control->rings[i].ba);
 889                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 890                         (sizeof(struct buffAdd *) * blk_cnt);
 891                 }
 892         }
 893
 894         if (mac_control->stats_mem) {
 895                 pci_free_consistent(nic->pdev,
 896                                     mac_control->stats_mem_sz,
 897                                     mac_control->stats_mem,
 898                                     mac_control->stats_mem_phy);
 899                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 900                         mac_control->stats_mem_sz;
 901         }
 902         if (nic->ufo_in_band_v) {
 903                 kfree(nic->ufo_in_band_v);
 904                 nic->mac_control.stats_info->sw_stat.mem_freed
 905                         += (ufo_size * sizeof(u64));
 906         }
 907 }
 908
 909 /**
 910  * s2io_verify_pci_mode -
 911  */
 912
 913 static int s2io_verify_pci_mode(struct s2io_nic *nic)
 914 {
 915         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 916         register u64 val64 = 0;
 917         int     mode;
 918
 919         val64 = readq(&bar0->pci_mode);
 920         mode = (u8)GET_PCI_MODE(val64);
 921
 922         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 923                 return -1;      /* Unknown PCI mode */
 924         return mode;
 925 }
 926
 927 #define NEC_VENID   0x1033
 928 #define NEC_DEVID   0x0125
 929 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 930 {
 931         struct pci_dev *tdev = NULL;
 932         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 933                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
 934                         if (tdev->bus == s2io_pdev->bus->parent)
 935                                 pci_dev_put(tdev);
 936                                 return 1;
 937                 }
 938         }
 939         return 0;
 940 }
 941
 942 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 943 /**
 944  * s2io_print_pci_mode -
 945  */
 946 static int s2io_print_pci_mode(struct s2io_nic *nic)
 947 {
 948         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 949         register u64 val64 = 0;
 950         int     mode;
 951         struct config_param *config = &nic->config;
 952
 953         val64 = readq(&bar0->pci_mode);
 954         mode = (u8)GET_PCI_MODE(val64);
 955
 956         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 957                 return -1;      /* Unknown PCI mode */
 958
 959         config->bus_speed = bus_speed[mode];
 960
 961         if (s2io_on_nec_bridge(nic->pdev)) {
 962                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 963                                                         nic->dev->name);
 964                 return mode;
 965         }
 966
 967         if (val64 & PCI_MODE_32_BITS) {
 968                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 969         } else {
 970                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 971         }
 972
 973         switch(mode) {
 974                 case PCI_MODE_PCI_33:
 975                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 976                         break;
 977                 case PCI_MODE_PCI_66:
 978                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 979                         break;
 980                 case PCI_MODE_PCIX_M1_66:
 981                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 982                         break;
 983                 case PCI_MODE_PCIX_M1_100:
 984                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 985                         break;
 986                 case PCI_MODE_PCIX_M1_133:
 987                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 988                         break;
 989                 case PCI_MODE_PCIX_M2_66:
 990                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 991                         break;
 992                 case PCI_MODE_PCIX_M2_100:
 993                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 994                         break;
 995                 case PCI_MODE_PCIX_M2_133:
 996                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 997                         break;
 998                 default:
 999                         return -1;      /* Unsupported bus speed */
1000         }
1001
1002         return mode;
1003 }
1004
1005 /**
1006  *  init_nic - Initialization of hardware
1007  *  @nic: device peivate variable
1008  *  Description: The function sequentially configures every block
1009  *  of the H/W from their reset values.
1010  *  Return Value:  SUCCESS on success and
1011  *  '-1' on failure (endian settings incorrect).
1012  */
1013
1014 static int init_nic(struct s2io_nic *nic)
1015 {
1016         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1017         struct net_device *dev = nic->dev;
1018         register u64 val64 = 0;
1019         void __iomem *add;
1020         u32 time;
1021         int i, j;
1022         struct mac_info *mac_control;
1023         struct config_param *config;
1024         int dtx_cnt = 0;
1025         unsigned long long mem_share;
1026         int mem_size;
1027
1028         mac_control = &nic->mac_control;
1029         config = &nic->config;
1030
1031         /* to set the swapper controle on the card */
1032         if(s2io_set_swapper(nic)) {
1033                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1034                 return -1;
1035         }
1036
1037         /*
1038          * Herc requires EOI to be removed from reset before XGXS, so..
1039          */
1040         if (nic->device_type & XFRAME_II_DEVICE) {
1041                 val64 = 0xA500000000ULL;
1042                 writeq(val64, &bar0->sw_reset);
1043                 msleep(500);
1044                 val64 = readq(&bar0->sw_reset);
1045         }
1046
1047         /* Remove XGXS from reset state */
1048         val64 = 0;
1049         writeq(val64, &bar0->sw_reset);
1050         msleep(500);
1051         val64 = readq(&bar0->sw_reset);
1052
1053         /*  Enable Receiving broadcasts */
1054         add = &bar0->mac_cfg;
1055         val64 = readq(&bar0->mac_cfg);
1056         val64 |= MAC_RMAC_BCAST_ENABLE;
1057         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1058         writel((u32) val64, add);
1059         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1060         writel((u32) (val64 >> 32), (add + 4));
1061
1062         /* Read registers in all blocks */
1063         val64 = readq(&bar0->mac_int_mask);
1064         val64 = readq(&bar0->mc_int_mask);
1065         val64 = readq(&bar0->xgxs_int_mask);
1066
1067         /*  Set MTU */
1068         val64 = dev->mtu;
1069         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1070
1071         if (nic->device_type & XFRAME_II_DEVICE) {
1072                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1073                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1074                                           &bar0->dtx_control, UF);
1075                         if (dtx_cnt & 0x1)
1076                                 msleep(1); /* Necessary!! */
1077                         dtx_cnt++;
1078                 }
1079         } else {
1080                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1081                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1082                                           &bar0->dtx_control, UF);
1083                         val64 = readq(&bar0->dtx_control);
1084                         dtx_cnt++;
1085                 }
1086         }
1087
1088         /*  Tx DMA Initialization */
1089         val64 = 0;
1090         writeq(val64, &bar0->tx_fifo_partition_0);
1091         writeq(val64, &bar0->tx_fifo_partition_1);
1092         writeq(val64, &bar0->tx_fifo_partition_2);
1093         writeq(val64, &bar0->tx_fifo_partition_3);
1094
1095
1096         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1097                 val64 |=
1098                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1099                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1100                                     ((i * 32) + 5), 3);
1101
1102                 if (i == (config->tx_fifo_num - 1)) {
1103                         if (i % 2 == 0)
1104                                 i++;
1105                 }
1106
1107                 switch (i) {
1108                 case 1:
1109                         writeq(val64, &bar0->tx_fifo_partition_0);
1110                         val64 = 0;
1111                         break;
1112                 case 3:
1113                         writeq(val64, &bar0->tx_fifo_partition_1);
1114                         val64 = 0;
1115                         break;
1116                 case 5:
1117                         writeq(val64, &bar0->tx_fifo_partition_2);
1118                         val64 = 0;
1119                         break;
1120                 case 7:
1121                         writeq(val64, &bar0->tx_fifo_partition_3);
1122                         break;
1123                 }
1124         }
1125
1126         /*
1127          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1128          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1129          */
1130         if ((nic->device_type == XFRAME_I_DEVICE) &&
1131                 (get_xena_rev_id(nic->pdev) < 4))
1132                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1133
1134         val64 = readq(&bar0->tx_fifo_partition_0);
1135         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1136                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1137
1138         /*
1139          * Initialization of Tx_PA_CONFIG register to ignore packet
1140          * integrity checking.
1141          */
1142         val64 = readq(&bar0->tx_pa_cfg);
1143         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1144             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1145         writeq(val64, &bar0->tx_pa_cfg);
1146
1147         /* Rx DMA intialization. */
1148         val64 = 0;
1149         for (i = 0; i < config->rx_ring_num; i++) {
1150                 val64 |=
1151                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1152                          3);
1153         }
1154         writeq(val64, &bar0->rx_queue_priority);
1155
1156         /*
1157          * Allocating equal share of memory to all the
1158          * configured Rings.
1159          */
1160         val64 = 0;
1161         if (nic->device_type & XFRAME_II_DEVICE)
1162                 mem_size = 32;
1163         else
1164                 mem_size = 64;
1165
1166         for (i = 0; i < config->rx_ring_num; i++) {
1167                 switch (i) {
1168                 case 0:
1169                         mem_share = (mem_size / config->rx_ring_num +
1170                                      mem_size % config->rx_ring_num);
1171                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1172                         continue;
1173                 case 1:
1174                         mem_share = (mem_size / config->rx_ring_num);
1175                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1176                         continue;
1177                 case 2:
1178                         mem_share = (mem_size / config->rx_ring_num);
1179                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1180                         continue;
1181                 case 3:
1182                         mem_share = (mem_size / config->rx_ring_num);
1183                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1184                         continue;
1185                 case 4:
1186                         mem_share = (mem_size / config->rx_ring_num);
1187                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1188                         continue;
1189                 case 5:
1190                         mem_share = (mem_size / config->rx_ring_num);
1191                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1192                         continue;
1193                 case 6:
1194                         mem_share = (mem_size / config->rx_ring_num);
1195                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1196                         continue;
1197                 case 7:
1198                         mem_share = (mem_size / config->rx_ring_num);
1199                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1200                         continue;
1201                 }
1202         }
1203         writeq(val64, &bar0->rx_queue_cfg);
1204
1205         /*
1206          * Filling Tx round robin registers
1207          * as per the number of FIFOs
1208          */
1209         switch (config->tx_fifo_num) {
1210         case 1:
1211                 val64 = 0x0000000000000000ULL;
1212                 writeq(val64, &bar0->tx_w_round_robin_0);
1213                 writeq(val64, &bar0->tx_w_round_robin_1);
1214                 writeq(val64, &bar0->tx_w_round_robin_2);
1215                 writeq(val64, &bar0->tx_w_round_robin_3);
1216                 writeq(val64, &bar0->tx_w_round_robin_4);
1217                 break;
1218         case 2:
1219                 val64 = 0x0000010000010000ULL;
1220                 writeq(val64, &bar0->tx_w_round_robin_0);
1221                 val64 = 0x0100000100000100ULL;
1222                 writeq(val64, &bar0->tx_w_round_robin_1);
1223                 val64 = 0x0001000001000001ULL;
1224                 writeq(val64, &bar0->tx_w_round_robin_2);
1225                 val64 = 0x0000010000010000ULL;
1226                 writeq(val64, &bar0->tx_w_round_robin_3);
1227                 val64 = 0x0100000000000000ULL;
1228                 writeq(val64, &bar0->tx_w_round_robin_4);
1229                 break;
1230         case 3:
1231                 val64 = 0x0001000102000001ULL;
1232                 writeq(val64, &bar0->tx_w_round_robin_0);
1233                 val64 = 0x0001020000010001ULL;
1234                 writeq(val64, &bar0->tx_w_round_robin_1);
1235                 val64 = 0x0200000100010200ULL;
1236                 writeq(val64, &bar0->tx_w_round_robin_2);
1237                 val64 = 0x0001000102000001ULL;
1238                 writeq(val64, &bar0->tx_w_round_robin_3);
1239                 val64 = 0x0001020000000000ULL;
1240                 writeq(val64, &bar0->tx_w_round_robin_4);
1241                 break;
1242         case 4:
1243                 val64 = 0x0001020300010200ULL;
1244                 writeq(val64, &bar0->tx_w_round_robin_0);
1245                 val64 = 0x0100000102030001ULL;
1246                 writeq(val64, &bar0->tx_w_round_robin_1);
1247                 val64 = 0x0200010000010203ULL;
1248                 writeq(val64, &bar0->tx_w_round_robin_2);
1249                 val64 = 0x0001020001000001ULL;
1250                 writeq(val64, &bar0->tx_w_round_robin_3);
1251                 val64 = 0x0203000100000000ULL;
1252                 writeq(val64, &bar0->tx_w_round_robin_4);
1253                 break;
1254         case 5:
1255                 val64 = 0x0001000203000102ULL;
1256                 writeq(val64, &bar0->tx_w_round_robin_0);
1257                 val64 = 0x0001020001030004ULL;
1258                 writeq(val64, &bar0->tx_w_round_robin_1);
1259                 val64 = 0x0001000203000102ULL;
1260                 writeq(val64, &bar0->tx_w_round_robin_2);
1261                 val64 = 0x0001020001030004ULL;
1262                 writeq(val64, &bar0->tx_w_round_robin_3);
1263                 val64 = 0x0001000000000000ULL;
1264                 writeq(val64, &bar0->tx_w_round_robin_4);
1265                 break;
1266         case 6:
1267                 val64 = 0x0001020304000102ULL;
1268                 writeq(val64, &bar0->tx_w_round_robin_0);
1269                 val64 = 0x0304050001020001ULL;
1270                 writeq(val64, &bar0->tx_w_round_robin_1);
1271                 val64 = 0x0203000100000102ULL;
1272                 writeq(val64, &bar0->tx_w_round_robin_2);
1273                 val64 = 0x0304000102030405ULL;
1274                 writeq(val64, &bar0->tx_w_round_robin_3);
1275                 val64 = 0x0001000200000000ULL;
1276                 writeq(val64, &bar0->tx_w_round_robin_4);
1277                 break;
1278         case 7:
1279                 val64 = 0x0001020001020300ULL;
1280                 writeq(val64, &bar0->tx_w_round_robin_0);
1281                 val64 = 0x0102030400010203ULL;
1282                 writeq(val64, &bar0->tx_w_round_robin_1);
1283                 val64 = 0x0405060001020001ULL;
1284                 writeq(val64, &bar0->tx_w_round_robin_2);
1285                 val64 = 0x0304050000010200ULL;
1286                 writeq(val64, &bar0->tx_w_round_robin_3);
1287                 val64 = 0x0102030000000000ULL;
1288                 writeq(val64, &bar0->tx_w_round_robin_4);
1289                 break;
1290         case 8:
1291                 val64 = 0x0001020300040105ULL;
1292                 writeq(val64, &bar0->tx_w_round_robin_0);
1293                 val64 = 0x0200030106000204ULL;
1294                 writeq(val64, &bar0->tx_w_round_robin_1);
1295                 val64 = 0x0103000502010007ULL;
1296                 writeq(val64, &bar0->tx_w_round_robin_2);
1297                 val64 = 0x0304010002060500ULL;
1298                 writeq(val64, &bar0->tx_w_round_robin_3);
1299                 val64 = 0x0103020400000000ULL;
1300                 writeq(val64, &bar0->tx_w_round_robin_4);
1301                 break;
1302         }
1303
1304         /* Enable all configured Tx FIFO partitions */
1305         val64 = readq(&bar0->tx_fifo_partition_0);
1306         val64 |= (TX_FIFO_PARTITION_EN);
1307         writeq(val64, &bar0->tx_fifo_partition_0);
1308
1309         /* Filling the Rx round robin registers as per the
1310          * number of Rings and steering based on QoS.
1311          */
1312         switch (config->rx_ring_num) {
1313         case 1:
1314                 val64 = 0x8080808080808080ULL;
1315                 writeq(val64, &bar0->rts_qos_steering);
1316                 break;
1317         case 2:
1318                 val64 = 0x0000010000010000ULL;
1319                 writeq(val64, &bar0->rx_w_round_robin_0);
1320                 val64 = 0x0100000100000100ULL;
1321                 writeq(val64, &bar0->rx_w_round_robin_1);
1322                 val64 = 0x0001000001000001ULL;
1323                 writeq(val64, &bar0->rx_w_round_robin_2);
1324                 val64 = 0x0000010000010000ULL;
1325                 writeq(val64, &bar0->rx_w_round_robin_3);
1326                 val64 = 0x0100000000000000ULL;
1327                 writeq(val64, &bar0->rx_w_round_robin_4);
1328
1329                 val64 = 0x8080808040404040ULL;
1330                 writeq(val64, &bar0->rts_qos_steering);
1331                 break;
1332         case 3:
1333                 val64 = 0x0001000102000001ULL;
1334                 writeq(val64, &bar0->rx_w_round_robin_0);
1335                 val64 = 0x0001020000010001ULL;
1336                 writeq(val64, &bar0->rx_w_round_robin_1);
1337                 val64 = 0x0200000100010200ULL;
1338                 writeq(val64, &bar0->rx_w_round_robin_2);
1339                 val64 = 0x0001000102000001ULL;
1340                 writeq(val64, &bar0->rx_w_round_robin_3);
1341                 val64 = 0x0001020000000000ULL;
1342                 writeq(val64, &bar0->rx_w_round_robin_4);
1343
1344                 val64 = 0x8080804040402020ULL;
1345                 writeq(val64, &bar0->rts_qos_steering);
1346                 break;
1347         case 4:
1348                 val64 = 0x0001020300010200ULL;
1349                 writeq(val64, &bar0->rx_w_round_robin_0);
1350                 val64 = 0x0100000102030001ULL;
1351                 writeq(val64, &bar0->rx_w_round_robin_1);
1352                 val64 = 0x0200010000010203ULL;
1353                 writeq(val64, &bar0->rx_w_round_robin_2);
1354                 val64 = 0x0001020001000001ULL;
1355                 writeq(val64, &bar0->rx_w_round_robin_3);
1356                 val64 = 0x0203000100000000ULL;
1357                 writeq(val64, &bar0->rx_w_round_robin_4);
1358
1359                 val64 = 0x8080404020201010ULL;
1360                 writeq(val64, &bar0->rts_qos_steering);
1361                 break;
1362         case 5:
1363                 val64 = 0x0001000203000102ULL;
1364                 writeq(val64, &bar0->rx_w_round_robin_0);
1365                 val64 = 0x0001020001030004ULL;
1366                 writeq(val64, &bar0->rx_w_round_robin_1);
1367                 val64 = 0x0001000203000102ULL;
1368                 writeq(val64, &bar0->rx_w_round_robin_2);
1369                 val64 = 0x0001020001030004ULL;
1370                 writeq(val64, &bar0->rx_w_round_robin_3);
1371                 val64 = 0x0001000000000000ULL;
1372                 writeq(val64, &bar0->rx_w_round_robin_4);
1373
1374                 val64 = 0x8080404020201008ULL;
1375                 writeq(val64, &bar0->rts_qos_steering);
1376                 break;
1377         case 6:
1378                 val64 = 0x0001020304000102ULL;
1379                 writeq(val64, &bar0->rx_w_round_robin_0);
1380                 val64 = 0x0304050001020001ULL;
1381                 writeq(val64, &bar0->rx_w_round_robin_1);
1382                 val64 = 0x0203000100000102ULL;
1383                 writeq(val64, &bar0->rx_w_round_robin_2);
1384                 val64 = 0x0304000102030405ULL;
1385                 writeq(val64, &bar0->rx_w_round_robin_3);
1386                 val64 = 0x0001000200000000ULL;
1387                 writeq(val64, &bar0->rx_w_round_robin_4);
1388
1389                 val64 = 0x8080404020100804ULL;
1390                 writeq(val64, &bar0->rts_qos_steering);
1391                 break;
1392         case 7:
1393                 val64 = 0x0001020001020300ULL;
1394                 writeq(val64, &bar0->rx_w_round_robin_0);
1395                 val64 = 0x0102030400010203ULL;
1396                 writeq(val64, &bar0->rx_w_round_robin_1);
1397                 val64 = 0x0405060001020001ULL;
1398                 writeq(val64, &bar0->rx_w_round_robin_2);
1399                 val64 = 0x0304050000010200ULL;
1400                 writeq(val64, &bar0->rx_w_round_robin_3);
1401                 val64 = 0x0102030000000000ULL;
1402                 writeq(val64, &bar0->rx_w_round_robin_4);
1403
1404                 val64 = 0x8080402010080402ULL;
1405                 writeq(val64, &bar0->rts_qos_steering);
1406                 break;
1407         case 8:
1408                 val64 = 0x0001020300040105ULL;
1409                 writeq(val64, &bar0->rx_w_round_robin_0);
1410                 val64 = 0x0200030106000204ULL;
1411                 writeq(val64, &bar0->rx_w_round_robin_1);
1412                 val64 = 0x0103000502010007ULL;
1413                 writeq(val64, &bar0->rx_w_round_robin_2);
1414                 val64 = 0x0304010002060500ULL;
1415                 writeq(val64, &bar0->rx_w_round_robin_3);
1416                 val64 = 0x0103020400000000ULL;
1417                 writeq(val64, &bar0->rx_w_round_robin_4);
1418
1419                 val64 = 0x8040201008040201ULL;
1420                 writeq(val64, &bar0->rts_qos_steering);
1421                 break;
1422         }
1423
1424         /* UDP Fix */
1425         val64 = 0;
1426         for (i = 0; i < 8; i++)
1427                 writeq(val64, &bar0->rts_frm_len_n[i]);
1428
1429         /* Set the default rts frame length for the rings configured */
1430         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1431         for (i = 0 ; i < config->rx_ring_num ; i++)
1432                 writeq(val64, &bar0->rts_frm_len_n[i]);
1433
1434         /* Set the frame length for the configured rings
1435          * desired by the user
1436          */
1437         for (i = 0; i < config->rx_ring_num; i++) {
1438                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1439                  * specified frame length steering.
1440                  * If the user provides the frame length then program
1441                  * the rts_frm_len register for those values or else
1442                  * leave it as it is.
1443                  */
1444                 if (rts_frm_len[i] != 0) {
1445                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1446                                 &bar0->rts_frm_len_n[i]);
1447                 }
1448         }
1449
1450         /* Disable differentiated services steering logic */
1451         for (i = 0; i < 64; i++) {
1452                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1453                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1454                                 dev->name);
1455                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1456                         return FAILURE;
1457                 }
1458         }
1459
1460         /* Program statistics memory */
1461         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1462
1463         if (nic->device_type == XFRAME_II_DEVICE) {
1464                 val64 = STAT_BC(0x320);
1465                 writeq(val64, &bar0->stat_byte_cnt);
1466         }
1467
1468         /*
1469          * Initializing the sampling rate for the device to calculate the
1470          * bandwidth utilization.
1471          */
1472         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1473             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1474         writeq(val64, &bar0->mac_link_util);
1475
1476
1477         /*
1478          * Initializing the Transmit and Receive Traffic Interrupt
1479          * Scheme.
1480          */
1481         /*
1482          * TTI Initialization. Default Tx timer gets us about
1483          * 250 interrupts per sec. Continuous interrupts are enabled
1484          * by default.
1485          */
1486         if (nic->device_type == XFRAME_II_DEVICE) {
1487                 int count = (nic->config.bus_speed * 125)/2;
1488                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1489         } else {
1490
1491                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1492         }
1493         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1494             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1495             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1496                 if (use_continuous_tx_intrs)
1497                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1498         writeq(val64, &bar0->tti_data1_mem);
1499
1500         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1501             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1502             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1503         writeq(val64, &bar0->tti_data2_mem);
1504
1505         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1506         writeq(val64, &bar0->tti_command_mem);
1507
1508         /*
1509          * Once the operation completes, the Strobe bit of the command
1510          * register will be reset. We poll for this particular condition
1511          * We wait for a maximum of 500ms for the operation to complete,
1512          * if it's not complete by then we return error.
1513          */
1514         time = 0;
1515         while (TRUE) {
1516                 val64 = readq(&bar0->tti_command_mem);
1517                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1518                         break;
1519                 }
1520                 if (time > 10) {
1521                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1522                                   dev->name);
1523                         return -1;
1524                 }
1525                 msleep(50);
1526                 time++;
1527         }
1528
1529         if (nic->config.bimodal) {
1530                 int k = 0;
1531                 for (k = 0; k < config->rx_ring_num; k++) {
1532                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1533                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1534                         writeq(val64, &bar0->tti_command_mem);
1535
1536                 /*
1537                  * Once the operation completes, the Strobe bit of the command
1538                  * register will be reset. We poll for this particular condition
1539                  * We wait for a maximum of 500ms for the operation to complete,
1540                  * if it's not complete by then we return error.
1541                 */
1542                         time = 0;
1543                         while (TRUE) {
1544                                 val64 = readq(&bar0->tti_command_mem);
1545                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1546                                         break;
1547                                 }
1548                                 if (time > 10) {
1549                                         DBG_PRINT(ERR_DBG,
1550                                                 "%s: TTI init Failed\n",
1551                                         dev->name);
1552                                         return -1;
1553                                 }
1554                                 time++;
1555                                 msleep(50);
1556                         }
1557                 }
1558         } else {
1559
1560                 /* RTI Initialization */
1561                 if (nic->device_type == XFRAME_II_DEVICE) {
1562                         /*
1563                          * Programmed to generate Apprx 500 Intrs per
1564                          * second
1565                          */
1566                         int count = (nic->config.bus_speed * 125)/4;
1567                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1568                 } else {
1569                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1570                 }
1571                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1572                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1573                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1574
1575                 writeq(val64, &bar0->rti_data1_mem);
1576
1577                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1578                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1579                 if (nic->intr_type == MSI_X)
1580                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1581                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1582                 else
1583                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1584                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1585                 writeq(val64, &bar0->rti_data2_mem);
1586
1587                 for (i = 0; i < config->rx_ring_num; i++) {
1588                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1589                                         | RTI_CMD_MEM_OFFSET(i);
1590                         writeq(val64, &bar0->rti_command_mem);
1591
1592                         /*
1593                          * Once the operation completes, the Strobe bit of the
1594                          * command register will be reset. We poll for this
1595                          * particular condition. We wait for a maximum of 500ms
1596                          * for the operation to complete, if it's not complete
1597                          * by then we return error.
1598                          */
1599                         time = 0;
1600                         while (TRUE) {
1601                                 val64 = readq(&bar0->rti_command_mem);
1602                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1603                                         break;
1604                                 }
1605                                 if (time > 10) {
1606                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1607                                                   dev->name);
1608                                         return -1;
1609                                 }
1610                                 time++;
1611                                 msleep(50);
1612                         }
1613                 }
1614         }
1615
1616         /*
1617          * Initializing proper values as Pause threshold into all
1618          * the 8 Queues on Rx side.
1619          */
1620         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1621         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1622
1623         /* Disable RMAC PAD STRIPPING */
1624         add = &bar0->mac_cfg;
1625         val64 = readq(&bar0->mac_cfg);
1626         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1627         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1628         writel((u32) (val64), add);
1629         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1630         writel((u32) (val64 >> 32), (add + 4));
1631         val64 = readq(&bar0->mac_cfg);
1632
1633         /* Enable FCS stripping by adapter */
1634         add = &bar0->mac_cfg;
1635         val64 = readq(&bar0->mac_cfg);
1636         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1637         if (nic->device_type == XFRAME_II_DEVICE)
1638                 writeq(val64, &bar0->mac_cfg);
1639         else {
1640                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1641                 writel((u32) (val64), add);
1642                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1643                 writel((u32) (val64 >> 32), (add + 4));
1644         }
1645
1646         /*
1647          * Set the time value to be inserted in the pause frame
1648          * generated by xena.
1649          */
1650         val64 = readq(&bar0->rmac_pause_cfg);
1651         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1652         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1653         writeq(val64, &bar0->rmac_pause_cfg);
1654
1655         /*
1656          * Set the Threshold Limit for Generating the pause frame
1657          * If the amount of data in any Queue exceeds ratio of
1658          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1659          * pause frame is generated
1660          */
1661         val64 = 0;
1662         for (i = 0; i < 4; i++) {
1663                 val64 |=
1664                     (((u64) 0xFF00 | nic->mac_control.
1665                       mc_pause_threshold_q0q3)
1666                      << (i * 2 * 8));
1667         }
1668         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1669
1670         val64 = 0;
1671         for (i = 0; i < 4; i++) {
1672                 val64 |=
1673                     (((u64) 0xFF00 | nic->mac_control.
1674                       mc_pause_threshold_q4q7)
1675                      << (i * 2 * 8));
1676         }
1677         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1678
1679         /*
1680          * TxDMA will stop Read request if the number of read split has
1681          * exceeded the limit pointed by shared_splits
1682          */
1683         val64 = readq(&bar0->pic_control);
1684         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1685         writeq(val64, &bar0->pic_control);
1686
1687         if (nic->config.bus_speed == 266) {
1688                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1689                 writeq(0x0, &bar0->read_retry_delay);
1690                 writeq(0x0, &bar0->write_retry_delay);
1691         }
1692
1693         /*
1694          * Programming the Herc to split every write transaction
1695          * that does not start on an ADB to reduce disconnects.
1696          */
1697         if (nic->device_type == XFRAME_II_DEVICE) {
1698                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1699                         MISC_LINK_STABILITY_PRD(3);
1700                 writeq(val64, &bar0->misc_control);
1701                 val64 = readq(&bar0->pic_control2);
1702                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1703                 writeq(val64, &bar0->pic_control2);
1704         }
1705         if (strstr(nic->product_name, "CX4")) {
1706                 val64 = TMAC_AVG_IPG(0x17);
1707                 writeq(val64, &bar0->tmac_avg_ipg);
1708         }
1709
1710         return SUCCESS;
1711 }
1712 #define LINK_UP_DOWN_INTERRUPT          1
1713 #define MAC_RMAC_ERR_TIMER              2
1714
1715 static int s2io_link_fault_indication(struct s2io_nic *nic)
1716 {
1717         if (nic->intr_type != INTA)
1718                 return MAC_RMAC_ERR_TIMER;
1719         if (nic->device_type == XFRAME_II_DEVICE)
1720                 return LINK_UP_DOWN_INTERRUPT;
1721         else
1722                 return MAC_RMAC_ERR_TIMER;
1723 }
1724
1725 /**
1726  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1727  *  @nic: device private variable,
1728  *  @mask: A mask indicating which Intr block must be modified and,
1729  *  @flag: A flag indicating whether to enable or disable the Intrs.
1730  *  Description: This function will either disable or enable the interrupts
1731  *  depending on the flag argument. The mask argument can be used to
1732  *  enable/disable any Intr block.
1733  *  Return Value: NONE.
1734  */
1735
1736 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1737 {
1738         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1739         register u64 val64 = 0, temp64 = 0;
1740
1741         /*  Top level interrupt classification */
1742         /*  PIC Interrupts */
1743         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1744                 /*  Enable PIC Intrs in the general intr mask register */
1745                 val64 = TXPIC_INT_M;
1746                 if (flag == ENABLE_INTRS) {
1747                         temp64 = readq(&bar0->general_int_mask);
1748                         temp64 &= ~((u64) val64);
1749                         writeq(temp64, &bar0->general_int_mask);
1750                         /*
1751                          * If Hercules adapter enable GPIO otherwise
1752                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1753                          * interrupts for now.
1754                          * TODO
1755                          */
1756                         if (s2io_link_fault_indication(nic) ==
1757                                         LINK_UP_DOWN_INTERRUPT ) {
1758                                 temp64 = readq(&bar0->pic_int_mask);
1759                                 temp64 &= ~((u64) PIC_INT_GPIO);
1760                                 writeq(temp64, &bar0->pic_int_mask);
1761                                 temp64 = readq(&bar0->gpio_int_mask);
1762                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1763                                 writeq(temp64, &bar0->gpio_int_mask);
1764                         } else {
1765                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1766                         }
1767                         /*
1768                          * No MSI Support is available presently, so TTI and
1769                          * RTI interrupts are also disabled.
1770                          */
1771                 } else if (flag == DISABLE_INTRS) {
1772                         /*
1773                          * Disable PIC Intrs in the general
1774                          * intr mask register
1775                          */
1776                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1777                         temp64 = readq(&bar0->general_int_mask);
1778                         val64 |= temp64;
1779                         writeq(val64, &bar0->general_int_mask);
1780                 }
1781         }
1782
1783         /*  MAC Interrupts */
1784         /*  Enabling/Disabling MAC interrupts */
1785         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1786                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1787                 if (flag == ENABLE_INTRS) {
1788                         temp64 = readq(&bar0->general_int_mask);
1789                         temp64 &= ~((u64) val64);
1790                         writeq(temp64, &bar0->general_int_mask);
1791                         /*
1792                          * All MAC block error interrupts are disabled for now
1793                          * TODO
1794                          */
1795                 } else if (flag == DISABLE_INTRS) {
1796                         /*
1797                          * Disable MAC Intrs in the general intr mask register
1798                          */
1799                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1800                         writeq(DISABLE_ALL_INTRS,
1801                                &bar0->mac_rmac_err_mask);
1802
1803                         temp64 = readq(&bar0->general_int_mask);
1804                         val64 |= temp64;
1805                         writeq(val64, &bar0->general_int_mask);
1806                 }
1807         }
1808
1809         /*  Tx traffic interrupts */
1810         if (mask & TX_TRAFFIC_INTR) {
1811                 val64 = TXTRAFFIC_INT_M;
1812                 if (flag == ENABLE_INTRS) {
1813                         temp64 = readq(&bar0->general_int_mask);
1814                         temp64 &= ~((u64) val64);
1815                         writeq(temp64, &bar0->general_int_mask);
1816                         /*
1817                          * Enable all the Tx side interrupts
1818                          * writing 0 Enables all 64 TX interrupt levels
1819                          */
1820                         writeq(0x0, &bar0->tx_traffic_mask);
1821                 } else if (flag == DISABLE_INTRS) {
1822                         /*
1823                          * Disable Tx Traffic Intrs in the general intr mask
1824                          * register.
1825                          */
1826                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1827                         temp64 = readq(&bar0->general_int_mask);
1828                         val64 |= temp64;
1829                         writeq(val64, &bar0->general_int_mask);
1830                 }
1831         }
1832
1833         /*  Rx traffic interrupts */
1834         if (mask & RX_TRAFFIC_INTR) {
1835                 val64 = RXTRAFFIC_INT_M;
1836                 if (flag == ENABLE_INTRS) {
1837                         temp64 = readq(&bar0->general_int_mask);
1838                         temp64 &= ~((u64) val64);
1839                         writeq(temp64, &bar0->general_int_mask);
1840                         /* writing 0 Enables all 8 RX interrupt levels */
1841                         writeq(0x0, &bar0->rx_traffic_mask);
1842                 } else if (flag == DISABLE_INTRS) {
1843                         /*
1844                          * Disable Rx Traffic Intrs in the general intr mask
1845                          * register.
1846                          */
1847                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1848                         temp64 = readq(&bar0->general_int_mask);
1849                         val64 |= temp64;
1850                         writeq(val64, &bar0->general_int_mask);
1851                 }
1852         }
1853 }
1854
1855 /**
1856  *  verify_pcc_quiescent- Checks for PCC quiescent state
1857  *  Return: 1 If PCC is quiescence
1858  *          0 If PCC is not quiescence
1859  */
1860 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1861 {
1862         int ret = 0, herc;
1863         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1864         u64 val64 = readq(&bar0->adapter_status);
1865
1866         herc = (sp->device_type == XFRAME_II_DEVICE);
1867
1868         if (flag == FALSE) {
1869                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1870                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1871                                 ret = 1;
1872                 } else {
1873                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1874                                 ret = 1;
1875                 }
1876         } else {
1877                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1878                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1879                              ADAPTER_STATUS_RMAC_PCC_IDLE))
1880                                 ret = 1;
1881                 } else {
1882                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1883                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1884                                 ret = 1;
1885                 }
1886         }
1887
1888         return ret;
1889 }
1890 /**
1891  *  verify_xena_quiescence - Checks whether the H/W is ready
1892  *  Description: Returns whether the H/W is ready to go or not. Depending
1893  *  on whether adapter enable bit was written or not the comparison
1894  *  differs and the calling function passes the input argument flag to
1895  *  indicate this.
1896  *  Return: 1 If xena is quiescence
1897  *          0 If Xena is not quiescence
1898  */
1899
1900 static int verify_xena_quiescence(struct s2io_nic *sp)
1901 {
1902         int  mode;
1903         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1904         u64 val64 = readq(&bar0->adapter_status);
1905         mode = s2io_verify_pci_mode(sp);
1906
1907         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1908                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1909                 return 0;
1910         }
1911         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1912         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1913                 return 0;
1914         }
1915         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1916                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1917                 return 0;
1918         }
1919         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1920                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1921                 return 0;
1922         }
1923         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1924                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1925                 return 0;
1926         }
1927         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1928                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1929                 return 0;
1930         }
1931         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1932                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1933                 return 0;
1934         }
1935         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1936                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1937                 return 0;
1938         }
1939
1940         /*
1941          * In PCI 33 mode, the P_PLL is not used, and therefore,
1942          * the the P_PLL_LOCK bit in the adapter_status register will
1943          * not be asserted.
1944          */
1945         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1946                 sp->device_type == XFRAME_II_DEVICE && mode !=
1947                 PCI_MODE_PCI_33) {
1948                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1949                 return 0;
1950         }
1951         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1952                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1953                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1954                 return 0;
1955         }
1956         return 1;
1957 }
1958
1959 /**
1960  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1961  * @sp: Pointer to device specifc structure
1962  * Description :
1963  * New procedure to clear mac address reading  problems on Alpha platforms
1964  *
1965  */
1966
1967 static void fix_mac_address(struct s2io_nic * sp)
1968 {
1969         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1970         u64 val64;
1971         int i = 0;
1972
1973         while (fix_mac[i] != END_SIGN) {
1974                 writeq(fix_mac[i++], &bar0->gpio_control);
1975                 udelay(10);
1976                 val64 = readq(&bar0->gpio_control);
1977         }
1978 }
1979
1980 /**
1981  *  start_nic - Turns the device on
1982  *  @nic : device private variable.
1983  *  Description:
1984  *  This function actually turns the device on. Before this  function is
1985  *  called,all Registers are configured from their reset states
1986  *  and shared memory is allocated but the NIC is still quiescent. On
1987  *  calling this function, the device interrupts are cleared and the NIC is
1988  *  literally switched on by writing into the adapter control register.
1989  *  Return Value:
1990  *  SUCCESS on success and -1 on failure.
1991  */
1992
1993 static int start_nic(struct s2io_nic *nic)
1994 {
1995         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1996         struct net_device *dev = nic->dev;
1997         register u64 val64 = 0;
1998         u16 subid, i;
1999         struct mac_info *mac_control;
2000         struct config_param *config;
2001
2002         mac_control = &nic->mac_control;
2003         config = &nic->config;
2004
2005         /*  PRC Initialization and configuration */
2006         for (i = 0; i < config->rx_ring_num; i++) {
2007                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2008                        &bar0->prc_rxd0_n[i]);
2009
2010                 val64 = readq(&bar0->prc_ctrl_n[i]);
2011                 if (nic->config.bimodal)
2012                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2013                 if (nic->rxd_mode == RXD_MODE_1)
2014                         val64 |= PRC_CTRL_RC_ENABLED;
2015                 else
2016                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2017                 if (nic->device_type == XFRAME_II_DEVICE)
2018                         val64 |= PRC_CTRL_GROUP_READS;
2019                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2020                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2021                 writeq(val64, &bar0->prc_ctrl_n[i]);
2022         }
2023
2024         if (nic->rxd_mode == RXD_MODE_3B) {
2025                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2026                 val64 = readq(&bar0->rx_pa_cfg);
2027                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2028                 writeq(val64, &bar0->rx_pa_cfg);
2029         }
2030
2031         if (vlan_tag_strip == 0) {
2032                 val64 = readq(&bar0->rx_pa_cfg);
2033                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2034                 writeq(val64, &bar0->rx_pa_cfg);
2035                 vlan_strip_flag = 0;
2036         }
2037
2038         /*
2039          * Enabling MC-RLDRAM. After enabling the device, we timeout
2040          * for around 100ms, which is approximately the time required
2041          * for the device to be ready for operation.
2042          */
2043         val64 = readq(&bar0->mc_rldram_mrs);
2044         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2045         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2046         val64 = readq(&bar0->mc_rldram_mrs);
2047
2048         msleep(100);    /* Delay by around 100 ms. */
2049
2050         /* Enabling ECC Protection. */
2051         val64 = readq(&bar0->adapter_control);
2052         val64 &= ~ADAPTER_ECC_EN;
2053         writeq(val64, &bar0->adapter_control);
2054
2055         /*
2056          * Clearing any possible Link state change interrupts that
2057          * could have popped up just before Enabling the card.
2058          */
2059         val64 = readq(&bar0->mac_rmac_err_reg);
2060         if (val64)
2061                 writeq(val64, &bar0->mac_rmac_err_reg);
2062
2063         /*
2064          * Verify if the device is ready to be enabled, if so enable
2065          * it.
2066          */
2067         val64 = readq(&bar0->adapter_status);
2068         if (!verify_xena_quiescence(nic)) {
2069                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2070                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2071                           (unsigned long long) val64);
2072                 return FAILURE;
2073         }
2074
2075         /*
2076          * With some switches, link might be already up at this point.
2077          * Because of this weird behavior, when we enable laser,
2078          * we may not get link. We need to handle this. We cannot
2079          * figure out which switch is misbehaving. So we are forced to
2080          * make a global change.
2081          */
2082
2083         /* Enabling Laser. */
2084         val64 = readq(&bar0->adapter_control);
2085         val64 |= ADAPTER_EOI_TX_ON;
2086         writeq(val64, &bar0->adapter_control);
2087
2088         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2089                 /*
2090                  * Dont see link state interrupts initally on some switches,
2091                  * so directly scheduling the link state task here.
2092                  */
2093                 schedule_work(&nic->set_link_task);
2094         }
2095         /* SXE-002: Initialize link and activity LED */
2096         subid = nic->pdev->subsystem_device;
2097         if (((subid & 0xFF) >= 0x07) &&
2098             (nic->device_type == XFRAME_I_DEVICE)) {
2099                 val64 = readq(&bar0->gpio_control);
2100                 val64 |= 0x0000800000000000ULL;
2101                 writeq(val64, &bar0->gpio_control);
2102                 val64 = 0x0411040400000000ULL;
2103                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2104         }
2105
2106         return SUCCESS;
2107 }
2108 /**
2109  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2110  */
2111 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2112                                         TxD *txdlp, int get_off)
2113 {
2114         struct s2io_nic *nic = fifo_data->nic;
2115         struct sk_buff *skb;
2116         struct TxD *txds;
2117         u16 j, frg_cnt;
2118
2119         txds = txdlp;
2120         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2121                 pci_unmap_single(nic->pdev, (dma_addr_t)
2122                         txds->Buffer_Pointer, sizeof(u64),
2123                         PCI_DMA_TODEVICE);
2124                 txds++;
2125         }
2126
2127         skb = (struct sk_buff *) ((unsigned long)
2128                         txds->Host_Control);
2129         if (!skb) {
2130                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2131                 return NULL;
2132         }
2133         pci_unmap_single(nic->pdev, (dma_addr_t)
2134                          txds->Buffer_Pointer,
2135                          skb->len - skb->data_len,
2136                          PCI_DMA_TODEVICE);
2137         frg_cnt = skb_shinfo(skb)->nr_frags;
2138         if (frg_cnt) {
2139                 txds++;
2140                 for (j = 0; j < frg_cnt; j++, txds++) {
2141                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2142                         if (!txds->Buffer_Pointer)
2143                                 break;
2144                         pci_unmap_page(nic->pdev, (dma_addr_t)
2145                                         txds->Buffer_Pointer,
2146                                        frag->size, PCI_DMA_TODEVICE);
2147                 }
2148         }
2149         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2150         return(skb);
2151 }
2152
2153 /**
2154  *  free_tx_buffers - Free all queued Tx buffers
2155  *  @nic : device private variable.
2156  *  Description:
2157  *  Free all queued Tx buffers.
2158  *  Return Value: void
2159 */
2160
2161 static void free_tx_buffers(struct s2io_nic *nic)
2162 {
2163         struct net_device *dev = nic->dev;
2164         struct sk_buff *skb;
2165         struct TxD *txdp;
2166         int i, j;
2167         struct mac_info *mac_control;
2168         struct config_param *config;
2169         int cnt = 0;
2170
2171         mac_control = &nic->mac_control;
2172         config = &nic->config;
2173
2174         for (i = 0; i < config->tx_fifo_num; i++) {
2175                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2176                         txdp = (struct TxD *) \
2177                         mac_control->fifos[i].list_info[j].list_virt_addr;
2178                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2179                         if (skb) {
2180                                 nic->mac_control.stats_info->sw_stat.mem_freed
2181                                         += skb->truesize;
2182                                 dev_kfree_skb(skb);
2183                                 cnt++;
2184                         }
2185                 }
2186                 DBG_PRINT(INTR_DBG,
2187                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2188                           dev->name, cnt, i);
2189                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2190                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2191         }
2192 }
2193
2194 /**
2195  *   stop_nic -  To stop the nic
2196  *   @nic ; device private variable.
2197  *   Description:
2198  *   This function does exactly the opposite of what the start_nic()
2199  *   function does. This function is called to stop the device.
2200  *   Return Value:
2201  *   void.
2202  */
2203
2204 static void stop_nic(struct s2io_nic *nic)
2205 {
2206         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2207         register u64 val64 = 0;
2208         u16 interruptible;
2209         struct mac_info *mac_control;
2210         struct config_param *config;
2211
2212         mac_control = &nic->mac_control;
2213         config = &nic->config;
2214
2215         /*  Disable all interrupts */
2216         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2217         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2218         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2219         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2220
2221         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2222         val64 = readq(&bar0->adapter_control);
2223         val64 &= ~(ADAPTER_CNTL_EN);
2224         writeq(val64, &bar0->adapter_control);
2225 }
2226
2227 static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2228                                 sk_buff *skb)
2229 {
2230         struct net_device *dev = nic->dev;
2231         struct sk_buff *frag_list;
2232         void *tmp;
2233
2234         /* Buffer-1 receives L3/L4 headers */
2235         ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
2236                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2237                         PCI_DMA_FROMDEVICE);
2238
2239         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2240         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2241         if (skb_shinfo(skb)->frag_list == NULL) {
2242                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
2243                 DBG_PRINT(INFO_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2244                 return -ENOMEM ;
2245         }
2246         frag_list = skb_shinfo(skb)->frag_list;
2247         skb->truesize += frag_list->truesize;
2248         nic->mac_control.stats_info->sw_stat.mem_allocated
2249                 += frag_list->truesize;
2250         frag_list->next = NULL;
2251         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2252         frag_list->data = tmp;
2253         skb_reset_tail_pointer(frag_list);
2254
2255         /* Buffer-2 receives L4 data payload */
2256         ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2257                                 frag_list->data, dev->mtu,
2258                                 PCI_DMA_FROMDEVICE);
2259         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2260         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2261
2262         return SUCCESS;
2263 }
2264
2265 /**
2266  *  fill_rx_buffers - Allocates the Rx side skbs
2267  *  @nic:  device private variable
2268  *  @ring_no: ring number
2269  *  Description:
2270  *  The function allocates Rx side skbs and puts the physical
2271  *  address of these buffers into the RxD buffer pointers, so that the NIC
2272  *  can DMA the received frame into these locations.
2273  *  The NIC supports 3 receive modes, viz
2274  *  1. single buffer,
2275  *  2. three buffer and
2276  *  3. Five buffer modes.
2277  *  Each mode defines how many fragments the received frame will be split
2278  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2279  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2280  *  is split into 3 fragments. As of now only single buffer mode is
2281  *  supported.
2282  *   Return Value:
2283  *  SUCCESS on success or an appropriate -ve value on failure.
2284  */
2285
2286 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2287 {
2288         struct net_device *dev = nic->dev;
2289         struct sk_buff *skb;
2290         struct RxD_t *rxdp;
2291         int off, off1, size, block_no, block_no1;
2292         u32 alloc_tab = 0;
2293         u32 alloc_cnt;
2294         struct mac_info *mac_control;
2295         struct config_param *config;
2296         u64 tmp;
2297         struct buffAdd *ba;
2298         unsigned long flags;
2299         struct RxD_t *first_rxdp = NULL;
2300         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2301
2302         mac_control = &nic->mac_control;
2303         config = &nic->config;
2304         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2305             atomic_read(&nic->rx_bufs_left[ring_no]);
2306
2307         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2308         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2309         while (alloc_tab < alloc_cnt) {
2310                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2311                     block_index;
2312                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2313
2314                 rxdp = mac_control->rings[ring_no].
2315                                 rx_blocks[block_no].rxds[off].virt_addr;
2316
2317                 if ((block_no == block_no1) && (off == off1) &&
2318                                         (rxdp->Host_Control)) {
2319                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2320                                   dev->name);
2321                         DBG_PRINT(INTR_DBG, " info equated\n");
2322                         goto end;
2323                 }
2324                 if (off && (off == rxd_count[nic->rxd_mode])) {
2325                         mac_control->rings[ring_no].rx_curr_put_info.
2326                             block_index++;
2327                         if (mac_control->rings[ring_no].rx_curr_put_info.
2328                             block_index == mac_control->rings[ring_no].
2329                                         block_count)
2330                                 mac_control->rings[ring_no].rx_curr_put_info.
2331                                         block_index = 0;
2332                         block_no = mac_control->rings[ring_no].
2333                                         rx_curr_put_info.block_index;
2334                         if (off == rxd_count[nic->rxd_mode])
2335                                 off = 0;
2336                         mac_control->rings[ring_no].rx_curr_put_info.
2337                                 offset = off;
2338                         rxdp = mac_control->rings[ring_no].
2339                                 rx_blocks[block_no].block_virt_addr;
2340                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2341                                   dev->name, rxdp);
2342                 }
2343                 if(!napi) {
2344                         spin_lock_irqsave(&nic->put_lock, flags);
2345                         mac_control->rings[ring_no].put_pos =
2346                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2347                         spin_unlock_irqrestore(&nic->put_lock, flags);
2348                 } else {
2349                         mac_control->rings[ring_no].put_pos =
2350                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2351                 }
2352                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2353                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2354                                 (rxdp->Control_2 & BIT(0)))) {
2355                         mac_control->rings[ring_no].rx_curr_put_info.
2356                                         offset = off;
2357                         goto end;
2358                 }
2359                 /* calculate size of skb based on ring mode */
2360                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2361                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2362                 if (nic->rxd_mode == RXD_MODE_1)
2363                         size += NET_IP_ALIGN;
2364                 else if (nic->rxd_mode == RXD_MODE_3B)
2365                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2366                 else
2367                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2368
2369                 /* allocate skb */
2370                 skb = dev_alloc_skb(size);
2371                 if(!skb) {
2372                         DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2373                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2374                         if (first_rxdp) {
2375                                 wmb();
2376                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2377                         }
2378                         nic->mac_control.stats_info->sw_stat. \
2379                                 mem_alloc_fail_cnt++;
2380                         return -ENOMEM ;
2381                 }
2382                 nic->mac_control.stats_info->sw_stat.mem_allocated
2383                         += skb->truesize;
2384                 if (nic->rxd_mode == RXD_MODE_1) {
2385                         /* 1 buffer mode - normal operation mode */
2386                         memset(rxdp, 0, sizeof(struct RxD1));
2387                         skb_reserve(skb, NET_IP_ALIGN);
2388                         ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
2389                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2390                                 PCI_DMA_FROMDEVICE);
2391                         rxdp->Control_2 =
2392                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2393
2394                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2395                         /*
2396                          * 2 or 3 buffer mode -
2397                          * Both 2 buffer mode and 3 buffer mode provides 128
2398                          * byte aligned receive buffers.
2399                          *
2400                          * 3 buffer mode provides header separation where in
2401                          * skb->data will have L3/L4 headers where as
2402                          * skb_shinfo(skb)->frag_list will have the L4 data
2403                          * payload
2404                          */
2405
2406                         /* save buffer pointers to avoid frequent dma mapping */
2407                         Buffer0_ptr = ((struct RxD3*)rxdp)->Buffer0_ptr;
2408                         Buffer1_ptr = ((struct RxD3*)rxdp)->Buffer1_ptr;
2409                         memset(rxdp, 0, sizeof(struct RxD3));
2410                         /* restore the buffer pointers for dma sync*/
2411                         ((struct RxD3*)rxdp)->Buffer0_ptr = Buffer0_ptr;
2412                         ((struct RxD3*)rxdp)->Buffer1_ptr = Buffer1_ptr;
2413
2414                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2415                         skb_reserve(skb, BUF0_LEN);
2416                         tmp = (u64)(unsigned long) skb->data;
2417                         tmp += ALIGN_SIZE;
2418                         tmp &= ~ALIGN_SIZE;
2419                         skb->data = (void *) (unsigned long)tmp;
2420                         skb_reset_tail_pointer(skb);
2421
2422                         if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2423                                 ((struct RxD3*)rxdp)->Buffer0_ptr =
2424                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2425                                            PCI_DMA_FROMDEVICE);
2426                         else
2427                                 pci_dma_sync_single_for_device(nic->pdev,
2428                                 (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
2429                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2430                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2431                         if (nic->rxd_mode == RXD_MODE_3B) {
2432                                 /* Two buffer mode */
2433
2434                                 /*
2435                                  * Buffer2 will have L3/L4 header plus
2436                                  * L4 payload
2437                                  */
2438                                 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
2439                                 (nic->pdev, skb->data, dev->mtu + 4,
2440                                                 PCI_DMA_FROMDEVICE);
2441
2442                                 /* Buffer-1 will be dummy buffer. Not used */
2443                                 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2444                                         ((struct RxD3*)rxdp)->Buffer1_ptr =
2445                                                 pci_map_single(nic->pdev,
2446                                                 ba->ba_1, BUF1_LEN,
2447                                                 PCI_DMA_FROMDEVICE);
2448                                 }
2449                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2450                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2451                                                                 (dev->mtu + 4);
2452                         } else {
2453                                 /* 3 buffer mode */
2454                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2455                                         nic->mac_control.stats_info->sw_stat.\
2456                                         mem_freed += skb->truesize;
2457                                         dev_kfree_skb_irq(skb);
2458                                         if (first_rxdp) {
2459                                                 wmb();
2460                                                 first_rxdp->Control_1 |=
2461                                                         RXD_OWN_XENA;
2462                                         }
2463                                         return -ENOMEM ;
2464                                 }
2465                         }
2466                         rxdp->Control_2 |= BIT(0);
2467                 }
2468                 rxdp->Host_Control = (unsigned long) (skb);
2469                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2470                         rxdp->Control_1 |= RXD_OWN_XENA;
2471                 off++;
2472                 if (off == (rxd_count[nic->rxd_mode] + 1))
2473                         off = 0;
2474                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2475
2476                 rxdp->Control_2 |= SET_RXD_MARKER;
2477                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2478                         if (first_rxdp) {
2479                                 wmb();
2480                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2481                         }
2482                         first_rxdp = rxdp;
2483                 }
2484                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2485                 alloc_tab++;
2486         }
2487
2488       end:
2489         /* Transfer ownership of first descriptor to adapter just before
2490          * exiting. Before that, use memory barrier so that ownership
2491          * and other fields are seen by adapter correctly.
2492          */
2493         if (first_rxdp) {
2494                 wmb();
2495                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2496         }
2497
2498         return SUCCESS;
2499 }
2500
2501 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2502 {
2503         struct net_device *dev = sp->dev;
2504         int j;
2505         struct sk_buff *skb;
2506         struct RxD_t *rxdp;
2507         struct mac_info *mac_control;
2508         struct buffAdd *ba;
2509
2510         mac_control = &sp->mac_control;
2511         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2512                 rxdp = mac_control->rings[ring_no].
2513                                 rx_blocks[blk].rxds[j].virt_addr;
2514                 skb = (struct sk_buff *)
2515                         ((unsigned long) rxdp->Host_Control);
2516                 if (!skb) {
2517                         continue;
2518                 }
2519                 if (sp->rxd_mode == RXD_MODE_1) {
2520                         pci_unmap_single(sp->pdev, (dma_addr_t)
2521                                  ((struct RxD1*)rxdp)->Buffer0_ptr,
2522                                  dev->mtu +
2523                                  HEADER_ETHERNET_II_802_3_SIZE
2524                                  + HEADER_802_2_SIZE +
2525                                  HEADER_SNAP_SIZE,
2526                                  PCI_DMA_FROMDEVICE);
2527                         memset(rxdp, 0, sizeof(struct RxD1));
2528                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2529                         ba = &mac_control->rings[ring_no].
2530                                 ba[blk][j];
2531                         pci_unmap_single(sp->pdev, (dma_addr_t)
2532                                  ((struct RxD3*)rxdp)->Buffer0_ptr,
2533                                  BUF0_LEN,
2534                                  PCI_DMA_FROMDEVICE);
2535                         pci_unmap_single(sp->pdev, (dma_addr_t)
2536                                  ((struct RxD3*)rxdp)->Buffer1_ptr,
2537                                  BUF1_LEN,
2538                                  PCI_DMA_FROMDEVICE);
2539                         pci_unmap_single(sp->pdev, (dma_addr_t)
2540                                  ((struct RxD3*)rxdp)->Buffer2_ptr,
2541                                  dev->mtu + 4,
2542                                  PCI_DMA_FROMDEVICE);
2543                         memset(rxdp, 0, sizeof(struct RxD3));
2544                 } else {
2545                         pci_unmap_single(sp->pdev, (dma_addr_t)
2546                                 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2547                                 PCI_DMA_FROMDEVICE);
2548                         pci_unmap_single(sp->pdev, (dma_addr_t)
2549                                 ((struct RxD3*)rxdp)->Buffer1_ptr,
2550                                 l3l4hdr_size + 4,
2551                                 PCI_DMA_FROMDEVICE);
2552                         pci_unmap_single(sp->pdev, (dma_addr_t)
2553                                 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
2554                                 PCI_DMA_FROMDEVICE);
2555                         memset(rxdp, 0, sizeof(struct RxD3));
2556                 }
2557                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2558                 dev_kfree_skb(skb);
2559                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2560         }
2561 }
2562
2563 /**
2564  *  free_rx_buffers - Frees all Rx buffers
2565  *  @sp: device private variable.
2566  *  Description:
2567  *  This function will free all Rx buffers allocated by host.
2568  *  Return Value:
2569  *  NONE.
2570  */
2571
2572 static void free_rx_buffers(struct s2io_nic *sp)
2573 {
2574         struct net_device *dev = sp->dev;
2575         int i, blk = 0, buf_cnt = 0;
2576         struct mac_info *mac_control;
2577         struct config_param *config;
2578
2579         mac_control = &sp->mac_control;
2580         config = &sp->config;
2581
2582         for (i = 0; i < config->rx_ring_num; i++) {
2583                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2584                         free_rxd_blk(sp,i,blk);
2585
2586                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2587                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2588                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2589                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2590                 atomic_set(&sp->rx_bufs_left[i], 0);
2591                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2592                           dev->name, buf_cnt, i);
2593         }
2594 }
2595
2596 /**
2597  * s2io_poll - Rx interrupt handler for NAPI support
2598  * @dev : pointer to the device structure.
2599  * @budget : The number of packets that were budgeted to be processed
2600  * during  one pass through the 'Poll" function.
2601  * Description:
2602  * Comes into picture only if NAPI support has been incorporated. It does
2603  * the same thing that rx_intr_handler does, but not in a interrupt context
2604  * also It will process only a given number of packets.
2605  * Return value:
2606  * 0 on success and 1 if there are No Rx packets to be processed.
2607  */
2608
2609 static int s2io_poll(struct net_device *dev, int *budget)
2610 {
2611         struct s2io_nic *nic = dev->priv;
2612         int pkt_cnt = 0, org_pkts_to_process;
2613         struct mac_info *mac_control;
2614         struct config_param *config;
2615         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2616         int i;
2617
2618         atomic_inc(&nic->isr_cnt);
2619         mac_control = &nic->mac_control;
2620         config = &nic->config;
2621
2622         nic->pkts_to_process = *budget;
2623         if (nic->pkts_to_process > dev->quota)
2624                 nic->pkts_to_process = dev->quota;
2625         org_pkts_to_process = nic->pkts_to_process;
2626
2627         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2628         readl(&bar0->rx_traffic_int);
2629
2630         for (i = 0; i < config->rx_ring_num; i++) {
2631                 rx_intr_handler(&mac_control->rings[i]);
2632                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2633                 if (!nic->pkts_to_process) {
2634                         /* Quota for the current iteration has been met */
2635                         goto no_rx;
2636                 }
2637         }
2638         if (!pkt_cnt)
2639                 pkt_cnt = 1;
2640
2641         dev->quota -= pkt_cnt;
2642         *budget -= pkt_cnt;
2643         netif_rx_complete(dev);
2644
2645         for (i = 0; i < config->rx_ring_num; i++) {
2646                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2647                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2648                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2649                         break;
2650                 }
2651         }
2652         /* Re enable the Rx interrupts. */
2653         writeq(0x0, &bar0->rx_traffic_mask);
2654         readl(&bar0->rx_traffic_mask);
2655         atomic_dec(&nic->isr_cnt);
2656         return 0;
2657
2658 no_rx:
2659         dev->quota -= pkt_cnt;
2660         *budget -= pkt_cnt;
2661
2662         for (i = 0; i < config->rx_ring_num; i++) {
2663                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2664                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2665                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2666                         break;
2667                 }
2668         }
2669         atomic_dec(&nic->isr_cnt);
2670         return 1;
2671 }
2672
2673 #ifdef CONFIG_NET_POLL_CONTROLLER
2674 /**
2675  * s2io_netpoll - netpoll event handler entry point
2676  * @dev : pointer to the device structure.
2677  * Description:
2678  *      This function will be called by upper layer to check for events on the
2679  * interface in situations where interrupts are disabled. It is used for
2680  * specific in-kernel networking tasks, such as remote consoles and kernel
2681  * debugging over the network (example netdump in RedHat).
2682  */
2683 static void s2io_netpoll(struct net_device *dev)
2684 {
2685         struct s2io_nic *nic = dev->priv;
2686         struct mac_info *mac_control;
2687         struct config_param *config;
2688         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2689         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2690         int i;
2691
2692         disable_irq(dev->irq);
2693
2694         atomic_inc(&nic->isr_cnt);
2695         mac_control = &nic->mac_control;
2696         config = &nic->config;
2697
2698         writeq(val64, &bar0->rx_traffic_int);
2699         writeq(val64, &bar0->tx_traffic_int);
2700
2701         /* we need to free up the transmitted skbufs or else netpoll will
2702          * run out of skbs and will fail and eventually netpoll application such
2703          * as netdump will fail.
2704          */
2705         for (i = 0; i < config->tx_fifo_num; i++)
2706                 tx_intr_handler(&mac_control->fifos[i]);
2707
2708         /* check for received packet and indicate up to network */
2709         for (i = 0; i < config->rx_ring_num; i++)
2710                 rx_intr_handler(&mac_control->rings[i]);
2711
2712         for (i = 0; i < config->rx_ring_num; i++) {
2713                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2714                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2715                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2716                         break;
2717                 }
2718         }
2719         atomic_dec(&nic->isr_cnt);
2720         enable_irq(dev->irq);
2721         return;
2722 }
2723 #endif
2724
2725 /**
2726  *  rx_intr_handler - Rx interrupt handler
2727  *  @nic: device private variable.
2728  *  Description:
2729  *  If the interrupt is because of a received frame or if the
2730  *  receive ring contains fresh as yet un-processed frames,this function is
2731  *  called. It picks out the RxD at which place the last Rx processing had
2732  *  stopped and sends the skb to the OSM's Rx handler and then increments
2733  *  the offset.
2734  *  Return Value:
2735  *  NONE.
2736  */
2737 static void rx_intr_handler(struct ring_info *ring_data)
2738 {
2739         struct s2io_nic *nic = ring_data->nic;
2740         struct net_device *dev = (struct net_device *) nic->dev;
2741         int get_block, put_block, put_offset;
2742         struct rx_curr_get_info get_info, put_info;
2743         struct RxD_t *rxdp;
2744         struct sk_buff *skb;
2745         int pkt_cnt = 0;
2746         int i;
2747
2748         spin_lock(&nic->rx_lock);
2749         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2750                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2751                           __FUNCTION__, dev->name);
2752                 spin_unlock(&nic->rx_lock);
2753                 return;
2754         }
2755
2756         get_info = ring_data->rx_curr_get_info;
2757         get_block = get_info.block_index;
2758         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2759         put_block = put_info.block_index;
2760         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2761         if (!napi) {
2762                 spin_lock(&nic->put_lock);
2763                 put_offset = ring_data->put_pos;
2764                 spin_unlock(&nic->put_lock);
2765         } else
2766                 put_offset = ring_data->put_pos;
2767
2768         while (RXD_IS_UP2DT(rxdp)) {
2769                 /*
2770                  * If your are next to put index then it's
2771                  * FIFO full condition
2772                  */
2773                 if ((get_block == put_block) &&
2774                     (get_info.offset + 1) == put_info.offset) {
2775                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2776                         break;
2777                 }
2778                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2779                 if (skb == NULL) {
2780                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2781                                   dev->name);
2782                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2783                         spin_unlock(&nic->rx_lock);
2784                         return;
2785                 }
2786                 if (nic->rxd_mode == RXD_MODE_1) {
2787                         pci_unmap_single(nic->pdev, (dma_addr_t)
2788                                  ((struct RxD1*)rxdp)->Buffer0_ptr,
2789                                  dev->mtu +
2790                                  HEADER_ETHERNET_II_802_3_SIZE +
2791                                  HEADER_802_2_SIZE +
2792                                  HEADER_SNAP_SIZE,
2793                                  PCI_DMA_FROMDEVICE);
2794                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2795                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2796                                  ((struct RxD3*)rxdp)->Buffer0_ptr,
2797                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2798                         pci_unmap_single(nic->pdev, (dma_addr_t)
2799                                  ((struct RxD3*)rxdp)->Buffer2_ptr,
2800                                  dev->mtu + 4,
2801                                  PCI_DMA_FROMDEVICE);
2802                 } else {
2803                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2804                                          ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2805                                          PCI_DMA_FROMDEVICE);
2806                         pci_unmap_single(nic->pdev, (dma_addr_t)
2807                                          ((struct RxD3*)rxdp)->Buffer1_ptr,
2808                                          l3l4hdr_size + 4,
2809                                          PCI_DMA_FROMDEVICE);
2810                         pci_unmap_single(nic->pdev, (dma_addr_t)
2811                                          ((struct RxD3*)rxdp)->Buffer2_ptr,
2812                                          dev->mtu, PCI_DMA_FROMDEVICE);
2813                 }
2814                 prefetch(skb->data);
2815                 rx_osm_handler(ring_data, rxdp);
2816                 get_info.offset++;
2817                 ring_data->rx_curr_get_info.offset = get_info.offset;
2818                 rxdp = ring_data->rx_blocks[get_block].
2819                                 rxds[get_info.offset].virt_addr;
2820                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2821                         get_info.offset = 0;
2822                         ring_data->rx_curr_get_info.offset = get_info.offset;
2823                         get_block++;
2824                         if (get_block == ring_data->block_count)
2825                                 get_block = 0;
2826                         ring_data->rx_curr_get_info.block_index = get_block;
2827                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2828                 }
2829
2830                 nic->pkts_to_process -= 1;
2831                 if ((napi) && (!nic->pkts_to_process))
2832                         break;
2833                 pkt_cnt++;
2834                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2835                         break;
2836         }
2837         if (nic->lro) {
2838                 /* Clear all LRO sessions before exiting */
2839                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2840                         struct lro *lro = &nic->lro0_n[i];
2841                         if (lro->in_use) {
2842                                 update_L3L4_header(nic, lro);
2843                                 queue_rx_frame(lro->parent);
2844                                 clear_lro_session(lro);
2845                         }
2846                 }
2847         }
2848
2849         spin_unlock(&nic->rx_lock);
2850 }
2851
2852 /**
2853  *  tx_intr_handler - Transmit interrupt handler
2854  *  @nic : device private variable
2855  *  Description:
2856  *  If an interrupt was raised to indicate DMA complete of the
2857  *  Tx packet, this function is called. It identifies the last TxD
2858  *  whose buffer was freed and frees all skbs whose data have already
2859  *  DMA'ed into the NICs internal memory.
2860  *  Return Value:
2861  *  NONE
2862  */
2863
2864 static void tx_intr_handler(struct fifo_info *fifo_data)
2865 {
2866         struct s2io_nic *nic = fifo_data->nic;
2867         struct net_device *dev = (struct net_device *) nic->dev;
2868         struct tx_curr_get_info get_info, put_info;
2869         struct sk_buff *skb;
2870         struct TxD *txdlp;
2871
2872         get_info = fifo_data->tx_curr_get_info;
2873         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2874         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2875             list_virt_addr;
2876         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2877                (get_info.offset != put_info.offset) &&
2878                (txdlp->Host_Control)) {
2879                 /* Check for TxD errors */
2880                 if (txdlp->Control_1 & TXD_T_CODE) {
2881                         unsigned long long err;
2882                         err = txdlp->Control_1 & TXD_T_CODE;
2883                         if (err & 0x1) {
2884                                 nic->mac_control.stats_info->sw_stat.
2885                                                 parity_err_cnt++;
2886                         }
2887
2888                         /* update t_code statistics */
2889                         err >>= 48;
2890                         switch(err) {
2891                                 case 2:
2892                                         nic->mac_control.stats_info->sw_stat.
2893                                                         tx_buf_abort_cnt++;
2894                                 break;
2895
2896                                 case 3:
2897                                         nic->mac_control.stats_info->sw_stat.
2898                                                         tx_desc_abort_cnt++;
2899                                 break;
2900
2901                                 case 7:
2902                                         nic->mac_control.stats_info->sw_stat.
2903                                                         tx_parity_err_cnt++;
2904                                 break;
2905
2906                                 case 10:
2907                                         nic->mac_control.stats_info->sw_stat.
2908                                                         tx_link_loss_cnt++;
2909                                 break;
2910
2911                                 case 15:
2912                                         nic->mac_control.stats_info->sw_stat.
2913                                                         tx_list_proc_err_cnt++;
2914                                 break;
2915                         }
2916                 }
2917
2918                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2919                 if (skb == NULL) {
2920                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2921                         __FUNCTION__);
2922                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2923                         return;
2924                 }
2925
2926                 /* Updating the statistics block */
2927                 nic->stats.tx_bytes += skb->len;
2928                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2929                 dev_kfree_skb_irq(skb);
2930
2931                 get_info.offset++;
2932                 if (get_info.offset == get_info.fifo_len + 1)
2933                         get_info.offset = 0;
2934                 txdlp = (struct TxD *) fifo_data->list_info
2935                     [get_info.offset].list_virt_addr;
2936                 fifo_data->tx_curr_get_info.offset =
2937                     get_info.offset;
2938         }
2939
2940         spin_lock(&nic->tx_lock);
2941         if (netif_queue_stopped(dev))
2942                 netif_wake_queue(dev);
2943         spin_unlock(&nic->tx_lock);
2944 }
2945
2946 /**
2947  *  s2io_mdio_write - Function to write in to MDIO registers
2948  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2949  *  @addr     : address value
2950  *  @value    : data value
2951  *  @dev      : pointer to net_device structure
2952  *  Description:
2953  *  This function is used to write values to the MDIO registers
2954  *  NONE
2955  */
2956 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2957 {
2958         u64 val64 = 0x0;
2959         struct s2io_nic *sp = dev->priv;
2960         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2961
2962         //address transaction
2963         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2964                         | MDIO_MMD_DEV_ADDR(mmd_type)
2965                         | MDIO_MMS_PRT_ADDR(0x0);
2966         writeq(val64, &bar0->mdio_control);
2967         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2968         writeq(val64, &bar0->mdio_control);
2969         udelay(100);
2970
2971         //Data transaction
2972         val64 = 0x0;
2973         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2974                         | MDIO_MMD_DEV_ADDR(mmd_type)
2975                         | MDIO_MMS_PRT_ADDR(0x0)
2976                         | MDIO_MDIO_DATA(value)
2977                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2978         writeq(val64, &bar0->mdio_control);
2979         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2980         writeq(val64, &bar0->mdio_control);
2981         udelay(100);
2982
2983         val64 = 0x0;
2984         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2985         | MDIO_MMD_DEV_ADDR(mmd_type)
2986         | MDIO_MMS_PRT_ADDR(0x0)
2987         | MDIO_OP(MDIO_OP_READ_TRANS);
2988         writeq(val64, &bar0->mdio_control);
2989         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2990         writeq(val64, &bar0->mdio_control);
2991         udelay(100);
2992
2993 }
2994
2995 /**
2996  *  s2io_mdio_read - Function to write in to MDIO registers
2997  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2998  *  @addr     : address value
2999  *  @dev      : pointer to net_device structure
3000  *  Description:
3001  *  This function is used to read values to the MDIO registers
3002  *  NONE
3003  */
3004 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3005 {
3006         u64 val64 = 0x0;
3007         u64 rval64 = 0x0;
3008         struct s2io_nic *sp = dev->priv;
3009         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3010
3011         /* address transaction */
3012         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3013                         | MDIO_MMD_DEV_ADDR(mmd_type)
3014                         | MDIO_MMS_PRT_ADDR(0x0);
3015         writeq(val64, &bar0->mdio_control);
3016         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3017         writeq(val64, &bar0->mdio_control);
3018         udelay(100);
3019
3020         /* Data transaction */
3021         val64 = 0x0;
3022         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3023                         | MDIO_MMD_DEV_ADDR(mmd_type)
3024                         | MDIO_MMS_PRT_ADDR(0x0)
3025                         | MDIO_OP(MDIO_OP_READ_TRANS);
3026         writeq(val64, &bar0->mdio_control);
3027         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3028         writeq(val64, &bar0->mdio_control);
3029         udelay(100);
3030
3031         /* Read the value from regs */
3032         rval64 = readq(&bar0->mdio_control);
3033         rval64 = rval64 & 0xFFFF0000;
3034         rval64 = rval64 >> 16;
3035         return rval64;
3036 }
3037 /**
3038  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3039  *  @counter      : couter value to be updated
3040  *  @flag         : flag to indicate the status
3041  *  @type         : counter type
3042  *  Description:
3043  *  This function is to check the status of the xpak counters value
3044  *  NONE
3045  */
3046
3047 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3048 {
3049         u64 mask = 0x3;
3050         u64 val64;
3051         int i;
3052         for(i = 0; i <index; i++)
3053                 mask = mask << 0x2;
3054
3055         if(flag > 0)
3056         {
3057                 *counter = *counter + 1;
3058                 val64 = *regs_stat & mask;
3059                 val64 = val64 >> (index * 0x2);
3060                 val64 = val64 + 1;
3061                 if(val64 == 3)
3062                 {
3063                         switch(type)
3064                         {
3065                         case 1:
3066                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3067                                           "service. Excessive temperatures may "
3068                                           "result in premature transceiver "
3069                                           "failure \n");
3070                         break;
3071                         case 2:
3072                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3073                                           "service Excessive bias currents may "
3074                                           "indicate imminent laser diode "
3075                                           "failure \n");
3076                         break;
3077                         case 3:
3078                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3079                                           "service Excessive laser output "
3080                                           "power may saturate far-end "
3081                                           "receiver\n");
3082                         break;
3083                         default:
3084                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3085                                           "type \n");
3086                         }
3087                         val64 = 0x0;
3088                 }
3089                 val64 = val64 << (index * 0x2);
3090                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3091
3092         } else {
3093                 *regs_stat = *regs_stat & (~mask);
3094         }
3095 }
3096
3097 /**
3098  *  s2io_updt_xpak_counter - Function to update the xpak counters
3099  *  @dev         : pointer to net_device struct
3100  *  Description:
3101  *  This function is to upate the status of the xpak counters value
3102  *  NONE
3103  */
3104 static void s2io_updt_xpak_counter(struct net_device *dev)
3105 {
3106         u16 flag  = 0x0;
3107         u16 type  = 0x0;
3108         u16 val16 = 0x0;
3109         u64 val64 = 0x0;
3110         u64 addr  = 0x0;
3111
3112         struct s2io_nic *sp = dev->priv;
3113         struct stat_block *stat_info = sp->mac_control.stats_info;
3114
3115         /* Check the communication with the MDIO slave */
3116         addr = 0x0000;
3117         val64 = 0x0;
3118         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3119         if((val64 == 0xFFFF) || (val64 == 0x0000))
3120         {
3121                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3122                           "Returned %llx\n", (unsigned long long)val64);
3123                 return;
3124         }
3125
3126         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3127         if(val64 != 0x2040)
3128         {
3129                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3130                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3131                           (unsigned long long)val64);
3132                 return;
3133         }
3134
3135         /* Loading the DOM register to MDIO register */
3136         addr = 0xA100;
3137         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3138         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3139
3140         /* Reading the Alarm flags */
3141         addr = 0xA070;
3142         val64 = 0x0;
3143         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3144
3145         flag = CHECKBIT(val64, 0x7);
3146         type = 1;
3147         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3148                                 &stat_info->xpak_stat.xpak_regs_stat,
3149                                 0x0, flag, type);
3150
3151         if(CHECKBIT(val64, 0x6))
3152                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3153
3154         flag = CHECKBIT(val64, 0x3);
3155         type = 2;
3156         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3157                                 &stat_info->xpak_stat.xpak_regs_stat,
3158                                 0x2, flag, type);
3159
3160         if(CHECKBIT(val64, 0x2))
3161                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3162
3163         flag = CHECKBIT(val64, 0x1);
3164         type = 3;
3165         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3166                                 &stat_info->xpak_stat.xpak_regs_stat,
3167                                 0x4, flag, type);
3168
3169         if(CHECKBIT(val64, 0x0))
3170                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3171
3172         /* Reading the Warning flags */
3173         addr = 0xA074;
3174         val64 = 0x0;
3175         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3176
3177         if(CHECKBIT(val64, 0x7))
3178                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3179
3180         if(CHECKBIT(val64, 0x6))
3181                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3182
3183         if(CHECKBIT(val64, 0x3))
3184                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3185
3186         if(CHECKBIT(val64, 0x2))
3187                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3188
3189         if(CHECKBIT(val64, 0x1))
3190                 stat_info->xpak_stat.warn_laser_output_power_high++;
3191
3192         if(CHECKBIT(val64, 0x0))
3193                 stat_info->xpak_stat.warn_laser_output_power_low++;
3194 }
3195
3196 /**
3197  *  alarm_intr_handler - Alarm Interrrupt handler
3198  *  @nic: device private variable
3199  *  Description: If the interrupt was neither because of Rx packet or Tx
3200  *  complete, this function is called. If the interrupt was to indicate
3201  *  a loss of link, the OSM link status handler is invoked for any other
3202  *  alarm interrupt the block that raised the interrupt is displayed
3203  *  and a H/W reset is issued.
3204  *  Return Value:
3205  *  NONE
3206 */
3207
3208 static void alarm_intr_handler(struct s2io_nic *nic)
3209 {
3210         struct net_device *dev = (struct net_device *) nic->dev;
3211         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3212         register u64 val64 = 0, err_reg = 0;
3213         u64 cnt;
3214         int i;
3215         if (atomic_read(&nic->card_state) == CARD_DOWN)
3216                 return;
3217         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3218         /* Handling the XPAK counters update */
3219         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3220                 /* waiting for an hour */
3221                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3222         } else {
3223                 s2io_updt_xpak_counter(dev);
3224                 /* reset the count to zero */
3225                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3226         }
3227
3228         /* Handling link status change error Intr */
3229         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3230                 err_reg = readq(&bar0->mac_rmac_err_reg);
3231                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3232                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3233                         schedule_work(&nic->set_link_task);
3234                 }
3235         }
3236
3237         /* Handling Ecc errors */
3238         val64 = readq(&bar0->mc_err_reg);
3239         writeq(val64, &bar0->mc_err_reg);
3240         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3241                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3242                         nic->mac_control.stats_info->sw_stat.
3243                                 double_ecc_errs++;
3244                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3245                                   dev->name);
3246                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3247                         if (nic->device_type != XFRAME_II_DEVICE) {
3248                                 /* Reset XframeI only if critical error */
3249                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3250                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3251                                         netif_stop_queue(dev);
3252                                         schedule_work(&nic->rst_timer_task);
3253                                         nic->mac_control.stats_info->sw_stat.
3254                                                         soft_reset_cnt++;
3255                                 }
3256                         }
3257                 } else {
3258                         nic->mac_control.stats_info->sw_stat.
3259                                 single_ecc_errs++;
3260                 }
3261         }
3262
3263         /* In case of a serious error, the device will be Reset. */
3264         val64 = readq(&bar0->serr_source);
3265         if (val64 & SERR_SOURCE_ANY) {
3266                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3267                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3268                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3269                           (unsigned long long)val64);
3270                 netif_stop_queue(dev);
3271                 schedule_work(&nic->rst_timer_task);
3272                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3273         }
3274
3275         /*
3276          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3277          * Error occurs, the adapter will be recycled by disabling the
3278          * adapter enable bit and enabling it again after the device
3279          * becomes Quiescent.
3280          */
3281         val64 = readq(&bar0->pcc_err_reg);
3282         writeq(val64, &bar0->pcc_err_reg);
3283         if (val64 & PCC_FB_ECC_DB_ERR) {
3284                 u64 ac = readq(&bar0->adapter_control);
3285                 ac &= ~(ADAPTER_CNTL_EN);
3286                 writeq(ac, &bar0->adapter_control);
3287                 ac = readq(&bar0->adapter_control);
3288                 schedule_work(&nic->set_link_task);
3289         }
3290         /* Check for data parity error */
3291         val64 = readq(&bar0->pic_int_status);
3292         if (val64 & PIC_INT_GPIO) {
3293                 val64 = readq(&bar0->gpio_int_reg);
3294                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3295                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3296                         schedule_work(&nic->rst_timer_task);
3297                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3298                 }
3299         }
3300
3301         /* Check for ring full counter */
3302         if (nic->device_type & XFRAME_II_DEVICE) {
3303                 val64 = readq(&bar0->ring_bump_counter1);
3304                 for (i=0; i<4; i++) {
3305                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3306                         cnt >>= 64 - ((i+1)*16);
3307                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3308                                 += cnt;
3309                 }
3310
3311                 val64 = readq(&bar0->ring_bump_counter2);
3312                 for (i=0; i<4; i++) {
3313                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3314                         cnt >>= 64 - ((i+1)*16);
3315                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3316                                 += cnt;
3317                 }
3318         }
3319
3320         /* Other type of interrupts are not being handled now,  TODO */
3321 }
3322
3323 /**
3324  *  wait_for_cmd_complete - waits for a command to complete.
3325  *  @sp : private member of the device structure, which is a pointer to the
3326  *  s2io_nic structure.
3327  *  Description: Function that waits for a command to Write into RMAC
3328  *  ADDR DATA registers to be completed and returns either success or
3329  *  error depending on whether the command was complete or not.
3330  *  Return value:
3331  *   SUCCESS on success and FAILURE on failure.
3332  */
3333
3334 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3335                                 int bit_state)
3336 {
3337         int ret = FAILURE, cnt = 0, delay = 1;
3338         u64 val64;
3339
3340         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3341                 return FAILURE;
3342
3343         do {
3344                 val64 = readq(addr);
3345                 if (bit_state == S2IO_BIT_RESET) {
3346                         if (!(val64 & busy_bit)) {
3347                                 ret = SUCCESS;
3348                                 break;
3349                         }
3350                 } else {
3351                         if (!(val64 & busy_bit)) {
3352                                 ret = SUCCESS;
3353                                 break;
3354                         }
3355                 }
3356
3357                 if(in_interrupt())
3358                         mdelay(delay);
3359                 else
3360                         msleep(delay);
3361
3362                 if (++cnt >= 10)
3363                         delay = 50;
3364         } while (cnt < 20);
3365         return ret;
3366 }
3367 /*
3368  * check_pci_device_id - Checks if the device id is supported
3369  * @id : device id
3370  * Description: Function to check if the pci device id is supported by driver.
3371  * Return value: Actual device id if supported else PCI_ANY_ID
3372  */
3373 static u16 check_pci_device_id(u16 id)
3374 {
3375         switch (id) {
3376         case PCI_DEVICE_ID_HERC_WIN:
3377         case PCI_DEVICE_ID_HERC_UNI:
3378                 return XFRAME_II_DEVICE;
3379         case PCI_DEVICE_ID_S2IO_UNI:
3380         case PCI_DEVICE_ID_S2IO_WIN:
3381                 return XFRAME_I_DEVICE;
3382         default:
3383                 return PCI_ANY_ID;
3384         }
3385 }
3386
3387 /**
3388  *  s2io_reset - Resets the card.
3389  *  @sp : private member of the device structure.
3390  *  Description: Function to Reset the card. This function then also
3391  *  restores the previously saved PCI configuration space registers as
3392  *  the card reset also resets the configuration space.
3393  *  Return value:
3394  *  void.
3395  */
3396
3397 static void s2io_reset(struct s2io_nic * sp)
3398 {
3399         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3400         u64 val64;
3401         u16 subid, pci_cmd;
3402         int i;
3403         u16 val16;
3404         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3405         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3406
3407         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3408                         __FUNCTION__, sp->dev->name);
3409
3410         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3411         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3412
3413         if (sp->device_type == XFRAME_II_DEVICE) {
3414                 int ret;
3415                 ret = pci_set_power_state(sp->pdev, 3);
3416                 if (!ret)
3417                         ret = pci_set_power_state(sp->pdev, 0);
3418                 else {
3419                         DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3420                                         __FUNCTION__);
3421                         goto old_way;
3422                 }
3423                 msleep(20);
3424                 goto new_way;
3425         }
3426 old_way:
3427         val64 = SW_RESET_ALL;
3428         writeq(val64, &bar0->sw_reset);
3429 new_way:
3430         if (strstr(sp->product_name, "CX4")) {
3431                 msleep(750);
3432         }
3433         msleep(250);
3434         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3435
3436                 /* Restore the PCI state saved during initialization. */
3437                 pci_restore_state(sp->pdev);
3438                 pci_read_config_word(sp->pdev, 0x2, &val16);
3439                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3440                         break;
3441                 msleep(200);
3442         }
3443
3444         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3445                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3446         }
3447
3448         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3449
3450         s2io_init_pci(sp);
3451
3452         /* Set swapper to enable I/O register access */
3453         s2io_set_swapper(sp);
3454
3455         /* Restore the MSIX table entries from local variables */
3456         restore_xmsi_data(sp);
3457
3458         /* Clear certain PCI/PCI-X fields after reset */
3459         if (sp->device_type == XFRAME_II_DEVICE) {
3460                 /* Clear "detected parity error" bit */
3461                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3462
3463                 /* Clearing PCIX Ecc status register */
3464                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3465
3466                 /* Clearing PCI_STATUS error reflected here */
3467                 writeq(BIT(62), &bar0->txpic_int_reg);
3468         }
3469
3470         /* Reset device statistics maintained by OS */
3471         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3472
3473         up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3474         down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3475         up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3476         down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3477         reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3478         mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3479         mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3480         watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3481         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3482         memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3483         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3484         sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3485         sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3486         sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3487         sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3488         sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3489         sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3490         sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3491         sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3492
3493         /* SXE-002: Configure link and activity LED to turn it off */
3494         subid = sp->pdev->subsystem_device;
3495         if (((subid & 0xFF) >= 0x07) &&
3496             (sp->device_type == XFRAME_I_DEVICE)) {
3497                 val64 = readq(&bar0->gpio_control);
3498                 val64 |= 0x0000800000000000ULL;
3499                 writeq(val64, &bar0->gpio_control);
3500                 val64 = 0x0411040400000000ULL;
3501                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3502         }
3503
3504         /*
3505          * Clear spurious ECC interrupts that would have occured on
3506          * XFRAME II cards after reset.
3507          */
3508         if (sp->device_type == XFRAME_II_DEVICE) {
3509                 val64 = readq(&bar0->pcc_err_reg);
3510                 writeq(val64, &bar0->pcc_err_reg);
3511         }
3512
3513         /* restore the previously assigned mac address */
3514         s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3515
3516         sp->device_enabled_once = FALSE;
3517 }
3518
3519 /**
3520  *  s2io_set_swapper - to set the swapper controle on the card
3521  *  @sp : private member of the device structure,
3522  *  pointer to the s2io_nic structure.
3523  *  Description: Function to set the swapper control on the card
3524  *  correctly depending on the 'endianness' of the system.
3525  *  Return value:
3526  *  SUCCESS on success and FAILURE on failure.
3527  */
3528
3529 static int s2io_set_swapper(struct s2io_nic * sp)
3530 {
3531         struct net_device *dev = sp->dev;
3532         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3533         u64 val64, valt, valr;
3534
3535         /*
3536          * Set proper endian settings and verify the same by reading
3537          * the PIF Feed-back register.
3538          */
3539
3540         val64 = readq(&bar0->pif_rd_swapper_fb);
3541         if (val64 != 0x0123456789ABCDEFULL) {
3542                 int i = 0;
3543                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3544                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3545                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3546                                 0};                     /* FE=0, SE=0 */
3547
3548                 while(i<4) {
3549                         writeq(value[i], &bar0->swapper_ctrl);
3550                         val64 = readq(&bar0->pif_rd_swapper_fb);
3551                         if (val64 == 0x0123456789ABCDEFULL)
3552                                 break;
3553                         i++;
3554                 }
3555                 if (i == 4) {
3556                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3557                                 dev->name);
3558                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3559                                 (unsigned long long) val64);
3560                         return FAILURE;
3561                 }
3562                 valr = value[i];
3563         } else {
3564                 valr = readq(&bar0->swapper_ctrl);
3565         }
3566
3567         valt = 0x0123456789ABCDEFULL;
3568         writeq(valt, &bar0->xmsi_address);
3569         val64 = readq(&bar0->xmsi_address);
3570
3571         if(val64 != valt) {
3572                 int i = 0;
3573                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3574                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3575                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3576                                 0};                     /* FE=0, SE=0 */
3577
3578                 while(i<4) {
3579                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3580                         writeq(valt, &bar0->xmsi_address);
3581                         val64 = readq(&bar0->xmsi_address);
3582                         if(val64 == valt)
3583                                 break;
3584                         i++;
3585                 }
3586                 if(i == 4) {
3587                         unsigned long long x = val64;
3588                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3589                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3590                         return FAILURE;
3591                 }
3592         }
3593         val64 = readq(&bar0->swapper_ctrl);
3594         val64 &= 0xFFFF000000000000ULL;
3595
3596 #ifdef  __BIG_ENDIAN
3597         /*
3598          * The device by default set to a big endian format, so a
3599          * big endian driver need not set anything.
3600          */
3601         val64 |= (SWAPPER_CTRL_TXP_FE |
3602                  SWAPPER_CTRL_TXP_SE |
3603                  SWAPPER_CTRL_TXD_R_FE |
3604                  SWAPPER_CTRL_TXD_W_FE |
3605                  SWAPPER_CTRL_TXF_R_FE |
3606                  SWAPPER_CTRL_RXD_R_FE |
3607                  SWAPPER_CTRL_RXD_W_FE |
3608                  SWAPPER_CTRL_RXF_W_FE |
3609                  SWAPPER_CTRL_XMSI_FE |
3610                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3611         if (sp->intr_type == INTA)
3612                 val64 |= SWAPPER_CTRL_XMSI_SE;
3613         writeq(val64, &bar0->swapper_ctrl);
3614 #else
3615         /*
3616          * Initially we enable all bits to make it accessible by the
3617          * driver, then we selectively enable only those bits that
3618          * we want to set.
3619          */
3620         val64 |= (SWAPPER_CTRL_TXP_FE |
3621                  SWAPPER_CTRL_TXP_SE |
3622                  SWAPPER_CTRL_TXD_R_FE |
3623                  SWAPPER_CTRL_TXD_R_SE |
3624                  SWAPPER_CTRL_TXD_W_FE |
3625                  SWAPPER_CTRL_TXD_W_SE |
3626                  SWAPPER_CTRL_TXF_R_FE |
3627                  SWAPPER_CTRL_RXD_R_FE |
3628                  SWAPPER_CTRL_RXD_R_SE |
3629                  SWAPPER_CTRL_RXD_W_FE |
3630                  SWAPPER_CTRL_RXD_W_SE |
3631                  SWAPPER_CTRL_RXF_W_FE |
3632                  SWAPPER_CTRL_XMSI_FE |
3633                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3634         if (sp->intr_type == INTA)
3635                 val64 |= SWAPPER_CTRL_XMSI_SE;
3636         writeq(val64, &bar0->swapper_ctrl);
3637 #endif
3638         val64 = readq(&bar0->swapper_ctrl);
3639
3640         /*
3641          * Verifying if endian settings are accurate by reading a
3642          * feedback register.
3643          */
3644         val64 = readq(&bar0->pif_rd_swapper_fb);
3645         if (val64 != 0x0123456789ABCDEFULL) {
3646                 /* Endian settings are incorrect, calls for another dekko. */
3647                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3648                           dev->name);
3649                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3650                           (unsigned long long) val64);
3651                 return FAILURE;
3652         }
3653
3654         return SUCCESS;
3655 }
3656
3657 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3658 {
3659         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3660         u64 val64;
3661         int ret = 0, cnt = 0;
3662
3663         do {
3664                 val64 = readq(&bar0->xmsi_access);
3665                 if (!(val64 & BIT(15)))
3666                         break;
3667                 mdelay(1);
3668                 cnt++;
3669         } while(cnt < 5);
3670         if (cnt == 5) {
3671                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3672                 ret = 1;
3673         }
3674
3675         return ret;
3676 }
3677
3678 static void restore_xmsi_data(struct s2io_nic *nic)
3679 {
3680         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3681         u64 val64;
3682         int i;
3683
3684         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3685                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3686                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3687                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3688                 writeq(val64, &bar0->xmsi_access);
3689                 if (wait_for_msix_trans(nic, i)) {
3690                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3691                         continue;
3692                 }
3693         }
3694 }
3695
3696 static void store_xmsi_data(struct s2io_nic *nic)
3697 {
3698         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3699         u64 val64, addr, data;
3700         int i;
3701
3702         /* Store and display */
3703         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3704                 val64 = (BIT(15) | vBIT(i, 26, 6));
3705                 writeq(val64, &bar0->xmsi_access);
3706                 if (wait_for_msix_trans(nic, i)) {
3707                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3708                         continue;
3709                 }
3710                 addr = readq(&bar0->xmsi_address);
3711                 data = readq(&bar0->xmsi_data);
3712                 if (addr && data) {
3713                         nic->msix_info[i].addr = addr;
3714                         nic->msix_info[i].data = data;
3715                 }
3716         }
3717 }
3718
3719 int s2io_enable_msi(struct s2io_nic *nic)
3720 {
3721         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3722         u16 msi_ctrl, msg_val;
3723         struct config_param *config = &nic->config;
3724         struct net_device *dev = nic->dev;
3725         u64 val64, tx_mat, rx_mat;
3726         int i, err;
3727
3728         val64 = readq(&bar0->pic_control);
3729         val64 &= ~BIT(1);
3730         writeq(val64, &bar0->pic_control);
3731
3732         err = pci_enable_msi(nic->pdev);
3733         if (err) {
3734                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3735                           nic->dev->name);
3736                 return err;
3737         }
3738
3739         /*
3740          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3741          * for interrupt handling.
3742          */
3743         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3744         msg_val ^= 0x1;
3745         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3746         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3747
3748         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3749         msi_ctrl |= 0x10;
3750         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3751
3752         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3753         tx_mat = readq(&bar0->tx_mat0_n[0]);
3754         for (i=0; i<config->tx_fifo_num; i++) {
3755                 tx_mat |= TX_MAT_SET(i, 1);
3756         }
3757         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3758
3759         rx_mat = readq(&bar0->rx_mat);
3760         for (i=0; i<config->rx_ring_num; i++) {
3761                 rx_mat |= RX_MAT_SET(i, 1);
3762         }
3763         writeq(rx_mat, &bar0->rx_mat);
3764
3765         dev->irq = nic->pdev->irq;
3766         return 0;
3767 }
3768
3769 static int s2io_enable_msi_x(struct s2io_nic *nic)
3770 {
3771         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3772         u64 tx_mat, rx_mat;
3773         u16 msi_control; /* Temp variable */
3774         int ret, i, j, msix_indx = 1;
3775
3776         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3777                                GFP_KERNEL);
3778         if (nic->entries == NULL) {
3779                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3780                         __FUNCTION__);
3781                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3782                 return -ENOMEM;
3783         }
3784         nic->mac_control.stats_info->sw_stat.mem_allocated
3785                 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3786         memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3787
3788         nic->s2io_entries =
3789                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3790                                    GFP_KERNEL);
3791         if (nic->s2io_entries == NULL) {
3792                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3793                         __FUNCTION__);
3794                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3795                 kfree(nic->entries);
3796                 nic->mac_control.stats_info->sw_stat.mem_freed
3797                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3798                 return -ENOMEM;
3799         }
3800          nic->mac_control.stats_info->sw_stat.mem_allocated
3801                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3802         memset(nic->s2io_entries, 0,
3803                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3804
3805         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3806                 nic->entries[i].entry = i;
3807                 nic->s2io_entries[i].entry = i;
3808                 nic->s2io_entries[i].arg = NULL;
3809                 nic->s2io_entries[i].in_use = 0;
3810         }
3811
3812         tx_mat = readq(&bar0->tx_mat0_n[0]);
3813         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3814                 tx_mat |= TX_MAT_SET(i, msix_indx);
3815                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3816                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3817                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3818         }
3819         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3820
3821         if (!nic->config.bimodal) {
3822                 rx_mat = readq(&bar0->rx_mat);
3823                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3824                         rx_mat |= RX_MAT_SET(j, msix_indx);
3825                         nic->s2io_entries[msix_indx].arg
3826                                 = &nic->mac_control.rings[j];
3827                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3828                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3829                 }
3830                 writeq(rx_mat, &bar0->rx_mat);
3831         } else {
3832                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3833                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3834                         tx_mat |= TX_MAT_SET(i, msix_indx);
3835                         nic->s2io_entries[msix_indx].arg
3836                                 = &nic->mac_control.rings[j];
3837                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3838                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3839                 }
3840                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3841         }
3842
3843         nic->avail_msix_vectors = 0;
3844         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3845         /* We fail init if error or we get less vectors than min required */
3846         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3847                 nic->avail_msix_vectors = ret;
3848                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3849         }
3850         if (ret) {
3851                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3852                 kfree(nic->entries);
3853                 nic->mac_control.stats_info->sw_stat.mem_freed
3854                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3855                 kfree(nic->s2io_entries);
3856                 nic->mac_control.stats_info->sw_stat.mem_freed
3857                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3858                 nic->entries = NULL;
3859                 nic->s2io_entries = NULL;
3860                 nic->avail_msix_vectors = 0;
3861                 return -ENOMEM;
3862         }
3863         if (!nic->avail_msix_vectors)
3864                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3865
3866         /*
3867          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3868          * in the herc NIC. (Temp change, needs to be removed later)
3869          */
3870         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3871         msi_control |= 0x1; /* Enable MSI */
3872         pci_write_config_word(nic->pdev, 0x42, msi_control);
3873
3874         return 0;
3875 }
3876
3877 /* ********************************************************* *
3878  * Functions defined below concern the OS part of the driver *
3879  * ********************************************************* */
3880
3881 /**
3882  *  s2io_open - open entry point of the driver
3883  *  @dev : pointer to the device structure.
3884  *  Description:
3885  *  This function is the open entry point of the driver. It mainly calls a
3886  *  function to allocate Rx buffers and inserts them into the buffer
3887  *  descriptors and then enables the Rx part of the NIC.
3888  *  Return value:
3889  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3890  *   file on failure.
3891  */
3892
3893 static int s2io_open(struct net_device *dev)
3894 {
3895         struct s2io_nic *sp = dev->priv;
3896         int err = 0;
3897
3898         /*
3899          * Make sure you have link off by default every time
3900          * Nic is initialized
3901          */
3902         netif_carrier_off(dev);
3903         sp->last_link_state = 0;
3904
3905         /* Initialize H/W and enable interrupts */
3906         err = s2io_card_up(sp);
3907         if (err) {
3908                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3909                           dev->name);
3910                 goto hw_init_failed;
3911         }
3912
3913         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3914                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3915                 s2io_card_down(sp);
3916                 err = -ENODEV;
3917                 goto hw_init_failed;
3918         }
3919
3920         netif_start_queue(dev);
3921         return 0;
3922
3923 hw_init_failed:
3924         if (sp->intr_type == MSI_X) {
3925                 if (sp->entries) {
3926                         kfree(sp->entries);
3927                         sp->mac_control.stats_info->sw_stat.mem_freed
3928                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3929                 }
3930                 if (sp->s2io_entries) {
3931                         kfree(sp->s2io_entries);
3932                         sp->mac_control.stats_info->sw_stat.mem_freed
3933                         += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3934                 }
3935         }
3936         return err;
3937 }
3938
3939 /**
3940  *  s2io_close -close entry point of the driver
3941  *  @dev : device pointer.
3942  *  Description:
3943  *  This is the stop entry point of the driver. It needs to undo exactly
3944  *  whatever was done by the open entry point,thus it's usually referred to
3945  *  as the close function.Among other things this function mainly stops the
3946  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3947  *  Return value:
3948  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3949  *  file on failure.
3950  */
3951
3952 static int s2io_close(struct net_device *dev)
3953 {
3954         struct s2io_nic *sp = dev->priv;
3955
3956         netif_stop_queue(dev);
3957         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3958         s2io_card_down(sp);
3959
3960         sp->device_close_flag = TRUE;   /* Device is shut down. */
3961         return 0;
3962 }
3963
3964 /**
3965  *  s2io_xmit - Tx entry point of te driver
3966  *  @skb : the socket buffer containing the Tx data.
3967  *  @dev : device pointer.
3968  *  Description :
3969  *  This function is the Tx entry point of the driver. S2IO NIC supports
3970  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3971  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3972  *  not be upadted.
3973  *  Return value:
3974  *  0 on success & 1 on failure.
3975  */
3976
3977 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3978 {
3979         struct s2io_nic *sp = dev->priv;
3980         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3981         register u64 val64;
3982         struct TxD *txdp;
3983         struct TxFIFO_element __iomem *tx_fifo;
3984         unsigned long flags;
3985         u16 vlan_tag = 0;
3986         int vlan_priority = 0;
3987         struct mac_info *mac_control;
3988         struct config_param *config;
3989         int offload_type;
3990
3991         mac_control = &sp->mac_control;
3992         config = &sp->config;
3993
3994         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3995
3996         if (unlikely(skb->len <= 0)) {
3997                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3998                 dev_kfree_skb_any(skb);
3999                 return 0;
4000 }
4001
4002         spin_lock_irqsave(&sp->tx_lock, flags);
4003         if (atomic_read(&sp->card_state) == CARD_DOWN) {
4004                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4005                           dev->name);
4006                 spin_unlock_irqrestore(&sp->tx_lock, flags);
4007                 dev_kfree_skb(skb);
4008                 return 0;
4009         }
4010
4011         queue = 0;
4012         /* Get Fifo number to Transmit based on vlan priority */
4013         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4014                 vlan_tag = vlan_tx_tag_get(skb);
4015                 vlan_priority = vlan_tag >> 13;
4016                 queue = config->fifo_mapping[vlan_priority];
4017         }
4018
4019         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
4020         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
4021         txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
4022                 list_virt_addr;
4023
4024         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
4025         /* Avoid "put" pointer going beyond "get" pointer */
4026         if (txdp->Host_Control ||
4027                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4028                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4029                 netif_stop_queue(dev);
4030                 dev_kfree_skb(skb);
4031                 spin_unlock_irqrestore(&sp->tx_lock, flags);
4032                 return 0;
4033         }
4034
4035         offload_type = s2io_offload_type(skb);
4036         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4037                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4038                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4039         }
4040         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4041                 txdp->Control_2 |=
4042                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4043                      TXD_TX_CKO_UDP_EN);
4044         }
4045         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4046         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4047         txdp->Control_2 |= config->tx_intr_type;
4048
4049         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4050                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4051                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4052         }
4053
4054         frg_len = skb->len - skb->data_len;
4055         if (offload_type == SKB_GSO_UDP) {
4056                 int ufo_size;
4057
4058                 ufo_size = s2io_udp_mss(skb);
4059                 ufo_size &= ~7;
4060                 txdp->Control_1 |= TXD_UFO_EN;
4061                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4062                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4063 #ifdef __BIG_ENDIAN
4064                 sp->ufo_in_band_v[put_off] =
4065                                 (u64)skb_shinfo(skb)->ip6_frag_id;
4066 #else
4067                 sp->ufo_in_band_v[put_off] =
4068                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4069 #endif
4070                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4071                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4072                                         sp->ufo_in_band_v,
4073                                         sizeof(u64), PCI_DMA_TODEVICE);
4074                 txdp++;
4075         }
4076
4077         txdp->Buffer_Pointer = pci_map_single
4078             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4079         txdp->Host_Control = (unsigned long) skb;
4080         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4081         if (offload_type == SKB_GSO_UDP)
4082                 txdp->Control_1 |= TXD_UFO_EN;
4083
4084         frg_cnt = skb_shinfo(skb)->nr_frags;
4085         /* For fragmented SKB. */
4086         for (i = 0; i < frg_cnt; i++) {
4087                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4088                 /* A '0' length fragment will be ignored */
4089                 if (!frag->size)
4090                         continue;
4091                 txdp++;
4092                 txdp->Buffer_Pointer = (u64) pci_map_page
4093                     (sp->pdev, frag->page, frag->page_offset,
4094                      frag->size, PCI_DMA_TODEVICE);
4095                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4096                 if (offload_type == SKB_GSO_UDP)
4097                         txdp->Control_1 |= TXD_UFO_EN;
4098         }
4099         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4100
4101         if (offload_type == SKB_GSO_UDP)
4102                 frg_cnt++; /* as Txd0 was used for inband header */
4103
4104         tx_fifo = mac_control->tx_FIFO_start[queue];
4105         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4106         writeq(val64, &tx_fifo->TxDL_Pointer);
4107
4108         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4109                  TX_FIFO_LAST_LIST);
4110         if (offload_type)
4111                 val64 |= TX_FIFO_SPECIAL_FUNC;
4112
4113         writeq(val64, &tx_fifo->List_Control);
4114
4115         mmiowb();
4116
4117         put_off++;
4118         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4119                 put_off = 0;
4120         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4121
4122         /* Avoid "put" pointer going beyond "get" pointer */
4123         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4124                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4125                 DBG_PRINT(TX_DBG,
4126                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4127                           put_off, get_off);
4128                 netif_stop_queue(dev);
4129         }
4130         mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4131         dev->trans_start = jiffies;
4132         spin_unlock_irqrestore(&sp->tx_lock, flags);
4133
4134         return 0;
4135 }
4136
4137 static void
4138 s2io_alarm_handle(unsigned long data)
4139 {
4140         struct s2io_nic *sp = (struct s2io_nic *)data;
4141
4142         alarm_intr_handler(sp);
4143         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4144 }
4145
4146 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4147 {
4148         int rxb_size, level;
4149
4150         if (!sp->lro) {
4151                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4152                 level = rx_buffer_level(sp, rxb_size, rng_n);
4153
4154                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4155                         int ret;
4156                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4157                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4158                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4159                                 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4160                                           __FUNCTION__);
4161                                 clear_bit(0, (&sp->tasklet_status));
4162                                 return -1;
4163                         }
4164                         clear_bit(0, (&sp->tasklet_status));
4165                 } else if (level == LOW)
4166                         tasklet_schedule(&sp->task);
4167
4168         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4169                         DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4170                         DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4171         }
4172         return 0;
4173 }
4174
4175 static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
4176 {
4177         struct net_device *dev = (struct net_device *) dev_id;
4178         struct s2io_nic *sp = dev->priv;
4179         int i;
4180         struct mac_info *mac_control;
4181         struct config_param *config;
4182
4183         atomic_inc(&sp->isr_cnt);
4184         mac_control = &sp->mac_control;
4185         config = &sp->config;
4186         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4187
4188         /* If Intr is because of Rx Traffic */
4189         for (i = 0; i < config->rx_ring_num; i++)
4190                 rx_intr_handler(&mac_control->rings[i]);
4191
4192         /* If Intr is because of Tx Traffic */
4193         for (i = 0; i < config->tx_fifo_num; i++)
4194                 tx_intr_handler(&mac_control->fifos[i]);
4195
4196         /*
4197          * If the Rx buffer count is below the panic threshold then
4198          * reallocate the buffers from the interrupt handler itself,
4199          * else schedule a tasklet to reallocate the buffers.
4200          */
4201         for (i = 0; i < config->rx_ring_num; i++)
4202                 s2io_chk_rx_buffers(sp, i);
4203
4204         atomic_dec(&sp->isr_cnt);
4205         return IRQ_HANDLED;
4206 }
4207
4208 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4209 {
4210         struct ring_info *ring = (struct ring_info *)dev_id;
4211         struct s2io_nic *sp = ring->nic;
4212
4213         atomic_inc(&sp->isr_cnt);
4214
4215         rx_intr_handler(ring);
4216         s2io_chk_rx_buffers(sp, ring->ring_no);
4217
4218         atomic_dec(&sp->isr_cnt);
4219         return IRQ_HANDLED;
4220 }
4221
4222 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4223 {
4224         struct fifo_info *fifo = (struct fifo_info *)dev_id;
4225         struct s2io_nic *sp = fifo->nic;
4226
4227         atomic_inc(&sp->isr_cnt);
4228         tx_intr_handler(fifo);
4229         atomic_dec(&sp->isr_cnt);
4230         return IRQ_HANDLED;
4231 }
4232 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4233 {
4234         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4235         u64 val64;
4236
4237         val64 = readq(&bar0->pic_int_status);
4238         if (val64 & PIC_INT_GPIO) {
4239                 val64 = readq(&bar0->gpio_int_reg);
4240                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4241                     (val64 & GPIO_INT_REG_LINK_UP)) {
4242                         /*
4243                          * This is unstable state so clear both up/down
4244                          * interrupt and adapter to re-evaluate the link state.
4245                          */
4246                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4247                         val64 |= GPIO_INT_REG_LINK_UP;
4248                         writeq(val64, &bar0->gpio_int_reg);
4249                         val64 = readq(&bar0->gpio_int_mask);
4250                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4251                                    GPIO_INT_MASK_LINK_DOWN);
4252                         writeq(val64, &bar0->gpio_int_mask);
4253                 }
4254                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4255                         val64 = readq(&bar0->adapter_status);
4256                                 /* Enable Adapter */
4257                         val64 = readq(&bar0->adapter_control);
4258                         val64 |= ADAPTER_CNTL_EN;
4259                         writeq(val64, &bar0->adapter_control);
4260                         val64 |= ADAPTER_LED_ON;
4261                         writeq(val64, &bar0->adapter_control);
4262                         if (!sp->device_enabled_once)
4263                                 sp->device_enabled_once = 1;
4264
4265                         s2io_link(sp, LINK_UP);
4266                         /*
4267                          * unmask link down interrupt and mask link-up
4268                          * intr
4269                          */
4270                         val64 = readq(&bar0->gpio_int_mask);
4271                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4272                         val64 |= GPIO_INT_MASK_LINK_UP;
4273                         writeq(val64, &bar0->gpio_int_mask);
4274
4275                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4276                         val64 = readq(&bar0->adapter_status);
4277                         s2io_link(sp, LINK_DOWN);
4278                         /* Link is down so unmaks link up interrupt */
4279                         val64 = readq(&bar0->gpio_int_mask);
4280                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4281                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4282                         writeq(val64, &bar0->gpio_int_mask);
4283
4284                         /* turn off LED */
4285                         val64 = readq(&bar0->adapter_control);
4286                         val64 = val64 &(~ADAPTER_LED_ON);
4287                         writeq(val64, &bar0->adapter_control);
4288                 }
4289         }
4290         val64 = readq(&bar0->gpio_int_mask);
4291 }
4292
4293 /**
4294  *  s2io_isr - ISR handler of the device .
4295  *  @irq: the irq of the device.
4296  *  @dev_id: a void pointer to the dev structure of the NIC.
4297  *  Description:  This function is the ISR handler of the device. It
4298  *  identifies the reason for the interrupt and calls the relevant
4299  *  service routines. As a contongency measure, this ISR allocates the
4300  *  recv buffers, if their numbers are below the panic value which is
4301  *  presently set to 25% of the original number of rcv buffers allocated.
4302  *  Return value:
4303  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4304  *   IRQ_NONE: will be returned if interrupt is not from our device
4305  */
4306 static irqreturn_t s2io_isr(int irq, void *dev_id)
4307 {
4308         struct net_device *dev = (struct net_device *) dev_id;
4309         struct s2io_nic *sp = dev->priv;
4310         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4311         int i;
4312         u64 reason = 0;
4313         struct mac_info *mac_control;
4314         struct config_param *config;
4315
4316         atomic_inc(&sp->isr_cnt);
4317         mac_control = &sp->mac_control;
4318         config = &sp->config;
4319
4320         /*
4321          * Identify the cause for interrupt and call the appropriate
4322          * interrupt handler. Causes for the interrupt could be;
4323          * 1. Rx of packet.
4324          * 2. Tx complete.
4325          * 3. Link down.
4326          * 4. Error in any functional blocks of the NIC.
4327          */
4328         reason = readq(&bar0->general_int_status);
4329
4330         if (!reason) {
4331                 /* The interrupt was not raised by us. */
4332                 atomic_dec(&sp->isr_cnt);
4333                 return IRQ_NONE;
4334         }
4335         else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4336                 /* Disable device and get out */
4337                 atomic_dec(&sp->isr_cnt);
4338                 return IRQ_NONE;
4339         }
4340
4341         if (napi) {
4342                 if (reason & GEN_INTR_RXTRAFFIC) {
4343                         if ( likely ( netif_rx_schedule_prep(dev)) ) {
4344                                 __netif_rx_schedule(dev);
4345                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4346                         }
4347                         else
4348                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4349                 }
4350         } else {
4351                 /*
4352                  * Rx handler is called by default, without checking for the
4353                  * cause of interrupt.
4354                  * rx_traffic_int reg is an R1 register, writing all 1's
4355                  * will ensure that the actual interrupt causing bit get's
4356                  * cleared and hence a read can be avoided.
4357                  */
4358                 if (reason & GEN_INTR_RXTRAFFIC)
4359                         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4360
4361                 for (i = 0; i < config->rx_ring_num; i++) {
4362                         rx_intr_handler(&mac_control->rings[i]);
4363                 }
4364         }
4365
4366         /*
4367          * tx_traffic_int reg is an R1 register, writing all 1's
4368          * will ensure that the actual interrupt causing bit get's
4369          * cleared and hence a read can be avoided.
4370          */
4371         if (reason & GEN_INTR_TXTRAFFIC)
4372                 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4373
4374         for (i = 0; i < config->tx_fifo_num; i++)
4375                 tx_intr_handler(&mac_control->fifos[i]);
4376
4377         if (reason & GEN_INTR_TXPIC)
4378                 s2io_txpic_intr_handle(sp);
4379         /*
4380          * If the Rx buffer count is below the panic threshold then
4381          * reallocate the buffers from the interrupt handler itself,
4382          * else schedule a tasklet to reallocate the buffers.
4383          */
4384         if (!napi) {
4385                 for (i = 0; i < config->rx_ring_num; i++)
4386                         s2io_chk_rx_buffers(sp, i);
4387         }
4388
4389         writeq(0, &bar0->general_int_mask);
4390         readl(&bar0->general_int_status);
4391
4392         atomic_dec(&sp->isr_cnt);
4393         return IRQ_HANDLED;
4394 }
4395
4396 /**
4397  * s2io_updt_stats -
4398  */
4399 static void s2io_updt_stats(struct s2io_nic *sp)
4400 {
4401         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4402         u64 val64;
4403         int cnt = 0;
4404
4405         if (atomic_read(&sp->card_state) == CARD_UP) {
4406                 /* Apprx 30us on a 133 MHz bus */
4407                 val64 = SET_UPDT_CLICKS(10) |
4408                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4409                 writeq(val64, &bar0->stat_cfg);
4410                 do {
4411                         udelay(100);
4412                         val64 = readq(&bar0->stat_cfg);
4413                         if (!(val64 & BIT(0)))
4414                                 break;
4415                         cnt++;
4416                         if (cnt == 5)
4417                                 break; /* Updt failed */
4418                 } while(1);
4419         }
4420 }
4421
4422 /**
4423  *  s2io_get_stats - Updates the device statistics structure.
4424  *  @dev : pointer to the device structure.
4425  *  Description:
4426  *  This function updates the device statistics structure in the s2io_nic
4427  *  structure and returns a pointer to the same.
4428  *  Return value:
4429  *  pointer to the updated net_device_stats structure.
4430  */
4431
4432 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4433 {
4434         struct s2io_nic *sp = dev->priv;
4435         struct mac_info *mac_control;
4436         struct config_param *config;
4437
4438
4439         mac_control = &sp->mac_control;
4440         config = &sp->config;
4441
4442         /* Configure Stats for immediate updt */
4443         s2io_updt_stats(sp);
4444
4445         sp->stats.tx_packets =
4446                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4447         sp->stats.tx_errors =
4448                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4449         sp->stats.rx_errors =
4450                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4451         sp->stats.multicast =
4452                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4453         sp->stats.rx_length_errors =
4454                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4455
4456         return (&sp->stats);
4457 }
4458
4459 /**
4460  *  s2io_set_multicast - entry point for multicast address enable/disable.
4461  *  @dev : pointer to the device structure
4462  *  Description:
4463  *  This function is a driver entry point which gets called by the kernel
4464  *  whenever multicast addresses must be enabled/disabled. This also gets
4465  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4466  *  determine, if multicast address must be enabled or if promiscuous mode
4467  *  is to be disabled etc.
4468  *  Return value:
4469  *  void.
4470  */
4471
4472 static void s2io_set_multicast(struct net_device *dev)
4473 {
4474         int i, j, prev_cnt;
4475         struct dev_mc_list *mclist;
4476         struct s2io_nic *sp = dev->priv;
4477         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4478         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4479             0xfeffffffffffULL;
4480         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4481         void __iomem *add;
4482
4483         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4484                 /*  Enable all Multicast addresses */
4485                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4486                        &bar0->rmac_addr_data0_mem);
4487                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4488                        &bar0->rmac_addr_data1_mem);
4489                 val64 = RMAC_ADDR_CMD_MEM_WE |
4490                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4491                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4492                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4493                 /* Wait till command completes */
4494                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4495                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4496                                         S2IO_BIT_RESET);
4497
4498                 sp->m_cast_flg = 1;
4499                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4500         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4501                 /*  Disable all Multicast addresses */
4502                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4503                        &bar0->rmac_addr_data0_mem);
4504                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4505                        &bar0->rmac_addr_data1_mem);
4506                 val64 = RMAC_ADDR_CMD_MEM_WE |
4507                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4508                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4509                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4510                 /* Wait till command completes */
4511                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4512                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4513                                         S2IO_BIT_RESET);
4514
4515                 sp->m_cast_flg = 0;
4516                 sp->all_multi_pos = 0;
4517         }
4518
4519         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4520                 /*  Put the NIC into promiscuous mode */
4521                 add = &bar0->mac_cfg;
4522                 val64 = readq(&bar0->mac_cfg);
4523                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4524
4525                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4526                 writel((u32) val64, add);
4527                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4528                 writel((u32) (val64 >> 32), (add + 4));
4529
4530                 if (vlan_tag_strip != 1) {
4531                         val64 = readq(&bar0->rx_pa_cfg);
4532                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4533                         writeq(val64, &bar0->rx_pa_cfg);
4534                         vlan_strip_flag = 0;
4535                 }
4536
4537                 val64 = readq(&bar0->mac_cfg);
4538                 sp->promisc_flg = 1;
4539                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4540                           dev->name);
4541         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4542                 /*  Remove the NIC from promiscuous mode */
4543                 add = &bar0->mac_cfg;
4544                 val64 = readq(&bar0->mac_cfg);
4545                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4546
4547                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4548                 writel((u32) val64, add);
4549                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4550                 writel((u32) (val64 >> 32), (add + 4));
4551
4552                 if (vlan_tag_strip != 0) {
4553                         val64 = readq(&bar0->rx_pa_cfg);
4554                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4555                         writeq(val64, &bar0->rx_pa_cfg);
4556                         vlan_strip_flag = 1;
4557                 }
4558
4559                 val64 = readq(&bar0->mac_cfg);
4560                 sp->promisc_flg = 0;
4561                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4562                           dev->name);
4563         }
4564
4565         /*  Update individual M_CAST address list */
4566         if ((!sp->m_cast_flg) && dev->mc_count) {
4567                 if (dev->mc_count >
4568                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4569                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4570                                   dev->name);
4571                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4572                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4573                         return;
4574                 }
4575
4576                 prev_cnt = sp->mc_addr_count;
4577                 sp->mc_addr_count = dev->mc_count;
4578
4579                 /* Clear out the previous list of Mc in the H/W. */
4580                 for (i = 0; i < prev_cnt; i++) {
4581                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4582                                &bar0->rmac_addr_data0_mem);
4583                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4584                                 &bar0->rmac_addr_data1_mem);
4585                         val64 = RMAC_ADDR_CMD_MEM_WE |
4586                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4587                             RMAC_ADDR_CMD_MEM_OFFSET
4588                             (MAC_MC_ADDR_START_OFFSET + i);
4589                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4590
4591                         /* Wait for command completes */
4592                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4593                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4594                                         S2IO_BIT_RESET)) {
4595                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4596                                           dev->name);
4597                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4598                                 return;
4599                         }
4600                 }
4601
4602                 /* Create the new Rx filter list and update the same in H/W. */
4603                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4604                      i++, mclist = mclist->next) {
4605                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4606                                ETH_ALEN);
4607                         mac_addr = 0;
4608                         for (j = 0; j < ETH_ALEN; j++) {
4609                                 mac_addr |= mclist->dmi_addr[j];
4610                                 mac_addr <<= 8;
4611                         }
4612                         mac_addr >>= 8;
4613                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4614                                &bar0->rmac_addr_data0_mem);
4615                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4616                                 &bar0->rmac_addr_data1_mem);
4617                         val64 = RMAC_ADDR_CMD_MEM_WE |
4618                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4619                             RMAC_ADDR_CMD_MEM_OFFSET
4620                             (i + MAC_MC_ADDR_START_OFFSET);
4621                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4622
4623                         /* Wait for command completes */
4624                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4625                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4626                                         S2IO_BIT_RESET)) {
4627                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4628                                           dev->name);
4629                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4630                                 return;
4631                         }
4632                 }
4633         }
4634 }
4635
4636 /**
4637  *  s2io_set_mac_addr - Programs the Xframe mac address
4638  *  @dev : pointer to the device structure.
4639  *  @addr: a uchar pointer to the new mac address which is to be set.
4640  *  Description : This procedure will program the Xframe to receive
4641  *  frames with new Mac Address
4642  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4643  *  as defined in errno.h file on failure.
4644  */
4645
4646 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4647 {
4648         struct s2io_nic *sp = dev->priv;
4649         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4650         register u64 val64, mac_addr = 0;
4651         int i;
4652         u64 old_mac_addr = 0;
4653
4654         /*
4655          * Set the new MAC address as the new unicast filter and reflect this
4656          * change on the device address registered with the OS. It will be
4657          * at offset 0.
4658          */
4659         for (i = 0; i < ETH_ALEN; i++) {
4660                 mac_addr <<= 8;
4661                 mac_addr |= addr[i];
4662                 old_mac_addr <<= 8;
4663                 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4664         }
4665
4666         if(0 == mac_addr)
4667                 return SUCCESS;
4668
4669         /* Update the internal structure with this new mac address */
4670         if(mac_addr != old_mac_addr) {
4671                 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4672                 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4673                 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4674                 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4675                 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4676                 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4677                 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
4678         }
4679
4680         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4681                &bar0->rmac_addr_data0_mem);
4682
4683         val64 =
4684             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4685             RMAC_ADDR_CMD_MEM_OFFSET(0);
4686         writeq(val64, &bar0->rmac_addr_cmd_mem);
4687         /* Wait till command completes */
4688         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4689                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
4690                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4691                 return FAILURE;
4692         }
4693
4694         return SUCCESS;
4695 }
4696
4697 /**
4698  * s2io_ethtool_sset - Sets different link parameters.
4699  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4700  * @info: pointer to the structure with parameters given by ethtool to set
4701  * link information.
4702  * Description:
4703  * The function sets different link parameters provided by the user onto
4704  * the NIC.
4705  * Return value:
4706  * 0 on success.
4707 */
4708
4709 static int s2io_ethtool_sset(struct net_device *dev,
4710                              struct ethtool_cmd *info)
4711 {
4712         struct s2io_nic *sp = dev->priv;
4713         if ((info->autoneg == AUTONEG_ENABLE) ||
4714             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4715                 return -EINVAL;
4716         else {
4717                 s2io_close(sp->dev);
4718                 s2io_open(sp->dev);
4719         }
4720
4721         return 0;
4722 }
4723
4724 /**
4725  * s2io_ethtol_gset - Return link specific information.
4726  * @sp : private member of the device structure, pointer to the
4727  *      s2io_nic structure.
4728  * @info : pointer to the structure with parameters given by ethtool
4729  * to return link information.
4730  * Description:
4731  * Returns link specific information like speed, duplex etc.. to ethtool.
4732  * Return value :
4733  * return 0 on success.
4734  */
4735
4736 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4737 {
4738         struct s2io_nic *sp = dev->priv;
4739         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4740         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4741         info->port = PORT_FIBRE;
4742         /* info->transceiver?? TODO */
4743
4744         if (netif_carrier_ok(sp->dev)) {
4745                 info->speed = 10000;
4746                 info->duplex = DUPLEX_FULL;
4747         } else {
4748                 info->speed = -1;
4749                 info->duplex = -1;
4750         }
4751
4752         info->autoneg = AUTONEG_DISABLE;
4753         return 0;
4754 }
4755
4756 /**
4757  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4758  * @sp : private member of the device structure, which is a pointer to the
4759  * s2io_nic structure.
4760  * @info : pointer to the structure with parameters given by ethtool to
4761  * return driver information.
4762  * Description:
4763  * Returns driver specefic information like name, version etc.. to ethtool.
4764  * Return value:
4765  *  void
4766  */
4767
4768 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4769                                   struct ethtool_drvinfo *info)
4770 {
4771         struct s2io_nic *sp = dev->priv;
4772
4773         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4774         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4775         strncpy(info->fw_version, "", sizeof(info->fw_version));
4776         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4777         info->regdump_len = XENA_REG_SPACE;
4778         info->eedump_len = XENA_EEPROM_SPACE;
4779         info->testinfo_len = S2IO_TEST_LEN;
4780
4781         if (sp->device_type == XFRAME_I_DEVICE)
4782                 info->n_stats = XFRAME_I_STAT_LEN;
4783         else
4784                 info->n_stats = XFRAME_II_STAT_LEN;
4785 }
4786
4787 /**
4788  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4789  *  @sp: private member of the device structure, which is a pointer to the
4790  *  s2io_nic structure.
4791  *  @regs : pointer to the structure with parameters given by ethtool for
4792  *  dumping the registers.
4793  *  @reg_space: The input argumnet into which all the registers are dumped.
4794  *  Description:
4795  *  Dumps the entire register space of xFrame NIC into the user given
4796  *  buffer area.
4797  * Return value :
4798  * void .
4799 */
4800
4801 static void s2io_ethtool_gregs(struct net_device *dev,
4802                                struct ethtool_regs *regs, void *space)
4803 {
4804         int i;
4805         u64 reg;
4806         u8 *reg_space = (u8 *) space;
4807         struct s2io_nic *sp = dev->priv;
4808
4809         regs->len = XENA_REG_SPACE;
4810         regs->version = sp->pdev->subsystem_device;
4811
4812         for (i = 0; i < regs->len; i += 8) {
4813                 reg = readq(sp->bar0 + i);
4814                 memcpy((reg_space + i), &reg, 8);
4815         }
4816 }
4817
4818 /**
4819  *  s2io_phy_id  - timer function that alternates adapter LED.
4820  *  @data : address of the private member of the device structure, which
4821  *  is a pointer to the s2io_nic structure, provided as an u32.
4822  * Description: This is actually the timer function that alternates the
4823  * adapter LED bit of the adapter control bit to set/reset every time on
4824  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4825  *  once every second.
4826 */
4827 static void s2io_phy_id(unsigned long data)
4828 {
4829         struct s2io_nic *sp = (struct s2io_nic *) data;
4830         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4831         u64 val64 = 0;
4832         u16 subid;
4833
4834         subid = sp->pdev->subsystem_device;
4835         if ((sp->device_type == XFRAME_II_DEVICE) ||
4836                    ((subid & 0xFF) >= 0x07)) {
4837                 val64 = readq(&bar0->gpio_control);
4838                 val64 ^= GPIO_CTRL_GPIO_0;
4839                 writeq(val64, &bar0->gpio_control);
4840         } else {
4841                 val64 = readq(&bar0->adapter_control);
4842                 val64 ^= ADAPTER_LED_ON;
4843                 writeq(val64, &bar0->adapter_control);
4844         }
4845
4846         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4847 }
4848
4849 /**
4850  * s2io_ethtool_idnic - To physically identify the nic on the system.
4851  * @sp : private member of the device structure, which is a pointer to the
4852  * s2io_nic structure.
4853  * @id : pointer to the structure with identification parameters given by
4854  * ethtool.
4855  * Description: Used to physically identify the NIC on the system.
4856  * The Link LED will blink for a time specified by the user for
4857  * identification.
4858  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4859  * identification is possible only if it's link is up.
4860  * Return value:
4861  * int , returns 0 on success
4862  */
4863
4864 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4865 {
4866         u64 val64 = 0, last_gpio_ctrl_val;
4867         struct s2io_nic *sp = dev->priv;
4868         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4869         u16 subid;
4870
4871         subid = sp->pdev->subsystem_device;
4872         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4873         if ((sp->device_type == XFRAME_I_DEVICE) &&
4874                 ((subid & 0xFF) < 0x07)) {
4875                 val64 = readq(&bar0->adapter_control);
4876                 if (!(val64 & ADAPTER_CNTL_EN)) {
4877                         printk(KERN_ERR
4878                                "Adapter Link down, cannot blink LED\n");
4879                         return -EFAULT;
4880                 }
4881         }
4882         if (sp->id_timer.function == NULL) {
4883                 init_timer(&sp->id_timer);
4884                 sp->id_timer.function = s2io_phy_id;
4885                 sp->id_timer.data = (unsigned long) sp;
4886         }
4887         mod_timer(&sp->id_timer, jiffies);
4888         if (data)
4889                 msleep_interruptible(data * HZ);
4890         else
4891                 msleep_interruptible(MAX_FLICKER_TIME);
4892         del_timer_sync(&sp->id_timer);
4893
4894         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4895                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4896                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4897         }
4898
4899         return 0;
4900 }
4901
4902 static void s2io_ethtool_gringparam(struct net_device *dev,
4903                                     struct ethtool_ringparam *ering)
4904 {
4905         struct s2io_nic *sp = dev->priv;
4906         int i,tx_desc_count=0,rx_desc_count=0;
4907
4908         if (sp->rxd_mode == RXD_MODE_1)
4909                 ering->rx_max_pending = MAX_RX_DESC_1;
4910         else if (sp->rxd_mode == RXD_MODE_3B)
4911                 ering->rx_max_pending = MAX_RX_DESC_2;
4912         else if (sp->rxd_mode == RXD_MODE_3A)
4913                 ering->rx_max_pending = MAX_RX_DESC_3;
4914
4915         ering->tx_max_pending = MAX_TX_DESC;
4916         for (i = 0 ; i < sp->config.tx_fifo_num ; i++) {
4917                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
4918         }
4919         DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
4920         ering->tx_pending = tx_desc_count;
4921         rx_desc_count = 0;
4922         for (i = 0 ; i < sp->config.rx_ring_num ; i++) {
4923                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
4924         }
4925         ering->rx_pending = rx_desc_count;
4926
4927         ering->rx_mini_max_pending = 0;
4928         ering->rx_mini_pending = 0;
4929         if(sp->rxd_mode == RXD_MODE_1)
4930                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
4931         else if (sp->rxd_mode == RXD_MODE_3B)
4932                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
4933         ering->rx_jumbo_pending = rx_desc_count;
4934 }
4935
4936 /**
4937  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4938  * @sp : private member of the device structure, which is a pointer to the
4939  *      s2io_nic structure.
4940  * @ep : pointer to the structure with pause parameters given by ethtool.
4941  * Description:
4942  * Returns the Pause frame generation and reception capability of the NIC.
4943  * Return value:
4944  *  void
4945  */
4946 static void s2io_ethtool_getpause_data(struct net_device *dev,
4947                                        struct ethtool_pauseparam *ep)
4948 {
4949         u64 val64;
4950         struct s2io_nic *sp = dev->priv;
4951         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4952
4953         val64 = readq(&bar0->rmac_pause_cfg);
4954         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4955                 ep->tx_pause = TRUE;
4956         if (val64 & RMAC_PAUSE_RX_ENABLE)
4957                 ep->rx_pause = TRUE;
4958         ep->autoneg = FALSE;
4959 }
4960
4961 /**
4962  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4963  * @sp : private member of the device structure, which is a pointer to the
4964  *      s2io_nic structure.
4965  * @ep : pointer to the structure with pause parameters given by ethtool.
4966  * Description:
4967  * It can be used to set or reset Pause frame generation or reception
4968  * support of the NIC.
4969  * Return value:
4970  * int, returns 0 on Success
4971  */
4972
4973 static int s2io_ethtool_setpause_data(struct net_device *dev,
4974                                struct ethtool_pauseparam *ep)
4975 {
4976         u64 val64;
4977         struct s2io_nic *sp = dev->priv;
4978         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4979
4980         val64 = readq(&bar0->rmac_pause_cfg);
4981         if (ep->tx_pause)
4982                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4983         else
4984                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4985         if (ep->rx_pause)
4986                 val64 |= RMAC_PAUSE_RX_ENABLE;
4987         else
4988                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4989         writeq(val64, &bar0->rmac_pause_cfg);
4990         return 0;
4991 }
4992
4993 /**
4994  * read_eeprom - reads 4 bytes of data from user given offset.
4995  * @sp : private member of the device structure, which is a pointer to the
4996  *      s2io_nic structure.
4997  * @off : offset at which the data must be written
4998  * @data : Its an output parameter where the data read at the given
4999  *      offset is stored.
5000  * Description:
5001  * Will read 4 bytes of data from the user given offset and return the
5002  * read data.
5003  * NOTE: Will allow to read only part of the EEPROM visible through the
5004  *   I2C bus.
5005  * Return value:
5006  *  -1 on failure and 0 on success.
5007  */
5008
5009 #define S2IO_DEV_ID             5
5010 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5011 {
5012         int ret = -1;
5013         u32 exit_cnt = 0;
5014         u64 val64;
5015         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5016
5017         if (sp->device_type == XFRAME_I_DEVICE) {
5018                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5019                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5020                     I2C_CONTROL_CNTL_START;
5021                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5022
5023                 while (exit_cnt < 5) {
5024                         val64 = readq(&bar0->i2c_control);
5025                         if (I2C_CONTROL_CNTL_END(val64)) {
5026                                 *data = I2C_CONTROL_GET_DATA(val64);
5027                                 ret = 0;
5028                                 break;
5029                         }
5030                         msleep(50);
5031                         exit_cnt++;
5032                 }
5033         }
5034
5035         if (sp->device_type == XFRAME_II_DEVICE) {
5036                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5037                         SPI_CONTROL_BYTECNT(0x3) |
5038                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5039                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5040                 val64 |= SPI_CONTROL_REQ;
5041                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5042                 while (exit_cnt < 5) {
5043                         val64 = readq(&bar0->spi_control);
5044                         if (val64 & SPI_CONTROL_NACK) {
5045                                 ret = 1;
5046                                 break;
5047                         } else if (val64 & SPI_CONTROL_DONE) {
5048                                 *data = readq(&bar0->spi_data);
5049                                 *data &= 0xffffff;
5050                                 ret = 0;
5051                                 break;
5052                         }
5053                         msleep(50);
5054                         exit_cnt++;
5055                 }
5056         }
5057         return ret;
5058 }
5059
5060 /**
5061  *  write_eeprom - actually writes the relevant part of the data value.
5062  *  @sp : private member of the device structure, which is a pointer to the
5063  *       s2io_nic structure.
5064  *  @off : offset at which the data must be written
5065  *  @data : The data that is to be written
5066  *  @cnt : Number of bytes of the data that are actually to be written into
5067  *  the Eeprom. (max of 3)
5068  * Description:
5069  *  Actually writes the relevant part of the data value into the Eeprom
5070  *  through the I2C bus.
5071  * Return value:
5072  *  0 on success, -1 on failure.
5073  */
5074
5075 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5076 {
5077         int exit_cnt = 0, ret = -1;
5078         u64 val64;
5079         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5080
5081         if (sp->device_type == XFRAME_I_DEVICE) {
5082                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5083                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5084                     I2C_CONTROL_CNTL_START;
5085                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5086
5087                 while (exit_cnt < 5) {
5088                         val64 = readq(&bar0->i2c_control);
5089                         if (I2C_CONTROL_CNTL_END(val64)) {
5090                                 if (!(val64 & I2C_CONTROL_NACK))
5091                                         ret = 0;
5092                                 break;
5093                         }
5094                         msleep(50);
5095                         exit_cnt++;
5096                 }
5097         }
5098
5099         if (sp->device_type == XFRAME_II_DEVICE) {
5100                 int write_cnt = (cnt == 8) ? 0 : cnt;
5101                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5102
5103                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5104                         SPI_CONTROL_BYTECNT(write_cnt) |
5105                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5106                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5107                 val64 |= SPI_CONTROL_REQ;
5108                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5109                 while (exit_cnt < 5) {
5110                         val64 = readq(&bar0->spi_control);
5111                         if (val64 & SPI_CONTROL_NACK) {
5112                                 ret = 1;
5113                                 break;
5114                         } else if (val64 & SPI_CONTROL_DONE) {
5115                                 ret = 0;
5116                                 break;
5117                         }
5118                         msleep(50);
5119                         exit_cnt++;
5120                 }
5121         }
5122         return ret;
5123 }
5124 static void s2io_vpd_read(struct s2io_nic *nic)
5125 {
5126         u8 *vpd_data;
5127         u8 data;
5128         int i=0, cnt, fail = 0;
5129         int vpd_addr = 0x80;
5130
5131         if (nic->device_type == XFRAME_II_DEVICE) {
5132                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5133                 vpd_addr = 0x80;
5134         }
5135         else {
5136                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5137                 vpd_addr = 0x50;
5138         }
5139         strcpy(nic->serial_num, "NOT AVAILABLE");
5140
5141         vpd_data = kmalloc(256, GFP_KERNEL);
5142         if (!vpd_data) {
5143                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5144                 return;
5145         }
5146         nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5147
5148         for (i = 0; i < 256; i +=4 ) {
5149                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5150                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5151                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5152                 for (cnt = 0; cnt <5; cnt++) {
5153                         msleep(2);
5154                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5155                         if (data == 0x80)
5156                                 break;
5157                 }
5158                 if (cnt >= 5) {
5159                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5160                         fail = 1;
5161                         break;
5162                 }
5163                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5164                                       (u32 *)&vpd_data[i]);
5165         }
5166
5167         if(!fail) {
5168                 /* read serial number of adapter */
5169                 for (cnt = 0; cnt < 256; cnt++) {
5170                 if ((vpd_data[cnt] == 'S') &&
5171                         (vpd_data[cnt+1] == 'N') &&
5172                         (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5173                                 memset(nic->serial_num, 0, VPD_STRING_LEN);
5174                                 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5175                                         vpd_data[cnt+2]);
5176                                 break;
5177                         }
5178                 }
5179         }
5180
5181         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5182                 memset(nic->product_name, 0, vpd_data[1]);
5183                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5184         }
5185         kfree(vpd_data);
5186         nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5187 }
5188
5189 /**
5190  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5191  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5192  *  @eeprom : pointer to the user level structure provided by ethtool,
5193  *  containing all relevant information.
5194  *  @data_buf : user defined value to be written into Eeprom.
5195  *  Description: Reads the values stored in the Eeprom at given offset
5196  *  for a given length. Stores these values int the input argument data
5197  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5198  *  Return value:
5199  *  int  0 on success
5200  */
5201
5202 static int s2io_ethtool_geeprom(struct net_device *dev,
5203                          struct ethtool_eeprom *eeprom, u8 * data_buf)
5204 {
5205         u32 i, valid;
5206         u64 data;
5207         struct s2io_nic *sp = dev->priv;
5208
5209         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5210
5211         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5212                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5213
5214         for (i = 0; i < eeprom->len; i += 4) {
5215                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5216                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5217                         return -EFAULT;
5218                 }
5219                 valid = INV(data);
5220                 memcpy((data_buf + i), &valid, 4);
5221         }
5222         return 0;
5223 }
5224
5225 /**
5226  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5227  *  @sp : private member of the device structure, which is a pointer to the
5228  *  s2io_nic structure.
5229  *  @eeprom : pointer to the user level structure provided by ethtool,
5230  *  containing all relevant information.
5231  *  @data_buf ; user defined value to be written into Eeprom.
5232  *  Description:
5233  *  Tries to write the user provided value in the Eeprom, at the offset
5234  *  given by the user.
5235  *  Return value:
5236  *  0 on success, -EFAULT on failure.
5237  */
5238
5239 static int s2io_ethtool_seeprom(struct net_device *dev,
5240                                 struct ethtool_eeprom *eeprom,
5241                                 u8 * data_buf)
5242 {
5243         int len = eeprom->len, cnt = 0;
5244         u64 valid = 0, data;
5245         struct s2io_nic *sp = dev->priv;
5246
5247         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5248                 DBG_PRINT(ERR_DBG,
5249                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5250                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5251                           eeprom->magic);
5252                 return -EFAULT;
5253         }
5254
5255         while (len) {
5256                 data = (u32) data_buf[cnt] & 0x000000FF;
5257                 if (data) {
5258                         valid = (u32) (data << 24);
5259                 } else
5260                         valid = data;
5261
5262                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5263                         DBG_PRINT(ERR_DBG,
5264                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5265                         DBG_PRINT(ERR_DBG,
5266                                   "write into the specified offset\n");
5267                         return -EFAULT;
5268                 }
5269                 cnt++;
5270                 len--;
5271         }
5272
5273         return 0;
5274 }
5275
5276 /**
5277  * s2io_register_test - reads and writes into all clock domains.
5278  * @sp : private member of the device structure, which is a pointer to the
5279  * s2io_nic structure.
5280  * @data : variable that returns the result of each of the test conducted b
5281  * by the driver.
5282  * Description:
5283  * Read and write into all clock domains. The NIC has 3 clock domains,
5284  * see that registers in all the three regions are accessible.
5285  * Return value:
5286  * 0 on success.
5287  */
5288
5289 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5290 {
5291         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5292         u64 val64 = 0, exp_val;
5293         int fail = 0;
5294
5295         val64 = readq(&bar0->pif_rd_swapper_fb);
5296         if (val64 != 0x123456789abcdefULL) {
5297                 fail = 1;
5298                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5299         }
5300
5301         val64 = readq(&bar0->rmac_pause_cfg);
5302         if (val64 != 0xc000ffff00000000ULL) {
5303                 fail = 1;
5304                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5305         }
5306
5307         val64 = readq(&bar0->rx_queue_cfg);
5308         if (sp->device_type == XFRAME_II_DEVICE)
5309                 exp_val = 0x0404040404040404ULL;
5310         else
5311                 exp_val = 0x0808080808080808ULL;
5312         if (val64 != exp_val) {
5313                 fail = 1;
5314                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5315         }
5316
5317         val64 = readq(&bar0->xgxs_efifo_cfg);
5318         if (val64 != 0x000000001923141EULL) {
5319                 fail = 1;
5320                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5321         }
5322
5323         val64 = 0x5A5A5A5A5A5A5A5AULL;
5324         writeq(val64, &bar0->xmsi_data);
5325         val64 = readq(&bar0->xmsi_data);
5326         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5327                 fail = 1;
5328                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5329         }
5330
5331         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5332         writeq(val64, &bar0->xmsi_data);
5333         val64 = readq(&bar0->xmsi_data);
5334         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5335                 fail = 1;
5336                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5337         }
5338
5339         *data = fail;
5340         return fail;
5341 }
5342
5343 /**
5344  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5345  * @sp : private member of the device structure, which is a pointer to the
5346  * s2io_nic structure.
5347  * @data:variable that returns the result of each of the test conducted by
5348  * the driver.
5349  * Description:
5350  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5351  * register.
5352  * Return value:
5353  * 0 on success.
5354  */
5355
5356 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5357 {
5358         int fail = 0;
5359         u64 ret_data, org_4F0, org_7F0;
5360         u8 saved_4F0 = 0, saved_7F0 = 0;
5361         struct net_device *dev = sp->dev;
5362
5363         /* Test Write Error at offset 0 */
5364         /* Note that SPI interface allows write access to all areas
5365          * of EEPROM. Hence doing all negative testing only for Xframe I.
5366          */
5367         if (sp->device_type == XFRAME_I_DEVICE)
5368                 if (!write_eeprom(sp, 0, 0, 3))
5369                         fail = 1;
5370
5371         /* Save current values at offsets 0x4F0 and 0x7F0 */
5372         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5373                 saved_4F0 = 1;
5374         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5375                 saved_7F0 = 1;
5376
5377         /* Test Write at offset 4f0 */
5378         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5379                 fail = 1;
5380         if (read_eeprom(sp, 0x4F0, &ret_data))
5381                 fail = 1;
5382
5383         if (ret_data != 0x012345) {
5384                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5385                         "Data written %llx Data read %llx\n",
5386                         dev->name, (unsigned long long)0x12345,
5387                         (unsigned long long)ret_data);
5388                 fail = 1;
5389         }
5390
5391         /* Reset the EEPROM data go FFFF */
5392         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5393
5394         /* Test Write Request Error at offset 0x7c */
5395         if (sp->device_type == XFRAME_I_DEVICE)
5396                 if (!write_eeprom(sp, 0x07C, 0, 3))
5397                         fail = 1;
5398
5399         /* Test Write Request at offset 0x7f0 */
5400         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5401                 fail = 1;
5402         if (read_eeprom(sp, 0x7F0, &ret_data))
5403                 fail = 1;
5404
5405         if (ret_data != 0x012345) {
5406                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5407                         "Data written %llx Data read %llx\n",
5408                         dev->name, (unsigned long long)0x12345,
5409                         (unsigned long long)ret_data);
5410                 fail = 1;
5411         }
5412
5413         /* Reset the EEPROM data go FFFF */
5414         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5415
5416         if (sp->device_type == XFRAME_I_DEVICE) {
5417                 /* Test Write Error at offset 0x80 */
5418                 if (!write_eeprom(sp, 0x080, 0, 3))
5419                         fail = 1;
5420
5421                 /* Test Write Error at offset 0xfc */
5422                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5423                         fail = 1;
5424
5425                 /* Test Write Error at offset 0x100 */
5426                 if (!write_eeprom(sp, 0x100, 0, 3))
5427                         fail = 1;
5428
5429                 /* Test Write Error at offset 4ec */
5430                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5431                         fail = 1;
5432         }
5433
5434         /* Restore values at offsets 0x4F0 and 0x7F0 */
5435         if (saved_4F0)
5436                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5437         if (saved_7F0)
5438                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5439
5440         *data = fail;
5441         return fail;
5442 }
5443
5444 /**
5445  * s2io_bist_test - invokes the MemBist test of the card .
5446  * @sp : private member of the device structure, which is a pointer to the
5447  * s2io_nic structure.
5448  * @data:variable that returns the result of each of the test conducted by
5449  * the driver.
5450  * Description:
5451  * This invokes the MemBist test of the card. We give around
5452  * 2 secs time for the Test to complete. If it's still not complete
5453  * within this peiod, we consider that the test failed.
5454  * Return value:
5455  * 0 on success and -1 on failure.
5456  */
5457
5458 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5459 {
5460         u8 bist = 0;
5461         int cnt = 0, ret = -1;
5462
5463         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5464         bist |= PCI_BIST_START;
5465         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5466
5467         while (cnt < 20) {
5468                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5469                 if (!(bist & PCI_BIST_START)) {
5470                         *data = (bist & PCI_BIST_CODE_MASK);
5471                         ret = 0;
5472                         break;
5473                 }
5474                 msleep(100);
5475                 cnt++;
5476         }
5477
5478         return ret;
5479 }
5480
5481 /**
5482  * s2io-link_test - verifies the link state of the nic
5483  * @sp ; private member of the device structure, which is a pointer to the
5484  * s2io_nic structure.
5485  * @data: variable that returns the result of each of the test conducted by
5486  * the driver.
5487  * Description:
5488  * The function verifies the link state of the NIC and updates the input
5489  * argument 'data' appropriately.
5490  * Return value:
5491  * 0 on success.
5492  */
5493
5494 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5495 {
5496         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5497         u64 val64;
5498
5499         val64 = readq(&bar0->adapter_status);
5500         if(!(LINK_IS_UP(val64)))
5501                 *data = 1;
5502         else
5503                 *data = 0;
5504
5505         return *data;
5506 }
5507
5508 /**
5509  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5510  * @sp - private member of the device structure, which is a pointer to the
5511  * s2io_nic structure.
5512  * @data - variable that returns the result of each of the test
5513  * conducted by the driver.
5514  * Description:
5515  *  This is one of the offline test that tests the read and write
5516  *  access to the RldRam chip on the NIC.
5517  * Return value:
5518  *  0 on success.
5519  */
5520
5521 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5522 {
5523         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5524         u64 val64;
5525         int cnt, iteration = 0, test_fail = 0;
5526
5527         val64 = readq(&bar0->adapter_control);
5528         val64 &= ~ADAPTER_ECC_EN;
5529         writeq(val64, &bar0->adapter_control);
5530
5531         val64 = readq(&bar0->mc_rldram_test_ctrl);
5532         val64 |= MC_RLDRAM_TEST_MODE;
5533         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5534
5535         val64 = readq(&bar0->mc_rldram_mrs);
5536         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5537         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5538
5539         val64 |= MC_RLDRAM_MRS_ENABLE;
5540         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5541
5542         while (iteration < 2) {
5543                 val64 = 0x55555555aaaa0000ULL;
5544                 if (iteration == 1) {
5545                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5546                 }
5547                 writeq(val64, &bar0->mc_rldram_test_d0);
5548
5549                 val64 = 0xaaaa5a5555550000ULL;
5550                 if (iteration == 1) {
5551                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5552                 }
5553                 writeq(val64, &bar0->mc_rldram_test_d1);
5554
5555                 val64 = 0x55aaaaaaaa5a0000ULL;
5556                 if (iteration == 1) {
5557                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5558                 }
5559                 writeq(val64, &bar0->mc_rldram_test_d2);
5560
5561                 val64 = (u64) (0x0000003ffffe0100ULL);
5562                 writeq(val64, &bar0->mc_rldram_test_add);
5563
5564                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5565                         MC_RLDRAM_TEST_GO;
5566                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5567
5568                 for (cnt = 0; cnt < 5; cnt++) {
5569                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5570                         if (val64 & MC_RLDRAM_TEST_DONE)
5571                                 break;
5572                         msleep(200);
5573                 }
5574
5575                 if (cnt == 5)
5576                         break;
5577
5578                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5579                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5580
5581                 for (cnt = 0; cnt < 5; cnt++) {
5582                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5583                         if (val64 & MC_RLDRAM_TEST_DONE)
5584                                 break;
5585                         msleep(500);
5586                 }
5587
5588                 if (cnt == 5)
5589                         break;
5590
5591                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5592                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5593                         test_fail = 1;
5594
5595                 iteration++;
5596         }
5597
5598         *data = test_fail;
5599
5600         /* Bring the adapter out of test mode */
5601         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5602
5603         return test_fail;
5604 }
5605
5606 /**
5607  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5608  *  @sp : private member of the device structure, which is a pointer to the
5609  *  s2io_nic structure.
5610  *  @ethtest : pointer to a ethtool command specific structure that will be
5611  *  returned to the user.
5612  *  @data : variable that returns the result of each of the test
5613  * conducted by the driver.
5614  * Description:
5615  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5616  *  the health of the card.
5617  * Return value:
5618  *  void
5619  */
5620
5621 static void s2io_ethtool_test(struct net_device *dev,
5622                               struct ethtool_test *ethtest,
5623                               uint64_t * data)
5624 {
5625         struct s2io_nic *sp = dev->priv;
5626         int orig_state = netif_running(sp->dev);
5627
5628         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5629                 /* Offline Tests. */
5630                 if (orig_state)
5631                         s2io_close(sp->dev);
5632
5633                 if (s2io_register_test(sp, &data[0]))
5634                         ethtest->flags |= ETH_TEST_FL_FAILED;
5635
5636                 s2io_reset(sp);
5637
5638                 if (s2io_rldram_test(sp, &data[3]))
5639                         ethtest->flags |= ETH_TEST_FL_FAILED;
5640
5641                 s2io_reset(sp);
5642
5643                 if (s2io_eeprom_test(sp, &data[1]))
5644                         ethtest->flags |= ETH_TEST_FL_FAILED;
5645
5646                 if (s2io_bist_test(sp, &data[4]))
5647                         ethtest->flags |= ETH_TEST_FL_FAILED;
5648
5649                 if (orig_state)
5650                         s2io_open(sp->dev);
5651
5652                 data[2] = 0;
5653         } else {
5654                 /* Online Tests. */
5655                 if (!orig_state) {
5656                         DBG_PRINT(ERR_DBG,
5657                                   "%s: is not up, cannot run test\n",
5658                                   dev->name);
5659                         data[0] = -1;
5660                         data[1] = -1;
5661                         data[2] = -1;
5662                         data[3] = -1;
5663                         data[4] = -1;
5664                 }
5665
5666                 if (s2io_link_test(sp, &data[2]))
5667                         ethtest->flags |= ETH_TEST_FL_FAILED;
5668
5669                 data[0] = 0;
5670                 data[1] = 0;
5671                 data[3] = 0;
5672                 data[4] = 0;
5673         }
5674 }
5675
5676 static void s2io_get_ethtool_stats(struct net_device *dev,
5677                                    struct ethtool_stats *estats,
5678                                    u64 * tmp_stats)
5679 {
5680         int i = 0;
5681         struct s2io_nic *sp = dev->priv;
5682         struct stat_block *stat_info = sp->mac_control.stats_info;
5683
5684         s2io_updt_stats(sp);
5685         tmp_stats[i++] =
5686                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5687                 le32_to_cpu(stat_info->tmac_frms);
5688         tmp_stats[i++] =
5689                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5690                 le32_to_cpu(stat_info->tmac_data_octets);
5691         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5692         tmp_stats[i++] =
5693                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5694                 le32_to_cpu(stat_info->tmac_mcst_frms);
5695         tmp_stats[i++] =
5696                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5697                 le32_to_cpu(stat_info->tmac_bcst_frms);
5698         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5699         tmp_stats[i++] =
5700                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5701                 le32_to_cpu(stat_info->tmac_ttl_octets);
5702         tmp_stats[i++] =
5703                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5704                 le32_to_cpu(stat_info->tmac_ucst_frms);
5705         tmp_stats[i++] =
5706                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5707                 le32_to_cpu(stat_info->tmac_nucst_frms);
5708         tmp_stats[i++] =
5709                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5710                 le32_to_cpu(stat_info->tmac_any_err_frms);
5711         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5712         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5713         tmp_stats[i++] =
5714                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5715                 le32_to_cpu(stat_info->tmac_vld_ip);
5716         tmp_stats[i++] =
5717                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5718                 le32_to_cpu(stat_info->tmac_drop_ip);
5719         tmp_stats[i++] =
5720                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5721                 le32_to_cpu(stat_info->tmac_icmp);
5722         tmp_stats[i++] =
5723                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5724                 le32_to_cpu(stat_info->tmac_rst_tcp);
5725         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5726         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5727                 le32_to_cpu(stat_info->tmac_udp);
5728         tmp_stats[i++] =
5729                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5730                 le32_to_cpu(stat_info->rmac_vld_frms);
5731         tmp_stats[i++] =
5732                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5733                 le32_to_cpu(stat_info->rmac_data_octets);
5734         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5735         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5736         tmp_stats[i++] =
5737                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5738                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5739         tmp_stats[i++] =
5740                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5741                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5742         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5743         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5744         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5745         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5746         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5747         tmp_stats[i++] =
5748                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5749                 le32_to_cpu(stat_info->rmac_ttl_octets);
5750         tmp_stats[i++] =
5751                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5752                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5753         tmp_stats[i++] =
5754                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5755                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5756         tmp_stats[i++] =
5757                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5758                 le32_to_cpu(stat_info->rmac_discarded_frms);
5759         tmp_stats[i++] =
5760                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5761                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5762         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5763         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5764         tmp_stats[i++] =
5765                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5766                 le32_to_cpu(stat_info->rmac_usized_frms);
5767         tmp_stats[i++] =
5768                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5769                 le32_to_cpu(stat_info->rmac_osized_frms);
5770         tmp_stats[i++] =
5771                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5772                 le32_to_cpu(stat_info->rmac_frag_frms);
5773         tmp_stats[i++] =
5774                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5775                 le32_to_cpu(stat_info->rmac_jabber_frms);
5776         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5777         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5778         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5779         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5780         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5781         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5782         tmp_stats[i++] =
5783                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5784                 le32_to_cpu(stat_info->rmac_ip);
5785         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5786         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5787         tmp_stats[i++] =
5788                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5789                 le32_to_cpu(stat_info->rmac_drop_ip);
5790         tmp_stats[i++] =
5791                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5792                 le32_to_cpu(stat_info->rmac_icmp);
5793         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5794         tmp_stats[i++] =
5795                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5796                 le32_to_cpu(stat_info->rmac_udp);
5797         tmp_stats[i++] =
5798                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5799                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5800         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5801         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5802         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5803         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5804         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5805         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5806         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5807         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5808         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5809         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5810         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5811         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5812         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5813         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5814         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5815         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5816         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5817         tmp_stats[i++] =
5818                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5819                 le32_to_cpu(stat_info->rmac_pause_cnt);
5820         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5821         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5822         tmp_stats[i++] =
5823                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5824                 le32_to_cpu(stat_info->rmac_accepted_ip);
5825         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5826         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5827         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5828         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5829         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5830         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5831         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5832         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5833         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5834         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5835         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5836         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5837         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5838         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5839         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5840         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5841         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5842         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5843         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5844
5845         /* Enhanced statistics exist only for Hercules */
5846         if(sp->device_type == XFRAME_II_DEVICE) {
5847                 tmp_stats[i++] =
5848                                 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5849                 tmp_stats[i++] =
5850                                 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5851                 tmp_stats[i++] =
5852                                 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5853                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5854                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5855                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5856                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5857                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5858                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5859                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5860                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5861                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5862                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5863                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5864                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5865                 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5866         }
5867
5868         tmp_stats[i++] = 0;
5869         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5870         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5871         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5872         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5873         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5874         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5875         tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5876         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5877         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5878         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5879         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5880         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5881         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5882         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5883         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5884         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5885         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5886         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5887         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5888         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5889         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5890         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5891         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5892         if (stat_info->sw_stat.num_aggregations) {
5893                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5894                 int count = 0;
5895                 /*
5896                  * Since 64-bit divide does not work on all platforms,
5897                  * do repeated subtraction.
5898                  */
5899                 while (tmp >= stat_info->sw_stat.num_aggregations) {
5900                         tmp -= stat_info->sw_stat.num_aggregations;
5901                         count++;
5902                 }
5903                 tmp_stats[i++] = count;
5904         }
5905         else
5906                 tmp_stats[i++] = 0;
5907         tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
5908         tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
5909         tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
5910         tmp_stats[i++] = stat_info->sw_stat.mem_freed;
5911         tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
5912         tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
5913         tmp_stats[i++] = stat_info->sw_stat.link_up_time;
5914         tmp_stats[i++] = stat_info->sw_stat.link_down_time;
5915
5916         tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
5917         tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
5918         tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
5919         tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
5920         tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
5921
5922         tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
5923         tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
5924         tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
5925         tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
5926         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
5927         tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
5928         tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
5929         tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
5930         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
5931 }
5932
5933 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5934 {
5935         return (XENA_REG_SPACE);
5936 }
5937
5938
5939 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5940 {
5941         struct s2io_nic *sp = dev->priv;
5942
5943         return (sp->rx_csum);
5944 }
5945
5946 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5947 {
5948         struct s2io_nic *sp = dev->priv;
5949
5950         if (data)
5951                 sp->rx_csum = 1;
5952         else
5953                 sp->rx_csum = 0;
5954
5955         return 0;
5956 }
5957
5958 static int s2io_get_eeprom_len(struct net_device *dev)
5959 {
5960         return (XENA_EEPROM_SPACE);
5961 }
5962
5963 static int s2io_ethtool_self_test_count(struct net_device *dev)
5964 {
5965         return (S2IO_TEST_LEN);
5966 }
5967
5968 static void s2io_ethtool_get_strings(struct net_device *dev,
5969                                      u32 stringset, u8 * data)
5970 {
5971         int stat_size = 0;
5972         struct s2io_nic *sp = dev->priv;
5973
5974         switch (stringset) {
5975         case ETH_SS_TEST:
5976                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5977                 break;
5978         case ETH_SS_STATS:
5979                 stat_size = sizeof(ethtool_xena_stats_keys);
5980                 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5981                 if(sp->device_type == XFRAME_II_DEVICE) {
5982                         memcpy(data + stat_size,
5983                                 &ethtool_enhanced_stats_keys,
5984                                 sizeof(ethtool_enhanced_stats_keys));
5985                         stat_size += sizeof(ethtool_enhanced_stats_keys);
5986                 }
5987
5988                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
5989                         sizeof(ethtool_driver_stats_keys));
5990         }
5991 }
5992 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5993 {
5994         struct s2io_nic *sp = dev->priv;
5995         int stat_count = 0;
5996         switch(sp->device_type) {
5997         case XFRAME_I_DEVICE:
5998                 stat_count = XFRAME_I_STAT_LEN;
5999         break;
6000
6001         case XFRAME_II_DEVICE:
6002                 stat_count = XFRAME_II_STAT_LEN;
6003         break;
6004         }
6005
6006         return stat_count;
6007 }
6008
6009 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6010 {
6011         if (data)
6012                 dev->features |= NETIF_F_IP_CSUM;
6013         else
6014                 dev->features &= ~NETIF_F_IP_CSUM;
6015
6016         return 0;
6017 }
6018
6019 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6020 {
6021         return (dev->features & NETIF_F_TSO) != 0;
6022 }
6023 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6024 {
6025         if (data)
6026                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6027         else
6028                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6029
6030         return 0;
6031 }
6032
6033 static const struct ethtool_ops netdev_ethtool_ops = {
6034         .get_settings = s2io_ethtool_gset,
6035         .set_settings = s2io_ethtool_sset,
6036         .get_drvinfo = s2io_ethtool_gdrvinfo,
6037         .get_regs_len = s2io_ethtool_get_regs_len,
6038         .get_regs = s2io_ethtool_gregs,
6039         .get_link = ethtool_op_get_link,
6040         .get_eeprom_len = s2io_get_eeprom_len,
6041         .get_eeprom = s2io_ethtool_geeprom,
6042         .set_eeprom = s2io_ethtool_seeprom,
6043         .get_ringparam = s2io_ethtool_gringparam,
6044         .get_pauseparam = s2io_ethtool_getpause_data,
6045         .set_pauseparam = s2io_ethtool_setpause_data,
6046         .get_rx_csum = s2io_ethtool_get_rx_csum,
6047         .set_rx_csum = s2io_ethtool_set_rx_csum,
6048         .get_tx_csum = ethtool_op_get_tx_csum,
6049         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6050         .get_sg = ethtool_op_get_sg,
6051         .set_sg = ethtool_op_set_sg,
6052         .get_tso = s2io_ethtool_op_get_tso,
6053         .set_tso = s2io_ethtool_op_set_tso,
6054         .get_ufo = ethtool_op_get_ufo,
6055         .set_ufo = ethtool_op_set_ufo,
6056         .self_test_count = s2io_ethtool_self_test_count,
6057         .self_test = s2io_ethtool_test,
6058         .get_strings = s2io_ethtool_get_strings,
6059         .phys_id = s2io_ethtool_idnic,
6060         .get_stats_count = s2io_ethtool_get_stats_count,
6061         .get_ethtool_stats = s2io_get_ethtool_stats
6062 };
6063
6064 /**
6065  *  s2io_ioctl - Entry point for the Ioctl
6066  *  @dev :  Device pointer.
6067  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6068  *  a proprietary structure used to pass information to the driver.
6069  *  @cmd :  This is used to distinguish between the different commands that
6070  *  can be passed to the IOCTL functions.
6071  *  Description:
6072  *  Currently there are no special functionality supported in IOCTL, hence
6073  *  function always return EOPNOTSUPPORTED
6074  */
6075
6076 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6077 {
6078         return -EOPNOTSUPP;
6079 }
6080
6081 /**
6082  *  s2io_change_mtu - entry point to change MTU size for the device.
6083  *   @dev : device pointer.
6084  *   @new_mtu : the new MTU size for the device.
6085  *   Description: A driver entry point to change MTU size for the device.
6086  *   Before changing the MTU the device must be stopped.
6087  *  Return value:
6088  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6089  *   file on failure.
6090  */
6091
6092 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6093 {
6094         struct s2io_nic *sp = dev->priv;
6095
6096         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6097                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6098                           dev->name);
6099                 return -EPERM;
6100         }
6101
6102         dev->mtu = new_mtu;
6103         if (netif_running(dev)) {
6104                 s2io_card_down(sp);
6105                 netif_stop_queue(dev);
6106                 if (s2io_card_up(sp)) {
6107                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6108                                   __FUNCTION__);
6109                 }
6110                 if (netif_queue_stopped(dev))
6111                         netif_wake_queue(dev);
6112         } else { /* Device is down */
6113                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6114                 u64 val64 = new_mtu;
6115
6116                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6117         }
6118
6119         return 0;
6120 }
6121
6122 /**
6123  *  s2io_tasklet - Bottom half of the ISR.
6124  *  @dev_adr : address of the device structure in dma_addr_t format.
6125  *  Description:
6126  *  This is the tasklet or the bottom half of the ISR. This is
6127  *  an extension of the ISR which is scheduled by the scheduler to be run
6128  *  when the load on the CPU is low. All low priority tasks of the ISR can
6129  *  be pushed into the tasklet. For now the tasklet is used only to
6130  *  replenish the Rx buffers in the Rx buffer descriptors.
6131  *  Return value:
6132  *  void.
6133  */
6134
6135 static void s2io_tasklet(unsigned long dev_addr)
6136 {
6137         struct net_device *dev = (struct net_device *) dev_addr;
6138         struct s2io_nic *sp = dev->priv;
6139         int i, ret;
6140         struct mac_info *mac_control;
6141         struct config_param *config;
6142
6143         mac_control = &sp->mac_control;
6144         config = &sp->config;
6145
6146         if (!TASKLET_IN_USE) {
6147                 for (i = 0; i < config->rx_ring_num; i++) {
6148                         ret = fill_rx_buffers(sp, i);
6149                         if (ret == -ENOMEM) {
6150                                 DBG_PRINT(INFO_DBG, "%s: Out of ",
6151                                           dev->name);
6152                                 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6153                                 break;
6154                         } else if (ret == -EFILL) {
6155                                 DBG_PRINT(INFO_DBG,
6156                                           "%s: Rx Ring %d is full\n",
6157                                           dev->name, i);
6158                                 break;
6159                         }
6160                 }
6161                 clear_bit(0, (&sp->tasklet_status));
6162         }
6163 }
6164
6165 /**
6166  * s2io_set_link - Set the LInk status
6167  * @data: long pointer to device private structue
6168  * Description: Sets the link status for the adapter
6169  */
6170
6171 static void s2io_set_link(struct work_struct *work)
6172 {
6173         struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6174         struct net_device *dev = nic->dev;
6175         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6176         register u64 val64;
6177         u16 subid;
6178
6179         rtnl_lock();
6180
6181         if (!netif_running(dev))
6182                 goto out_unlock;
6183
6184         if (test_and_set_bit(0, &(nic->link_state))) {
6185                 /* The card is being reset, no point doing anything */
6186                 goto out_unlock;
6187         }
6188
6189         subid = nic->pdev->subsystem_device;
6190         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6191                 /*
6192                  * Allow a small delay for the NICs self initiated
6193                  * cleanup to complete.
6194                  */
6195                 msleep(100);
6196         }
6197
6198         val64 = readq(&bar0->adapter_status);
6199         if (LINK_IS_UP(val64)) {
6200                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6201                         if (verify_xena_quiescence(nic)) {
6202                                 val64 = readq(&bar0->adapter_control);
6203                                 val64 |= ADAPTER_CNTL_EN;
6204                                 writeq(val64, &bar0->adapter_control);
6205                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6206                                         nic->device_type, subid)) {
6207                                         val64 = readq(&bar0->gpio_control);
6208                                         val64 |= GPIO_CTRL_GPIO_0;
6209                                         writeq(val64, &bar0->gpio_control);
6210                                         val64 = readq(&bar0->gpio_control);
6211                                 } else {
6212                                         val64 |= ADAPTER_LED_ON;
6213                                         writeq(val64, &bar0->adapter_control);
6214                                 }
6215                                 nic->device_enabled_once = TRUE;
6216                         } else {
6217                                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6218                                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6219                                 netif_stop_queue(dev);
6220                         }
6221                 }
6222                 val64 = readq(&bar0->adapter_status);
6223                 if (!LINK_IS_UP(val64)) {
6224                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
6225                         DBG_PRINT(ERR_DBG, " Link down after enabling ");
6226                         DBG_PRINT(ERR_DBG, "device \n");
6227                 } else
6228                         s2io_link(nic, LINK_UP);
6229         } else {
6230                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6231                                                       subid)) {
6232                         val64 = readq(&bar0->gpio_control);
6233                         val64 &= ~GPIO_CTRL_GPIO_0;
6234                         writeq(val64, &bar0->gpio_control);
6235                         val64 = readq(&bar0->gpio_control);
6236                 }
6237                 s2io_link(nic, LINK_DOWN);
6238         }
6239         clear_bit(0, &(nic->link_state));
6240
6241 out_unlock:
6242         rtnl_unlock();
6243 }
6244
6245 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6246                                 struct buffAdd *ba,
6247                                 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6248                                 u64 *temp2, int size)
6249 {
6250         struct net_device *dev = sp->dev;
6251         struct sk_buff *frag_list;
6252
6253         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6254                 /* allocate skb */
6255                 if (*skb) {
6256                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6257                         /*
6258                          * As Rx frame are not going to be processed,
6259                          * using same mapped address for the Rxd
6260                          * buffer pointer
6261                          */
6262                         ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
6263                 } else {
6264                         *skb = dev_alloc_skb(size);
6265                         if (!(*skb)) {
6266                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6267                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6268                                 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6269                                 sp->mac_control.stats_info->sw_stat. \
6270                                         mem_alloc_fail_cnt++;
6271                                 return -ENOMEM ;
6272                         }
6273                         sp->mac_control.stats_info->sw_stat.mem_allocated
6274                                 += (*skb)->truesize;
6275                         /* storing the mapped addr in a temp variable
6276                          * such it will be used for next rxd whose
6277                          * Host Control is NULL
6278                          */
6279                         ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
6280                                 pci_map_single( sp->pdev, (*skb)->data,
6281                                         size - NET_IP_ALIGN,
6282                                         PCI_DMA_FROMDEVICE);
6283                         rxdp->Host_Control = (unsigned long) (*skb);
6284                 }
6285         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6286                 /* Two buffer Mode */
6287                 if (*skb) {
6288                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6289                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6290                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6291                 } else {
6292                         *skb = dev_alloc_skb(size);
6293                         if (!(*skb)) {
6294                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6295                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6296                                 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6297                                 sp->mac_control.stats_info->sw_stat. \
6298                                         mem_alloc_fail_cnt++;
6299                                 return -ENOMEM;
6300                         }
6301                         sp->mac_control.stats_info->sw_stat.mem_allocated
6302                                 += (*skb)->truesize;
6303                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
6304                                 pci_map_single(sp->pdev, (*skb)->data,
6305                                                dev->mtu + 4,
6306                                                PCI_DMA_FROMDEVICE);
6307                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
6308                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6309                                                 PCI_DMA_FROMDEVICE);
6310                         rxdp->Host_Control = (unsigned long) (*skb);
6311
6312                         /* Buffer-1 will be dummy buffer not used */
6313                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
6314                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6315                                                PCI_DMA_FROMDEVICE);
6316                 }
6317         } else if ((rxdp->Host_Control == 0)) {
6318                 /* Three buffer mode */
6319                 if (*skb) {
6320                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6321                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6322                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6323                 } else {
6324                         *skb = dev_alloc_skb(size);
6325                         if (!(*skb)) {
6326                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6327                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6328                                 DBG_PRINT(INFO_DBG, "3 buf mode SKBs\n");
6329                                 sp->mac_control.stats_info->sw_stat. \
6330                                         mem_alloc_fail_cnt++;
6331                                 return -ENOMEM;
6332                         }
6333                         sp->mac_control.stats_info->sw_stat.mem_allocated
6334                                 += (*skb)->truesize;
6335                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
6336                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6337                                                PCI_DMA_FROMDEVICE);
6338                         /* Buffer-1 receives L3/L4 headers */
6339                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
6340                                 pci_map_single( sp->pdev, (*skb)->data,
6341                                                 l3l4hdr_size + 4,
6342                                                 PCI_DMA_FROMDEVICE);
6343                         /*
6344                          * skb_shinfo(skb)->frag_list will have L4
6345                          * data payload
6346                          */
6347                         skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6348                                                                    ALIGN_SIZE);
6349                         if (skb_shinfo(*skb)->frag_list == NULL) {
6350                                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6351                                           failed\n ", dev->name);
6352                                 sp->mac_control.stats_info->sw_stat. \
6353                                         mem_alloc_fail_cnt++;
6354                                 return -ENOMEM ;
6355                         }
6356                         frag_list = skb_shinfo(*skb)->frag_list;
6357                         frag_list->next = NULL;
6358                         sp->mac_control.stats_info->sw_stat.mem_allocated
6359                                 += frag_list->truesize;
6360                         /*
6361                          * Buffer-2 receives L4 data payload
6362                          */
6363                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
6364                                 pci_map_single( sp->pdev, frag_list->data,
6365                                                 dev->mtu, PCI_DMA_FROMDEVICE);
6366                 }
6367         }
6368         return 0;
6369 }
6370 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6371                                 int size)
6372 {
6373         struct net_device *dev = sp->dev;
6374         if (sp->rxd_mode == RXD_MODE_1) {
6375                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6376         } else if (sp->rxd_mode == RXD_MODE_3B) {
6377                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6378                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6379                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6380         } else {
6381                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6382                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6383                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6384         }
6385 }
6386
6387 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6388 {
6389         int i, j, k, blk_cnt = 0, size;
6390         struct mac_info * mac_control = &sp->mac_control;
6391         struct config_param *config = &sp->config;
6392         struct net_device *dev = sp->dev;
6393         struct RxD_t *rxdp = NULL;
6394         struct sk_buff *skb = NULL;
6395         struct buffAdd *ba = NULL;
6396         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6397
6398         /* Calculate the size based on ring mode */
6399         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6400                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6401         if (sp->rxd_mode == RXD_MODE_1)
6402                 size += NET_IP_ALIGN;
6403         else if (sp->rxd_mode == RXD_MODE_3B)
6404                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6405         else
6406                 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6407
6408         for (i = 0; i < config->rx_ring_num; i++) {
6409                 blk_cnt = config->rx_cfg[i].num_rxd /
6410                         (rxd_count[sp->rxd_mode] +1);
6411
6412                 for (j = 0; j < blk_cnt; j++) {
6413                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6414                                 rxdp = mac_control->rings[i].
6415                                         rx_blocks[j].rxds[k].virt_addr;
6416                                 if(sp->rxd_mode >= RXD_MODE_3A)
6417                                         ba = &mac_control->rings[i].ba[j][k];
6418                                 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6419                                                        &skb,(u64 *)&temp0_64,
6420                                                        (u64 *)&temp1_64,
6421                                                        (u64 *)&temp2_64,
6422                                                         size) == ENOMEM) {
6423                                         return 0;
6424                                 }
6425
6426                                 set_rxd_buffer_size(sp, rxdp, size);
6427                                 wmb();
6428                                 /* flip the Ownership bit to Hardware */
6429                                 rxdp->Control_1 |= RXD_OWN_XENA;
6430                         }
6431                 }
6432         }
6433         return 0;
6434
6435 }
6436
6437 static int s2io_add_isr(struct s2io_nic * sp)
6438 {
6439         int ret = 0;
6440         struct net_device *dev = sp->dev;
6441         int err = 0;
6442
6443         if (sp->intr_type == MSI)
6444                 ret = s2io_enable_msi(sp);
6445         else if (sp->intr_type == MSI_X)
6446                 ret = s2io_enable_msi_x(sp);
6447         if (ret) {
6448                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6449                 sp->intr_type = INTA;
6450         }
6451
6452         /* Store the values of the MSIX table in the struct s2io_nic structure */
6453         store_xmsi_data(sp);
6454
6455         /* After proper initialization of H/W, register ISR */
6456         if (sp->intr_type == MSI) {
6457                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6458                         IRQF_SHARED, sp->name, dev);
6459                 if (err) {
6460                         pci_disable_msi(sp->pdev);
6461                         DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6462                                   dev->name);
6463                         return -1;
6464                 }
6465         }
6466         if (sp->intr_type == MSI_X) {
6467                 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6468
6469                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6470                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6471                                 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6472                                         dev->name, i);
6473                                 err = request_irq(sp->entries[i].vector,
6474                                           s2io_msix_fifo_handle, 0, sp->desc[i],
6475                                                   sp->s2io_entries[i].arg);
6476                                 /* If either data or addr is zero print it */
6477                                 if(!(sp->msix_info[i].addr &&
6478                                         sp->msix_info[i].data)) {
6479                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6480                                                 "Data:0x%lx\n",sp->desc[i],
6481                                                 (unsigned long long)
6482                                                 sp->msix_info[i].addr,
6483                                                 (unsigned long)
6484                                                 ntohl(sp->msix_info[i].data));
6485                                 } else {
6486                                         msix_tx_cnt++;
6487                                 }
6488                         } else {
6489                                 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6490                                         dev->name, i);
6491                                 err = request_irq(sp->entries[i].vector,
6492                                           s2io_msix_ring_handle, 0, sp->desc[i],
6493                                                   sp->s2io_entries[i].arg);
6494                                 /* If either data or addr is zero print it */
6495                                 if(!(sp->msix_info[i].addr &&
6496                                         sp->msix_info[i].data)) {
6497                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6498                                                 "Data:0x%lx\n",sp->desc[i],
6499                                                 (unsigned long long)
6500                                                 sp->msix_info[i].addr,
6501                                                 (unsigned long)
6502                                                 ntohl(sp->msix_info[i].data));
6503                                 } else {
6504                                         msix_rx_cnt++;
6505                                 }
6506                         }
6507                         if (err) {
6508                                 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6509                                           "failed\n", dev->name, i);
6510                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6511                                 return -1;
6512                         }
6513                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6514                 }
6515                 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6516                 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
6517         }
6518         if (sp->intr_type == INTA) {
6519                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6520                                 sp->name, dev);
6521                 if (err) {
6522                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6523                                   dev->name);
6524                         return -1;
6525                 }
6526         }
6527         return 0;
6528 }
6529 static void s2io_rem_isr(struct s2io_nic * sp)
6530 {
6531         int cnt = 0;
6532         struct net_device *dev = sp->dev;
6533
6534         if (sp->intr_type == MSI_X) {
6535                 int i;
6536                 u16 msi_control;
6537
6538                 for (i=1; (sp->s2io_entries[i].in_use ==
6539                         MSIX_REGISTERED_SUCCESS); i++) {
6540                         int vector = sp->entries[i].vector;
6541                         void *arg = sp->s2io_entries[i].arg;
6542
6543                         free_irq(vector, arg);
6544                 }
6545                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6546                 msi_control &= 0xFFFE; /* Disable MSI */
6547                 pci_write_config_word(sp->pdev, 0x42, msi_control);
6548
6549                 pci_disable_msix(sp->pdev);
6550         } else {
6551                 free_irq(sp->pdev->irq, dev);
6552                 if (sp->intr_type == MSI) {
6553                         u16 val;
6554
6555                         pci_disable_msi(sp->pdev);
6556                         pci_read_config_word(sp->pdev, 0x4c, &val);
6557                         val ^= 0x1;
6558                         pci_write_config_word(sp->pdev, 0x4c, val);
6559                 }
6560         }
6561         /* Waiting till all Interrupt handlers are complete */
6562         cnt = 0;
6563         do {
6564                 msleep(10);
6565                 if (!atomic_read(&sp->isr_cnt))
6566                         break;
6567                 cnt++;
6568         } while(cnt < 5);
6569 }
6570
6571 static void s2io_card_down(struct s2io_nic * sp)
6572 {
6573         int cnt = 0;
6574         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6575         unsigned long flags;
6576         register u64 val64 = 0;
6577
6578         del_timer_sync(&sp->alarm_timer);
6579         /* If s2io_set_link task is executing, wait till it completes. */
6580         while (test_and_set_bit(0, &(sp->link_state))) {
6581                 msleep(50);
6582         }
6583         atomic_set(&sp->card_state, CARD_DOWN);
6584
6585         /* disable Tx and Rx traffic on the NIC */
6586         stop_nic(sp);
6587
6588         s2io_rem_isr(sp);
6589
6590         /* Kill tasklet. */
6591         tasklet_kill(&sp->task);
6592
6593         /* Check if the device is Quiescent and then Reset the NIC */
6594         do {
6595                 /* As per the HW requirement we need to replenish the
6596                  * receive buffer to avoid the ring bump. Since there is
6597                  * no intention of processing the Rx frame at this pointwe are
6598                  * just settting the ownership bit of rxd in Each Rx
6599                  * ring to HW and set the appropriate buffer size
6600                  * based on the ring mode
6601                  */
6602                 rxd_owner_bit_reset(sp);
6603
6604                 val64 = readq(&bar0->adapter_status);
6605                 if (verify_xena_quiescence(sp)) {
6606                         if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6607                         break;
6608                 }
6609
6610                 msleep(50);
6611                 cnt++;
6612                 if (cnt == 10) {
6613                         DBG_PRINT(ERR_DBG,
6614                                   "s2io_close:Device not Quiescent ");
6615                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6616                                   (unsigned long long) val64);
6617                         break;
6618                 }
6619         } while (1);
6620         s2io_reset(sp);
6621
6622         spin_lock_irqsave(&sp->tx_lock, flags);
6623         /* Free all Tx buffers */
6624         free_tx_buffers(sp);
6625         spin_unlock_irqrestore(&sp->tx_lock, flags);
6626
6627         /* Free all Rx buffers */
6628         spin_lock_irqsave(&sp->rx_lock, flags);
6629         free_rx_buffers(sp);
6630         spin_unlock_irqrestore(&sp->rx_lock, flags);
6631
6632         clear_bit(0, &(sp->link_state));
6633 }
6634
6635 static int s2io_card_up(struct s2io_nic * sp)
6636 {
6637         int i, ret = 0;
6638         struct mac_info *mac_control;
6639         struct config_param *config;
6640         struct net_device *dev = (struct net_device *) sp->dev;
6641         u16 interruptible;
6642
6643         /* Initialize the H/W I/O registers */
6644         if (init_nic(sp) != 0) {
6645                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6646                           dev->name);
6647                 s2io_reset(sp);
6648                 return -ENODEV;
6649         }
6650
6651         /*
6652          * Initializing the Rx buffers. For now we are considering only 1
6653          * Rx ring and initializing buffers into 30 Rx blocks
6654          */
6655         mac_control = &sp->mac_control;
6656         config = &sp->config;
6657
6658         for (i = 0; i < config->rx_ring_num; i++) {
6659                 if ((ret = fill_rx_buffers(sp, i))) {
6660                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6661                                   dev->name);
6662                         s2io_reset(sp);
6663                         free_rx_buffers(sp);
6664                         return -ENOMEM;
6665                 }
6666                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6667                           atomic_read(&sp->rx_bufs_left[i]));
6668         }
6669         /* Maintain the state prior to the open */
6670         if (sp->promisc_flg)
6671                 sp->promisc_flg = 0;
6672         if (sp->m_cast_flg) {
6673                 sp->m_cast_flg = 0;
6674                 sp->all_multi_pos= 0;
6675         }
6676
6677         /* Setting its receive mode */
6678         s2io_set_multicast(dev);
6679
6680         if (sp->lro) {
6681                 /* Initialize max aggregatable pkts per session based on MTU */
6682                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6683                 /* Check if we can use(if specified) user provided value */
6684                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6685                         sp->lro_max_aggr_per_sess = lro_max_pkts;
6686         }
6687
6688         /* Enable Rx Traffic and interrupts on the NIC */
6689         if (start_nic(sp)) {
6690                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6691                 s2io_reset(sp);
6692                 free_rx_buffers(sp);
6693                 return -ENODEV;
6694         }
6695
6696         /* Add interrupt service routine */
6697         if (s2io_add_isr(sp) != 0) {
6698                 if (sp->intr_type == MSI_X)
6699                         s2io_rem_isr(sp);
6700                 s2io_reset(sp);
6701                 free_rx_buffers(sp);
6702                 return -ENODEV;
6703         }
6704
6705         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6706
6707         /* Enable tasklet for the device */
6708         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6709
6710         /*  Enable select interrupts */
6711         if (sp->intr_type != INTA)
6712                 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6713         else {
6714                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6715                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6716                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6717                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6718         }
6719
6720
6721         atomic_set(&sp->card_state, CARD_UP);
6722         return 0;
6723 }
6724
6725 /**
6726  * s2io_restart_nic - Resets the NIC.
6727  * @data : long pointer to the device private structure
6728  * Description:
6729  * This function is scheduled to be run by the s2io_tx_watchdog
6730  * function after 0.5 secs to reset the NIC. The idea is to reduce
6731  * the run time of the watch dog routine which is run holding a
6732  * spin lock.
6733  */
6734
6735 static void s2io_restart_nic(struct work_struct *work)
6736 {
6737         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
6738         struct net_device *dev = sp->dev;
6739
6740         rtnl_lock();
6741
6742         if (!netif_running(dev))
6743                 goto out_unlock;
6744
6745         s2io_card_down(sp);
6746         if (s2io_card_up(sp)) {
6747                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6748                           dev->name);
6749         }
6750         netif_wake_queue(dev);
6751         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6752                   dev->name);
6753 out_unlock:
6754         rtnl_unlock();
6755 }
6756
6757 /**
6758  *  s2io_tx_watchdog - Watchdog for transmit side.
6759  *  @dev : Pointer to net device structure
6760  *  Description:
6761  *  This function is triggered if the Tx Queue is stopped
6762  *  for a pre-defined amount of time when the Interface is still up.
6763  *  If the Interface is jammed in such a situation, the hardware is
6764  *  reset (by s2io_close) and restarted again (by s2io_open) to
6765  *  overcome any problem that might have been caused in the hardware.
6766  *  Return value:
6767  *  void
6768  */
6769
6770 static void s2io_tx_watchdog(struct net_device *dev)
6771 {
6772         struct s2io_nic *sp = dev->priv;
6773
6774         if (netif_carrier_ok(dev)) {
6775                 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
6776                 schedule_work(&sp->rst_timer_task);
6777                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6778         }
6779 }
6780
6781 /**
6782  *   rx_osm_handler - To perform some OS related operations on SKB.
6783  *   @sp: private member of the device structure,pointer to s2io_nic structure.
6784  *   @skb : the socket buffer pointer.
6785  *   @len : length of the packet
6786  *   @cksum : FCS checksum of the frame.
6787  *   @ring_no : the ring from which this RxD was extracted.
6788  *   Description:
6789  *   This function is called by the Rx interrupt serivce routine to perform
6790  *   some OS related operations on the SKB before passing it to the upper
6791  *   layers. It mainly checks if the checksum is OK, if so adds it to the
6792  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
6793  *   to the upper layer. If the checksum is wrong, it increments the Rx
6794  *   packet error count, frees the SKB and returns error.
6795  *   Return value:
6796  *   SUCCESS on success and -1 on failure.
6797  */
6798 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
6799 {
6800         struct s2io_nic *sp = ring_data->nic;
6801         struct net_device *dev = (struct net_device *) sp->dev;
6802         struct sk_buff *skb = (struct sk_buff *)
6803                 ((unsigned long) rxdp->Host_Control);
6804         int ring_no = ring_data->ring_no;
6805         u16 l3_csum, l4_csum;
6806         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6807         struct lro *lro;
6808
6809         skb->dev = dev;
6810
6811         if (err) {
6812                 /* Check for parity error */
6813                 if (err & 0x1) {
6814                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6815                 }
6816                 err >>= 48;
6817                 switch(err) {
6818                         case 1:
6819                                 sp->mac_control.stats_info->sw_stat.
6820                                 rx_parity_err_cnt++;
6821                         break;
6822
6823                         case 2:
6824                                 sp->mac_control.stats_info->sw_stat.
6825                                 rx_abort_cnt++;
6826                         break;
6827
6828                         case 3:
6829                                 sp->mac_control.stats_info->sw_stat.
6830                                 rx_parity_abort_cnt++;
6831                         break;
6832
6833                         case 4:
6834                                 sp->mac_control.stats_info->sw_stat.
6835                                 rx_rda_fail_cnt++;
6836                         break;
6837
6838                         case 5:
6839                                 sp->mac_control.stats_info->sw_stat.
6840                                 rx_unkn_prot_cnt++;
6841                         break;
6842
6843                         case 6:
6844                                 sp->mac_control.stats_info->sw_stat.
6845                                 rx_fcs_err_cnt++;
6846                         break;
6847
6848                         case 7:
6849                                 sp->mac_control.stats_info->sw_stat.
6850                                 rx_buf_size_err_cnt++;
6851                         break;
6852
6853                         case 8:
6854                                 sp->mac_control.stats_info->sw_stat.
6855                                 rx_rxd_corrupt_cnt++;
6856                         break;
6857
6858                         case 15:
6859                                 sp->mac_control.stats_info->sw_stat.
6860                                 rx_unkn_err_cnt++;
6861                         break;
6862                 }
6863                 /*
6864                 * Drop the packet if bad transfer code. Exception being
6865                 * 0x5, which could be due to unsupported IPv6 extension header.
6866                 * In this case, we let stack handle the packet.
6867                 * Note that in this case, since checksum will be incorrect,
6868                 * stack will validate the same.
6869                 */
6870                 if (err != 0x5) {
6871                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6872                                 dev->name, err);
6873                         sp->stats.rx_crc_errors++;
6874                         sp->mac_control.stats_info->sw_stat.mem_freed
6875                                 += skb->truesize;
6876                         dev_kfree_skb(skb);
6877                         atomic_dec(&sp->rx_bufs_left[ring_no]);
6878                         rxdp->Host_Control = 0;
6879                         return 0;
6880                 }
6881         }
6882
6883         /* Updating statistics */
6884         rxdp->Host_Control = 0;
6885         if (sp->rxd_mode == RXD_MODE_1) {
6886                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6887
6888                 sp->stats.rx_bytes += len;
6889                 skb_put(skb, len);
6890
6891         } else if (sp->rxd_mode >= RXD_MODE_3A) {
6892                 int get_block = ring_data->rx_curr_get_info.block_index;
6893                 int get_off = ring_data->rx_curr_get_info.offset;
6894                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6895                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6896                 unsigned char *buff = skb_push(skb, buf0_len);
6897
6898                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
6899                 sp->stats.rx_bytes += buf0_len + buf2_len;
6900                 memcpy(buff, ba->ba_0, buf0_len);
6901
6902                 if (sp->rxd_mode == RXD_MODE_3A) {
6903                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6904
6905                         skb_put(skb, buf1_len);
6906                         skb->len += buf2_len;
6907                         skb->data_len += buf2_len;
6908                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6909                         sp->stats.rx_bytes += buf1_len;
6910
6911                 } else
6912                         skb_put(skb, buf2_len);
6913         }
6914
6915         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6916             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6917             (sp->rx_csum)) {
6918                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6919                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6920                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6921                         /*
6922                          * NIC verifies if the Checksum of the received
6923                          * frame is Ok or not and accordingly returns
6924                          * a flag in the RxD.
6925                          */
6926                         skb->ip_summed = CHECKSUM_UNNECESSARY;
6927                         if (sp->lro) {
6928                                 u32 tcp_len;
6929                                 u8 *tcp;
6930                                 int ret = 0;
6931
6932                                 ret = s2io_club_tcp_session(skb->data, &tcp,
6933                                                 &tcp_len, &lro, rxdp, sp);
6934                                 switch (ret) {
6935                                         case 3: /* Begin anew */
6936                                                 lro->parent = skb;
6937                                                 goto aggregate;
6938                                         case 1: /* Aggregate */
6939                                         {
6940                                                 lro_append_pkt(sp, lro,
6941                                                         skb, tcp_len);
6942                                                 goto aggregate;
6943                                         }
6944                                         case 4: /* Flush session */
6945                                         {
6946                                                 lro_append_pkt(sp, lro,
6947                                                         skb, tcp_len);
6948                                                 queue_rx_frame(lro->parent);
6949                                                 clear_lro_session(lro);
6950                                                 sp->mac_control.stats_info->
6951                                                     sw_stat.flush_max_pkts++;
6952                                                 goto aggregate;
6953                                         }
6954                                         case 2: /* Flush both */
6955                                                 lro->parent->data_len =
6956                                                         lro->frags_len;
6957                                                 sp->mac_control.stats_info->
6958                                                      sw_stat.sending_both++;
6959                                                 queue_rx_frame(lro->parent);
6960                                                 clear_lro_session(lro);
6961                                                 goto send_up;
6962                                         case 0: /* sessions exceeded */
6963                                         case -1: /* non-TCP or not
6964                                                   * L2 aggregatable
6965                                                   */
6966                                         case 5: /*
6967                                                  * First pkt in session not
6968                                                  * L3/L4 aggregatable
6969                                                  */
6970                                                 break;
6971                                         default:
6972                                                 DBG_PRINT(ERR_DBG,
6973                                                         "%s: Samadhana!!\n",
6974                                                          __FUNCTION__);
6975                                                 BUG();
6976                                 }
6977                         }
6978                 } else {
6979                         /*
6980                          * Packet with erroneous checksum, let the
6981                          * upper layers deal with it.
6982                          */
6983                         skb->ip_summed = CHECKSUM_NONE;
6984                 }
6985         } else {
6986                 skb->ip_summed = CHECKSUM_NONE;
6987         }
6988         sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
6989         if (!sp->lro) {
6990                 skb->protocol = eth_type_trans(skb, dev);
6991                 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
6992                         vlan_strip_flag)) {
6993                         /* Queueing the vlan frame to the upper layer */
6994                         if (napi)
6995                                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6996                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
6997                         else
6998                                 vlan_hwaccel_rx(skb, sp->vlgrp,
6999                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
7000                 } else {
7001                         if (napi)
7002                                 netif_receive_skb(skb);
7003                         else
7004                                 netif_rx(skb);
7005                 }
7006         } else {
7007 send_up:
7008                 queue_rx_frame(skb);
7009         }
7010         dev->last_rx = jiffies;
7011 aggregate:
7012         atomic_dec(&sp->rx_bufs_left[ring_no]);
7013         return SUCCESS;
7014 }
7015
7016 /**
7017  *  s2io_link - stops/starts the Tx queue.
7018  *  @sp : private member of the device structure, which is a pointer to the
7019  *  s2io_nic structure.
7020  *  @link : inidicates whether link is UP/DOWN.
7021  *  Description:
7022  *  This function stops/starts the Tx queue depending on whether the link
7023  *  status of the NIC is is down or up. This is called by the Alarm
7024  *  interrupt handler whenever a link change interrupt comes up.
7025  *  Return value:
7026  *  void.
7027  */
7028
7029 static void s2io_link(struct s2io_nic * sp, int link)
7030 {
7031         struct net_device *dev = (struct net_device *) sp->dev;
7032
7033         if (link != sp->last_link_state) {
7034                 if (link == LINK_DOWN) {
7035                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7036                         netif_carrier_off(dev);
7037                         if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7038                         sp->mac_control.stats_info->sw_stat.link_up_time =
7039                                 jiffies - sp->start_time;
7040                         sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7041                 } else {
7042                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7043                         if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7044                         sp->mac_control.stats_info->sw_stat.link_down_time =
7045                                 jiffies - sp->start_time;
7046                         sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7047                         netif_carrier_on(dev);
7048                 }
7049         }
7050         sp->last_link_state = link;
7051         sp->start_time = jiffies;
7052 }
7053
7054 /**
7055  *  get_xena_rev_id - to identify revision ID of xena.
7056  *  @pdev : PCI Dev structure
7057  *  Description:
7058  *  Function to identify the Revision ID of xena.
7059  *  Return value:
7060  *  returns the revision ID of the device.
7061  */
7062
7063 static int get_xena_rev_id(struct pci_dev *pdev)
7064 {
7065         u8 id = 0;
7066         int ret;
7067         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
7068         return id;
7069 }
7070
7071 /**
7072  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7073  *  @sp : private member of the device structure, which is a pointer to the
7074  *  s2io_nic structure.
7075  *  Description:
7076  *  This function initializes a few of the PCI and PCI-X configuration registers
7077  *  with recommended values.
7078  *  Return value:
7079  *  void
7080  */
7081
7082 static void s2io_init_pci(struct s2io_nic * sp)
7083 {
7084         u16 pci_cmd = 0, pcix_cmd = 0;
7085
7086         /* Enable Data Parity Error Recovery in PCI-X command register. */
7087         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7088                              &(pcix_cmd));
7089         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7090                               (pcix_cmd | 1));
7091         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7092                              &(pcix_cmd));
7093
7094         /* Set the PErr Response bit in PCI command register. */
7095         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7096         pci_write_config_word(sp->pdev, PCI_COMMAND,
7097                               (pci_cmd | PCI_COMMAND_PARITY));
7098         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7099 }
7100
7101 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7102 {
7103         if ( tx_fifo_num > 8) {
7104                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7105                          "supported\n");
7106                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7107                 tx_fifo_num = 8;
7108         }
7109         if ( rx_ring_num > 8) {
7110                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7111                          "supported\n");
7112                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7113                 rx_ring_num = 8;
7114         }
7115         if (*dev_intr_type != INTA)
7116                 napi = 0;
7117
7118 #ifndef CONFIG_PCI_MSI
7119         if (*dev_intr_type != INTA) {
7120                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
7121                           "MSI/MSI-X. Defaulting to INTA\n");
7122                 *dev_intr_type = INTA;
7123         }
7124 #else
7125         if (*dev_intr_type > MSI_X) {
7126                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7127                           "Defaulting to INTA\n");
7128                 *dev_intr_type = INTA;
7129         }
7130 #endif
7131         if ((*dev_intr_type == MSI_X) &&
7132                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7133                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7134                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7135                                         "Defaulting to INTA\n");
7136                 *dev_intr_type = INTA;
7137         }
7138
7139         if (rx_ring_mode > 3) {
7140                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7141                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
7142                 rx_ring_mode = 3;
7143         }
7144         return SUCCESS;
7145 }
7146
7147 /**
7148  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7149  * or Traffic class respectively.
7150  * @nic: device peivate variable
7151  * Description: The function configures the receive steering to
7152  * desired receive ring.
7153  * Return Value:  SUCCESS on success and
7154  * '-1' on failure (endian settings incorrect).
7155  */
7156 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7157 {
7158         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7159         register u64 val64 = 0;
7160
7161         if (ds_codepoint > 63)
7162                 return FAILURE;
7163
7164         val64 = RTS_DS_MEM_DATA(ring);
7165         writeq(val64, &bar0->rts_ds_mem_data);
7166
7167         val64 = RTS_DS_MEM_CTRL_WE |
7168                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7169                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7170
7171         writeq(val64, &bar0->rts_ds_mem_ctrl);
7172
7173         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7174                                 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7175                                 S2IO_BIT_RESET);
7176 }
7177
7178 /**
7179  *  s2io_init_nic - Initialization of the adapter .
7180  *  @pdev : structure containing the PCI related information of the device.
7181  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7182  *  Description:
7183  *  The function initializes an adapter identified by the pci_dec structure.
7184  *  All OS related initialization including memory and device structure and
7185  *  initlaization of the device private variable is done. Also the swapper
7186  *  control register is initialized to enable read and write into the I/O
7187  *  registers of the device.
7188  *  Return value:
7189  *  returns 0 on success and negative on failure.
7190  */
7191
7192 static int __devinit
7193 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7194 {
7195         struct s2io_nic *sp;
7196         struct net_device *dev;
7197         int i, j, ret;
7198         int dma_flag = FALSE;
7199         u32 mac_up, mac_down;
7200         u64 val64 = 0, tmp64 = 0;
7201         struct XENA_dev_config __iomem *bar0 = NULL;
7202         u16 subid;
7203         struct mac_info *mac_control;
7204         struct config_param *config;
7205         int mode;
7206         u8 dev_intr_type = intr_type;
7207
7208         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7209                 return ret;
7210
7211         if ((ret = pci_enable_device(pdev))) {
7212                 DBG_PRINT(ERR_DBG,
7213                           "s2io_init_nic: pci_enable_device failed\n");
7214                 return ret;
7215         }
7216
7217         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7218                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7219                 dma_flag = TRUE;
7220                 if (pci_set_consistent_dma_mask
7221                     (pdev, DMA_64BIT_MASK)) {
7222                         DBG_PRINT(ERR_DBG,
7223                                   "Unable to obtain 64bit DMA for \
7224                                         consistent allocations\n");
7225                         pci_disable_device(pdev);
7226                         return -ENOMEM;
7227                 }
7228         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7229                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7230         } else {
7231                 pci_disable_device(pdev);
7232                 return -ENOMEM;
7233         }
7234         if (dev_intr_type != MSI_X) {
7235                 if (pci_request_regions(pdev, s2io_driver_name)) {
7236                         DBG_PRINT(ERR_DBG, "Request Regions failed\n");
7237                         pci_disable_device(pdev);
7238                         return -ENODEV;
7239                 }
7240         }
7241         else {
7242                 if (!(request_mem_region(pci_resource_start(pdev, 0),
7243                          pci_resource_len(pdev, 0), s2io_driver_name))) {
7244                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
7245                         pci_disable_device(pdev);
7246                         return -ENODEV;
7247                 }
7248                 if (!(request_mem_region(pci_resource_start(pdev, 2),
7249                          pci_resource_len(pdev, 2), s2io_driver_name))) {
7250                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
7251                         release_mem_region(pci_resource_start(pdev, 0),
7252                                    pci_resource_len(pdev, 0));
7253                         pci_disable_device(pdev);
7254                         return -ENODEV;
7255                 }
7256         }
7257
7258         dev = alloc_etherdev(sizeof(struct s2io_nic));
7259         if (dev == NULL) {
7260                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7261                 pci_disable_device(pdev);
7262                 pci_release_regions(pdev);
7263                 return -ENODEV;
7264         }
7265
7266         pci_set_master(pdev);
7267         pci_set_drvdata(pdev, dev);
7268         SET_MODULE_OWNER(dev);
7269         SET_NETDEV_DEV(dev, &pdev->dev);
7270
7271         /*  Private member variable initialized to s2io NIC structure */
7272         sp = dev->priv;
7273         memset(sp, 0, sizeof(struct s2io_nic));
7274         sp->dev = dev;
7275         sp->pdev = pdev;
7276         sp->high_dma_flag = dma_flag;
7277         sp->device_enabled_once = FALSE;
7278         if (rx_ring_mode == 1)
7279                 sp->rxd_mode = RXD_MODE_1;
7280         if (rx_ring_mode == 2)
7281                 sp->rxd_mode = RXD_MODE_3B;
7282         if (rx_ring_mode == 3)
7283                 sp->rxd_mode = RXD_MODE_3A;
7284
7285         sp->intr_type = dev_intr_type;
7286
7287         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7288                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7289                 sp->device_type = XFRAME_II_DEVICE;
7290         else
7291                 sp->device_type = XFRAME_I_DEVICE;
7292
7293         sp->lro = lro;
7294
7295         /* Initialize some PCI/PCI-X fields of the NIC. */
7296         s2io_init_pci(sp);
7297
7298         /*
7299          * Setting the device configuration parameters.
7300          * Most of these parameters can be specified by the user during
7301          * module insertion as they are module loadable parameters. If
7302          * these parameters are not not specified during load time, they
7303          * are initialized with default values.
7304          */
7305         mac_control = &sp->mac_control;
7306         config = &sp->config;
7307
7308         /* Tx side parameters. */
7309         config->tx_fifo_num = tx_fifo_num;
7310         for (i = 0; i < MAX_TX_FIFOS; i++) {
7311                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7312                 config->tx_cfg[i].fifo_priority = i;
7313         }
7314
7315         /* mapping the QoS priority to the configured fifos */
7316         for (i = 0; i < MAX_TX_FIFOS; i++)
7317                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7318
7319         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7320         for (i = 0; i < config->tx_fifo_num; i++) {
7321                 config->tx_cfg[i].f_no_snoop =
7322                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7323                 if (config->tx_cfg[i].fifo_len < 65) {
7324                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7325                         break;
7326                 }
7327         }
7328         /* + 2 because one Txd for skb->data and one Txd for UFO */
7329         config->max_txds = MAX_SKB_FRAGS + 2;
7330
7331         /* Rx side parameters. */
7332         config->rx_ring_num = rx_ring_num;
7333         for (i = 0; i < MAX_RX_RINGS; i++) {
7334                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7335                     (rxd_count[sp->rxd_mode] + 1);
7336                 config->rx_cfg[i].ring_priority = i;
7337         }
7338
7339         for (i = 0; i < rx_ring_num; i++) {
7340                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7341                 config->rx_cfg[i].f_no_snoop =
7342                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7343         }
7344
7345         /*  Setting Mac Control parameters */
7346         mac_control->rmac_pause_time = rmac_pause_time;
7347         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7348         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7349
7350
7351         /* Initialize Ring buffer parameters. */
7352         for (i = 0; i < config->rx_ring_num; i++)
7353                 atomic_set(&sp->rx_bufs_left[i], 0);
7354
7355         /* Initialize the number of ISRs currently running */
7356         atomic_set(&sp->isr_cnt, 0);
7357
7358         /*  initialize the shared memory used by the NIC and the host */
7359         if (init_shared_mem(sp)) {
7360                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7361                           dev->name);
7362                 ret = -ENOMEM;
7363                 goto mem_alloc_failed;
7364         }
7365
7366         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7367                                      pci_resource_len(pdev, 0));
7368         if (!sp->bar0) {
7369                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7370                           dev->name);
7371                 ret = -ENOMEM;
7372                 goto bar0_remap_failed;
7373         }
7374
7375         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7376                                      pci_resource_len(pdev, 2));
7377         if (!sp->bar1) {
7378                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7379                           dev->name);
7380                 ret = -ENOMEM;
7381                 goto bar1_remap_failed;
7382         }
7383
7384         dev->irq = pdev->irq;
7385         dev->base_addr = (unsigned long) sp->bar0;
7386
7387         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7388         for (j = 0; j < MAX_TX_FIFOS; j++) {
7389                 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7390                     (sp->bar1 + (j * 0x00020000));
7391         }
7392
7393         /*  Driver entry points */
7394         dev->open = &s2io_open;
7395         dev->stop = &s2io_close;
7396         dev->hard_start_xmit = &s2io_xmit;
7397         dev->get_stats = &s2io_get_stats;
7398         dev->set_multicast_list = &s2io_set_multicast;
7399         dev->do_ioctl = &s2io_ioctl;
7400         dev->change_mtu = &s2io_change_mtu;
7401         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7402         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7403         dev->vlan_rx_register = s2io_vlan_rx_register;
7404
7405         /*
7406          * will use eth_mac_addr() for  dev->set_mac_address
7407          * mac address will be set every time dev->open() is called
7408          */
7409         dev->poll = s2io_poll;
7410         dev->weight = 32;
7411
7412 #ifdef CONFIG_NET_POLL_CONTROLLER
7413         dev->poll_controller = s2io_netpoll;
7414 #endif
7415
7416         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7417         if (sp->high_dma_flag == TRUE)
7418                 dev->features |= NETIF_F_HIGHDMA;
7419         dev->features |= NETIF_F_TSO;
7420         dev->features |= NETIF_F_TSO6;
7421         if ((sp->device_type & XFRAME_II_DEVICE) && (ufo))  {
7422                 dev->features |= NETIF_F_UFO;
7423                 dev->features |= NETIF_F_HW_CSUM;
7424         }
7425
7426         dev->tx_timeout = &s2io_tx_watchdog;
7427         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7428         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7429         INIT_WORK(&sp->set_link_task, s2io_set_link);
7430
7431         pci_save_state(sp->pdev);
7432
7433         /* Setting swapper control on the NIC, for proper reset operation */
7434         if (s2io_set_swapper(sp)) {
7435                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7436                           dev->name);
7437                 ret = -EAGAIN;
7438                 goto set_swap_failed;
7439         }
7440
7441         /* Verify if the Herc works on the slot its placed into */
7442         if (sp->device_type & XFRAME_II_DEVICE) {
7443                 mode = s2io_verify_pci_mode(sp);
7444                 if (mode < 0) {
7445                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7446                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7447                         ret = -EBADSLT;
7448                         goto set_swap_failed;
7449                 }
7450         }
7451
7452         /* Not needed for Herc */
7453         if (sp->device_type & XFRAME_I_DEVICE) {
7454                 /*
7455                  * Fix for all "FFs" MAC address problems observed on
7456                  * Alpha platforms
7457                  */
7458                 fix_mac_address(sp);
7459                 s2io_reset(sp);
7460         }
7461
7462         /*
7463          * MAC address initialization.
7464          * For now only one mac address will be read and used.
7465          */
7466         bar0 = sp->bar0;
7467         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7468             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7469         writeq(val64, &bar0->rmac_addr_cmd_mem);
7470         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7471                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7472         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7473         mac_down = (u32) tmp64;
7474         mac_up = (u32) (tmp64 >> 32);
7475
7476         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7477         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7478         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7479         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7480         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7481         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7482
7483         /*  Set the factory defined MAC address initially   */
7484         dev->addr_len = ETH_ALEN;
7485         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7486
7487         /* reset Nic and bring it to known state */
7488         s2io_reset(sp);
7489
7490         /*
7491          * Initialize the tasklet status and link state flags
7492          * and the card state parameter
7493          */
7494         atomic_set(&(sp->card_state), 0);
7495         sp->tasklet_status = 0;
7496         sp->link_state = 0;
7497
7498         /* Initialize spinlocks */
7499         spin_lock_init(&sp->tx_lock);
7500
7501         if (!napi)
7502                 spin_lock_init(&sp->put_lock);
7503         spin_lock_init(&sp->rx_lock);
7504
7505         /*
7506          * SXE-002: Configure link and activity LED to init state
7507          * on driver load.
7508          */
7509         subid = sp->pdev->subsystem_device;
7510         if ((subid & 0xFF) >= 0x07) {
7511                 val64 = readq(&bar0->gpio_control);
7512                 val64 |= 0x0000800000000000ULL;
7513                 writeq(val64, &bar0->gpio_control);
7514                 val64 = 0x0411040400000000ULL;
7515                 writeq(val64, (void __iomem *) bar0 + 0x2700);
7516                 val64 = readq(&bar0->gpio_control);
7517         }
7518
7519         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
7520
7521         if (register_netdev(dev)) {
7522                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7523                 ret = -ENODEV;
7524                 goto register_failed;
7525         }
7526         s2io_vpd_read(sp);
7527         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7528         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7529                   sp->product_name, get_xena_rev_id(sp->pdev));
7530         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7531                   s2io_driver_version);
7532         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7533                           "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
7534                           sp->def_mac_addr[0].mac_addr[0],
7535                           sp->def_mac_addr[0].mac_addr[1],
7536                           sp->def_mac_addr[0].mac_addr[2],
7537                           sp->def_mac_addr[0].mac_addr[3],
7538                           sp->def_mac_addr[0].mac_addr[4],
7539                           sp->def_mac_addr[0].mac_addr[5]);
7540         DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7541         if (sp->device_type & XFRAME_II_DEVICE) {
7542                 mode = s2io_print_pci_mode(sp);
7543                 if (mode < 0) {
7544                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7545                         ret = -EBADSLT;
7546                         unregister_netdev(dev);
7547                         goto set_swap_failed;
7548                 }
7549         }
7550         switch(sp->rxd_mode) {
7551                 case RXD_MODE_1:
7552                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7553                                                 dev->name);
7554                     break;
7555                 case RXD_MODE_3B:
7556                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7557                                                 dev->name);
7558                     break;
7559                 case RXD_MODE_3A:
7560                     DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7561                                                 dev->name);
7562                     break;
7563         }
7564
7565         if (napi)
7566                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7567         switch(sp->intr_type) {
7568                 case INTA:
7569                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7570                     break;
7571                 case MSI:
7572                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7573                     break;
7574                 case MSI_X:
7575                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7576                     break;
7577         }
7578         if (sp->lro)
7579                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7580                           dev->name);
7581         if (ufo)
7582                 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7583                                         " enabled\n", dev->name);
7584         /* Initialize device name */
7585         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7586
7587         /* Initialize bimodal Interrupts */
7588         sp->config.bimodal = bimodal;
7589         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7590                 sp->config.bimodal = 0;
7591                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7592                         dev->name);
7593         }
7594
7595         /*
7596          * Make Link state as off at this point, when the Link change
7597          * interrupt comes the state will be automatically changed to
7598          * the right state.
7599          */
7600         netif_carrier_off(dev);
7601
7602         return 0;
7603
7604       register_failed:
7605       set_swap_failed:
7606         iounmap(sp->bar1);
7607       bar1_remap_failed:
7608         iounmap(sp->bar0);
7609       bar0_remap_failed:
7610       mem_alloc_failed:
7611         free_shared_mem(sp);
7612         pci_disable_device(pdev);
7613         if (dev_intr_type != MSI_X)
7614                 pci_release_regions(pdev);
7615         else {
7616                 release_mem_region(pci_resource_start(pdev, 0),
7617                         pci_resource_len(pdev, 0));
7618                 release_mem_region(pci_resource_start(pdev, 2),
7619                         pci_resource_len(pdev, 2));
7620         }
7621         pci_set_drvdata(pdev, NULL);
7622         free_netdev(dev);
7623
7624         return ret;
7625 }
7626
7627 /**
7628  * s2io_rem_nic - Free the PCI device
7629  * @pdev: structure containing the PCI related information of the device.
7630  * Description: This function is called by the Pci subsystem to release a
7631  * PCI device and free up all resource held up by the device. This could
7632  * be in response to a Hot plug event or when the driver is to be removed
7633  * from memory.
7634  */
7635
7636 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7637 {
7638         struct net_device *dev =
7639             (struct net_device *) pci_get_drvdata(pdev);
7640         struct s2io_nic *sp;
7641
7642         if (dev == NULL) {
7643                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7644                 return;
7645         }
7646
7647         flush_scheduled_work();
7648
7649         sp = dev->priv;
7650         unregister_netdev(dev);
7651
7652         free_shared_mem(sp);
7653         iounmap(sp->bar0);
7654         iounmap(sp->bar1);
7655         if (sp->intr_type != MSI_X)
7656                 pci_release_regions(pdev);
7657         else {
7658                 release_mem_region(pci_resource_start(pdev, 0),
7659                         pci_resource_len(pdev, 0));
7660                 release_mem_region(pci_resource_start(pdev, 2),
7661                         pci_resource_len(pdev, 2));
7662         }
7663         pci_set_drvdata(pdev, NULL);
7664         free_netdev(dev);
7665         pci_disable_device(pdev);
7666 }
7667
7668 /**
7669  * s2io_starter - Entry point for the driver
7670  * Description: This function is the entry point for the driver. It verifies
7671  * the module loadable parameters and initializes PCI configuration space.
7672  */
7673
7674 int __init s2io_starter(void)
7675 {
7676         return pci_register_driver(&s2io_driver);
7677 }
7678
7679 /**
7680  * s2io_closer - Cleanup routine for the driver
7681  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7682  */
7683
7684 static __exit void s2io_closer(void)
7685 {
7686         pci_unregister_driver(&s2io_driver);
7687         DBG_PRINT(INIT_DBG, "cleanup done\n");
7688 }
7689
7690 module_init(s2io_starter);
7691 module_exit(s2io_closer);
7692
7693 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7694                 struct tcphdr **tcp, struct RxD_t *rxdp)
7695 {
7696         int ip_off;
7697         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7698
7699         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7700                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7701                           __FUNCTION__);
7702                 return -1;
7703         }
7704
7705         /* TODO:
7706          * By default the VLAN field in the MAC is stripped by the card, if this
7707          * feature is turned off in rx_pa_cfg register, then the ip_off field
7708          * has to be shifted by a further 2 bytes
7709          */
7710         switch (l2_type) {
7711                 case 0: /* DIX type */
7712                 case 4: /* DIX type with VLAN */
7713                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7714                         break;
7715                 /* LLC, SNAP etc are considered non-mergeable */
7716                 default:
7717                         return -1;
7718         }
7719
7720         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7721         ip_len = (u8)((*ip)->ihl);
7722         ip_len <<= 2;
7723         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7724
7725         return 0;
7726 }
7727
7728 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7729                                   struct tcphdr *tcp)
7730 {
7731         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7732         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7733            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7734                 return -1;
7735         return 0;
7736 }
7737
7738 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7739 {
7740         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7741 }
7742
7743 static void initiate_new_session(struct lro *lro, u8 *l2h,
7744                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7745 {
7746         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7747         lro->l2h = l2h;
7748         lro->iph = ip;
7749         lro->tcph = tcp;
7750         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7751         lro->tcp_ack = ntohl(tcp->ack_seq);
7752         lro->sg_num = 1;
7753         lro->total_len = ntohs(ip->tot_len);
7754         lro->frags_len = 0;
7755         /*
7756          * check if we saw TCP timestamp. Other consistency checks have
7757          * already been done.
7758          */
7759         if (tcp->doff == 8) {
7760                 u32 *ptr;
7761                 ptr = (u32 *)(tcp+1);
7762                 lro->saw_ts = 1;
7763                 lro->cur_tsval = *(ptr+1);
7764                 lro->cur_tsecr = *(ptr+2);
7765         }
7766         lro->in_use = 1;
7767 }
7768
7769 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7770 {
7771         struct iphdr *ip = lro->iph;
7772         struct tcphdr *tcp = lro->tcph;
7773         __sum16 nchk;
7774         struct stat_block *statinfo = sp->mac_control.stats_info;
7775         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7776
7777         /* Update L3 header */
7778         ip->tot_len = htons(lro->total_len);
7779         ip->check = 0;
7780         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7781         ip->check = nchk;
7782
7783         /* Update L4 header */
7784         tcp->ack_seq = lro->tcp_ack;
7785         tcp->window = lro->window;
7786
7787         /* Update tsecr field if this session has timestamps enabled */
7788         if (lro->saw_ts) {
7789                 u32 *ptr = (u32 *)(tcp + 1);
7790                 *(ptr+2) = lro->cur_tsecr;
7791         }
7792
7793         /* Update counters required for calculation of
7794          * average no. of packets aggregated.
7795          */
7796         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7797         statinfo->sw_stat.num_aggregations++;
7798 }
7799
7800 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7801                 struct tcphdr *tcp, u32 l4_pyld)
7802 {
7803         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7804         lro->total_len += l4_pyld;
7805         lro->frags_len += l4_pyld;
7806         lro->tcp_next_seq += l4_pyld;
7807         lro->sg_num++;
7808
7809         /* Update ack seq no. and window ad(from this pkt) in LRO object */
7810         lro->tcp_ack = tcp->ack_seq;
7811         lro->window = tcp->window;
7812
7813         if (lro->saw_ts) {
7814                 u32 *ptr;
7815                 /* Update tsecr and tsval from this packet */
7816                 ptr = (u32 *) (tcp + 1);
7817                 lro->cur_tsval = *(ptr + 1);
7818                 lro->cur_tsecr = *(ptr + 2);
7819         }
7820 }
7821
7822 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7823                                     struct tcphdr *tcp, u32 tcp_pyld_len)
7824 {
7825         u8 *ptr;
7826
7827         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7828
7829         if (!tcp_pyld_len) {
7830                 /* Runt frame or a pure ack */
7831                 return -1;
7832         }
7833
7834         if (ip->ihl != 5) /* IP has options */
7835                 return -1;
7836
7837         /* If we see CE codepoint in IP header, packet is not mergeable */
7838         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7839                 return -1;
7840
7841         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7842         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7843                                     tcp->ece || tcp->cwr || !tcp->ack) {
7844                 /*
7845                  * Currently recognize only the ack control word and
7846                  * any other control field being set would result in
7847                  * flushing the LRO session
7848                  */
7849                 return -1;
7850         }
7851
7852         /*
7853          * Allow only one TCP timestamp option. Don't aggregate if
7854          * any other options are detected.
7855          */
7856         if (tcp->doff != 5 && tcp->doff != 8)
7857                 return -1;
7858
7859         if (tcp->doff == 8) {
7860                 ptr = (u8 *)(tcp + 1);
7861                 while (*ptr == TCPOPT_NOP)
7862                         ptr++;
7863                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7864                         return -1;
7865
7866                 /* Ensure timestamp value increases monotonically */
7867                 if (l_lro)
7868                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7869                                 return -1;
7870
7871                 /* timestamp echo reply should be non-zero */
7872                 if (*((u32 *)(ptr+6)) == 0)
7873                         return -1;
7874         }
7875
7876         return 0;
7877 }
7878
7879 static int
7880 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7881                       struct RxD_t *rxdp, struct s2io_nic *sp)
7882 {
7883         struct iphdr *ip;
7884         struct tcphdr *tcph;
7885         int ret = 0, i;
7886
7887         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7888                                          rxdp))) {
7889                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7890                           ip->saddr, ip->daddr);
7891         } else {
7892                 return ret;
7893         }
7894
7895         tcph = (struct tcphdr *)*tcp;
7896         *tcp_len = get_l4_pyld_length(ip, tcph);
7897         for (i=0; i<MAX_LRO_SESSIONS; i++) {
7898                 struct lro *l_lro = &sp->lro0_n[i];
7899                 if (l_lro->in_use) {
7900                         if (check_for_socket_match(l_lro, ip, tcph))
7901                                 continue;
7902                         /* Sock pair matched */
7903                         *lro = l_lro;
7904
7905                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7906                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7907                                           "0x%x, actual 0x%x\n", __FUNCTION__,
7908                                           (*lro)->tcp_next_seq,
7909                                           ntohl(tcph->seq));
7910
7911                                 sp->mac_control.stats_info->
7912                                    sw_stat.outof_sequence_pkts++;
7913                                 ret = 2;
7914                                 break;
7915                         }
7916
7917                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7918                                 ret = 1; /* Aggregate */
7919                         else
7920                                 ret = 2; /* Flush both */
7921                         break;
7922                 }
7923         }
7924
7925         if (ret == 0) {
7926                 /* Before searching for available LRO objects,
7927                  * check if the pkt is L3/L4 aggregatable. If not
7928                  * don't create new LRO session. Just send this
7929                  * packet up.
7930                  */
7931                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7932                         return 5;
7933                 }
7934
7935                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7936                         struct lro *l_lro = &sp->lro0_n[i];
7937                         if (!(l_lro->in_use)) {
7938                                 *lro = l_lro;
7939                                 ret = 3; /* Begin anew */
7940                                 break;
7941                         }
7942                 }
7943         }
7944
7945         if (ret == 0) { /* sessions exceeded */
7946                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7947                           __FUNCTION__);
7948                 *lro = NULL;
7949                 return ret;
7950         }
7951
7952         switch (ret) {
7953                 case 3:
7954                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7955                         break;
7956                 case 2:
7957                         update_L3L4_header(sp, *lro);
7958                         break;
7959                 case 1:
7960                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7961                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7962                                 update_L3L4_header(sp, *lro);
7963                                 ret = 4; /* Flush the LRO */
7964                         }
7965                         break;
7966                 default:
7967                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7968                                 __FUNCTION__);
7969                         break;
7970         }
7971
7972         return ret;
7973 }
7974
7975 static void clear_lro_session(struct lro *lro)
7976 {
7977         static u16 lro_struct_size = sizeof(struct lro);
7978
7979         memset(lro, 0, lro_struct_size);
7980 }
7981
7982 static void queue_rx_frame(struct sk_buff *skb)
7983 {
7984         struct net_device *dev = skb->dev;
7985
7986         skb->protocol = eth_type_trans(skb, dev);
7987         if (napi)
7988                 netif_receive_skb(skb);
7989         else
7990                 netif_rx(skb);
7991 }
7992
7993 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7994                            struct sk_buff *skb,
7995                            u32 tcp_len)
7996 {
7997         struct sk_buff *first = lro->parent;
7998
7999         first->len += tcp_len;
8000         first->data_len = lro->frags_len;
8001         skb_pull(skb, (skb->len - tcp_len));
8002         if (skb_shinfo(first)->frag_list)
8003                 lro->last_frag->next = skb;
8004         else
8005                 skb_shinfo(first)->frag_list = skb;
8006         first->truesize += skb->truesize;
8007         lro->last_frag = skb;
8008         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8009         return;
8010 }