1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
4 * Driver for Realtek PHYs
6 * Author: Johnson Leung <r58129@freescale.com>
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 #include <linux/bitops.h>
12 #include <linux/phy.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
17 #define RTL821x_PHYSR 0x11
18 #define RTL821x_PHYSR_DUPLEX BIT(13)
19 #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
21 #define RTL821x_INER 0x12
22 #define RTL8211B_INER_INIT 0x6400
23 #define RTL8211E_INER_LINK_STATUS BIT(10)
24 #define RTL8211F_INER_LINK_STATUS BIT(4)
26 #define RTL821x_INSR 0x13
28 #define RTL821x_EXT_PAGE_SELECT 0x1e
29 #define RTL821x_PAGE_SELECT 0x1f
31 #define RTL8211F_PHYCR1 0x18
32 #define RTL8211F_PHYCR2 0x19
33 #define RTL8211F_INSR 0x1d
35 #define RTL8211F_TX_DELAY BIT(8)
36 #define RTL8211F_RX_DELAY BIT(3)
38 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
39 #define RTL8211F_ALDPS_ENABLE BIT(2)
40 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
42 #define RTL8211E_CTRL_DELAY BIT(13)
43 #define RTL8211E_TX_DELAY BIT(12)
44 #define RTL8211E_RX_DELAY BIT(11)
46 #define RTL8211F_CLKOUT_EN BIT(0)
48 #define RTL8201F_ISR 0x1e
49 #define RTL8201F_ISR_ANERR BIT(15)
50 #define RTL8201F_ISR_DUPLEX BIT(13)
51 #define RTL8201F_ISR_LINK BIT(11)
52 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
53 RTL8201F_ISR_DUPLEX | \
55 #define RTL8201F_IER 0x13
57 #define RTL8366RB_POWER_SAVE 0x15
58 #define RTL8366RB_POWER_SAVE_ON BIT(12)
60 #define RTL_SUPPORTS_5000FULL BIT(14)
61 #define RTL_SUPPORTS_2500FULL BIT(13)
62 #define RTL_SUPPORTS_10000FULL BIT(0)
63 #define RTL_ADV_2500FULL BIT(7)
64 #define RTL_LPADV_10000FULL BIT(11)
65 #define RTL_LPADV_5000FULL BIT(6)
66 #define RTL_LPADV_2500FULL BIT(5)
68 #define RTL9000A_GINMR 0x14
69 #define RTL9000A_GINMR_LINK_STATUS BIT(4)
71 #define RTLGEN_SPEED_MASK 0x0630
73 #define RTL_GENERIC_PHYID 0x001cc800
74 #define RTL_8211FVD_PHYID 0x001cc878
76 MODULE_DESCRIPTION("Realtek PHY driver");
77 MODULE_AUTHOR("Johnson Leung");
78 MODULE_LICENSE("GPL");
87 static int rtl821x_read_page(struct phy_device *phydev)
89 return __phy_read(phydev, RTL821x_PAGE_SELECT);
92 static int rtl821x_write_page(struct phy_device *phydev, int page)
94 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
97 static int rtl821x_probe(struct phy_device *phydev)
99 struct device *dev = &phydev->mdio.dev;
100 struct rtl821x_priv *priv;
101 u32 phy_id = phydev->drv->phy_id;
104 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
108 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
109 if (IS_ERR(priv->clk))
110 return dev_err_probe(dev, PTR_ERR(priv->clk),
111 "failed to get phy clock\n");
113 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
117 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
118 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
119 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
121 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
122 if (priv->has_phycr2) {
123 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
127 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
128 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
129 priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
137 static int rtl8201_ack_interrupt(struct phy_device *phydev)
141 err = phy_read(phydev, RTL8201F_ISR);
143 return (err < 0) ? err : 0;
146 static int rtl821x_ack_interrupt(struct phy_device *phydev)
150 err = phy_read(phydev, RTL821x_INSR);
152 return (err < 0) ? err : 0;
155 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
159 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
161 return (err < 0) ? err : 0;
164 static int rtl8201_config_intr(struct phy_device *phydev)
169 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
170 err = rtl8201_ack_interrupt(phydev);
174 val = BIT(13) | BIT(12) | BIT(11);
175 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
178 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
182 err = rtl8201_ack_interrupt(phydev);
188 static int rtl8211b_config_intr(struct phy_device *phydev)
192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
193 err = rtl821x_ack_interrupt(phydev);
197 err = phy_write(phydev, RTL821x_INER,
200 err = phy_write(phydev, RTL821x_INER, 0);
204 err = rtl821x_ack_interrupt(phydev);
210 static int rtl8211e_config_intr(struct phy_device *phydev)
214 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
215 err = rtl821x_ack_interrupt(phydev);
219 err = phy_write(phydev, RTL821x_INER,
220 RTL8211E_INER_LINK_STATUS);
222 err = phy_write(phydev, RTL821x_INER, 0);
226 err = rtl821x_ack_interrupt(phydev);
232 static int rtl8211f_config_intr(struct phy_device *phydev)
237 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
238 err = rtl8211f_ack_interrupt(phydev);
242 val = RTL8211F_INER_LINK_STATUS;
243 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
246 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
250 err = rtl8211f_ack_interrupt(phydev);
256 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
260 irq_status = phy_read(phydev, RTL8201F_ISR);
261 if (irq_status < 0) {
266 if (!(irq_status & RTL8201F_ISR_MASK))
269 phy_trigger_machine(phydev);
274 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
276 int irq_status, irq_enabled;
278 irq_status = phy_read(phydev, RTL821x_INSR);
279 if (irq_status < 0) {
284 irq_enabled = phy_read(phydev, RTL821x_INER);
285 if (irq_enabled < 0) {
290 if (!(irq_status & irq_enabled))
293 phy_trigger_machine(phydev);
298 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
302 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
303 if (irq_status < 0) {
308 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
311 phy_trigger_machine(phydev);
316 static int rtl8211_config_aneg(struct phy_device *phydev)
320 ret = genphy_config_aneg(phydev);
324 /* Quirk was copied from vendor driver. Unfortunately it includes no
325 * description of the magic numbers.
327 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
328 phy_write(phydev, 0x17, 0x2138);
329 phy_write(phydev, 0x0e, 0x0260);
331 phy_write(phydev, 0x17, 0x2108);
332 phy_write(phydev, 0x0e, 0x0000);
338 static int rtl8211c_config_init(struct phy_device *phydev)
340 /* RTL8211C has an issue when operating in Gigabit slave mode */
341 return phy_set_bits(phydev, MII_CTRL1000,
342 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
345 static int rtl8211f_config_init(struct phy_device *phydev)
347 struct rtl821x_priv *priv = phydev->priv;
348 struct device *dev = &phydev->mdio.dev;
349 u16 val_txdly, val_rxdly;
352 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
353 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
356 dev_err(dev, "aldps mode configuration failed: %pe\n",
361 switch (phydev->interface) {
362 case PHY_INTERFACE_MODE_RGMII:
367 case PHY_INTERFACE_MODE_RGMII_RXID:
369 val_rxdly = RTL8211F_RX_DELAY;
372 case PHY_INTERFACE_MODE_RGMII_TXID:
373 val_txdly = RTL8211F_TX_DELAY;
377 case PHY_INTERFACE_MODE_RGMII_ID:
378 val_txdly = RTL8211F_TX_DELAY;
379 val_rxdly = RTL8211F_RX_DELAY;
382 default: /* the rest of the modes imply leaving delay as is. */
386 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
389 dev_err(dev, "Failed to update the TX delay register\n");
393 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
394 val_txdly ? "Enabling" : "Disabling");
397 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
398 val_txdly ? "enabled" : "disabled");
401 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
404 dev_err(dev, "Failed to update the RX delay register\n");
408 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
409 val_rxdly ? "Enabling" : "Disabling");
412 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
413 val_rxdly ? "enabled" : "disabled");
416 if (priv->has_phycr2) {
417 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
418 RTL8211F_CLKOUT_EN, priv->phycr2);
420 dev_err(dev, "clkout configuration failed: %pe\n",
425 return genphy_soft_reset(phydev);
431 static int rtl821x_suspend(struct phy_device *phydev)
433 struct rtl821x_priv *priv = phydev->priv;
436 if (!phydev->wol_enabled) {
437 ret = genphy_suspend(phydev);
442 clk_disable_unprepare(priv->clk);
448 static int rtl821x_resume(struct phy_device *phydev)
450 struct rtl821x_priv *priv = phydev->priv;
453 if (!phydev->wol_enabled)
454 clk_prepare_enable(priv->clk);
456 ret = genphy_resume(phydev);
465 static int rtl8211e_config_init(struct phy_device *phydev)
467 int ret = 0, oldpage;
470 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
471 switch (phydev->interface) {
472 case PHY_INTERFACE_MODE_RGMII:
473 val = RTL8211E_CTRL_DELAY | 0;
475 case PHY_INTERFACE_MODE_RGMII_ID:
476 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
478 case PHY_INTERFACE_MODE_RGMII_RXID:
479 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
481 case PHY_INTERFACE_MODE_RGMII_TXID:
482 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
484 default: /* the rest of the modes imply leaving delays as is. */
488 /* According to a sample driver there is a 0x1c config register on the
489 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
490 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
491 * The configuration register definition:
493 * 13 = Force Tx RX Delay controlled by bit12 bit11,
494 * 12 = RX Delay, 11 = TX Delay
495 * 10:0 = Test && debug settings reserved by realtek
497 oldpage = phy_select_page(phydev, 0x7);
499 goto err_restore_page;
501 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
503 goto err_restore_page;
505 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
506 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
510 return phy_restore_page(phydev, oldpage, ret);
513 static int rtl8211b_suspend(struct phy_device *phydev)
515 phy_write(phydev, MII_MMD_DATA, BIT(9));
517 return genphy_suspend(phydev);
520 static int rtl8211b_resume(struct phy_device *phydev)
522 phy_write(phydev, MII_MMD_DATA, 0);
524 return genphy_resume(phydev);
527 static int rtl8366rb_config_init(struct phy_device *phydev)
531 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
532 RTL8366RB_POWER_SAVE_ON);
534 dev_err(&phydev->mdio.dev,
535 "error enabling power management\n");
541 /* get actual speed to cover the downshift case */
542 static int rtlgen_get_speed(struct phy_device *phydev)
549 val = phy_read_paged(phydev, 0xa43, 0x12);
553 switch (val & RTLGEN_SPEED_MASK) {
555 phydev->speed = SPEED_10;
558 phydev->speed = SPEED_100;
561 phydev->speed = SPEED_1000;
564 phydev->speed = SPEED_10000;
567 phydev->speed = SPEED_2500;
570 phydev->speed = SPEED_5000;
579 static int rtlgen_read_status(struct phy_device *phydev)
583 ret = genphy_read_status(phydev);
587 return rtlgen_get_speed(phydev);
590 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
594 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
595 rtl821x_write_page(phydev, 0xa5c);
596 ret = __phy_read(phydev, 0x12);
597 rtl821x_write_page(phydev, 0);
598 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
599 rtl821x_write_page(phydev, 0xa5d);
600 ret = __phy_read(phydev, 0x10);
601 rtl821x_write_page(phydev, 0);
602 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
603 rtl821x_write_page(phydev, 0xa5d);
604 ret = __phy_read(phydev, 0x11);
605 rtl821x_write_page(phydev, 0);
613 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
618 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
619 rtl821x_write_page(phydev, 0xa5d);
620 ret = __phy_write(phydev, 0x10, val);
621 rtl821x_write_page(phydev, 0);
629 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
631 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
633 if (ret != -EOPNOTSUPP)
636 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
637 rtl821x_write_page(phydev, 0xa6e);
638 ret = __phy_read(phydev, 0x16);
639 rtl821x_write_page(phydev, 0);
640 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
641 rtl821x_write_page(phydev, 0xa6d);
642 ret = __phy_read(phydev, 0x12);
643 rtl821x_write_page(phydev, 0);
644 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
645 rtl821x_write_page(phydev, 0xa6d);
646 ret = __phy_read(phydev, 0x10);
647 rtl821x_write_page(phydev, 0);
653 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
656 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
658 if (ret != -EOPNOTSUPP)
661 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
662 rtl821x_write_page(phydev, 0xa6d);
663 ret = __phy_write(phydev, 0x12, val);
664 rtl821x_write_page(phydev, 0);
670 static int rtl822x_get_features(struct phy_device *phydev)
674 val = phy_read_paged(phydev, 0xa61, 0x13);
678 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
679 phydev->supported, val & RTL_SUPPORTS_2500FULL);
680 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
681 phydev->supported, val & RTL_SUPPORTS_5000FULL);
682 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
683 phydev->supported, val & RTL_SUPPORTS_10000FULL);
685 return genphy_read_abilities(phydev);
688 static int rtl822x_config_aneg(struct phy_device *phydev)
692 if (phydev->autoneg == AUTONEG_ENABLE) {
695 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
696 phydev->advertising))
697 adv2500 = RTL_ADV_2500FULL;
699 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
700 RTL_ADV_2500FULL, adv2500);
705 return __genphy_config_aneg(phydev, ret);
708 static int rtl822x_read_status(struct phy_device *phydev)
712 if (phydev->autoneg == AUTONEG_ENABLE) {
713 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
718 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
719 phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
720 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
721 phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
722 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
723 phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
726 ret = genphy_read_status(phydev);
730 return rtlgen_get_speed(phydev);
733 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
737 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
738 val = phy_read(phydev, 0x13);
739 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
741 return val >= 0 && val & RTL_SUPPORTS_2500FULL;
744 static int rtlgen_match_phy_device(struct phy_device *phydev)
746 return phydev->phy_id == RTL_GENERIC_PHYID &&
747 !rtlgen_supports_2_5gbps(phydev);
750 static int rtl8226_match_phy_device(struct phy_device *phydev)
752 return phydev->phy_id == RTL_GENERIC_PHYID &&
753 rtlgen_supports_2_5gbps(phydev);
756 static int rtlgen_resume(struct phy_device *phydev)
758 int ret = genphy_resume(phydev);
760 /* Internal PHY's from RTL8168h up may not be instantly ready */
766 static int rtl9000a_config_init(struct phy_device *phydev)
768 phydev->autoneg = AUTONEG_DISABLE;
769 phydev->speed = SPEED_100;
770 phydev->duplex = DUPLEX_FULL;
775 static int rtl9000a_config_aneg(struct phy_device *phydev)
780 switch (phydev->master_slave_set) {
781 case MASTER_SLAVE_CFG_MASTER_FORCE:
782 ctl |= CTL1000_AS_MASTER;
784 case MASTER_SLAVE_CFG_SLAVE_FORCE:
786 case MASTER_SLAVE_CFG_UNKNOWN:
787 case MASTER_SLAVE_CFG_UNSUPPORTED:
790 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
794 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
796 ret = genphy_soft_reset(phydev);
801 static int rtl9000a_read_status(struct phy_device *phydev)
805 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
806 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
808 ret = genphy_update_link(phydev);
812 ret = phy_read(phydev, MII_CTRL1000);
815 if (ret & CTL1000_AS_MASTER)
816 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
818 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
820 ret = phy_read(phydev, MII_STAT1000);
823 if (ret & LPA_1000MSRES)
824 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
826 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
831 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
835 err = phy_read(phydev, RTL8211F_INSR);
837 return (err < 0) ? err : 0;
840 static int rtl9000a_config_intr(struct phy_device *phydev)
845 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
846 err = rtl9000a_ack_interrupt(phydev);
850 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
851 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
854 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
858 err = rtl9000a_ack_interrupt(phydev);
861 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
864 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
868 irq_status = phy_read(phydev, RTL8211F_INSR);
869 if (irq_status < 0) {
874 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
877 phy_trigger_machine(phydev);
882 static struct phy_driver realtek_drvs[] = {
884 PHY_ID_MATCH_EXACT(0x00008201),
885 .name = "RTL8201CP Ethernet",
886 .read_page = rtl821x_read_page,
887 .write_page = rtl821x_write_page,
889 PHY_ID_MATCH_EXACT(0x001cc816),
890 .name = "RTL8201F Fast Ethernet",
891 .config_intr = &rtl8201_config_intr,
892 .handle_interrupt = rtl8201_handle_interrupt,
893 .suspend = genphy_suspend,
894 .resume = genphy_resume,
895 .read_page = rtl821x_read_page,
896 .write_page = rtl821x_write_page,
898 PHY_ID_MATCH_MODEL(0x001cc880),
899 .name = "RTL8208 Fast Ethernet",
900 .read_mmd = genphy_read_mmd_unsupported,
901 .write_mmd = genphy_write_mmd_unsupported,
902 .suspend = genphy_suspend,
903 .resume = genphy_resume,
904 .read_page = rtl821x_read_page,
905 .write_page = rtl821x_write_page,
907 PHY_ID_MATCH_EXACT(0x001cc910),
908 .name = "RTL8211 Gigabit Ethernet",
909 .config_aneg = rtl8211_config_aneg,
910 .read_mmd = &genphy_read_mmd_unsupported,
911 .write_mmd = &genphy_write_mmd_unsupported,
912 .read_page = rtl821x_read_page,
913 .write_page = rtl821x_write_page,
915 PHY_ID_MATCH_EXACT(0x001cc912),
916 .name = "RTL8211B Gigabit Ethernet",
917 .config_intr = &rtl8211b_config_intr,
918 .handle_interrupt = rtl821x_handle_interrupt,
919 .read_mmd = &genphy_read_mmd_unsupported,
920 .write_mmd = &genphy_write_mmd_unsupported,
921 .suspend = rtl8211b_suspend,
922 .resume = rtl8211b_resume,
923 .read_page = rtl821x_read_page,
924 .write_page = rtl821x_write_page,
926 PHY_ID_MATCH_EXACT(0x001cc913),
927 .name = "RTL8211C Gigabit Ethernet",
928 .config_init = rtl8211c_config_init,
929 .read_mmd = &genphy_read_mmd_unsupported,
930 .write_mmd = &genphy_write_mmd_unsupported,
931 .read_page = rtl821x_read_page,
932 .write_page = rtl821x_write_page,
934 PHY_ID_MATCH_EXACT(0x001cc914),
935 .name = "RTL8211DN Gigabit Ethernet",
936 .config_intr = rtl8211e_config_intr,
937 .handle_interrupt = rtl821x_handle_interrupt,
938 .suspend = genphy_suspend,
939 .resume = genphy_resume,
940 .read_page = rtl821x_read_page,
941 .write_page = rtl821x_write_page,
943 PHY_ID_MATCH_EXACT(0x001cc915),
944 .name = "RTL8211E Gigabit Ethernet",
945 .config_init = &rtl8211e_config_init,
946 .config_intr = &rtl8211e_config_intr,
947 .handle_interrupt = rtl821x_handle_interrupt,
948 .suspend = genphy_suspend,
949 .resume = genphy_resume,
950 .read_page = rtl821x_read_page,
951 .write_page = rtl821x_write_page,
953 PHY_ID_MATCH_EXACT(0x001cc916),
954 .name = "RTL8211F Gigabit Ethernet",
955 .probe = rtl821x_probe,
956 .config_init = &rtl8211f_config_init,
957 .read_status = rtlgen_read_status,
958 .config_intr = &rtl8211f_config_intr,
959 .handle_interrupt = rtl8211f_handle_interrupt,
960 .suspend = rtl821x_suspend,
961 .resume = rtl821x_resume,
962 .read_page = rtl821x_read_page,
963 .write_page = rtl821x_write_page,
964 .flags = PHY_ALWAYS_CALL_SUSPEND,
966 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
967 .name = "RTL8211F-VD Gigabit Ethernet",
968 .probe = rtl821x_probe,
969 .config_init = &rtl8211f_config_init,
970 .read_status = rtlgen_read_status,
971 .config_intr = &rtl8211f_config_intr,
972 .handle_interrupt = rtl8211f_handle_interrupt,
973 .suspend = rtl821x_suspend,
974 .resume = rtl821x_resume,
975 .read_page = rtl821x_read_page,
976 .write_page = rtl821x_write_page,
977 .flags = PHY_ALWAYS_CALL_SUSPEND,
979 .name = "Generic FE-GE Realtek PHY",
980 .match_phy_device = rtlgen_match_phy_device,
981 .read_status = rtlgen_read_status,
982 .suspend = genphy_suspend,
983 .resume = rtlgen_resume,
984 .read_page = rtl821x_read_page,
985 .write_page = rtl821x_write_page,
986 .read_mmd = rtlgen_read_mmd,
987 .write_mmd = rtlgen_write_mmd,
989 .name = "RTL8226 2.5Gbps PHY",
990 .match_phy_device = rtl8226_match_phy_device,
991 .get_features = rtl822x_get_features,
992 .config_aneg = rtl822x_config_aneg,
993 .read_status = rtl822x_read_status,
994 .suspend = genphy_suspend,
995 .resume = rtlgen_resume,
996 .read_page = rtl821x_read_page,
997 .write_page = rtl821x_write_page,
998 .read_mmd = rtl822x_read_mmd,
999 .write_mmd = rtl822x_write_mmd,
1001 PHY_ID_MATCH_EXACT(0x001cc840),
1002 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1003 .get_features = rtl822x_get_features,
1004 .config_aneg = rtl822x_config_aneg,
1005 .read_status = rtl822x_read_status,
1006 .suspend = genphy_suspend,
1007 .resume = rtlgen_resume,
1008 .read_page = rtl821x_read_page,
1009 .write_page = rtl821x_write_page,
1010 .read_mmd = rtl822x_read_mmd,
1011 .write_mmd = rtl822x_write_mmd,
1013 PHY_ID_MATCH_EXACT(0x001cc838),
1014 .name = "RTL8226-CG 2.5Gbps PHY",
1015 .get_features = rtl822x_get_features,
1016 .config_aneg = rtl822x_config_aneg,
1017 .read_status = rtl822x_read_status,
1018 .suspend = genphy_suspend,
1019 .resume = rtlgen_resume,
1020 .read_page = rtl821x_read_page,
1021 .write_page = rtl821x_write_page,
1023 PHY_ID_MATCH_EXACT(0x001cc848),
1024 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1025 .get_features = rtl822x_get_features,
1026 .config_aneg = rtl822x_config_aneg,
1027 .read_status = rtl822x_read_status,
1028 .suspend = genphy_suspend,
1029 .resume = rtlgen_resume,
1030 .read_page = rtl821x_read_page,
1031 .write_page = rtl821x_write_page,
1033 PHY_ID_MATCH_EXACT(0x001cc849),
1034 .name = "RTL8221B-VB-CG 2.5Gbps PHY",
1035 .get_features = rtl822x_get_features,
1036 .config_aneg = rtl822x_config_aneg,
1037 .read_status = rtl822x_read_status,
1038 .suspend = genphy_suspend,
1039 .resume = rtlgen_resume,
1040 .read_page = rtl821x_read_page,
1041 .write_page = rtl821x_write_page,
1043 PHY_ID_MATCH_EXACT(0x001cc84a),
1044 .name = "RTL8221B-VM-CG 2.5Gbps PHY",
1045 .get_features = rtl822x_get_features,
1046 .config_aneg = rtl822x_config_aneg,
1047 .read_status = rtl822x_read_status,
1048 .suspend = genphy_suspend,
1049 .resume = rtlgen_resume,
1050 .read_page = rtl821x_read_page,
1051 .write_page = rtl821x_write_page,
1053 PHY_ID_MATCH_EXACT(0x001cc961),
1054 .name = "RTL8366RB Gigabit Ethernet",
1055 .config_init = &rtl8366rb_config_init,
1056 /* These interrupts are handled by the irq controller
1057 * embedded inside the RTL8366RB, they get unmasked when the
1058 * irq is requested and ACKed by reading the status register,
1059 * which is done by the irqchip code.
1061 .config_intr = genphy_no_config_intr,
1062 .handle_interrupt = genphy_handle_interrupt_no_ack,
1063 .suspend = genphy_suspend,
1064 .resume = genphy_resume,
1066 PHY_ID_MATCH_EXACT(0x001ccb00),
1067 .name = "RTL9000AA_RTL9000AN Ethernet",
1068 .features = PHY_BASIC_T1_FEATURES,
1069 .config_init = rtl9000a_config_init,
1070 .config_aneg = rtl9000a_config_aneg,
1071 .read_status = rtl9000a_read_status,
1072 .config_intr = rtl9000a_config_intr,
1073 .handle_interrupt = rtl9000a_handle_interrupt,
1074 .suspend = genphy_suspend,
1075 .resume = genphy_resume,
1076 .read_page = rtl821x_read_page,
1077 .write_page = rtl821x_write_page,
1079 PHY_ID_MATCH_EXACT(0x001cc942),
1080 .name = "RTL8365MB-VC Gigabit Ethernet",
1081 /* Interrupt handling analogous to RTL8366RB */
1082 .config_intr = genphy_no_config_intr,
1083 .handle_interrupt = genphy_handle_interrupt_no_ack,
1084 .suspend = genphy_suspend,
1085 .resume = genphy_resume,
1089 module_phy_driver(realtek_drvs);
1091 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1092 { PHY_ID_MATCH_VENDOR(0x001cc800) },
1096 MODULE_DEVICE_TABLE(mdio, realtek_tbl);