2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/spi/spi.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <net/wpan-phy.h>
26 #include <net/mac802154.h>
27 #include <net/ieee802154.h>
29 /* MRF24J40 Short Address Registers */
30 #define REG_RXMCR 0x00 /* Receive MAC control */
31 #define REG_PANIDL 0x01 /* PAN ID (low) */
32 #define REG_PANIDH 0x02 /* PAN ID (high) */
33 #define REG_SADRL 0x03 /* Short address (low) */
34 #define REG_SADRH 0x04 /* Short address (high) */
35 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
36 #define REG_TXMCR 0x11 /* Transmit MAC control */
37 #define REG_PACON0 0x16 /* Power Amplifier Control */
38 #define REG_PACON1 0x17 /* Power Amplifier Control */
39 #define REG_PACON2 0x18 /* Power Amplifier Control */
40 #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
41 #define REG_TXSTAT 0x24 /* TX MAC Status Register */
42 #define REG_SOFTRST 0x2A /* Soft Reset */
43 #define REG_TXSTBL 0x2E /* TX Stabilization */
44 #define REG_INTSTAT 0x31 /* Interrupt Status */
45 #define REG_INTCON 0x32 /* Interrupt Control */
46 #define REG_RFCTL 0x36 /* RF Control Mode Register */
47 #define REG_BBREG1 0x39 /* Baseband Registers */
48 #define REG_BBREG2 0x3A /* */
49 #define REG_BBREG6 0x3E /* */
50 #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
52 /* MRF24J40 Long Address Registers */
53 #define REG_RFCON0 0x200 /* RF Control Registers */
54 #define REG_RFCON1 0x201
55 #define REG_RFCON2 0x202
56 #define REG_RFCON3 0x203
57 #define REG_RFCON5 0x205
58 #define REG_RFCON6 0x206
59 #define REG_RFCON7 0x207
60 #define REG_RFCON8 0x208
61 #define REG_RSSI 0x210
62 #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
63 #define REG_SLPCON1 0x220
64 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
65 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
66 #define REG_RX_FIFO 0x300 /* Receive FIFO */
68 /* Device configuration: Only channels 11-26 on page 0 are supported. */
69 #define MRF24J40_CHAN_MIN 11
70 #define MRF24J40_CHAN_MAX 26
71 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
72 - ((u32)1 << MRF24J40_CHAN_MIN))
74 #define TX_FIFO_SIZE 128 /* From datasheet */
75 #define RX_FIFO_SIZE 144 /* From datasheet */
76 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
78 /* Device Private Data */
80 struct spi_device *spi;
81 struct ieee802154_dev *dev;
83 struct mutex buffer_mutex; /* only used to protect buf */
84 struct completion tx_complete;
85 u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
88 /* Read/Write SPI Commands for Short and Long Address registers. */
89 #define MRF24J40_READSHORT(reg) ((reg) << 1)
90 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
91 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
92 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
94 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
95 #define MAX_SPI_SPEED_HZ 10000000
97 #define printdev(X) (&X->spi->dev)
99 static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
102 struct spi_message msg;
103 struct spi_transfer xfer = {
105 .tx_buf = devrec->buf,
106 .rx_buf = devrec->buf,
109 spi_message_init(&msg);
110 spi_message_add_tail(&xfer, &msg);
112 mutex_lock(&devrec->buffer_mutex);
113 devrec->buf[0] = MRF24J40_WRITESHORT(reg);
114 devrec->buf[1] = value;
116 ret = spi_sync(devrec->spi, &msg);
118 dev_err(printdev(devrec),
119 "SPI write Failed for short register 0x%hhx\n", reg);
121 mutex_unlock(&devrec->buffer_mutex);
125 static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
128 struct spi_message msg;
129 struct spi_transfer xfer = {
131 .tx_buf = devrec->buf,
132 .rx_buf = devrec->buf,
135 spi_message_init(&msg);
136 spi_message_add_tail(&xfer, &msg);
138 mutex_lock(&devrec->buffer_mutex);
139 devrec->buf[0] = MRF24J40_READSHORT(reg);
142 ret = spi_sync(devrec->spi, &msg);
144 dev_err(printdev(devrec),
145 "SPI read Failed for short register 0x%hhx\n", reg);
147 *val = devrec->buf[1];
149 mutex_unlock(&devrec->buffer_mutex);
153 static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
157 struct spi_message msg;
158 struct spi_transfer xfer = {
160 .tx_buf = devrec->buf,
161 .rx_buf = devrec->buf,
164 spi_message_init(&msg);
165 spi_message_add_tail(&xfer, &msg);
167 cmd = MRF24J40_READLONG(reg);
168 mutex_lock(&devrec->buffer_mutex);
169 devrec->buf[0] = cmd >> 8 & 0xff;
170 devrec->buf[1] = cmd & 0xff;
173 ret = spi_sync(devrec->spi, &msg);
175 dev_err(printdev(devrec),
176 "SPI read Failed for long register 0x%hx\n", reg);
178 *value = devrec->buf[2];
180 mutex_unlock(&devrec->buffer_mutex);
184 static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
188 struct spi_message msg;
189 struct spi_transfer xfer = {
191 .tx_buf = devrec->buf,
192 .rx_buf = devrec->buf,
195 spi_message_init(&msg);
196 spi_message_add_tail(&xfer, &msg);
198 cmd = MRF24J40_WRITELONG(reg);
199 mutex_lock(&devrec->buffer_mutex);
200 devrec->buf[0] = cmd >> 8 & 0xff;
201 devrec->buf[1] = cmd & 0xff;
202 devrec->buf[2] = val;
204 ret = spi_sync(devrec->spi, &msg);
206 dev_err(printdev(devrec),
207 "SPI write Failed for long register 0x%hx\n", reg);
209 mutex_unlock(&devrec->buffer_mutex);
213 /* This function relies on an undocumented write method. Once a write command
214 and address is set, as many bytes of data as desired can be clocked into
215 the device. The datasheet only shows setting one byte at a time. */
216 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
217 const u8 *data, size_t length)
222 struct spi_message msg;
223 struct spi_transfer addr_xfer = {
225 .tx_buf = devrec->buf,
227 struct spi_transfer lengths_xfer = {
229 .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
231 struct spi_transfer data_xfer = {
236 /* Range check the length. 2 bytes are used for the length fields.*/
237 if (length > TX_FIFO_SIZE-2) {
238 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
239 length = TX_FIFO_SIZE-2;
242 spi_message_init(&msg);
243 spi_message_add_tail(&addr_xfer, &msg);
244 spi_message_add_tail(&lengths_xfer, &msg);
245 spi_message_add_tail(&data_xfer, &msg);
247 cmd = MRF24J40_WRITELONG(reg);
248 mutex_lock(&devrec->buffer_mutex);
249 devrec->buf[0] = cmd >> 8 & 0xff;
250 devrec->buf[1] = cmd & 0xff;
251 lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
252 lengths[1] = length; /* Total length */
254 ret = spi_sync(devrec->spi, &msg);
256 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
258 mutex_unlock(&devrec->buffer_mutex);
262 static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
263 u8 *data, u8 *len, u8 *lqi)
270 struct spi_message msg;
271 struct spi_transfer addr_xfer = {
275 struct spi_transfer data_xfer = {
276 .len = 0x0, /* set below */
279 struct spi_transfer status_xfer = {
284 /* Get the length of the data in the RX FIFO. The length in this
285 * register exclues the 1-byte length field at the beginning. */
286 ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
290 /* Range check the RX FIFO length, accounting for the one-byte
291 * length field at the begining. */
292 if (rx_len > RX_FIFO_SIZE-1) {
293 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
294 rx_len = RX_FIFO_SIZE-1;
298 /* Passed in buffer wasn't big enough. Should never happen. */
299 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
303 /* Set up the commands to read the data. */
304 cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
305 addr[0] = cmd >> 8 & 0xff;
306 addr[1] = cmd & 0xff;
307 data_xfer.len = rx_len;
309 spi_message_init(&msg);
310 spi_message_add_tail(&addr_xfer, &msg);
311 spi_message_add_tail(&data_xfer, &msg);
312 spi_message_add_tail(&status_xfer, &msg);
314 ret = spi_sync(devrec->spi, &msg);
316 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
324 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
325 DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
326 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
327 lqi_rssi[0], lqi_rssi[1]);
334 static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb)
336 struct mrf24j40 *devrec = dev->priv;
340 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
342 ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
346 reinit_completion(&devrec->tx_complete);
348 /* Set TXNTRIG bit of TXNCON to send packet */
349 ret = read_short_reg(devrec, REG_TXNCON, &val);
353 /* Set TXNACKREQ if the ACK bit is set in the packet. */
354 if (skb->data[0] & IEEE802154_FC_ACK_REQ)
356 write_short_reg(devrec, REG_TXNCON, val);
358 /* Wait for the device to send the TX complete interrupt. */
359 ret = wait_for_completion_interruptible_timeout(
360 &devrec->tx_complete,
362 if (ret == -ERESTARTSYS)
365 dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n");
370 /* Check for send error from the device. */
371 ret = read_short_reg(devrec, REG_TXSTAT, &val);
375 dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n");
376 ret = -ECOMM; /* TODO: Better error code ? */
378 dev_dbg(printdev(devrec), "Packet Sent\n");
385 static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level)
388 pr_warn("mrf24j40: ed not implemented\n");
393 static int mrf24j40_start(struct ieee802154_dev *dev)
395 struct mrf24j40 *devrec = dev->priv;
399 dev_dbg(printdev(devrec), "start\n");
401 ret = read_short_reg(devrec, REG_INTCON, &val);
404 val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
405 write_short_reg(devrec, REG_INTCON, val);
410 static void mrf24j40_stop(struct ieee802154_dev *dev)
412 struct mrf24j40 *devrec = dev->priv;
416 dev_dbg(printdev(devrec), "stop\n");
418 ret = read_short_reg(devrec, REG_INTCON, &val);
421 val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
422 write_short_reg(devrec, REG_INTCON, val);
425 static int mrf24j40_set_channel(struct ieee802154_dev *dev,
426 int page, int channel)
428 struct mrf24j40 *devrec = dev->priv;
432 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
435 WARN_ON(channel < MRF24J40_CHAN_MIN);
436 WARN_ON(channel > MRF24J40_CHAN_MAX);
438 /* Set Channel TODO */
439 val = (channel-11) << 4 | 0x03;
440 write_long_reg(devrec, REG_RFCON0, val);
443 ret = read_short_reg(devrec, REG_RFCTL, &val);
447 write_short_reg(devrec, REG_RFCTL, val);
449 write_short_reg(devrec, REG_RFCTL, val);
451 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
456 static int mrf24j40_filter(struct ieee802154_dev *dev,
457 struct ieee802154_hw_addr_filt *filt,
458 unsigned long changed)
460 struct mrf24j40 *devrec = dev->priv;
462 dev_dbg(printdev(devrec), "filter\n");
464 if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
468 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
469 addrl = le16_to_cpu(filt->short_addr) & 0xff;
471 write_short_reg(devrec, REG_SADRH, addrh);
472 write_short_reg(devrec, REG_SADRL, addrl);
473 dev_dbg(printdev(devrec),
474 "Set short addr to %04hx\n", filt->short_addr);
477 if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
481 memcpy(addr, &filt->ieee_addr, 8);
482 for (i = 0; i < 8; i++)
483 write_short_reg(devrec, REG_EADR0 + i, addr[i]);
486 pr_debug("Set long addr to: ");
487 for (i = 0; i < 8; i++)
488 pr_debug("%02hhx ", addr[7 - i]);
493 if (changed & IEEE802515_AFILT_PANID_CHANGED) {
497 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
498 panidl = le16_to_cpu(filt->pan_id) & 0xff;
499 write_short_reg(devrec, REG_PANIDH, panidh);
500 write_short_reg(devrec, REG_PANIDL, panidl);
502 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
505 if (changed & IEEE802515_AFILT_PANC_CHANGED) {
506 /* Pan Coordinator */
510 ret = read_short_reg(devrec, REG_RXMCR, &val);
517 write_short_reg(devrec, REG_RXMCR, val);
519 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
520 * REG_ORDER is maintained as default (no beacon/superframe).
523 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
524 filt->pan_coord ? "on" : "off");
530 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
532 u8 len = RX_FIFO_SIZE;
538 /* Turn off reception of packets off the air. This prevents the
539 * device from overwriting the buffer while we're reading it. */
540 ret = read_short_reg(devrec, REG_BBREG1, &val);
543 val |= 4; /* SET RXDECINV */
544 write_short_reg(devrec, REG_BBREG1, val);
546 skb = alloc_skb(len, GFP_KERNEL);
552 ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
554 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
560 /* Cut off the checksum */
561 skb_trim(skb, len-2);
563 /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
564 * also from a workqueue). I think irqsafe is not necessary here.
565 * Can someone confirm? */
566 ieee802154_rx_irqsafe(devrec->dev, skb, lqi);
568 dev_dbg(printdev(devrec), "RX Handled\n");
571 /* Turn back on reception of packets off the air. */
572 ret = read_short_reg(devrec, REG_BBREG1, &val);
575 val &= ~0x4; /* Clear RXDECINV */
576 write_short_reg(devrec, REG_BBREG1, val);
581 static struct ieee802154_ops mrf24j40_ops = {
582 .owner = THIS_MODULE,
585 .start = mrf24j40_start,
586 .stop = mrf24j40_stop,
587 .set_channel = mrf24j40_set_channel,
588 .set_hw_addr_filt = mrf24j40_filter,
591 static irqreturn_t mrf24j40_isr(int irq, void *data)
593 struct mrf24j40 *devrec = data;
597 /* Read the interrupt status */
598 ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
602 /* Check for TX complete */
604 complete(&devrec->tx_complete);
608 mrf24j40_handle_rx(devrec);
614 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
619 /* Initialize the device.
620 From datasheet section 3.2: Initialization. */
621 ret = write_short_reg(devrec, REG_SOFTRST, 0x07);
625 ret = write_short_reg(devrec, REG_PACON2, 0x98);
629 ret = write_short_reg(devrec, REG_TXSTBL, 0x95);
633 ret = write_long_reg(devrec, REG_RFCON0, 0x03);
637 ret = write_long_reg(devrec, REG_RFCON1, 0x01);
641 ret = write_long_reg(devrec, REG_RFCON2, 0x80);
645 ret = write_long_reg(devrec, REG_RFCON6, 0x90);
649 ret = write_long_reg(devrec, REG_RFCON7, 0x80);
653 ret = write_long_reg(devrec, REG_RFCON8, 0x10);
657 ret = write_long_reg(devrec, REG_SLPCON1, 0x21);
661 ret = write_short_reg(devrec, REG_BBREG2, 0x80);
665 ret = write_short_reg(devrec, REG_CCAEDTH, 0x60);
669 ret = write_short_reg(devrec, REG_BBREG6, 0x40);
673 ret = write_short_reg(devrec, REG_RFCTL, 0x04);
677 ret = write_short_reg(devrec, REG_RFCTL, 0x0);
683 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
684 ret = read_short_reg(devrec, REG_RXMCR, &val);
688 val &= ~0x3; /* Clear RX mode (normal) */
690 ret = write_short_reg(devrec, REG_RXMCR, val);
700 static int mrf24j40_probe(struct spi_device *spi)
703 struct mrf24j40 *devrec;
705 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
707 devrec = devm_kzalloc(&spi->dev, sizeof(struct mrf24j40), GFP_KERNEL);
710 devrec->buf = devm_kzalloc(&spi->dev, 3, GFP_KERNEL);
714 spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
715 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
716 spi->max_speed_hz = MAX_SPI_SPEED_HZ;
718 mutex_init(&devrec->buffer_mutex);
719 init_completion(&devrec->tx_complete);
721 spi_set_drvdata(spi, devrec);
723 /* Register with the 802154 subsystem */
725 devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops);
729 devrec->dev->priv = devrec;
730 devrec->dev->parent = &devrec->spi->dev;
731 devrec->dev->phy->channels_supported[0] = CHANNEL_MASK;
732 devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK;
734 dev_dbg(printdev(devrec), "registered mrf24j40\n");
735 ret = ieee802154_register_device(devrec->dev);
737 goto err_register_device;
739 ret = mrf24j40_hw_init(devrec);
743 ret = devm_request_threaded_irq(&spi->dev,
747 IRQF_TRIGGER_LOW|IRQF_ONESHOT,
752 dev_err(printdev(devrec), "Unable to get IRQ");
760 ieee802154_unregister_device(devrec->dev);
762 ieee802154_free_device(devrec->dev);
767 static int mrf24j40_remove(struct spi_device *spi)
769 struct mrf24j40 *devrec = spi_get_drvdata(spi);
771 dev_dbg(printdev(devrec), "remove\n");
773 ieee802154_unregister_device(devrec->dev);
774 ieee802154_free_device(devrec->dev);
775 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
781 static const struct spi_device_id mrf24j40_ids[] = {
786 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
788 static struct spi_driver mrf24j40_driver = {
791 .bus = &spi_bus_type,
792 .owner = THIS_MODULE,
794 .id_table = mrf24j40_ids,
795 .probe = mrf24j40_probe,
796 .remove = mrf24j40_remove,
799 module_spi_driver(mrf24j40_driver);
801 MODULE_LICENSE("GPL");
802 MODULE_AUTHOR("Alan Ott");
803 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");