1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
58 /* Module parameters */
60 static int watchdog = TX_TIMEO;
61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
64 static int debug = -1;
65 module_param(debug, int, S_IRUGO | S_IWUSR);
66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
68 static int phyaddr = -1;
69 module_param(phyaddr, int, S_IRUGO);
70 MODULE_PARM_DESC(phyaddr, "Physical device address");
72 #define DMA_TX_SIZE 256
73 static int dma_txsize = DMA_TX_SIZE;
74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
77 #define DMA_RX_SIZE 256
78 static int dma_rxsize = DMA_RX_SIZE;
79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
82 static int flow_ctrl = FLOW_OFF;
83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
86 static int pause = PAUSE_TIME;
87 module_param(pause, int, S_IRUGO | S_IWUSR);
88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
91 static int tc = TC_DEFAULT;
92 module_param(tc, int, S_IRUGO | S_IWUSR);
93 MODULE_PARM_DESC(tc, "DMA threshold control value");
95 #define DEFAULT_BUFSIZE 1536
96 static int buf_sz = DEFAULT_BUFSIZE;
97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
101 NETIF_MSG_LINK | NETIF_MSG_IFUP |
102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
104 #define STMMAC_DEFAULT_LPI_TIMER 1000
105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111 * but passing this value so user can force to use the chain instead of the ring
113 static unsigned int chain_mode;
114 module_param(chain_mode, int, S_IRUGO);
115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
119 #ifdef CONFIG_DEBUG_FS
120 static int stmmac_init_fs(struct net_device *dev);
121 static void stmmac_exit_fs(void);
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
127 * stmmac_verify_args - verify the driver parameters.
128 * Description: it checks the driver parameters and set a default in case of
131 static void stmmac_verify_args(void)
133 if (unlikely(watchdog < 0))
135 if (unlikely(dma_rxsize < 0))
136 dma_rxsize = DMA_RX_SIZE;
137 if (unlikely(dma_txsize < 0))
138 dma_txsize = DMA_TX_SIZE;
139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140 buf_sz = DEFAULT_BUFSIZE;
141 if (unlikely(flow_ctrl > 1))
142 flow_ctrl = FLOW_AUTO;
143 else if (likely(flow_ctrl < 0))
144 flow_ctrl = FLOW_OFF;
145 if (unlikely((pause < 0) || (pause > 0xffff)))
148 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
152 * stmmac_clk_csr_set - dynamically set the MDC clock
153 * @priv: driver private structure
154 * Description: this is to dynamically set the MDC clock according to the csr
157 * If a specific clk_csr value is passed from the platform
158 * this means that the CSR Clock Range selection cannot be
159 * changed at run-time and it is fixed (as reported in the driver
160 * documentation). Viceversa the driver will try to set the MDC
161 * clock dynamically according to the actual clock input.
163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
167 clk_rate = clk_get_rate(priv->stmmac_clk);
169 /* Platform provided default clk_csr would be assumed valid
170 * for all other cases except for the below mentioned ones.
171 * For values higher than the IEEE 802.3 specified frequency
172 * we can not estimate the proper divider as it is not known
173 * the frequency of clk_csr_i. So we do not change the default
176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
177 if (clk_rate < CSR_F_35M)
178 priv->clk_csr = STMMAC_CSR_20_35M;
179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
180 priv->clk_csr = STMMAC_CSR_35_60M;
181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
182 priv->clk_csr = STMMAC_CSR_60_100M;
183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
184 priv->clk_csr = STMMAC_CSR_100_150M;
185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
186 priv->clk_csr = STMMAC_CSR_150_250M;
187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
188 priv->clk_csr = STMMAC_CSR_250_300M;
192 static void print_pkt(unsigned char *buf, int len)
194 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
195 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
198 /* minimum number of free TX descriptors required to wake up TX process */
199 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
201 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
203 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
207 * stmmac_hw_fix_mac_speed - callback for speed selection
208 * @priv: driver private structure
209 * Description: on some platforms (e.g. ST), some HW system configuraton
210 * registers have to be set according to the link speed negotiated.
212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
214 struct phy_device *phydev = priv->phydev;
216 if (likely(priv->plat->fix_mac_speed))
217 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
221 * stmmac_enable_eee_mode - check and enter in LPI mode
222 * @priv: driver private structure
223 * Description: this function is to verify and enter in LPI mode in case of
226 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
228 /* Check and enter in LPI mode */
229 if ((priv->dirty_tx == priv->cur_tx) &&
230 (priv->tx_path_in_lpi_mode == false))
231 priv->hw->mac->set_eee_mode(priv->hw);
235 * stmmac_disable_eee_mode - disable and exit from LPI mode
236 * @priv: driver private structure
237 * Description: this function is to exit and disable EEE in case of
238 * LPI state is true. This is called by the xmit.
240 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
242 priv->hw->mac->reset_eee_mode(priv->hw);
243 del_timer_sync(&priv->eee_ctrl_timer);
244 priv->tx_path_in_lpi_mode = false;
248 * stmmac_eee_ctrl_timer - EEE TX SW timer.
251 * if there is no data transfer and if we are not in LPI state,
252 * then MAC Transmitter can be moved to LPI state.
254 static void stmmac_eee_ctrl_timer(unsigned long arg)
256 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
258 stmmac_enable_eee_mode(priv);
259 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
263 * stmmac_eee_init - init EEE
264 * @priv: driver private structure
266 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
267 * can also manage EEE, this function enable the LPI state and start related
270 bool stmmac_eee_init(struct stmmac_priv *priv)
272 char *phy_bus_name = priv->plat->phy_bus_name;
276 /* Using PCS we cannot dial with the phy registers at this stage
277 * so we do not support extra feature like EEE.
279 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
280 (priv->pcs == STMMAC_PCS_RTBI))
283 /* Never init EEE in case of a switch is attached */
284 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
287 /* MAC core supports the EEE feature. */
288 if (priv->dma_cap.eee) {
289 int tx_lpi_timer = priv->tx_lpi_timer;
291 /* Check if the PHY supports EEE */
292 if (phy_init_eee(priv->phydev, 1)) {
293 /* To manage at run-time if the EEE cannot be supported
294 * anymore (for example because the lp caps have been
296 * In that case the driver disable own timers.
298 spin_lock_irqsave(&priv->lock, flags);
299 if (priv->eee_active) {
300 pr_debug("stmmac: disable EEE\n");
301 del_timer_sync(&priv->eee_ctrl_timer);
302 priv->hw->mac->set_eee_timer(priv->hw, 0,
305 priv->eee_active = 0;
306 spin_unlock_irqrestore(&priv->lock, flags);
309 /* Activate the EEE and start timers */
310 spin_lock_irqsave(&priv->lock, flags);
311 if (!priv->eee_active) {
312 priv->eee_active = 1;
313 setup_timer(&priv->eee_ctrl_timer,
314 stmmac_eee_ctrl_timer,
315 (unsigned long)priv);
316 mod_timer(&priv->eee_ctrl_timer,
317 STMMAC_LPI_T(eee_timer));
319 priv->hw->mac->set_eee_timer(priv->hw,
320 STMMAC_DEFAULT_LIT_LS,
323 /* Set HW EEE according to the speed */
324 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
327 spin_unlock_irqrestore(&priv->lock, flags);
329 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
335 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
336 * @priv: driver private structure
337 * @entry : descriptor index to be used.
338 * @skb : the socket buffer
340 * This function will read timestamp from the descriptor & pass it to stack.
341 * and also perform some sanity checks.
343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
344 unsigned int entry, struct sk_buff *skb)
346 struct skb_shared_hwtstamps shhwtstamp;
350 if (!priv->hwts_tx_en)
353 /* exit if skb doesn't support hw tstamp */
354 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
358 desc = (priv->dma_etx + entry);
360 desc = (priv->dma_tx + entry);
362 /* check tx tstamp status */
363 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
366 /* get the valid tstamp */
367 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
369 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
370 shhwtstamp.hwtstamp = ns_to_ktime(ns);
371 /* pass tstamp to stack */
372 skb_tstamp_tx(skb, &shhwtstamp);
377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
378 * @priv: driver private structure
379 * @entry : descriptor index to be used.
380 * @skb : the socket buffer
382 * This function will read received packet's timestamp from the descriptor
383 * and pass it to stack. It also perform some sanity checks.
385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
386 unsigned int entry, struct sk_buff *skb)
388 struct skb_shared_hwtstamps *shhwtstamp = NULL;
392 if (!priv->hwts_rx_en)
396 desc = (priv->dma_erx + entry);
398 desc = (priv->dma_rx + entry);
400 /* exit if rx tstamp is not valid */
401 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
404 /* get valid tstamp */
405 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
406 shhwtstamp = skb_hwtstamps(skb);
407 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
408 shhwtstamp->hwtstamp = ns_to_ktime(ns);
412 * stmmac_hwtstamp_ioctl - control hardware timestamping.
413 * @dev: device pointer.
414 * @ifr: An IOCTL specefic structure, that can contain a pointer to
415 * a proprietary structure used to pass information to the driver.
417 * This function configures the MAC to enable/disable both outgoing(TX)
418 * and incoming(RX) packets time stamping based on user input.
420 * 0 on success and an appropriate -ve integer on failure.
422 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
424 struct stmmac_priv *priv = netdev_priv(dev);
425 struct hwtstamp_config config;
430 u32 ptp_over_ipv4_udp = 0;
431 u32 ptp_over_ipv6_udp = 0;
432 u32 ptp_over_ethernet = 0;
433 u32 snap_type_sel = 0;
434 u32 ts_master_en = 0;
438 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
439 netdev_alert(priv->dev, "No support for HW time stamping\n");
440 priv->hwts_tx_en = 0;
441 priv->hwts_rx_en = 0;
446 if (copy_from_user(&config, ifr->ifr_data,
447 sizeof(struct hwtstamp_config)))
450 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
451 __func__, config.flags, config.tx_type, config.rx_filter);
453 /* reserved for future extensions */
457 if (config.tx_type != HWTSTAMP_TX_OFF &&
458 config.tx_type != HWTSTAMP_TX_ON)
462 switch (config.rx_filter) {
463 case HWTSTAMP_FILTER_NONE:
464 /* time stamp no incoming packet at all */
465 config.rx_filter = HWTSTAMP_FILTER_NONE;
468 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
469 /* PTP v1, UDP, any kind of event packet */
470 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
471 /* take time stamp for all event messages */
472 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
474 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
475 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
478 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
479 /* PTP v1, UDP, Sync packet */
480 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
481 /* take time stamp for SYNC messages only */
482 ts_event_en = PTP_TCR_TSEVNTENA;
484 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
485 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
488 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
489 /* PTP v1, UDP, Delay_req packet */
490 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
491 /* take time stamp for Delay_Req messages only */
492 ts_master_en = PTP_TCR_TSMSTRENA;
493 ts_event_en = PTP_TCR_TSEVNTENA;
495 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
496 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
499 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
500 /* PTP v2, UDP, any kind of event packet */
501 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
502 ptp_v2 = PTP_TCR_TSVER2ENA;
503 /* take time stamp for all event messages */
504 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
506 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
507 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
510 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
511 /* PTP v2, UDP, Sync packet */
512 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
513 ptp_v2 = PTP_TCR_TSVER2ENA;
514 /* take time stamp for SYNC messages only */
515 ts_event_en = PTP_TCR_TSEVNTENA;
517 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
518 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
522 /* PTP v2, UDP, Delay_req packet */
523 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
524 ptp_v2 = PTP_TCR_TSVER2ENA;
525 /* take time stamp for Delay_Req messages only */
526 ts_master_en = PTP_TCR_TSMSTRENA;
527 ts_event_en = PTP_TCR_TSEVNTENA;
529 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
530 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
533 case HWTSTAMP_FILTER_PTP_V2_EVENT:
534 /* PTP v2/802.AS1 any layer, any kind of event packet */
535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
536 ptp_v2 = PTP_TCR_TSVER2ENA;
537 /* take time stamp for all event messages */
538 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
540 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
541 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
542 ptp_over_ethernet = PTP_TCR_TSIPENA;
545 case HWTSTAMP_FILTER_PTP_V2_SYNC:
546 /* PTP v2/802.AS1, any layer, Sync packet */
547 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
548 ptp_v2 = PTP_TCR_TSVER2ENA;
549 /* take time stamp for SYNC messages only */
550 ts_event_en = PTP_TCR_TSEVNTENA;
552 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
553 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
554 ptp_over_ethernet = PTP_TCR_TSIPENA;
557 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
558 /* PTP v2/802.AS1, any layer, Delay_req packet */
559 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
560 ptp_v2 = PTP_TCR_TSVER2ENA;
561 /* take time stamp for Delay_Req messages only */
562 ts_master_en = PTP_TCR_TSMSTRENA;
563 ts_event_en = PTP_TCR_TSEVNTENA;
565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
567 ptp_over_ethernet = PTP_TCR_TSIPENA;
570 case HWTSTAMP_FILTER_ALL:
571 /* time stamp any incoming packet */
572 config.rx_filter = HWTSTAMP_FILTER_ALL;
573 tstamp_all = PTP_TCR_TSENALL;
580 switch (config.rx_filter) {
581 case HWTSTAMP_FILTER_NONE:
582 config.rx_filter = HWTSTAMP_FILTER_NONE;
585 /* PTP v1, UDP, any kind of event packet */
586 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
590 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
591 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
593 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
594 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
596 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
597 tstamp_all | ptp_v2 | ptp_over_ethernet |
598 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
599 ts_master_en | snap_type_sel);
601 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
603 /* program Sub Second Increment reg */
604 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
606 /* calculate default added value:
608 * addend = (2^32)/freq_div_ratio;
609 * where, freq_div_ratio = clk_ptp_ref_i/50MHz
610 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
611 * NOTE: clk_ptp_ref_i should be >= 50MHz to
612 * achive 20ns accuracy.
614 * 2^x * y == (y << x), hence
615 * 2^32 * 50000000 ==> (50000000 << 32)
617 temp = (u64) (50000000ULL << 32);
618 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
619 priv->hw->ptp->config_addend(priv->ioaddr,
620 priv->default_addend);
622 /* initialize system time */
623 getnstimeofday(&now);
624 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
628 return copy_to_user(ifr->ifr_data, &config,
629 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
633 * stmmac_init_ptp - init PTP
634 * @priv: driver private structure
635 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
636 * This is done by looking at the HW cap. register.
637 * This function also registers the ptp driver.
639 static int stmmac_init_ptp(struct stmmac_priv *priv)
641 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
644 /* Fall-back to main clock in case of no PTP ref is passed */
645 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
646 if (IS_ERR(priv->clk_ptp_ref)) {
647 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
648 priv->clk_ptp_ref = NULL;
650 clk_prepare_enable(priv->clk_ptp_ref);
651 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
655 if (priv->dma_cap.atime_stamp && priv->extend_desc)
658 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
659 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
661 if (netif_msg_hw(priv) && priv->adv_ts)
662 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
664 priv->hw->ptp = &stmmac_ptp;
665 priv->hwts_tx_en = 0;
666 priv->hwts_rx_en = 0;
668 return stmmac_ptp_register(priv);
671 static void stmmac_release_ptp(struct stmmac_priv *priv)
673 if (priv->clk_ptp_ref)
674 clk_disable_unprepare(priv->clk_ptp_ref);
675 stmmac_ptp_unregister(priv);
679 * stmmac_adjust_link - adjusts the link parameters
680 * @dev: net device structure
681 * Description: this is the helper called by the physical abstraction layer
682 * drivers to communicate the phy link status. According the speed and duplex
683 * this driver can invoke registered glue-logic as well.
684 * It also invoke the eee initialization because it could happen when switch
685 * on different networks (that are eee capable).
687 static void stmmac_adjust_link(struct net_device *dev)
689 struct stmmac_priv *priv = netdev_priv(dev);
690 struct phy_device *phydev = priv->phydev;
693 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
698 spin_lock_irqsave(&priv->lock, flags);
701 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
703 /* Now we make sure that we can be in full duplex mode.
704 * If not, we operate in half-duplex mode. */
705 if (phydev->duplex != priv->oldduplex) {
707 if (!(phydev->duplex))
708 ctrl &= ~priv->hw->link.duplex;
710 ctrl |= priv->hw->link.duplex;
711 priv->oldduplex = phydev->duplex;
713 /* Flow Control operation */
715 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
718 if (phydev->speed != priv->speed) {
720 switch (phydev->speed) {
722 if (likely(priv->plat->has_gmac))
723 ctrl &= ~priv->hw->link.port;
724 stmmac_hw_fix_mac_speed(priv);
728 if (priv->plat->has_gmac) {
729 ctrl |= priv->hw->link.port;
730 if (phydev->speed == SPEED_100) {
731 ctrl |= priv->hw->link.speed;
733 ctrl &= ~(priv->hw->link.speed);
736 ctrl &= ~priv->hw->link.port;
738 stmmac_hw_fix_mac_speed(priv);
741 if (netif_msg_link(priv))
742 pr_warn("%s: Speed (%d) not 10/100\n",
743 dev->name, phydev->speed);
747 priv->speed = phydev->speed;
750 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
752 if (!priv->oldlink) {
756 } else if (priv->oldlink) {
760 priv->oldduplex = -1;
763 if (new_state && netif_msg_link(priv))
764 phy_print_status(phydev);
766 spin_unlock_irqrestore(&priv->lock, flags);
768 /* At this stage, it could be needed to setup the EEE or adjust some
769 * MAC related HW registers.
771 priv->eee_enabled = stmmac_eee_init(priv);
775 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
776 * @priv: driver private structure
777 * Description: this is to verify if the HW supports the PCS.
778 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
779 * configured for the TBI, RTBI, or SGMII PHY interface.
781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
783 int interface = priv->plat->interface;
785 if (priv->dma_cap.pcs) {
786 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
787 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
788 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
789 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
790 pr_debug("STMMAC: PCS RGMII support enable\n");
791 priv->pcs = STMMAC_PCS_RGMII;
792 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
793 pr_debug("STMMAC: PCS SGMII support enable\n");
794 priv->pcs = STMMAC_PCS_SGMII;
800 * stmmac_init_phy - PHY initialization
801 * @dev: net device structure
802 * Description: it initializes the driver's PHY state, and attaches the PHY
807 static int stmmac_init_phy(struct net_device *dev)
809 struct stmmac_priv *priv = netdev_priv(dev);
810 struct phy_device *phydev;
811 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
812 char bus_id[MII_BUS_ID_SIZE];
813 int interface = priv->plat->interface;
814 int max_speed = priv->plat->max_speed;
817 priv->oldduplex = -1;
819 if (priv->plat->phy_bus_name)
820 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
821 priv->plat->phy_bus_name, priv->plat->bus_id);
823 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
826 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
827 priv->plat->phy_addr);
828 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
830 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
832 if (IS_ERR(phydev)) {
833 pr_err("%s: Could not attach to PHY\n", dev->name);
834 return PTR_ERR(phydev);
837 /* Stop Advertising 1000BASE Capability if interface is not GMII */
838 if ((interface == PHY_INTERFACE_MODE_MII) ||
839 (interface == PHY_INTERFACE_MODE_RMII) ||
840 (max_speed < 1000 && max_speed > 0))
841 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
842 SUPPORTED_1000baseT_Full);
845 * Broken HW is sometimes missing the pull-up resistor on the
846 * MDIO line, which results in reads to non-existent devices returning
847 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
849 * Note: phydev->phy_id is the result of reading the UID PHY registers.
851 if (phydev->phy_id == 0) {
852 phy_disconnect(phydev);
855 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
856 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
858 priv->phydev = phydev;
864 * stmmac_display_ring - display ring
865 * @head: pointer to the head of the ring passed.
866 * @size: size of the ring.
867 * @extend_desc: to verify if extended descriptors are used.
868 * Description: display the control/status and buffer descriptors.
870 static void stmmac_display_ring(void *head, int size, int extend_desc)
873 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
874 struct dma_desc *p = (struct dma_desc *)head;
876 for (i = 0; i < size; i++) {
880 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
881 i, (unsigned int)virt_to_phys(ep),
882 (unsigned int)x, (unsigned int)(x >> 32),
883 ep->basic.des2, ep->basic.des3);
887 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
888 i, (unsigned int)virt_to_phys(p),
889 (unsigned int)x, (unsigned int)(x >> 32),
897 static void stmmac_display_rings(struct stmmac_priv *priv)
899 unsigned int txsize = priv->dma_tx_size;
900 unsigned int rxsize = priv->dma_rx_size;
902 if (priv->extend_desc) {
903 pr_info("Extended RX descriptor ring:\n");
904 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
905 pr_info("Extended TX descriptor ring:\n");
906 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
908 pr_info("RX descriptor ring:\n");
909 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
910 pr_info("TX descriptor ring:\n");
911 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
915 static int stmmac_set_bfsize(int mtu, int bufsize)
919 if (mtu >= BUF_SIZE_4KiB)
921 else if (mtu >= BUF_SIZE_2KiB)
923 else if (mtu > DEFAULT_BUFSIZE)
926 ret = DEFAULT_BUFSIZE;
932 * stmmac_clear_descriptors - clear descriptors
933 * @priv: driver private structure
934 * Description: this function is called to clear the tx and rx descriptors
935 * in case of both basic and extended descriptors are used.
937 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
940 unsigned int txsize = priv->dma_tx_size;
941 unsigned int rxsize = priv->dma_rx_size;
943 /* Clear the Rx/Tx descriptors */
944 for (i = 0; i < rxsize; i++)
945 if (priv->extend_desc)
946 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
947 priv->use_riwt, priv->mode,
950 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
951 priv->use_riwt, priv->mode,
953 for (i = 0; i < txsize; i++)
954 if (priv->extend_desc)
955 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
959 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
965 * stmmac_init_rx_buffers - init the RX descriptor buffer.
966 * @priv: driver private structure
967 * @p: descriptor pointer
968 * @i: descriptor index
970 * Description: this function is called to allocate a receive buffer, perform
971 * the DMA mapping and init the descriptor.
973 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
978 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
981 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
984 skb_reserve(skb, NET_IP_ALIGN);
985 priv->rx_skbuff[i] = skb;
986 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
989 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
990 pr_err("%s: DMA mapping error\n", __func__);
991 dev_kfree_skb_any(skb);
995 p->des2 = priv->rx_skbuff_dma[i];
997 if ((priv->hw->mode->init_desc3) &&
998 (priv->dma_buf_sz == BUF_SIZE_16KiB))
999 priv->hw->mode->init_desc3(p);
1004 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1006 if (priv->rx_skbuff[i]) {
1007 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1008 priv->dma_buf_sz, DMA_FROM_DEVICE);
1009 dev_kfree_skb_any(priv->rx_skbuff[i]);
1011 priv->rx_skbuff[i] = NULL;
1015 * init_dma_desc_rings - init the RX/TX descriptor rings
1016 * @dev: net device structure
1018 * Description: this function initializes the DMA RX/TX descriptors
1019 * and allocates the socket buffers. It suppors the chained and ring
1022 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1025 struct stmmac_priv *priv = netdev_priv(dev);
1026 unsigned int txsize = priv->dma_tx_size;
1027 unsigned int rxsize = priv->dma_rx_size;
1028 unsigned int bfsize = 0;
1031 if (priv->hw->mode->set_16kib_bfsize)
1032 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1034 if (bfsize < BUF_SIZE_16KiB)
1035 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1037 priv->dma_buf_sz = bfsize;
1039 if (netif_msg_probe(priv))
1040 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1041 txsize, rxsize, bfsize);
1043 if (netif_msg_probe(priv)) {
1044 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1045 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1047 /* RX INITIALIZATION */
1048 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1050 for (i = 0; i < rxsize; i++) {
1052 if (priv->extend_desc)
1053 p = &((priv->dma_erx + i)->basic);
1055 p = priv->dma_rx + i;
1057 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1059 goto err_init_rx_buffers;
1061 if (netif_msg_probe(priv))
1062 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1063 priv->rx_skbuff[i]->data,
1064 (unsigned int)priv->rx_skbuff_dma[i]);
1067 priv->dirty_rx = (unsigned int)(i - rxsize);
1070 /* Setup the chained descriptor addresses */
1071 if (priv->mode == STMMAC_CHAIN_MODE) {
1072 if (priv->extend_desc) {
1073 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1075 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1078 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1080 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1085 /* TX INITIALIZATION */
1086 for (i = 0; i < txsize; i++) {
1088 if (priv->extend_desc)
1089 p = &((priv->dma_etx + i)->basic);
1091 p = priv->dma_tx + i;
1093 priv->tx_skbuff_dma[i].buf = 0;
1094 priv->tx_skbuff_dma[i].map_as_page = false;
1095 priv->tx_skbuff[i] = NULL;
1100 netdev_reset_queue(priv->dev);
1102 stmmac_clear_descriptors(priv);
1104 if (netif_msg_hw(priv))
1105 stmmac_display_rings(priv);
1108 err_init_rx_buffers:
1110 stmmac_free_rx_buffers(priv, i);
1114 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1118 for (i = 0; i < priv->dma_rx_size; i++)
1119 stmmac_free_rx_buffers(priv, i);
1122 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1126 for (i = 0; i < priv->dma_tx_size; i++) {
1129 if (priv->extend_desc)
1130 p = &((priv->dma_etx + i)->basic);
1132 p = priv->dma_tx + i;
1134 if (priv->tx_skbuff_dma[i].buf) {
1135 if (priv->tx_skbuff_dma[i].map_as_page)
1136 dma_unmap_page(priv->device,
1137 priv->tx_skbuff_dma[i].buf,
1138 priv->hw->desc->get_tx_len(p),
1141 dma_unmap_single(priv->device,
1142 priv->tx_skbuff_dma[i].buf,
1143 priv->hw->desc->get_tx_len(p),
1147 if (priv->tx_skbuff[i] != NULL) {
1148 dev_kfree_skb_any(priv->tx_skbuff[i]);
1149 priv->tx_skbuff[i] = NULL;
1150 priv->tx_skbuff_dma[i].buf = 0;
1151 priv->tx_skbuff_dma[i].map_as_page = false;
1157 * alloc_dma_desc_resources - alloc TX/RX resources.
1158 * @priv: private structure
1159 * Description: according to which descriptor can be used (extend or basic)
1160 * this function allocates the resources for TX and RX paths. In case of
1161 * reception, for example, it pre-allocated the RX socket buffer in order to
1162 * allow zero-copy mechanism.
1164 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1166 unsigned int txsize = priv->dma_tx_size;
1167 unsigned int rxsize = priv->dma_rx_size;
1170 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1172 if (!priv->rx_skbuff_dma)
1175 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1177 if (!priv->rx_skbuff)
1180 priv->tx_skbuff_dma = kmalloc_array(txsize,
1181 sizeof(*priv->tx_skbuff_dma),
1183 if (!priv->tx_skbuff_dma)
1184 goto err_tx_skbuff_dma;
1186 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1188 if (!priv->tx_skbuff)
1191 if (priv->extend_desc) {
1192 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1200 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1205 if (!priv->dma_etx) {
1206 dma_free_coherent(priv->device, priv->dma_rx_size *
1207 sizeof(struct dma_extended_desc),
1208 priv->dma_erx, priv->dma_rx_phy);
1212 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1213 sizeof(struct dma_desc),
1219 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1220 sizeof(struct dma_desc),
1223 if (!priv->dma_tx) {
1224 dma_free_coherent(priv->device, priv->dma_rx_size *
1225 sizeof(struct dma_desc),
1226 priv->dma_rx, priv->dma_rx_phy);
1234 kfree(priv->tx_skbuff);
1236 kfree(priv->tx_skbuff_dma);
1238 kfree(priv->rx_skbuff);
1240 kfree(priv->rx_skbuff_dma);
1244 static void free_dma_desc_resources(struct stmmac_priv *priv)
1246 /* Release the DMA TX/RX socket buffers */
1247 dma_free_rx_skbufs(priv);
1248 dma_free_tx_skbufs(priv);
1250 /* Free DMA regions of consistent memory previously allocated */
1251 if (!priv->extend_desc) {
1252 dma_free_coherent(priv->device,
1253 priv->dma_tx_size * sizeof(struct dma_desc),
1254 priv->dma_tx, priv->dma_tx_phy);
1255 dma_free_coherent(priv->device,
1256 priv->dma_rx_size * sizeof(struct dma_desc),
1257 priv->dma_rx, priv->dma_rx_phy);
1259 dma_free_coherent(priv->device, priv->dma_tx_size *
1260 sizeof(struct dma_extended_desc),
1261 priv->dma_etx, priv->dma_tx_phy);
1262 dma_free_coherent(priv->device, priv->dma_rx_size *
1263 sizeof(struct dma_extended_desc),
1264 priv->dma_erx, priv->dma_rx_phy);
1266 kfree(priv->rx_skbuff_dma);
1267 kfree(priv->rx_skbuff);
1268 kfree(priv->tx_skbuff_dma);
1269 kfree(priv->tx_skbuff);
1273 * stmmac_dma_operation_mode - HW DMA operation mode
1274 * @priv: driver private structure
1275 * Description: it is used for configuring the DMA operation mode register in
1276 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1278 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1280 if (priv->plat->force_thresh_dma_mode)
1281 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1282 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1284 * In case of GMAC, SF mode can be enabled
1285 * to perform the TX COE in HW. This depends on:
1286 * 1) TX COE if actually supported
1287 * 2) There is no bugged Jumbo frame support
1288 * that needs to not insert csum in the TDES.
1290 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1291 priv->xstats.threshold = SF_DMA_MODE;
1293 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1297 * stmmac_tx_clean - to manage the transmission completion
1298 * @priv: driver private structure
1299 * Description: it reclaims the transmit resources after transmission completes.
1301 static void stmmac_tx_clean(struct stmmac_priv *priv)
1303 unsigned int txsize = priv->dma_tx_size;
1304 unsigned int bytes_compl = 0, pkts_compl = 0;
1306 spin_lock(&priv->tx_lock);
1308 priv->xstats.tx_clean++;
1310 while (priv->dirty_tx != priv->cur_tx) {
1312 unsigned int entry = priv->dirty_tx % txsize;
1313 struct sk_buff *skb = priv->tx_skbuff[entry];
1316 if (priv->extend_desc)
1317 p = (struct dma_desc *)(priv->dma_etx + entry);
1319 p = priv->dma_tx + entry;
1321 /* Check if the descriptor is owned by the DMA. */
1322 if (priv->hw->desc->get_tx_owner(p))
1325 /* Verify tx error by looking at the last segment. */
1326 last = priv->hw->desc->get_tx_ls(p);
1329 priv->hw->desc->tx_status(&priv->dev->stats,
1332 if (likely(tx_error == 0)) {
1333 priv->dev->stats.tx_packets++;
1334 priv->xstats.tx_pkt_n++;
1336 priv->dev->stats.tx_errors++;
1338 stmmac_get_tx_hwtstamp(priv, entry, skb);
1340 if (netif_msg_tx_done(priv))
1341 pr_debug("%s: curr %d, dirty %d\n", __func__,
1342 priv->cur_tx, priv->dirty_tx);
1344 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1345 if (priv->tx_skbuff_dma[entry].map_as_page)
1346 dma_unmap_page(priv->device,
1347 priv->tx_skbuff_dma[entry].buf,
1348 priv->hw->desc->get_tx_len(p),
1351 dma_unmap_single(priv->device,
1352 priv->tx_skbuff_dma[entry].buf,
1353 priv->hw->desc->get_tx_len(p),
1355 priv->tx_skbuff_dma[entry].buf = 0;
1356 priv->tx_skbuff_dma[entry].map_as_page = false;
1358 priv->hw->mode->clean_desc3(priv, p);
1360 if (likely(skb != NULL)) {
1362 bytes_compl += skb->len;
1363 dev_consume_skb_any(skb);
1364 priv->tx_skbuff[entry] = NULL;
1367 priv->hw->desc->release_tx_desc(p, priv->mode);
1372 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1374 if (unlikely(netif_queue_stopped(priv->dev) &&
1375 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1376 netif_tx_lock(priv->dev);
1377 if (netif_queue_stopped(priv->dev) &&
1378 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1379 if (netif_msg_tx_done(priv))
1380 pr_debug("%s: restart transmit\n", __func__);
1381 netif_wake_queue(priv->dev);
1383 netif_tx_unlock(priv->dev);
1386 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1387 stmmac_enable_eee_mode(priv);
1388 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1390 spin_unlock(&priv->tx_lock);
1393 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1395 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1398 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1400 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1404 * stmmac_tx_err - to manage the tx error
1405 * @priv: driver private structure
1406 * Description: it cleans the descriptors and restarts the transmission
1407 * in case of transmission errors.
1409 static void stmmac_tx_err(struct stmmac_priv *priv)
1412 int txsize = priv->dma_tx_size;
1413 netif_stop_queue(priv->dev);
1415 priv->hw->dma->stop_tx(priv->ioaddr);
1416 dma_free_tx_skbufs(priv);
1417 for (i = 0; i < txsize; i++)
1418 if (priv->extend_desc)
1419 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1423 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1428 netdev_reset_queue(priv->dev);
1429 priv->hw->dma->start_tx(priv->ioaddr);
1431 priv->dev->stats.tx_errors++;
1432 netif_wake_queue(priv->dev);
1436 * stmmac_dma_interrupt - DMA ISR
1437 * @priv: driver private structure
1438 * Description: this is the DMA ISR. It is called by the main ISR.
1439 * It calls the dwmac dma routine and schedule poll method in case of some
1442 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1446 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1447 if (likely((status & handle_rx)) || (status & handle_tx)) {
1448 if (likely(napi_schedule_prep(&priv->napi))) {
1449 stmmac_disable_dma_irq(priv);
1450 __napi_schedule(&priv->napi);
1453 if (unlikely(status & tx_hard_error_bump_tc)) {
1454 /* Try to bump up the dma threshold on this failure */
1455 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1458 if (priv->plat->force_thresh_dma_mode)
1459 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1461 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1463 priv->xstats.threshold = tc;
1465 } else if (unlikely(status == tx_hard_error))
1466 stmmac_tx_err(priv);
1470 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1471 * @priv: driver private structure
1472 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1474 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1476 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1477 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1479 dwmac_mmc_intr_all_mask(priv->ioaddr);
1481 if (priv->dma_cap.rmon) {
1482 dwmac_mmc_ctrl(priv->ioaddr, mode);
1483 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1485 pr_info(" No MAC Management Counters available\n");
1489 * stmmac_get_synopsys_id - return the SYINID.
1490 * @priv: driver private structure
1491 * Description: this simple function is to decode and return the SYINID
1492 * starting from the HW core register.
1494 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1496 u32 hwid = priv->hw->synopsys_uid;
1498 /* Check Synopsys Id (not available on old chips) */
1500 u32 uid = ((hwid & 0x0000ff00) >> 8);
1501 u32 synid = (hwid & 0x000000ff);
1503 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1512 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1513 * @priv: driver private structure
1514 * Description: select the Enhanced/Alternate or Normal descriptors.
1515 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1516 * supported by the HW capability register.
1518 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1520 if (priv->plat->enh_desc) {
1521 pr_info(" Enhanced/Alternate descriptors\n");
1523 /* GMAC older than 3.50 has no extended descriptors */
1524 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1525 pr_info("\tEnabled extended descriptors\n");
1526 priv->extend_desc = 1;
1528 pr_warn("Extended descriptors not supported\n");
1530 priv->hw->desc = &enh_desc_ops;
1532 pr_info(" Normal descriptors\n");
1533 priv->hw->desc = &ndesc_ops;
1538 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1539 * @priv: driver private structure
1541 * new GMAC chip generations have a new register to indicate the
1542 * presence of the optional feature/functions.
1543 * This can be also used to override the value passed through the
1544 * platform and necessary for old MAC10/100 and GMAC chips.
1546 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1550 if (priv->hw->dma->get_hw_feature) {
1551 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1553 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1554 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1555 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1556 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1557 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1558 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1559 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1560 priv->dma_cap.pmt_remote_wake_up =
1561 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1562 priv->dma_cap.pmt_magic_frame =
1563 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1565 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1566 /* IEEE 1588-2002 */
1567 priv->dma_cap.time_stamp =
1568 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1569 /* IEEE 1588-2008 */
1570 priv->dma_cap.atime_stamp =
1571 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1572 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1573 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1574 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1575 /* TX and RX csum */
1576 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1577 priv->dma_cap.rx_coe_type1 =
1578 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1579 priv->dma_cap.rx_coe_type2 =
1580 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1581 priv->dma_cap.rxfifo_over_2048 =
1582 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1583 /* TX and RX number of channels */
1584 priv->dma_cap.number_rx_channel =
1585 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1586 priv->dma_cap.number_tx_channel =
1587 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1588 /* Alternate (enhanced) DESC mode */
1589 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1596 * stmmac_check_ether_addr - check if the MAC addr is valid
1597 * @priv: driver private structure
1599 * it is to verify if the MAC address is valid, in case of failures it
1600 * generates a random MAC address
1602 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1604 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1605 priv->hw->mac->get_umac_addr(priv->hw,
1606 priv->dev->dev_addr, 0);
1607 if (!is_valid_ether_addr(priv->dev->dev_addr))
1608 eth_hw_addr_random(priv->dev);
1609 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1610 priv->dev->dev_addr);
1615 * stmmac_init_dma_engine - DMA init.
1616 * @priv: driver private structure
1618 * It inits the DMA invoking the specific MAC/GMAC callback.
1619 * Some DMA parameters can be passed from the platform;
1620 * in case of these are not passed a default is kept for the MAC or GMAC.
1622 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1624 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1625 int mixed_burst = 0;
1628 if (priv->plat->dma_cfg) {
1629 pbl = priv->plat->dma_cfg->pbl;
1630 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1631 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1632 burst_len = priv->plat->dma_cfg->burst_len;
1635 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1638 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1639 burst_len, priv->dma_tx_phy,
1640 priv->dma_rx_phy, atds);
1644 * stmmac_tx_timer - mitigation sw timer for tx.
1645 * @data: data pointer
1647 * This is the timer handler to directly invoke the stmmac_tx_clean.
1649 static void stmmac_tx_timer(unsigned long data)
1651 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1653 stmmac_tx_clean(priv);
1657 * stmmac_init_tx_coalesce - init tx mitigation options.
1658 * @priv: driver private structure
1660 * This inits the transmit coalesce parameters: i.e. timer rate,
1661 * timer handler and default threshold used for enabling the
1662 * interrupt on completion bit.
1664 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1666 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1667 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1668 init_timer(&priv->txtimer);
1669 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1670 priv->txtimer.data = (unsigned long)priv;
1671 priv->txtimer.function = stmmac_tx_timer;
1672 add_timer(&priv->txtimer);
1676 * stmmac_hw_setup - setup mac in a usable state.
1677 * @dev : pointer to the device structure.
1679 * this is the main function to setup the HW in a usable state because the
1680 * dma engine is reset, the core registers are configured (e.g. AXI,
1681 * Checksum features, timers). The DMA is ready to start receiving and
1684 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1687 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1689 struct stmmac_priv *priv = netdev_priv(dev);
1692 /* DMA initialization and SW reset */
1693 ret = stmmac_init_dma_engine(priv);
1695 pr_err("%s: DMA engine initialization failed\n", __func__);
1699 /* Copy the MAC addr into the HW */
1700 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1702 /* If required, perform hw setup of the bus. */
1703 if (priv->plat->bus_setup)
1704 priv->plat->bus_setup(priv->ioaddr);
1706 /* Initialize the MAC Core */
1707 priv->hw->mac->core_init(priv->hw, dev->mtu);
1709 ret = priv->hw->mac->rx_ipc(priv->hw);
1711 pr_warn(" RX IPC Checksum Offload disabled\n");
1712 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1713 priv->hw->rx_csum = 0;
1716 /* Enable the MAC Rx/Tx */
1717 stmmac_set_mac(priv->ioaddr, true);
1719 /* Set the HW DMA mode and the COE */
1720 stmmac_dma_operation_mode(priv);
1722 stmmac_mmc_setup(priv);
1725 ret = stmmac_init_ptp(priv);
1726 if (ret && ret != -EOPNOTSUPP)
1727 pr_warn("%s: failed PTP initialisation\n", __func__);
1730 #ifdef CONFIG_DEBUG_FS
1731 ret = stmmac_init_fs(dev);
1733 pr_warn("%s: failed debugFS registration\n", __func__);
1735 /* Start the ball rolling... */
1736 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1737 priv->hw->dma->start_tx(priv->ioaddr);
1738 priv->hw->dma->start_rx(priv->ioaddr);
1740 /* Dump DMA/MAC registers */
1741 if (netif_msg_hw(priv)) {
1742 priv->hw->mac->dump_regs(priv->hw);
1743 priv->hw->dma->dump_regs(priv->ioaddr);
1745 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1747 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1748 priv->rx_riwt = MAX_DMA_RIWT;
1749 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1752 if (priv->pcs && priv->hw->mac->ctrl_ane)
1753 priv->hw->mac->ctrl_ane(priv->hw, 0);
1759 * stmmac_open - open entry point of the driver
1760 * @dev : pointer to the device structure.
1762 * This function is the open entry point of the driver.
1764 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1767 static int stmmac_open(struct net_device *dev)
1769 struct stmmac_priv *priv = netdev_priv(dev);
1772 stmmac_check_ether_addr(priv);
1774 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1775 priv->pcs != STMMAC_PCS_RTBI) {
1776 ret = stmmac_init_phy(dev);
1778 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1784 /* Extra statistics */
1785 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1786 priv->xstats.threshold = tc;
1788 /* Create and initialize the TX/RX descriptors chains. */
1789 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1790 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1791 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1793 ret = alloc_dma_desc_resources(priv);
1795 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1796 goto dma_desc_error;
1799 ret = init_dma_desc_rings(dev, GFP_KERNEL);
1801 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1805 ret = stmmac_hw_setup(dev, true);
1807 pr_err("%s: Hw setup failed\n", __func__);
1811 stmmac_init_tx_coalesce(priv);
1814 phy_start(priv->phydev);
1816 /* Request the IRQ lines */
1817 ret = request_irq(dev->irq, stmmac_interrupt,
1818 IRQF_SHARED, dev->name, dev);
1819 if (unlikely(ret < 0)) {
1820 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1821 __func__, dev->irq, ret);
1825 /* Request the Wake IRQ in case of another line is used for WoL */
1826 if (priv->wol_irq != dev->irq) {
1827 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1828 IRQF_SHARED, dev->name, dev);
1829 if (unlikely(ret < 0)) {
1830 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1831 __func__, priv->wol_irq, ret);
1836 /* Request the IRQ lines */
1837 if (priv->lpi_irq > 0) {
1838 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1840 if (unlikely(ret < 0)) {
1841 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1842 __func__, priv->lpi_irq, ret);
1847 napi_enable(&priv->napi);
1848 netif_start_queue(dev);
1853 if (priv->wol_irq != dev->irq)
1854 free_irq(priv->wol_irq, dev);
1856 free_irq(dev->irq, dev);
1859 free_dma_desc_resources(priv);
1862 phy_disconnect(priv->phydev);
1868 * stmmac_release - close entry point of the driver
1869 * @dev : device pointer.
1871 * This is the stop entry point of the driver.
1873 static int stmmac_release(struct net_device *dev)
1875 struct stmmac_priv *priv = netdev_priv(dev);
1877 if (priv->eee_enabled)
1878 del_timer_sync(&priv->eee_ctrl_timer);
1880 /* Stop and disconnect the PHY */
1882 phy_stop(priv->phydev);
1883 phy_disconnect(priv->phydev);
1884 priv->phydev = NULL;
1887 netif_stop_queue(dev);
1889 napi_disable(&priv->napi);
1891 del_timer_sync(&priv->txtimer);
1893 /* Free the IRQ lines */
1894 free_irq(dev->irq, dev);
1895 if (priv->wol_irq != dev->irq)
1896 free_irq(priv->wol_irq, dev);
1897 if (priv->lpi_irq > 0)
1898 free_irq(priv->lpi_irq, dev);
1900 /* Stop TX/RX DMA and clear the descriptors */
1901 priv->hw->dma->stop_tx(priv->ioaddr);
1902 priv->hw->dma->stop_rx(priv->ioaddr);
1904 /* Release and free the Rx/Tx resources */
1905 free_dma_desc_resources(priv);
1907 /* Disable the MAC Rx/Tx */
1908 stmmac_set_mac(priv->ioaddr, false);
1910 netif_carrier_off(dev);
1912 #ifdef CONFIG_DEBUG_FS
1916 stmmac_release_ptp(priv);
1922 * stmmac_xmit - Tx entry point of the driver
1923 * @skb : the socket buffer
1924 * @dev : device pointer
1925 * Description : this is the tx entry point of the driver.
1926 * It programs the chain or the ring and supports oversized frames
1929 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1931 struct stmmac_priv *priv = netdev_priv(dev);
1932 unsigned int txsize = priv->dma_tx_size;
1934 int i, csum_insertion = 0, is_jumbo = 0;
1935 int nfrags = skb_shinfo(skb)->nr_frags;
1936 struct dma_desc *desc, *first;
1937 unsigned int nopaged_len = skb_headlen(skb);
1938 unsigned int enh_desc = priv->plat->enh_desc;
1940 spin_lock(&priv->tx_lock);
1942 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1943 spin_unlock(&priv->tx_lock);
1944 if (!netif_queue_stopped(dev)) {
1945 netif_stop_queue(dev);
1946 /* This is a hard error, log it. */
1947 pr_err("%s: Tx Ring full when queue awake\n", __func__);
1949 return NETDEV_TX_BUSY;
1952 if (priv->tx_path_in_lpi_mode)
1953 stmmac_disable_eee_mode(priv);
1955 entry = priv->cur_tx % txsize;
1957 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1959 if (priv->extend_desc)
1960 desc = (struct dma_desc *)(priv->dma_etx + entry);
1962 desc = priv->dma_tx + entry;
1966 /* To program the descriptors according to the size of the frame */
1968 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1970 if (likely(!is_jumbo)) {
1971 desc->des2 = dma_map_single(priv->device, skb->data,
1972 nopaged_len, DMA_TO_DEVICE);
1973 if (dma_mapping_error(priv->device, desc->des2))
1975 priv->tx_skbuff_dma[entry].buf = desc->des2;
1976 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1977 csum_insertion, priv->mode);
1980 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1981 if (unlikely(entry < 0))
1985 for (i = 0; i < nfrags; i++) {
1986 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1987 int len = skb_frag_size(frag);
1989 priv->tx_skbuff[entry] = NULL;
1990 entry = (++priv->cur_tx) % txsize;
1991 if (priv->extend_desc)
1992 desc = (struct dma_desc *)(priv->dma_etx + entry);
1994 desc = priv->dma_tx + entry;
1996 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1998 if (dma_mapping_error(priv->device, desc->des2))
1999 goto dma_map_err; /* should reuse desc w/o issues */
2001 priv->tx_skbuff_dma[entry].buf = desc->des2;
2002 priv->tx_skbuff_dma[entry].map_as_page = true;
2003 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2006 priv->hw->desc->set_tx_owner(desc);
2010 priv->tx_skbuff[entry] = skb;
2012 /* Finalize the latest segment. */
2013 priv->hw->desc->close_tx_desc(desc);
2016 /* According to the coalesce parameter the IC bit for the latest
2017 * segment could be reset and the timer re-started to invoke the
2018 * stmmac_tx function. This approach takes care about the fragments.
2020 priv->tx_count_frames += nfrags + 1;
2021 if (priv->tx_coal_frames > priv->tx_count_frames) {
2022 priv->hw->desc->clear_tx_ic(desc);
2023 priv->xstats.tx_reset_ic_bit++;
2024 mod_timer(&priv->txtimer,
2025 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2027 priv->tx_count_frames = 0;
2029 /* To avoid raise condition */
2030 priv->hw->desc->set_tx_owner(first);
2035 if (netif_msg_pktdata(priv)) {
2036 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2037 __func__, (priv->cur_tx % txsize),
2038 (priv->dirty_tx % txsize), entry, first, nfrags);
2040 if (priv->extend_desc)
2041 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2043 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2045 pr_debug(">>> frame to be transmitted: ");
2046 print_pkt(skb->data, skb->len);
2048 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2049 if (netif_msg_hw(priv))
2050 pr_debug("%s: stop transmitted packets\n", __func__);
2051 netif_stop_queue(dev);
2054 dev->stats.tx_bytes += skb->len;
2056 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2057 priv->hwts_tx_en)) {
2058 /* declare that device is doing timestamping */
2059 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2060 priv->hw->desc->enable_tx_timestamp(first);
2063 if (!priv->hwts_tx_en)
2064 skb_tx_timestamp(skb);
2066 netdev_sent_queue(dev, skb->len);
2067 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2069 spin_unlock(&priv->tx_lock);
2070 return NETDEV_TX_OK;
2073 spin_unlock(&priv->tx_lock);
2074 dev_err(priv->device, "Tx dma map failed\n");
2076 priv->dev->stats.tx_dropped++;
2077 return NETDEV_TX_OK;
2080 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2082 struct ethhdr *ehdr;
2085 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2086 NETIF_F_HW_VLAN_CTAG_RX &&
2087 !__vlan_get_tag(skb, &vlanid)) {
2088 /* pop the vlan tag */
2089 ehdr = (struct ethhdr *)skb->data;
2090 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2091 skb_pull(skb, VLAN_HLEN);
2092 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2098 * stmmac_rx_refill - refill used skb preallocated buffers
2099 * @priv: driver private structure
2100 * Description : this is to reallocate the skb for the reception process
2101 * that is based on zero-copy.
2103 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2105 unsigned int rxsize = priv->dma_rx_size;
2106 int bfsize = priv->dma_buf_sz;
2108 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2109 unsigned int entry = priv->dirty_rx % rxsize;
2112 if (priv->extend_desc)
2113 p = (struct dma_desc *)(priv->dma_erx + entry);
2115 p = priv->dma_rx + entry;
2117 if (likely(priv->rx_skbuff[entry] == NULL)) {
2118 struct sk_buff *skb;
2120 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2122 if (unlikely(skb == NULL))
2125 priv->rx_skbuff[entry] = skb;
2126 priv->rx_skbuff_dma[entry] =
2127 dma_map_single(priv->device, skb->data, bfsize,
2129 if (dma_mapping_error(priv->device,
2130 priv->rx_skbuff_dma[entry])) {
2131 dev_err(priv->device, "Rx dma map failed\n");
2135 p->des2 = priv->rx_skbuff_dma[entry];
2137 priv->hw->mode->refill_desc3(priv, p);
2139 if (netif_msg_rx_status(priv))
2140 pr_debug("\trefill entry #%d\n", entry);
2143 priv->hw->desc->set_rx_owner(p);
2149 * stmmac_rx - manage the receive process
2150 * @priv: driver private structure
2151 * @limit: napi bugget.
2152 * Description : this the function called by the napi poll method.
2153 * It gets all the frames inside the ring.
2155 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2157 unsigned int rxsize = priv->dma_rx_size;
2158 unsigned int entry = priv->cur_rx % rxsize;
2159 unsigned int next_entry;
2160 unsigned int count = 0;
2161 int coe = priv->hw->rx_csum;
2163 if (netif_msg_rx_status(priv)) {
2164 pr_debug("%s: descriptor ring:\n", __func__);
2165 if (priv->extend_desc)
2166 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2168 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2170 while (count < limit) {
2174 if (priv->extend_desc)
2175 p = (struct dma_desc *)(priv->dma_erx + entry);
2177 p = priv->dma_rx + entry;
2179 if (priv->hw->desc->get_rx_owner(p))
2184 next_entry = (++priv->cur_rx) % rxsize;
2185 if (priv->extend_desc)
2186 prefetch(priv->dma_erx + next_entry);
2188 prefetch(priv->dma_rx + next_entry);
2190 /* read the status of the incoming frame */
2191 status = priv->hw->desc->rx_status(&priv->dev->stats,
2193 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2194 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2198 if (unlikely(status == discard_frame)) {
2199 priv->dev->stats.rx_errors++;
2200 if (priv->hwts_rx_en && !priv->extend_desc) {
2201 /* DESC2 & DESC3 will be overwitten by device
2202 * with timestamp value, hence reinitialize
2203 * them in stmmac_rx_refill() function so that
2204 * device can reuse it.
2206 priv->rx_skbuff[entry] = NULL;
2207 dma_unmap_single(priv->device,
2208 priv->rx_skbuff_dma[entry],
2213 struct sk_buff *skb;
2216 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2218 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2219 * Type frames (LLC/LLC-SNAP)
2221 if (unlikely(status != llc_snap))
2222 frame_len -= ETH_FCS_LEN;
2224 if (netif_msg_rx_status(priv)) {
2225 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2227 if (frame_len > ETH_FRAME_LEN)
2228 pr_debug("\tframe size %d, COE: %d\n",
2231 skb = priv->rx_skbuff[entry];
2232 if (unlikely(!skb)) {
2233 pr_err("%s: Inconsistent Rx descriptor chain\n",
2235 priv->dev->stats.rx_dropped++;
2238 prefetch(skb->data - NET_IP_ALIGN);
2239 priv->rx_skbuff[entry] = NULL;
2241 stmmac_get_rx_hwtstamp(priv, entry, skb);
2243 skb_put(skb, frame_len);
2244 dma_unmap_single(priv->device,
2245 priv->rx_skbuff_dma[entry],
2246 priv->dma_buf_sz, DMA_FROM_DEVICE);
2248 if (netif_msg_pktdata(priv)) {
2249 pr_debug("frame received (%dbytes)", frame_len);
2250 print_pkt(skb->data, frame_len);
2253 stmmac_rx_vlan(priv->dev, skb);
2255 skb->protocol = eth_type_trans(skb, priv->dev);
2258 skb_checksum_none_assert(skb);
2260 skb->ip_summed = CHECKSUM_UNNECESSARY;
2262 napi_gro_receive(&priv->napi, skb);
2264 priv->dev->stats.rx_packets++;
2265 priv->dev->stats.rx_bytes += frame_len;
2270 stmmac_rx_refill(priv);
2272 priv->xstats.rx_pkt_n += count;
2278 * stmmac_poll - stmmac poll method (NAPI)
2279 * @napi : pointer to the napi structure.
2280 * @budget : maximum number of packets that the current CPU can receive from
2283 * To look at the incoming frames and clear the tx resources.
2285 static int stmmac_poll(struct napi_struct *napi, int budget)
2287 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2290 priv->xstats.napi_poll++;
2291 stmmac_tx_clean(priv);
2293 work_done = stmmac_rx(priv, budget);
2294 if (work_done < budget) {
2295 napi_complete(napi);
2296 stmmac_enable_dma_irq(priv);
2303 * @dev : Pointer to net device structure
2304 * Description: this function is called when a packet transmission fails to
2305 * complete within a reasonable time. The driver will mark the error in the
2306 * netdev structure and arrange for the device to be reset to a sane state
2307 * in order to transmit a new packet.
2309 static void stmmac_tx_timeout(struct net_device *dev)
2311 struct stmmac_priv *priv = netdev_priv(dev);
2313 /* Clear Tx resources and restart transmitting again */
2314 stmmac_tx_err(priv);
2318 * stmmac_set_rx_mode - entry point for multicast addressing
2319 * @dev : pointer to the device structure
2321 * This function is a driver entry point which gets called by the kernel
2322 * whenever multicast addresses must be enabled/disabled.
2326 static void stmmac_set_rx_mode(struct net_device *dev)
2328 struct stmmac_priv *priv = netdev_priv(dev);
2330 priv->hw->mac->set_filter(priv->hw, dev);
2334 * stmmac_change_mtu - entry point to change MTU size for the device.
2335 * @dev : device pointer.
2336 * @new_mtu : the new MTU size for the device.
2337 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2338 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2339 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2341 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2344 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2346 struct stmmac_priv *priv = netdev_priv(dev);
2349 if (netif_running(dev)) {
2350 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2354 if (priv->plat->enh_desc)
2355 max_mtu = JUMBO_LEN;
2357 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2359 if (priv->plat->maxmtu < max_mtu)
2360 max_mtu = priv->plat->maxmtu;
2362 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2363 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2368 netdev_update_features(dev);
2373 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2374 netdev_features_t features)
2376 struct stmmac_priv *priv = netdev_priv(dev);
2378 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2379 features &= ~NETIF_F_RXCSUM;
2381 if (!priv->plat->tx_coe)
2382 features &= ~NETIF_F_ALL_CSUM;
2384 /* Some GMAC devices have a bugged Jumbo frame support that
2385 * needs to have the Tx COE disabled for oversized frames
2386 * (due to limited buffer sizes). In this case we disable
2387 * the TX csum insertionin the TDES and not use SF.
2389 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2390 features &= ~NETIF_F_ALL_CSUM;
2395 static int stmmac_set_features(struct net_device *netdev,
2396 netdev_features_t features)
2398 struct stmmac_priv *priv = netdev_priv(netdev);
2400 /* Keep the COE Type in case of csum is supporting */
2401 if (features & NETIF_F_RXCSUM)
2402 priv->hw->rx_csum = priv->plat->rx_coe;
2404 priv->hw->rx_csum = 0;
2405 /* No check needed because rx_coe has been set before and it will be
2406 * fixed in case of issue.
2408 priv->hw->mac->rx_ipc(priv->hw);
2414 * stmmac_interrupt - main ISR
2415 * @irq: interrupt number.
2416 * @dev_id: to pass the net device pointer.
2417 * Description: this is the main driver interrupt service routine.
2419 * o DMA service routine (to manage incoming frame reception and transmission
2421 * o Core interrupts to manage: remote wake-up, management counter, LPI
2424 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2426 struct net_device *dev = (struct net_device *)dev_id;
2427 struct stmmac_priv *priv = netdev_priv(dev);
2430 pm_wakeup_event(priv->device, 0);
2432 if (unlikely(!dev)) {
2433 pr_err("%s: invalid dev pointer\n", __func__);
2437 /* To handle GMAC own interrupts */
2438 if (priv->plat->has_gmac) {
2439 int status = priv->hw->mac->host_irq_status(priv->hw,
2441 if (unlikely(status)) {
2442 /* For LPI we need to save the tx status */
2443 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2444 priv->tx_path_in_lpi_mode = true;
2445 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2446 priv->tx_path_in_lpi_mode = false;
2450 /* To handle DMA interrupts */
2451 stmmac_dma_interrupt(priv);
2456 #ifdef CONFIG_NET_POLL_CONTROLLER
2457 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2458 * to allow network I/O with interrupts disabled.
2460 static void stmmac_poll_controller(struct net_device *dev)
2462 disable_irq(dev->irq);
2463 stmmac_interrupt(dev->irq, dev);
2464 enable_irq(dev->irq);
2469 * stmmac_ioctl - Entry point for the Ioctl
2470 * @dev: Device pointer.
2471 * @rq: An IOCTL specefic structure, that can contain a pointer to
2472 * a proprietary structure used to pass information to the driver.
2473 * @cmd: IOCTL command
2475 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2477 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2479 struct stmmac_priv *priv = netdev_priv(dev);
2480 int ret = -EOPNOTSUPP;
2482 if (!netif_running(dev))
2491 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2494 ret = stmmac_hwtstamp_ioctl(dev, rq);
2503 #ifdef CONFIG_DEBUG_FS
2504 static struct dentry *stmmac_fs_dir;
2505 static struct dentry *stmmac_rings_status;
2506 static struct dentry *stmmac_dma_cap;
2508 static void sysfs_display_ring(void *head, int size, int extend_desc,
2509 struct seq_file *seq)
2512 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2513 struct dma_desc *p = (struct dma_desc *)head;
2515 for (i = 0; i < size; i++) {
2519 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2520 i, (unsigned int)virt_to_phys(ep),
2521 (unsigned int)x, (unsigned int)(x >> 32),
2522 ep->basic.des2, ep->basic.des3);
2526 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2527 i, (unsigned int)virt_to_phys(ep),
2528 (unsigned int)x, (unsigned int)(x >> 32),
2532 seq_printf(seq, "\n");
2536 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2538 struct net_device *dev = seq->private;
2539 struct stmmac_priv *priv = netdev_priv(dev);
2540 unsigned int txsize = priv->dma_tx_size;
2541 unsigned int rxsize = priv->dma_rx_size;
2543 if (priv->extend_desc) {
2544 seq_printf(seq, "Extended RX descriptor ring:\n");
2545 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2546 seq_printf(seq, "Extended TX descriptor ring:\n");
2547 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2549 seq_printf(seq, "RX descriptor ring:\n");
2550 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2551 seq_printf(seq, "TX descriptor ring:\n");
2552 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2558 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2560 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2563 static const struct file_operations stmmac_rings_status_fops = {
2564 .owner = THIS_MODULE,
2565 .open = stmmac_sysfs_ring_open,
2567 .llseek = seq_lseek,
2568 .release = single_release,
2571 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2573 struct net_device *dev = seq->private;
2574 struct stmmac_priv *priv = netdev_priv(dev);
2576 if (!priv->hw_cap_support) {
2577 seq_printf(seq, "DMA HW features not supported\n");
2581 seq_printf(seq, "==============================\n");
2582 seq_printf(seq, "\tDMA HW features\n");
2583 seq_printf(seq, "==============================\n");
2585 seq_printf(seq, "\t10/100 Mbps %s\n",
2586 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2587 seq_printf(seq, "\t1000 Mbps %s\n",
2588 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2589 seq_printf(seq, "\tHalf duple %s\n",
2590 (priv->dma_cap.half_duplex) ? "Y" : "N");
2591 seq_printf(seq, "\tHash Filter: %s\n",
2592 (priv->dma_cap.hash_filter) ? "Y" : "N");
2593 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2594 (priv->dma_cap.multi_addr) ? "Y" : "N");
2595 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2596 (priv->dma_cap.pcs) ? "Y" : "N");
2597 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2598 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2599 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2600 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2601 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2602 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2603 seq_printf(seq, "\tRMON module: %s\n",
2604 (priv->dma_cap.rmon) ? "Y" : "N");
2605 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2606 (priv->dma_cap.time_stamp) ? "Y" : "N");
2607 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2608 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2609 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2610 (priv->dma_cap.eee) ? "Y" : "N");
2611 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2612 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2613 (priv->dma_cap.tx_coe) ? "Y" : "N");
2614 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2615 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2616 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2617 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2618 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2619 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2620 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2621 priv->dma_cap.number_rx_channel);
2622 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2623 priv->dma_cap.number_tx_channel);
2624 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2625 (priv->dma_cap.enh_desc) ? "Y" : "N");
2630 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2632 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2635 static const struct file_operations stmmac_dma_cap_fops = {
2636 .owner = THIS_MODULE,
2637 .open = stmmac_sysfs_dma_cap_open,
2639 .llseek = seq_lseek,
2640 .release = single_release,
2643 static int stmmac_init_fs(struct net_device *dev)
2645 /* Create debugfs entries */
2646 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2648 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2649 pr_err("ERROR %s, debugfs create directory failed\n",
2650 STMMAC_RESOURCE_NAME);
2655 /* Entry to report DMA RX/TX rings */
2656 stmmac_rings_status = debugfs_create_file("descriptors_status",
2657 S_IRUGO, stmmac_fs_dir, dev,
2658 &stmmac_rings_status_fops);
2660 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2661 pr_info("ERROR creating stmmac ring debugfs file\n");
2662 debugfs_remove(stmmac_fs_dir);
2667 /* Entry to report the DMA HW features */
2668 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2669 dev, &stmmac_dma_cap_fops);
2671 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2672 pr_info("ERROR creating stmmac MMC debugfs file\n");
2673 debugfs_remove(stmmac_rings_status);
2674 debugfs_remove(stmmac_fs_dir);
2682 static void stmmac_exit_fs(void)
2684 debugfs_remove(stmmac_rings_status);
2685 debugfs_remove(stmmac_dma_cap);
2686 debugfs_remove(stmmac_fs_dir);
2688 #endif /* CONFIG_DEBUG_FS */
2690 static const struct net_device_ops stmmac_netdev_ops = {
2691 .ndo_open = stmmac_open,
2692 .ndo_start_xmit = stmmac_xmit,
2693 .ndo_stop = stmmac_release,
2694 .ndo_change_mtu = stmmac_change_mtu,
2695 .ndo_fix_features = stmmac_fix_features,
2696 .ndo_set_features = stmmac_set_features,
2697 .ndo_set_rx_mode = stmmac_set_rx_mode,
2698 .ndo_tx_timeout = stmmac_tx_timeout,
2699 .ndo_do_ioctl = stmmac_ioctl,
2700 #ifdef CONFIG_NET_POLL_CONTROLLER
2701 .ndo_poll_controller = stmmac_poll_controller,
2703 .ndo_set_mac_address = eth_mac_addr,
2707 * stmmac_hw_init - Init the MAC device
2708 * @priv: driver private structure
2709 * Description: this function is to configure the MAC device according to
2710 * some platform parameters or the HW capability register. It prepares the
2711 * driver to use either ring or chain modes and to setup either enhanced or
2712 * normal descriptors.
2714 static int stmmac_hw_init(struct stmmac_priv *priv)
2716 struct mac_device_info *mac;
2718 /* Identify the MAC HW device */
2719 if (priv->plat->has_gmac) {
2720 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2721 mac = dwmac1000_setup(priv->ioaddr,
2722 priv->plat->multicast_filter_bins,
2723 priv->plat->unicast_filter_entries);
2725 mac = dwmac100_setup(priv->ioaddr);
2732 /* Get and dump the chip ID */
2733 priv->synopsys_id = stmmac_get_synopsys_id(priv);
2735 /* To use the chained or ring mode */
2737 priv->hw->mode = &chain_mode_ops;
2738 pr_info(" Chain mode enabled\n");
2739 priv->mode = STMMAC_CHAIN_MODE;
2741 priv->hw->mode = &ring_mode_ops;
2742 pr_info(" Ring mode enabled\n");
2743 priv->mode = STMMAC_RING_MODE;
2746 /* Get the HW capability (new GMAC newer than 3.50a) */
2747 priv->hw_cap_support = stmmac_get_hw_features(priv);
2748 if (priv->hw_cap_support) {
2749 pr_info(" DMA HW capability register supported");
2751 /* We can override some gmac/dma configuration fields: e.g.
2752 * enh_desc, tx_coe (e.g. that are passed through the
2753 * platform) with the values from the HW capability
2754 * register (if supported).
2756 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2757 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2759 /* TXCOE doesn't work in thresh DMA mode */
2760 if (priv->plat->force_thresh_dma_mode)
2761 priv->plat->tx_coe = 0;
2763 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2765 if (priv->dma_cap.rx_coe_type2)
2766 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2767 else if (priv->dma_cap.rx_coe_type1)
2768 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2771 pr_info(" No HW DMA feature register supported");
2773 /* To use alternate (extended) or normal descriptor structures */
2774 stmmac_selec_desc_mode(priv);
2776 if (priv->plat->rx_coe) {
2777 priv->hw->rx_csum = priv->plat->rx_coe;
2778 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2779 priv->plat->rx_coe);
2781 if (priv->plat->tx_coe)
2782 pr_info(" TX Checksum insertion supported\n");
2784 if (priv->plat->pmt) {
2785 pr_info(" Wake-Up On Lan supported\n");
2786 device_set_wakeup_capable(priv->device, 1);
2794 * @device: device pointer
2795 * @plat_dat: platform data pointer
2796 * @addr: iobase memory address
2797 * Description: this is the main probe function used to
2798 * call the alloc_etherdev, allocate the priv structure.
2800 * on success the new private structure is returned, otherwise the error
2803 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2804 struct plat_stmmacenet_data *plat_dat,
2808 struct net_device *ndev = NULL;
2809 struct stmmac_priv *priv;
2811 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2813 return ERR_PTR(-ENOMEM);
2815 SET_NETDEV_DEV(ndev, device);
2817 priv = netdev_priv(ndev);
2818 priv->device = device;
2821 stmmac_set_ethtool_ops(ndev);
2822 priv->pause = pause;
2823 priv->plat = plat_dat;
2824 priv->ioaddr = addr;
2825 priv->dev->base_addr = (unsigned long)addr;
2827 /* Verify driver arguments */
2828 stmmac_verify_args();
2830 /* Override with kernel parameters if supplied XXX CRS XXX
2831 * this needs to have multiple instances
2833 if ((phyaddr >= 0) && (phyaddr <= 31))
2834 priv->plat->phy_addr = phyaddr;
2836 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2837 if (IS_ERR(priv->stmmac_clk)) {
2838 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2840 /* If failed to obtain stmmac_clk and specific clk_csr value
2841 * is NOT passed from the platform, probe fail.
2843 if (!priv->plat->clk_csr) {
2844 ret = PTR_ERR(priv->stmmac_clk);
2847 priv->stmmac_clk = NULL;
2850 clk_prepare_enable(priv->stmmac_clk);
2852 priv->stmmac_rst = devm_reset_control_get(priv->device,
2853 STMMAC_RESOURCE_NAME);
2854 if (IS_ERR(priv->stmmac_rst)) {
2855 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2856 ret = -EPROBE_DEFER;
2859 dev_info(priv->device, "no reset control found\n");
2860 priv->stmmac_rst = NULL;
2862 if (priv->stmmac_rst)
2863 reset_control_deassert(priv->stmmac_rst);
2865 /* Init MAC and get the capabilities */
2866 ret = stmmac_hw_init(priv);
2870 ndev->netdev_ops = &stmmac_netdev_ops;
2872 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2874 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2875 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2876 #ifdef STMMAC_VLAN_TAG_USED
2877 /* Both mac100 and gmac support receive VLAN tag detection */
2878 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2880 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2883 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2885 /* Rx Watchdog is available in the COREs newer than the 3.40.
2886 * In some case, for example on bugged HW this feature
2887 * has to be disable and this can be done by passing the
2888 * riwt_off field from the platform.
2890 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2892 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2895 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2897 spin_lock_init(&priv->lock);
2898 spin_lock_init(&priv->tx_lock);
2900 ret = register_netdev(ndev);
2902 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2903 goto error_netdev_register;
2906 /* If a specific clk_csr value is passed from the platform
2907 * this means that the CSR Clock Range selection cannot be
2908 * changed at run-time and it is fixed. Viceversa the driver'll try to
2909 * set the MDC clock dynamically according to the csr actual
2912 if (!priv->plat->clk_csr)
2913 stmmac_clk_csr_set(priv);
2915 priv->clk_csr = priv->plat->clk_csr;
2917 stmmac_check_pcs_mode(priv);
2919 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2920 priv->pcs != STMMAC_PCS_RTBI) {
2921 /* MDIO bus Registration */
2922 ret = stmmac_mdio_register(ndev);
2924 pr_debug("%s: MDIO bus (id: %d) registration failed",
2925 __func__, priv->plat->bus_id);
2926 goto error_mdio_register;
2932 error_mdio_register:
2933 unregister_netdev(ndev);
2934 error_netdev_register:
2935 netif_napi_del(&priv->napi);
2937 clk_disable_unprepare(priv->stmmac_clk);
2941 return ERR_PTR(ret);
2943 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2947 * @ndev: net device pointer
2948 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2949 * changes the link status, releases the DMA descriptor rings.
2951 int stmmac_dvr_remove(struct net_device *ndev)
2953 struct stmmac_priv *priv = netdev_priv(ndev);
2955 pr_info("%s:\n\tremoving driver", __func__);
2957 priv->hw->dma->stop_rx(priv->ioaddr);
2958 priv->hw->dma->stop_tx(priv->ioaddr);
2960 stmmac_set_mac(priv->ioaddr, false);
2961 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2962 priv->pcs != STMMAC_PCS_RTBI)
2963 stmmac_mdio_unregister(ndev);
2964 netif_carrier_off(ndev);
2965 unregister_netdev(ndev);
2966 if (priv->stmmac_rst)
2967 reset_control_assert(priv->stmmac_rst);
2968 clk_disable_unprepare(priv->stmmac_clk);
2973 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
2976 * stmmac_suspend - suspend callback
2977 * @ndev: net device pointer
2978 * Description: this is the function to suspend the device and it is called
2979 * by the platform driver to stop the network queue, release the resources,
2980 * program the PMT register (for WoL), clean and release driver resources.
2982 int stmmac_suspend(struct net_device *ndev)
2984 struct stmmac_priv *priv = netdev_priv(ndev);
2985 unsigned long flags;
2987 if (!ndev || !netif_running(ndev))
2991 phy_stop(priv->phydev);
2993 spin_lock_irqsave(&priv->lock, flags);
2995 netif_device_detach(ndev);
2996 netif_stop_queue(ndev);
2998 napi_disable(&priv->napi);
3000 /* Stop TX/RX DMA */
3001 priv->hw->dma->stop_tx(priv->ioaddr);
3002 priv->hw->dma->stop_rx(priv->ioaddr);
3004 stmmac_clear_descriptors(priv);
3006 /* Enable Power down mode by programming the PMT regs */
3007 if (device_may_wakeup(priv->device)) {
3008 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3011 stmmac_set_mac(priv->ioaddr, false);
3012 pinctrl_pm_select_sleep_state(priv->device);
3013 /* Disable clock in case of PWM is off */
3014 clk_disable(priv->stmmac_clk);
3016 spin_unlock_irqrestore(&priv->lock, flags);
3020 priv->oldduplex = -1;
3023 EXPORT_SYMBOL_GPL(stmmac_suspend);
3026 * stmmac_resume - resume callback
3027 * @ndev: net device pointer
3028 * Description: when resume this function is invoked to setup the DMA and CORE
3029 * in a usable state.
3031 int stmmac_resume(struct net_device *ndev)
3033 struct stmmac_priv *priv = netdev_priv(ndev);
3034 unsigned long flags;
3036 if (!netif_running(ndev))
3039 spin_lock_irqsave(&priv->lock, flags);
3041 /* Power Down bit, into the PM register, is cleared
3042 * automatically as soon as a magic packet or a Wake-up frame
3043 * is received. Anyway, it's better to manually clear
3044 * this bit because it can generate problems while resuming
3045 * from another devices (e.g. serial console).
3047 if (device_may_wakeup(priv->device)) {
3048 priv->hw->mac->pmt(priv->hw, 0);
3051 pinctrl_pm_select_default_state(priv->device);
3052 /* enable the clk prevously disabled */
3053 clk_enable(priv->stmmac_clk);
3054 /* reset the phy so that it's ready */
3056 stmmac_mdio_reset(priv->mii);
3059 netif_device_attach(ndev);
3061 init_dma_desc_rings(ndev, GFP_ATOMIC);
3062 stmmac_hw_setup(ndev, false);
3063 stmmac_init_tx_coalesce(priv);
3065 napi_enable(&priv->napi);
3067 netif_start_queue(ndev);
3069 spin_unlock_irqrestore(&priv->lock, flags);
3072 phy_start(priv->phydev);
3076 EXPORT_SYMBOL_GPL(stmmac_resume);
3079 static int __init stmmac_cmdline_opt(char *str)
3085 while ((opt = strsep(&str, ",")) != NULL) {
3086 if (!strncmp(opt, "debug:", 6)) {
3087 if (kstrtoint(opt + 6, 0, &debug))
3089 } else if (!strncmp(opt, "phyaddr:", 8)) {
3090 if (kstrtoint(opt + 8, 0, &phyaddr))
3092 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3093 if (kstrtoint(opt + 11, 0, &dma_txsize))
3095 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3096 if (kstrtoint(opt + 11, 0, &dma_rxsize))
3098 } else if (!strncmp(opt, "buf_sz:", 7)) {
3099 if (kstrtoint(opt + 7, 0, &buf_sz))
3101 } else if (!strncmp(opt, "tc:", 3)) {
3102 if (kstrtoint(opt + 3, 0, &tc))
3104 } else if (!strncmp(opt, "watchdog:", 9)) {
3105 if (kstrtoint(opt + 9, 0, &watchdog))
3107 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3108 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3110 } else if (!strncmp(opt, "pause:", 6)) {
3111 if (kstrtoint(opt + 6, 0, &pause))
3113 } else if (!strncmp(opt, "eee_timer:", 10)) {
3114 if (kstrtoint(opt + 10, 0, &eee_timer))
3116 } else if (!strncmp(opt, "chain_mode:", 11)) {
3117 if (kstrtoint(opt + 11, 0, &chain_mode))
3124 pr_err("%s: ERROR broken module parameter conversion", __func__);
3128 __setup("stmmaceth=", stmmac_cmdline_opt);
3131 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3132 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3133 MODULE_LICENSE("GPL");