drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56 #include "dwmac1000.h"
  57
  58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  59
  60 /* Module parameters */
  61 #define TX_TIMEO        5000
  62 static int watchdog = TX_TIMEO;
  63 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  64 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  65
  66 static int debug = -1;
  67 module_param(debug, int, S_IRUGO | S_IWUSR);
  68 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  69
  70 static int phyaddr = -1;
  71 module_param(phyaddr, int, S_IRUGO);
  72 MODULE_PARM_DESC(phyaddr, "Physical device address");
  73
  74 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  75 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  76
  77 static int flow_ctrl = FLOW_OFF;
  78 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  79 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  80
  81 static int pause = PAUSE_TIME;
  82 module_param(pause, int, S_IRUGO | S_IWUSR);
  83 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  84
  85 #define TC_DEFAULT 64
  86 static int tc = TC_DEFAULT;
  87 module_param(tc, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(tc, "DMA threshold control value");
  89
  90 #define DEFAULT_BUFSIZE 1536
  91 static int buf_sz = DEFAULT_BUFSIZE;
  92 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  93 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  94
  95 #define STMMAC_RX_COPYBREAK     256
  96
  97 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  98                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  99                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 100
 101 #define STMMAC_DEFAULT_LPI_TIMER        1000
 102 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 103 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 104 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 105 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 106
 107 /* By default the driver will use the ring mode to manage tx and rx descriptors
 108  * but passing this value so user can force to use the chain instead of the ring
 109  */
 110 static unsigned int chain_mode;
 111 module_param(chain_mode, int, S_IRUGO);
 112 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 113
 114 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 115
 116 #ifdef CONFIG_DEBUG_FS
 117 static int stmmac_init_fs(struct net_device *dev);
 118 static void stmmac_exit_fs(struct net_device *dev);
 119 #endif
 120
 121 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 122
 123 /**
 124  * stmmac_verify_args - verify the driver parameters.
 125  * Description: it checks the driver parameters and set a default in case of
 126  * errors.
 127  */
 128 static void stmmac_verify_args(void)
 129 {
 130         if (unlikely(watchdog < 0))
 131                 watchdog = TX_TIMEO;
 132         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 133                 buf_sz = DEFAULT_BUFSIZE;
 134         if (unlikely(flow_ctrl > 1))
 135                 flow_ctrl = FLOW_AUTO;
 136         else if (likely(flow_ctrl < 0))
 137                 flow_ctrl = FLOW_OFF;
 138         if (unlikely((pause < 0) || (pause > 0xffff)))
 139                 pause = PAUSE_TIME;
 140         if (eee_timer < 0)
 141                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 142 }
 143
 144 /**
 145  * stmmac_clk_csr_set - dynamically set the MDC clock
 146  * @priv: driver private structure
 147  * Description: this is to dynamically set the MDC clock according to the csr
 148  * clock input.
 149  * Note:
 150  *      If a specific clk_csr value is passed from the platform
 151  *      this means that the CSR Clock Range selection cannot be
 152  *      changed at run-time and it is fixed (as reported in the driver
 153  *      documentation). Viceversa the driver will try to set the MDC
 154  *      clock dynamically according to the actual clock input.
 155  */
 156 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 157 {
 158         u32 clk_rate;
 159
 160         clk_rate = clk_get_rate(priv->stmmac_clk);
 161
 162         /* Platform provided default clk_csr would be assumed valid
 163          * for all other cases except for the below mentioned ones.
 164          * For values higher than the IEEE 802.3 specified frequency
 165          * we can not estimate the proper divider as it is not known
 166          * the frequency of clk_csr_i. So we do not change the default
 167          * divider.
 168          */
 169         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 170                 if (clk_rate < CSR_F_35M)
 171                         priv->clk_csr = STMMAC_CSR_20_35M;
 172                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 173                         priv->clk_csr = STMMAC_CSR_35_60M;
 174                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 175                         priv->clk_csr = STMMAC_CSR_60_100M;
 176                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 177                         priv->clk_csr = STMMAC_CSR_100_150M;
 178                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 179                         priv->clk_csr = STMMAC_CSR_150_250M;
 180                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 181                         priv->clk_csr = STMMAC_CSR_250_300M;
 182         }
 183 }
 184
 185 static void print_pkt(unsigned char *buf, int len)
 186 {
 187         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 188         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 189 }
 190
 191 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 192 {
 193         unsigned avail;
 194
 195         if (priv->dirty_tx > priv->cur_tx)
 196                 avail = priv->dirty_tx - priv->cur_tx - 1;
 197         else
 198                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
 199
 200         return avail;
 201 }
 202
 203 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
 204 {
 205         unsigned dirty;
 206
 207         if (priv->dirty_rx <= priv->cur_rx)
 208                 dirty = priv->cur_rx - priv->dirty_rx;
 209         else
 210                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
 211
 212         return dirty;
 213 }
 214
 215 /**
 216  * stmmac_hw_fix_mac_speed - callback for speed selection
 217  * @priv: driver private structure
 218  * Description: on some platforms (e.g. ST), some HW system configuraton
 219  * registers have to be set according to the link speed negotiated.
 220  */
 221 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 222 {
 223         struct phy_device *phydev = priv->phydev;
 224
 225         if (likely(priv->plat->fix_mac_speed))
 226                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 227 }
 228
 229 /**
 230  * stmmac_enable_eee_mode - check and enter in LPI mode
 231  * @priv: driver private structure
 232  * Description: this function is to verify and enter in LPI mode in case of
 233  * EEE.
 234  */
 235 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 236 {
 237         /* Check and enter in LPI mode */
 238         if ((priv->dirty_tx == priv->cur_tx) &&
 239             (priv->tx_path_in_lpi_mode == false))
 240                 priv->hw->mac->set_eee_mode(priv->hw);
 241 }
 242
 243 /**
 244  * stmmac_disable_eee_mode - disable and exit from LPI mode
 245  * @priv: driver private structure
 246  * Description: this function is to exit and disable EEE in case of
 247  * LPI state is true. This is called by the xmit.
 248  */
 249 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 250 {
 251         priv->hw->mac->reset_eee_mode(priv->hw);
 252         del_timer_sync(&priv->eee_ctrl_timer);
 253         priv->tx_path_in_lpi_mode = false;
 254 }
 255
 256 /**
 257  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 258  * @arg : data hook
 259  * Description:
 260  *  if there is no data transfer and if we are not in LPI state,
 261  *  then MAC Transmitter can be moved to LPI state.
 262  */
 263 static void stmmac_eee_ctrl_timer(unsigned long arg)
 264 {
 265         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 266
 267         stmmac_enable_eee_mode(priv);
 268         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 269 }
 270
 271 /**
 272  * stmmac_eee_init - init EEE
 273  * @priv: driver private structure
 274  * Description:
 275  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 276  *  can also manage EEE, this function enable the LPI state and start related
 277  *  timer.
 278  */
 279 bool stmmac_eee_init(struct stmmac_priv *priv)
 280 {
 281         unsigned long flags;
 282         bool ret = false;
 283
 284         /* Using PCS we cannot dial with the phy registers at this stage
 285          * so we do not support extra feature like EEE.
 286          */
 287         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 288             (priv->pcs == STMMAC_PCS_RTBI))
 289                 goto out;
 290
 291         /* Never init EEE in case of a switch is attached */
 292         if (priv->phydev->is_pseudo_fixed_link)
 293                 goto out;
 294
 295         /* MAC core supports the EEE feature. */
 296         if (priv->dma_cap.eee) {
 297                 int tx_lpi_timer = priv->tx_lpi_timer;
 298
 299                 /* Check if the PHY supports EEE */
 300                 if (phy_init_eee(priv->phydev, 1)) {
 301                         /* To manage at run-time if the EEE cannot be supported
 302                          * anymore (for example because the lp caps have been
 303                          * changed).
 304                          * In that case the driver disable own timers.
 305                          */
 306                         spin_lock_irqsave(&priv->lock, flags);
 307                         if (priv->eee_active) {
 308                                 pr_debug("stmmac: disable EEE\n");
 309                                 del_timer_sync(&priv->eee_ctrl_timer);
 310                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 311                                                              tx_lpi_timer);
 312                         }
 313                         priv->eee_active = 0;
 314                         spin_unlock_irqrestore(&priv->lock, flags);
 315                         goto out;
 316                 }
 317                 /* Activate the EEE and start timers */
 318                 spin_lock_irqsave(&priv->lock, flags);
 319                 if (!priv->eee_active) {
 320                         priv->eee_active = 1;
 321                         setup_timer(&priv->eee_ctrl_timer,
 322                                     stmmac_eee_ctrl_timer,
 323                                     (unsigned long)priv);
 324                         mod_timer(&priv->eee_ctrl_timer,
 325                                   STMMAC_LPI_T(eee_timer));
 326
 327                         priv->hw->mac->set_eee_timer(priv->hw,
 328                                                      STMMAC_DEFAULT_LIT_LS,
 329                                                      tx_lpi_timer);
 330                 }
 331                 /* Set HW EEE according to the speed */
 332                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 333
 334                 ret = true;
 335                 spin_unlock_irqrestore(&priv->lock, flags);
 336
 337                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 338         }
 339 out:
 340         return ret;
 341 }
 342
 343 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 344  * @priv: driver private structure
 345  * @entry : descriptor index to be used.
 346  * @skb : the socket buffer
 347  * Description :
 348  * This function will read timestamp from the descriptor & pass it to stack.
 349  * and also perform some sanity checks.
 350  */
 351 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 352                                    unsigned int entry, struct sk_buff *skb)
 353 {
 354         struct skb_shared_hwtstamps shhwtstamp;
 355         u64 ns;
 356         void *desc = NULL;
 357
 358         if (!priv->hwts_tx_en)
 359                 return;
 360
 361         /* exit if skb doesn't support hw tstamp */
 362         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 363                 return;
 364
 365         if (priv->adv_ts)
 366                 desc = (priv->dma_etx + entry);
 367         else
 368                 desc = (priv->dma_tx + entry);
 369
 370         /* check tx tstamp status */
 371         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 372                 return;
 373
 374         /* get the valid tstamp */
 375         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 376
 377         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 378         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 379         /* pass tstamp to stack */
 380         skb_tstamp_tx(skb, &shhwtstamp);
 381
 382         return;
 383 }
 384
 385 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 386  * @priv: driver private structure
 387  * @entry : descriptor index to be used.
 388  * @skb : the socket buffer
 389  * Description :
 390  * This function will read received packet's timestamp from the descriptor
 391  * and pass it to stack. It also perform some sanity checks.
 392  */
 393 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 394                                    unsigned int entry, struct sk_buff *skb)
 395 {
 396         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 397         u64 ns;
 398         void *desc = NULL;
 399
 400         if (!priv->hwts_rx_en)
 401                 return;
 402
 403         if (priv->adv_ts)
 404                 desc = (priv->dma_erx + entry);
 405         else
 406                 desc = (priv->dma_rx + entry);
 407
 408         /* exit if rx tstamp is not valid */
 409         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 410                 return;
 411
 412         /* get valid tstamp */
 413         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 414         shhwtstamp = skb_hwtstamps(skb);
 415         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 416         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 417 }
 418
 419 /**
 420  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 421  *  @dev: device pointer.
 422  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 423  *  a proprietary structure used to pass information to the driver.
 424  *  Description:
 425  *  This function configures the MAC to enable/disable both outgoing(TX)
 426  *  and incoming(RX) packets time stamping based on user input.
 427  *  Return Value:
 428  *  0 on success and an appropriate -ve integer on failure.
 429  */
 430 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 431 {
 432         struct stmmac_priv *priv = netdev_priv(dev);
 433         struct hwtstamp_config config;
 434         struct timespec64 now;
 435         u64 temp = 0;
 436         u32 ptp_v2 = 0;
 437         u32 tstamp_all = 0;
 438         u32 ptp_over_ipv4_udp = 0;
 439         u32 ptp_over_ipv6_udp = 0;
 440         u32 ptp_over_ethernet = 0;
 441         u32 snap_type_sel = 0;
 442         u32 ts_master_en = 0;
 443         u32 ts_event_en = 0;
 444         u32 value = 0;
 445         u32 sec_inc;
 446
 447         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 448                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 449                 priv->hwts_tx_en = 0;
 450                 priv->hwts_rx_en = 0;
 451
 452                 return -EOPNOTSUPP;
 453         }
 454
 455         if (copy_from_user(&config, ifr->ifr_data,
 456                            sizeof(struct hwtstamp_config)))
 457                 return -EFAULT;
 458
 459         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 460                  __func__, config.flags, config.tx_type, config.rx_filter);
 461
 462         /* reserved for future extensions */
 463         if (config.flags)
 464                 return -EINVAL;
 465
 466         if (config.tx_type != HWTSTAMP_TX_OFF &&
 467             config.tx_type != HWTSTAMP_TX_ON)
 468                 return -ERANGE;
 469
 470         if (priv->adv_ts) {
 471                 switch (config.rx_filter) {
 472                 case HWTSTAMP_FILTER_NONE:
 473                         /* time stamp no incoming packet at all */
 474                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 475                         break;
 476
 477                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 478                         /* PTP v1, UDP, any kind of event packet */
 479                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 480                         /* take time stamp for all event messages */
 481                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 482
 483                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 484                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 485                         break;
 486
 487                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 488                         /* PTP v1, UDP, Sync packet */
 489                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 490                         /* take time stamp for SYNC messages only */
 491                         ts_event_en = PTP_TCR_TSEVNTENA;
 492
 493                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 494                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 495                         break;
 496
 497                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 498                         /* PTP v1, UDP, Delay_req packet */
 499                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 500                         /* take time stamp for Delay_Req messages only */
 501                         ts_master_en = PTP_TCR_TSMSTRENA;
 502                         ts_event_en = PTP_TCR_TSEVNTENA;
 503
 504                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 505                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 506                         break;
 507
 508                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 509                         /* PTP v2, UDP, any kind of event packet */
 510                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 511                         ptp_v2 = PTP_TCR_TSVER2ENA;
 512                         /* take time stamp for all event messages */
 513                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 514
 515                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 516                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 517                         break;
 518
 519                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 520                         /* PTP v2, UDP, Sync packet */
 521                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 522                         ptp_v2 = PTP_TCR_TSVER2ENA;
 523                         /* take time stamp for SYNC messages only */
 524                         ts_event_en = PTP_TCR_TSEVNTENA;
 525
 526                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 527                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 528                         break;
 529
 530                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 531                         /* PTP v2, UDP, Delay_req packet */
 532                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 533                         ptp_v2 = PTP_TCR_TSVER2ENA;
 534                         /* take time stamp for Delay_Req messages only */
 535                         ts_master_en = PTP_TCR_TSMSTRENA;
 536                         ts_event_en = PTP_TCR_TSEVNTENA;
 537
 538                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 539                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 540                         break;
 541
 542                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 543                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 544                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 545                         ptp_v2 = PTP_TCR_TSVER2ENA;
 546                         /* take time stamp for all event messages */
 547                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 548
 549                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 550                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 551                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 552                         break;
 553
 554                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 555                         /* PTP v2/802.AS1, any layer, Sync packet */
 556                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 557                         ptp_v2 = PTP_TCR_TSVER2ENA;
 558                         /* take time stamp for SYNC messages only */
 559                         ts_event_en = PTP_TCR_TSEVNTENA;
 560
 561                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 562                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 563                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 564                         break;
 565
 566                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 567                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 568                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 569                         ptp_v2 = PTP_TCR_TSVER2ENA;
 570                         /* take time stamp for Delay_Req messages only */
 571                         ts_master_en = PTP_TCR_TSMSTRENA;
 572                         ts_event_en = PTP_TCR_TSEVNTENA;
 573
 574                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 575                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 576                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 577                         break;
 578
 579                 case HWTSTAMP_FILTER_ALL:
 580                         /* time stamp any incoming packet */
 581                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 582                         tstamp_all = PTP_TCR_TSENALL;
 583                         break;
 584
 585                 default:
 586                         return -ERANGE;
 587                 }
 588         } else {
 589                 switch (config.rx_filter) {
 590                 case HWTSTAMP_FILTER_NONE:
 591                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 592                         break;
 593                 default:
 594                         /* PTP v1, UDP, any kind of event packet */
 595                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 596                         break;
 597                 }
 598         }
 599         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 600         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 601
 602         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 603                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 604         else {
 605                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 606                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 607                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 608                          ts_master_en | snap_type_sel);
 609                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 610
 611                 /* program Sub Second Increment reg */
 612                 sec_inc = priv->hw->ptp->config_sub_second_increment(
 613                         priv->ioaddr, priv->clk_ptp_rate);
 614                 temp = div_u64(1000000000ULL, sec_inc);
 615
 616                 /* calculate default added value:
 617                  * formula is :
 618                  * addend = (2^32)/freq_div_ratio;
 619                  * where, freq_div_ratio = 1e9ns/sec_inc
 620                  */
 621                 temp = (u64)(temp << 32);
 622                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 623                 priv->hw->ptp->config_addend(priv->ioaddr,
 624                                              priv->default_addend);
 625
 626                 /* initialize system time */
 627                 ktime_get_real_ts64(&now);
 628
 629                 /* lower 32 bits of tv_sec are safe until y2106 */
 630                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
 631                                             now.tv_nsec);
 632         }
 633
 634         return copy_to_user(ifr->ifr_data, &config,
 635                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 636 }
 637
 638 /**
 639  * stmmac_init_ptp - init PTP
 640  * @priv: driver private structure
 641  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 642  * This is done by looking at the HW cap. register.
 643  * This function also registers the ptp driver.
 644  */
 645 static int stmmac_init_ptp(struct stmmac_priv *priv)
 646 {
 647         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 648                 return -EOPNOTSUPP;
 649
 650         /* Fall-back to main clock in case of no PTP ref is passed */
 651         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 652         if (IS_ERR(priv->clk_ptp_ref)) {
 653                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 654                 priv->clk_ptp_ref = NULL;
 655         } else {
 656                 clk_prepare_enable(priv->clk_ptp_ref);
 657                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 658         }
 659
 660         priv->adv_ts = 0;
 661         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 662                 priv->adv_ts = 1;
 663
 664         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 665                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 666
 667         if (netif_msg_hw(priv) && priv->adv_ts)
 668                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 669
 670         priv->hw->ptp = &stmmac_ptp;
 671         priv->hwts_tx_en = 0;
 672         priv->hwts_rx_en = 0;
 673
 674         return stmmac_ptp_register(priv);
 675 }
 676
 677 static void stmmac_release_ptp(struct stmmac_priv *priv)
 678 {
 679         if (priv->clk_ptp_ref)
 680                 clk_disable_unprepare(priv->clk_ptp_ref);
 681         stmmac_ptp_unregister(priv);
 682 }
 683
 684 /**
 685  * stmmac_adjust_link - adjusts the link parameters
 686  * @dev: net device structure
 687  * Description: this is the helper called by the physical abstraction layer
 688  * drivers to communicate the phy link status. According the speed and duplex
 689  * this driver can invoke registered glue-logic as well.
 690  * It also invoke the eee initialization because it could happen when switch
 691  * on different networks (that are eee capable).
 692  */
 693 static void stmmac_adjust_link(struct net_device *dev)
 694 {
 695         struct stmmac_priv *priv = netdev_priv(dev);
 696         struct phy_device *phydev = priv->phydev;
 697         unsigned long flags;
 698         int new_state = 0;
 699         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 700
 701         if (phydev == NULL)
 702                 return;
 703
 704         spin_lock_irqsave(&priv->lock, flags);
 705
 706         if (phydev->link) {
 707                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 708
 709                 /* Now we make sure that we can be in full duplex mode.
 710                  * If not, we operate in half-duplex mode. */
 711                 if (phydev->duplex != priv->oldduplex) {
 712                         new_state = 1;
 713                         if (!(phydev->duplex))
 714                                 ctrl &= ~priv->hw->link.duplex;
 715                         else
 716                                 ctrl |= priv->hw->link.duplex;
 717                         priv->oldduplex = phydev->duplex;
 718                 }
 719                 /* Flow Control operation */
 720                 if (phydev->pause)
 721                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 722                                                  fc, pause_time);
 723
 724                 if (phydev->speed != priv->speed) {
 725                         new_state = 1;
 726                         switch (phydev->speed) {
 727                         case 1000:
 728                                 if (likely(priv->plat->has_gmac))
 729                                         ctrl &= ~priv->hw->link.port;
 730                                 stmmac_hw_fix_mac_speed(priv);
 731                                 break;
 732                         case 100:
 733                         case 10:
 734                                 if (priv->plat->has_gmac) {
 735                                         ctrl |= priv->hw->link.port;
 736                                         if (phydev->speed == SPEED_100) {
 737                                                 ctrl |= priv->hw->link.speed;
 738                                         } else {
 739                                                 ctrl &= ~(priv->hw->link.speed);
 740                                         }
 741                                 } else {
 742                                         ctrl &= ~priv->hw->link.port;
 743                                 }
 744                                 stmmac_hw_fix_mac_speed(priv);
 745                                 break;
 746                         default:
 747                                 if (netif_msg_link(priv))
 748                                         pr_warn("%s: Speed (%d) not 10/100\n",
 749                                                 dev->name, phydev->speed);
 750                                 break;
 751                         }
 752
 753                         priv->speed = phydev->speed;
 754                 }
 755
 756                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 757
 758                 if (!priv->oldlink) {
 759                         new_state = 1;
 760                         priv->oldlink = 1;
 761                 }
 762         } else if (priv->oldlink) {
 763                 new_state = 1;
 764                 priv->oldlink = 0;
 765                 priv->speed = 0;
 766                 priv->oldduplex = -1;
 767         }
 768
 769         if (new_state && netif_msg_link(priv))
 770                 phy_print_status(phydev);
 771
 772         spin_unlock_irqrestore(&priv->lock, flags);
 773
 774         /* At this stage, it could be needed to setup the EEE or adjust some
 775          * MAC related HW registers.
 776          */
 777         priv->eee_enabled = stmmac_eee_init(priv);
 778 }
 779
 780 /**
 781  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 782  * @priv: driver private structure
 783  * Description: this is to verify if the HW supports the PCS.
 784  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 785  * configured for the TBI, RTBI, or SGMII PHY interface.
 786  */
 787 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 788 {
 789         int interface = priv->plat->interface;
 790
 791         if (priv->dma_cap.pcs) {
 792                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 793                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 794                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 795                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 796                         pr_debug("STMMAC: PCS RGMII support enable\n");
 797                         priv->pcs = STMMAC_PCS_RGMII;
 798                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 799                         pr_debug("STMMAC: PCS SGMII support enable\n");
 800                         priv->pcs = STMMAC_PCS_SGMII;
 801                 }
 802         }
 803 }
 804
 805 /**
 806  * stmmac_init_phy - PHY initialization
 807  * @dev: net device structure
 808  * Description: it initializes the driver's PHY state, and attaches the PHY
 809  * to the mac driver.
 810  *  Return value:
 811  *  0 on success
 812  */
 813 static int stmmac_init_phy(struct net_device *dev)
 814 {
 815         struct stmmac_priv *priv = netdev_priv(dev);
 816         struct phy_device *phydev;
 817         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 818         char bus_id[MII_BUS_ID_SIZE];
 819         int interface = priv->plat->interface;
 820         int max_speed = priv->plat->max_speed;
 821         priv->oldlink = 0;
 822         priv->speed = 0;
 823         priv->oldduplex = -1;
 824
 825         if (priv->plat->phy_node) {
 826                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 827                                         &stmmac_adjust_link, 0, interface);
 828         } else {
 829                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 830                          priv->plat->bus_id);
 831
 832                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 833                          priv->plat->phy_addr);
 834                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 835                          phy_id_fmt);
 836
 837                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 838                                      interface);
 839         }
 840
 841         if (IS_ERR_OR_NULL(phydev)) {
 842                 pr_err("%s: Could not attach to PHY\n", dev->name);
 843                 if (!phydev)
 844                         return -ENODEV;
 845
 846                 return PTR_ERR(phydev);
 847         }
 848
 849         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 850         if ((interface == PHY_INTERFACE_MODE_MII) ||
 851             (interface == PHY_INTERFACE_MODE_RMII) ||
 852                 (max_speed < 1000 && max_speed > 0))
 853                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 854                                          SUPPORTED_1000baseT_Full);
 855
 856         /*
 857          * Broken HW is sometimes missing the pull-up resistor on the
 858          * MDIO line, which results in reads to non-existent devices returning
 859          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 860          * device as well.
 861          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 862          */
 863         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 864                 phy_disconnect(phydev);
 865                 return -ENODEV;
 866         }
 867
 868         /* If attached to a switch, there is no reason to poll phy handler */
 869         if (phydev->is_pseudo_fixed_link)
 870                 phydev->irq = PHY_IGNORE_INTERRUPT;
 871
 872         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 873                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 874
 875         priv->phydev = phydev;
 876
 877         return 0;
 878 }
 879
 880 /**
 881  * stmmac_display_ring - display ring
 882  * @head: pointer to the head of the ring passed.
 883  * @size: size of the ring.
 884  * @extend_desc: to verify if extended descriptors are used.
 885  * Description: display the control/status and buffer descriptors.
 886  */
 887 static void stmmac_display_ring(void *head, int size, int extend_desc)
 888 {
 889         int i;
 890         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 891         struct dma_desc *p = (struct dma_desc *)head;
 892
 893         for (i = 0; i < size; i++) {
 894                 u64 x;
 895                 if (extend_desc) {
 896                         x = *(u64 *) ep;
 897                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 898                                 i, (unsigned int)virt_to_phys(ep),
 899                                 (unsigned int)x, (unsigned int)(x >> 32),
 900                                 ep->basic.des2, ep->basic.des3);
 901                         ep++;
 902                 } else {
 903                         x = *(u64 *) p;
 904                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 905                                 i, (unsigned int)virt_to_phys(p),
 906                                 (unsigned int)x, (unsigned int)(x >> 32),
 907                                 p->des2, p->des3);
 908                         p++;
 909                 }
 910                 pr_info("\n");
 911         }
 912 }
 913
 914 static void stmmac_display_rings(struct stmmac_priv *priv)
 915 {
 916         if (priv->extend_desc) {
 917                 pr_info("Extended RX descriptor ring:\n");
 918                 stmmac_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1);
 919                 pr_info("Extended TX descriptor ring:\n");
 920                 stmmac_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1);
 921         } else {
 922                 pr_info("RX descriptor ring:\n");
 923                 stmmac_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0);
 924                 pr_info("TX descriptor ring:\n");
 925                 stmmac_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0);
 926         }
 927 }
 928
 929 static int stmmac_set_bfsize(int mtu, int bufsize)
 930 {
 931         int ret = bufsize;
 932
 933         if (mtu >= BUF_SIZE_4KiB)
 934                 ret = BUF_SIZE_8KiB;
 935         else if (mtu >= BUF_SIZE_2KiB)
 936                 ret = BUF_SIZE_4KiB;
 937         else if (mtu > DEFAULT_BUFSIZE)
 938                 ret = BUF_SIZE_2KiB;
 939         else
 940                 ret = DEFAULT_BUFSIZE;
 941
 942         return ret;
 943 }
 944
 945 /**
 946  * stmmac_clear_descriptors - clear descriptors
 947  * @priv: driver private structure
 948  * Description: this function is called to clear the tx and rx descriptors
 949  * in case of both basic and extended descriptors are used.
 950  */
 951 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 952 {
 953         int i;
 954
 955         /* Clear the Rx/Tx descriptors */
 956         for (i = 0; i < DMA_RX_SIZE; i++)
 957                 if (priv->extend_desc)
 958                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 959                                                      priv->use_riwt, priv->mode,
 960                                                      (i == DMA_RX_SIZE - 1));
 961                 else
 962                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 963                                                      priv->use_riwt, priv->mode,
 964                                                      (i == DMA_RX_SIZE - 1));
 965         for (i = 0; i < DMA_TX_SIZE; i++)
 966                 if (priv->extend_desc)
 967                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 968                                                      priv->mode,
 969                                                      (i == DMA_TX_SIZE - 1));
 970                 else
 971                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 972                                                      priv->mode,
 973                                                      (i == DMA_TX_SIZE - 1));
 974 }
 975
 976 /**
 977  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 978  * @priv: driver private structure
 979  * @p: descriptor pointer
 980  * @i: descriptor index
 981  * @flags: gfp flag.
 982  * Description: this function is called to allocate a receive buffer, perform
 983  * the DMA mapping and init the descriptor.
 984  */
 985 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 986                                   int i, gfp_t flags)
 987 {
 988         struct sk_buff *skb;
 989
 990         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 991         if (!skb) {
 992                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 993                 return -ENOMEM;
 994         }
 995         priv->rx_skbuff[i] = skb;
 996         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 997                                                 priv->dma_buf_sz,
 998                                                 DMA_FROM_DEVICE);
 999         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1000                 pr_err("%s: DMA mapping error\n", __func__);
1001                 dev_kfree_skb_any(skb);
1002                 return -EINVAL;
1003         }
1004
1005         p->des2 = priv->rx_skbuff_dma[i];
1006
1007         if ((priv->hw->mode->init_desc3) &&
1008             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1009                 priv->hw->mode->init_desc3(p);
1010
1011         return 0;
1012 }
1013
1014 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1015 {
1016         if (priv->rx_skbuff[i]) {
1017                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1018                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1019                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1020         }
1021         priv->rx_skbuff[i] = NULL;
1022 }
1023
1024 /**
1025  * init_dma_desc_rings - init the RX/TX descriptor rings
1026  * @dev: net device structure
1027  * @flags: gfp flag.
1028  * Description: this function initializes the DMA RX/TX descriptors
1029  * and allocates the socket buffers. It suppors the chained and ring
1030  * modes.
1031  */
1032 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1033 {
1034         int i;
1035         struct stmmac_priv *priv = netdev_priv(dev);
1036         unsigned int bfsize = 0;
1037         int ret = -ENOMEM;
1038
1039         if (priv->hw->mode->set_16kib_bfsize)
1040                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1041
1042         if (bfsize < BUF_SIZE_16KiB)
1043                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1044
1045         priv->dma_buf_sz = bfsize;
1046
1047         if (netif_msg_probe(priv)) {
1048                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1049                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1050
1051                 /* RX INITIALIZATION */
1052                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1053         }
1054         for (i = 0; i < DMA_RX_SIZE; i++) {
1055                 struct dma_desc *p;
1056                 if (priv->extend_desc)
1057                         p = &((priv->dma_erx + i)->basic);
1058                 else
1059                         p = priv->dma_rx + i;
1060
1061                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1062                 if (ret)
1063                         goto err_init_rx_buffers;
1064
1065                 if (netif_msg_probe(priv))
1066                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1067                                  priv->rx_skbuff[i]->data,
1068                                  (unsigned int)priv->rx_skbuff_dma[i]);
1069         }
1070         priv->cur_rx = 0;
1071         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1072         buf_sz = bfsize;
1073
1074         /* Setup the chained descriptor addresses */
1075         if (priv->mode == STMMAC_CHAIN_MODE) {
1076                 if (priv->extend_desc) {
1077                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1078                                              DMA_RX_SIZE, 1);
1079                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1080                                              DMA_TX_SIZE, 1);
1081                 } else {
1082                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1083                                              DMA_RX_SIZE, 0);
1084                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1085                                              DMA_TX_SIZE, 0);
1086                 }
1087         }
1088
1089         /* TX INITIALIZATION */
1090         for (i = 0; i < DMA_TX_SIZE; i++) {
1091                 struct dma_desc *p;
1092                 if (priv->extend_desc)
1093                         p = &((priv->dma_etx + i)->basic);
1094                 else
1095                         p = priv->dma_tx + i;
1096                 p->des2 = 0;
1097                 priv->tx_skbuff_dma[i].buf = 0;
1098                 priv->tx_skbuff_dma[i].map_as_page = false;
1099                 priv->tx_skbuff_dma[i].len = 0;
1100                 priv->tx_skbuff_dma[i].last_segment = false;
1101                 priv->tx_skbuff[i] = NULL;
1102         }
1103
1104         priv->dirty_tx = 0;
1105         priv->cur_tx = 0;
1106         netdev_reset_queue(priv->dev);
1107
1108         stmmac_clear_descriptors(priv);
1109
1110         if (netif_msg_hw(priv))
1111                 stmmac_display_rings(priv);
1112
1113         return 0;
1114 err_init_rx_buffers:
1115         while (--i >= 0)
1116                 stmmac_free_rx_buffers(priv, i);
1117         return ret;
1118 }
1119
1120 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1121 {
1122         int i;
1123
1124         for (i = 0; i < DMA_RX_SIZE; i++)
1125                 stmmac_free_rx_buffers(priv, i);
1126 }
1127
1128 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1129 {
1130         int i;
1131
1132         for (i = 0; i < DMA_TX_SIZE; i++) {
1133                 struct dma_desc *p;
1134
1135                 if (priv->extend_desc)
1136                         p = &((priv->dma_etx + i)->basic);
1137                 else
1138                         p = priv->dma_tx + i;
1139
1140                 if (priv->tx_skbuff_dma[i].buf) {
1141                         if (priv->tx_skbuff_dma[i].map_as_page)
1142                                 dma_unmap_page(priv->device,
1143                                                priv->tx_skbuff_dma[i].buf,
1144                                                priv->tx_skbuff_dma[i].len,
1145                                                DMA_TO_DEVICE);
1146                         else
1147                                 dma_unmap_single(priv->device,
1148                                                  priv->tx_skbuff_dma[i].buf,
1149                                                  priv->tx_skbuff_dma[i].len,
1150                                                  DMA_TO_DEVICE);
1151                 }
1152
1153                 if (priv->tx_skbuff[i] != NULL) {
1154                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1155                         priv->tx_skbuff[i] = NULL;
1156                         priv->tx_skbuff_dma[i].buf = 0;
1157                         priv->tx_skbuff_dma[i].map_as_page = false;
1158                 }
1159         }
1160 }
1161
1162 /**
1163  * alloc_dma_desc_resources - alloc TX/RX resources.
1164  * @priv: private structure
1165  * Description: according to which descriptor can be used (extend or basic)
1166  * this function allocates the resources for TX and RX paths. In case of
1167  * reception, for example, it pre-allocated the RX socket buffer in order to
1168  * allow zero-copy mechanism.
1169  */
1170 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1171 {
1172         int ret = -ENOMEM;
1173
1174         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1175                                             GFP_KERNEL);
1176         if (!priv->rx_skbuff_dma)
1177                 return -ENOMEM;
1178
1179         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1180                                         GFP_KERNEL);
1181         if (!priv->rx_skbuff)
1182                 goto err_rx_skbuff;
1183
1184         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1185                                             sizeof(*priv->tx_skbuff_dma),
1186                                             GFP_KERNEL);
1187         if (!priv->tx_skbuff_dma)
1188                 goto err_tx_skbuff_dma;
1189
1190         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1191                                         GFP_KERNEL);
1192         if (!priv->tx_skbuff)
1193                 goto err_tx_skbuff;
1194
1195         if (priv->extend_desc) {
1196                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1197                                                     sizeof(struct
1198                                                            dma_extended_desc),
1199                                                     &priv->dma_rx_phy,
1200                                                     GFP_KERNEL);
1201                 if (!priv->dma_erx)
1202                         goto err_dma;
1203
1204                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1205                                                     sizeof(struct
1206                                                            dma_extended_desc),
1207                                                     &priv->dma_tx_phy,
1208                                                     GFP_KERNEL);
1209                 if (!priv->dma_etx) {
1210                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1211                                           sizeof(struct dma_extended_desc),
1212                                           priv->dma_erx, priv->dma_rx_phy);
1213                         goto err_dma;
1214                 }
1215         } else {
1216                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1217                                                    sizeof(struct dma_desc),
1218                                                    &priv->dma_rx_phy,
1219                                                    GFP_KERNEL);
1220                 if (!priv->dma_rx)
1221                         goto err_dma;
1222
1223                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1224                                                    sizeof(struct dma_desc),
1225                                                    &priv->dma_tx_phy,
1226                                                    GFP_KERNEL);
1227                 if (!priv->dma_tx) {
1228                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1229                                           sizeof(struct dma_desc),
1230                                           priv->dma_rx, priv->dma_rx_phy);
1231                         goto err_dma;
1232                 }
1233         }
1234
1235         return 0;
1236
1237 err_dma:
1238         kfree(priv->tx_skbuff);
1239 err_tx_skbuff:
1240         kfree(priv->tx_skbuff_dma);
1241 err_tx_skbuff_dma:
1242         kfree(priv->rx_skbuff);
1243 err_rx_skbuff:
1244         kfree(priv->rx_skbuff_dma);
1245         return ret;
1246 }
1247
1248 static void free_dma_desc_resources(struct stmmac_priv *priv)
1249 {
1250         /* Release the DMA TX/RX socket buffers */
1251         dma_free_rx_skbufs(priv);
1252         dma_free_tx_skbufs(priv);
1253
1254         /* Free DMA regions of consistent memory previously allocated */
1255         if (!priv->extend_desc) {
1256                 dma_free_coherent(priv->device,
1257                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1258                                   priv->dma_tx, priv->dma_tx_phy);
1259                 dma_free_coherent(priv->device,
1260                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1261                                   priv->dma_rx, priv->dma_rx_phy);
1262         } else {
1263                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1264                                   sizeof(struct dma_extended_desc),
1265                                   priv->dma_etx, priv->dma_tx_phy);
1266                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1267                                   sizeof(struct dma_extended_desc),
1268                                   priv->dma_erx, priv->dma_rx_phy);
1269         }
1270         kfree(priv->rx_skbuff_dma);
1271         kfree(priv->rx_skbuff);
1272         kfree(priv->tx_skbuff_dma);
1273         kfree(priv->tx_skbuff);
1274 }
1275
1276 /**
1277  *  stmmac_dma_operation_mode - HW DMA operation mode
1278  *  @priv: driver private structure
1279  *  Description: it is used for configuring the DMA operation mode register in
1280  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1281  */
1282 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1283 {
1284         int rxfifosz = priv->plat->rx_fifo_size;
1285
1286         if (priv->plat->force_thresh_dma_mode)
1287                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1288         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1289                 /*
1290                  * In case of GMAC, SF mode can be enabled
1291                  * to perform the TX COE in HW. This depends on:
1292                  * 1) TX COE if actually supported
1293                  * 2) There is no bugged Jumbo frame support
1294                  *    that needs to not insert csum in the TDES.
1295                  */
1296                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1297                                         rxfifosz);
1298                 priv->xstats.threshold = SF_DMA_MODE;
1299         } else
1300                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1301                                         rxfifosz);
1302 }
1303
1304 /**
1305  * stmmac_tx_clean - to manage the transmission completion
1306  * @priv: driver private structure
1307  * Description: it reclaims the transmit resources after transmission completes.
1308  */
1309 static void stmmac_tx_clean(struct stmmac_priv *priv)
1310 {
1311         unsigned int bytes_compl = 0, pkts_compl = 0;
1312         unsigned int entry = priv->dirty_tx;
1313
1314         spin_lock(&priv->tx_lock);
1315
1316         priv->xstats.tx_clean++;
1317
1318         while (entry != priv->cur_tx) {
1319                 struct sk_buff *skb = priv->tx_skbuff[entry];
1320                 struct dma_desc *p;
1321                 int status;
1322
1323                 if (priv->extend_desc)
1324                         p = (struct dma_desc *)(priv->dma_etx + entry);
1325                 else
1326                         p = priv->dma_tx + entry;
1327
1328                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1329                                                       &priv->xstats, p,
1330                                                       priv->ioaddr);
1331                 /* Check if the descriptor is owned by the DMA */
1332                 if (unlikely(status & tx_dma_own))
1333                         break;
1334
1335                 /* Just consider the last segment and ...*/
1336                 if (likely(!(status & tx_not_ls))) {
1337                         /* ... verify the status error condition */
1338                         if (unlikely(status & tx_err)) {
1339                                 priv->dev->stats.tx_errors++;
1340                         } else {
1341                                 priv->dev->stats.tx_packets++;
1342                                 priv->xstats.tx_pkt_n++;
1343                         }
1344                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1345                 }
1346
1347                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1348                         if (priv->tx_skbuff_dma[entry].map_as_page)
1349                                 dma_unmap_page(priv->device,
1350                                                priv->tx_skbuff_dma[entry].buf,
1351                                                priv->tx_skbuff_dma[entry].len,
1352                                                DMA_TO_DEVICE);
1353                         else
1354                                 dma_unmap_single(priv->device,
1355                                                  priv->tx_skbuff_dma[entry].buf,
1356                                                  priv->tx_skbuff_dma[entry].len,
1357                                                  DMA_TO_DEVICE);
1358                         priv->tx_skbuff_dma[entry].buf = 0;
1359                         priv->tx_skbuff_dma[entry].map_as_page = false;
1360                 }
1361                 priv->hw->mode->clean_desc3(priv, p);
1362                 priv->tx_skbuff_dma[entry].last_segment = false;
1363                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1364
1365                 if (likely(skb != NULL)) {
1366                         pkts_compl++;
1367                         bytes_compl += skb->len;
1368                         dev_consume_skb_any(skb);
1369                         priv->tx_skbuff[entry] = NULL;
1370                 }
1371
1372                 priv->hw->desc->release_tx_desc(p, priv->mode);
1373
1374                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1375         }
1376         priv->dirty_tx = entry;
1377
1378         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1379
1380         if (unlikely(netif_queue_stopped(priv->dev) &&
1381                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1382                 netif_tx_lock(priv->dev);
1383                 if (netif_queue_stopped(priv->dev) &&
1384                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1385                         if (netif_msg_tx_done(priv))
1386                                 pr_debug("%s: restart transmit\n", __func__);
1387                         netif_wake_queue(priv->dev);
1388                 }
1389                 netif_tx_unlock(priv->dev);
1390         }
1391
1392         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1393                 stmmac_enable_eee_mode(priv);
1394                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1395         }
1396         spin_unlock(&priv->tx_lock);
1397 }
1398
1399 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1400 {
1401         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1402 }
1403
1404 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1405 {
1406         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1407 }
1408
1409 /**
1410  * stmmac_tx_err - to manage the tx error
1411  * @priv: driver private structure
1412  * Description: it cleans the descriptors and restarts the transmission
1413  * in case of transmission errors.
1414  */
1415 static void stmmac_tx_err(struct stmmac_priv *priv)
1416 {
1417         int i;
1418         netif_stop_queue(priv->dev);
1419
1420         priv->hw->dma->stop_tx(priv->ioaddr);
1421         dma_free_tx_skbufs(priv);
1422         for (i = 0; i < DMA_TX_SIZE; i++)
1423                 if (priv->extend_desc)
1424                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1425                                                      priv->mode,
1426                                                      (i == DMA_TX_SIZE - 1));
1427                 else
1428                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1429                                                      priv->mode,
1430                                                      (i == DMA_TX_SIZE - 1));
1431         priv->dirty_tx = 0;
1432         priv->cur_tx = 0;
1433         netdev_reset_queue(priv->dev);
1434         priv->hw->dma->start_tx(priv->ioaddr);
1435
1436         priv->dev->stats.tx_errors++;
1437         netif_wake_queue(priv->dev);
1438 }
1439
1440 /**
1441  * stmmac_dma_interrupt - DMA ISR
1442  * @priv: driver private structure
1443  * Description: this is the DMA ISR. It is called by the main ISR.
1444  * It calls the dwmac dma routine and schedule poll method in case of some
1445  * work can be done.
1446  */
1447 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1448 {
1449         int status;
1450         int rxfifosz = priv->plat->rx_fifo_size;
1451
1452         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1453         if (likely((status & handle_rx)) || (status & handle_tx)) {
1454                 if (likely(napi_schedule_prep(&priv->napi))) {
1455                         stmmac_disable_dma_irq(priv);
1456                         __napi_schedule(&priv->napi);
1457                 }
1458         }
1459         if (unlikely(status & tx_hard_error_bump_tc)) {
1460                 /* Try to bump up the dma threshold on this failure */
1461                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1462                     (tc <= 256)) {
1463                         tc += 64;
1464                         if (priv->plat->force_thresh_dma_mode)
1465                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1466                                                         rxfifosz);
1467                         else
1468                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1469                                                         SF_DMA_MODE, rxfifosz);
1470                         priv->xstats.threshold = tc;
1471                 }
1472         } else if (unlikely(status == tx_hard_error))
1473                 stmmac_tx_err(priv);
1474 }
1475
1476 /**
1477  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1478  * @priv: driver private structure
1479  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1480  */
1481 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1482 {
1483         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1484             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1485
1486         dwmac_mmc_intr_all_mask(priv->ioaddr);
1487
1488         if (priv->dma_cap.rmon) {
1489                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1490                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1491         } else
1492                 pr_info(" No MAC Management Counters available\n");
1493 }
1494
1495 /**
1496  * stmmac_get_synopsys_id - return the SYINID.
1497  * @priv: driver private structure
1498  * Description: this simple function is to decode and return the SYINID
1499  * starting from the HW core register.
1500  */
1501 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1502 {
1503         u32 hwid = priv->hw->synopsys_uid;
1504
1505         /* Check Synopsys Id (not available on old chips) */
1506         if (likely(hwid)) {
1507                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1508                 u32 synid = (hwid & 0x000000ff);
1509
1510                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1511                         uid, synid);
1512
1513                 return synid;
1514         }
1515         return 0;
1516 }
1517
1518 /**
1519  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1520  * @priv: driver private structure
1521  * Description: select the Enhanced/Alternate or Normal descriptors.
1522  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1523  * supported by the HW capability register.
1524  */
1525 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1526 {
1527         if (priv->plat->enh_desc) {
1528                 pr_info(" Enhanced/Alternate descriptors\n");
1529
1530                 /* GMAC older than 3.50 has no extended descriptors */
1531                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1532                         pr_info("\tEnabled extended descriptors\n");
1533                         priv->extend_desc = 1;
1534                 } else
1535                         pr_warn("Extended descriptors not supported\n");
1536
1537                 priv->hw->desc = &enh_desc_ops;
1538         } else {
1539                 pr_info(" Normal descriptors\n");
1540                 priv->hw->desc = &ndesc_ops;
1541         }
1542 }
1543
1544 /**
1545  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1546  * @priv: driver private structure
1547  * Description:
1548  *  new GMAC chip generations have a new register to indicate the
1549  *  presence of the optional feature/functions.
1550  *  This can be also used to override the value passed through the
1551  *  platform and necessary for old MAC10/100 and GMAC chips.
1552  */
1553 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1554 {
1555         u32 hw_cap = 0;
1556
1557         if (priv->hw->dma->get_hw_feature) {
1558                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1559
1560                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1561                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1562                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1563                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1564                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1565                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1566                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1567                 priv->dma_cap.pmt_remote_wake_up =
1568                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1569                 priv->dma_cap.pmt_magic_frame =
1570                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1571                 /* MMC */
1572                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1573                 /* IEEE 1588-2002 */
1574                 priv->dma_cap.time_stamp =
1575                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1576                 /* IEEE 1588-2008 */
1577                 priv->dma_cap.atime_stamp =
1578                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1579                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1580                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1581                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1582                 /* TX and RX csum */
1583                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1584                 priv->dma_cap.rx_coe_type1 =
1585                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1586                 priv->dma_cap.rx_coe_type2 =
1587                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1588                 priv->dma_cap.rxfifo_over_2048 =
1589                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1590                 /* TX and RX number of channels */
1591                 priv->dma_cap.number_rx_channel =
1592                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1593                 priv->dma_cap.number_tx_channel =
1594                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1595                 /* Alternate (enhanced) DESC mode */
1596                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1597         }
1598
1599         return hw_cap;
1600 }
1601
1602 /**
1603  * stmmac_check_ether_addr - check if the MAC addr is valid
1604  * @priv: driver private structure
1605  * Description:
1606  * it is to verify if the MAC address is valid, in case of failures it
1607  * generates a random MAC address
1608  */
1609 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1610 {
1611         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1612                 priv->hw->mac->get_umac_addr(priv->hw,
1613                                              priv->dev->dev_addr, 0);
1614                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1615                         eth_hw_addr_random(priv->dev);
1616                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1617                         priv->dev->dev_addr);
1618         }
1619 }
1620
1621 /**
1622  * stmmac_init_dma_engine - DMA init.
1623  * @priv: driver private structure
1624  * Description:
1625  * It inits the DMA invoking the specific MAC/GMAC callback.
1626  * Some DMA parameters can be passed from the platform;
1627  * in case of these are not passed a default is kept for the MAC or GMAC.
1628  */
1629 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1630 {
1631         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1632         int mixed_burst = 0;
1633         int atds = 0;
1634         int ret = 0;
1635
1636         if (priv->plat->dma_cfg) {
1637                 pbl = priv->plat->dma_cfg->pbl;
1638                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1639                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1640                 aal = priv->plat->dma_cfg->aal;
1641         }
1642
1643         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1644                 atds = 1;
1645
1646         ret = priv->hw->dma->reset(priv->ioaddr);
1647         if (ret) {
1648                 dev_err(priv->device, "Failed to reset the dma\n");
1649                 return ret;
1650         }
1651
1652         priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1653                             aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1654
1655         if ((priv->synopsys_id >= DWMAC_CORE_3_50) &&
1656             (priv->plat->axi && priv->hw->dma->axi))
1657                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1658
1659         return ret;
1660 }
1661
1662 /**
1663  * stmmac_tx_timer - mitigation sw timer for tx.
1664  * @data: data pointer
1665  * Description:
1666  * This is the timer handler to directly invoke the stmmac_tx_clean.
1667  */
1668 static void stmmac_tx_timer(unsigned long data)
1669 {
1670         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1671
1672         stmmac_tx_clean(priv);
1673 }
1674
1675 /**
1676  * stmmac_init_tx_coalesce - init tx mitigation options.
1677  * @priv: driver private structure
1678  * Description:
1679  * This inits the transmit coalesce parameters: i.e. timer rate,
1680  * timer handler and default threshold used for enabling the
1681  * interrupt on completion bit.
1682  */
1683 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1684 {
1685         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1686         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1687         init_timer(&priv->txtimer);
1688         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1689         priv->txtimer.data = (unsigned long)priv;
1690         priv->txtimer.function = stmmac_tx_timer;
1691         add_timer(&priv->txtimer);
1692 }
1693
1694 /**
1695  * stmmac_hw_setup - setup mac in a usable state.
1696  *  @dev : pointer to the device structure.
1697  *  Description:
1698  *  this is the main function to setup the HW in a usable state because the
1699  *  dma engine is reset, the core registers are configured (e.g. AXI,
1700  *  Checksum features, timers). The DMA is ready to start receiving and
1701  *  transmitting.
1702  *  Return value:
1703  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1704  *  file on failure.
1705  */
1706 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1707 {
1708         struct stmmac_priv *priv = netdev_priv(dev);
1709         int ret;
1710
1711         /* DMA initialization and SW reset */
1712         ret = stmmac_init_dma_engine(priv);
1713         if (ret < 0) {
1714                 pr_err("%s: DMA engine initialization failed\n", __func__);
1715                 return ret;
1716         }
1717
1718         /* Copy the MAC addr into the HW  */
1719         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1720
1721         /* If required, perform hw setup of the bus. */
1722         if (priv->plat->bus_setup)
1723                 priv->plat->bus_setup(priv->ioaddr);
1724
1725         /* Initialize the MAC Core */
1726         priv->hw->mac->core_init(priv->hw, dev->mtu);
1727
1728         ret = priv->hw->mac->rx_ipc(priv->hw);
1729         if (!ret) {
1730                 pr_warn(" RX IPC Checksum Offload disabled\n");
1731                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1732                 priv->hw->rx_csum = 0;
1733         }
1734
1735         /* Enable the MAC Rx/Tx */
1736         stmmac_set_mac(priv->ioaddr, true);
1737
1738         /* Set the HW DMA mode and the COE */
1739         stmmac_dma_operation_mode(priv);
1740
1741         stmmac_mmc_setup(priv);
1742
1743         if (init_ptp) {
1744                 ret = stmmac_init_ptp(priv);
1745                 if (ret && ret != -EOPNOTSUPP)
1746                         pr_warn("%s: failed PTP initialisation\n", __func__);
1747         }
1748
1749 #ifdef CONFIG_DEBUG_FS
1750         ret = stmmac_init_fs(dev);
1751         if (ret < 0)
1752                 pr_warn("%s: failed debugFS registration\n", __func__);
1753 #endif
1754         /* Start the ball rolling... */
1755         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1756         priv->hw->dma->start_tx(priv->ioaddr);
1757         priv->hw->dma->start_rx(priv->ioaddr);
1758
1759         /* Dump DMA/MAC registers */
1760         if (netif_msg_hw(priv)) {
1761                 priv->hw->mac->dump_regs(priv->hw);
1762                 priv->hw->dma->dump_regs(priv->ioaddr);
1763         }
1764         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1765
1766         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1767                 priv->rx_riwt = MAX_DMA_RIWT;
1768                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1769         }
1770
1771         if (priv->pcs && priv->hw->mac->ctrl_ane)
1772                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1773
1774         return 0;
1775 }
1776
1777 /**
1778  *  stmmac_open - open entry point of the driver
1779  *  @dev : pointer to the device structure.
1780  *  Description:
1781  *  This function is the open entry point of the driver.
1782  *  Return value:
1783  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1784  *  file on failure.
1785  */
1786 static int stmmac_open(struct net_device *dev)
1787 {
1788         struct stmmac_priv *priv = netdev_priv(dev);
1789         int ret;
1790
1791         stmmac_check_ether_addr(priv);
1792
1793         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1794             priv->pcs != STMMAC_PCS_RTBI) {
1795                 ret = stmmac_init_phy(dev);
1796                 if (ret) {
1797                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1798                                __func__, ret);
1799                         return ret;
1800                 }
1801         }
1802
1803         /* Extra statistics */
1804         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1805         priv->xstats.threshold = tc;
1806
1807         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1808         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1809
1810         ret = alloc_dma_desc_resources(priv);
1811         if (ret < 0) {
1812                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1813                 goto dma_desc_error;
1814         }
1815
1816         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1817         if (ret < 0) {
1818                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1819                 goto init_error;
1820         }
1821
1822         ret = stmmac_hw_setup(dev, true);
1823         if (ret < 0) {
1824                 pr_err("%s: Hw setup failed\n", __func__);
1825                 goto init_error;
1826         }
1827
1828         stmmac_init_tx_coalesce(priv);
1829
1830         if (priv->phydev)
1831                 phy_start(priv->phydev);
1832
1833         /* Request the IRQ lines */
1834         ret = request_irq(dev->irq, stmmac_interrupt,
1835                           IRQF_SHARED, dev->name, dev);
1836         if (unlikely(ret < 0)) {
1837                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1838                        __func__, dev->irq, ret);
1839                 goto init_error;
1840         }
1841
1842         /* Request the Wake IRQ in case of another line is used for WoL */
1843         if (priv->wol_irq != dev->irq) {
1844                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1845                                   IRQF_SHARED, dev->name, dev);
1846                 if (unlikely(ret < 0)) {
1847                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1848                                __func__, priv->wol_irq, ret);
1849                         goto wolirq_error;
1850                 }
1851         }
1852
1853         /* Request the IRQ lines */
1854         if (priv->lpi_irq > 0) {
1855                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1856                                   dev->name, dev);
1857                 if (unlikely(ret < 0)) {
1858                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1859                                __func__, priv->lpi_irq, ret);
1860                         goto lpiirq_error;
1861                 }
1862         }
1863
1864         napi_enable(&priv->napi);
1865         netif_start_queue(dev);
1866
1867         return 0;
1868
1869 lpiirq_error:
1870         if (priv->wol_irq != dev->irq)
1871                 free_irq(priv->wol_irq, dev);
1872 wolirq_error:
1873         free_irq(dev->irq, dev);
1874
1875 init_error:
1876         free_dma_desc_resources(priv);
1877 dma_desc_error:
1878         if (priv->phydev)
1879                 phy_disconnect(priv->phydev);
1880
1881         return ret;
1882 }
1883
1884 /**
1885  *  stmmac_release - close entry point of the driver
1886  *  @dev : device pointer.
1887  *  Description:
1888  *  This is the stop entry point of the driver.
1889  */
1890 static int stmmac_release(struct net_device *dev)
1891 {
1892         struct stmmac_priv *priv = netdev_priv(dev);
1893
1894         if (priv->eee_enabled)
1895                 del_timer_sync(&priv->eee_ctrl_timer);
1896
1897         /* Stop and disconnect the PHY */
1898         if (priv->phydev) {
1899                 phy_stop(priv->phydev);
1900                 phy_disconnect(priv->phydev);
1901                 priv->phydev = NULL;
1902         }
1903
1904         netif_stop_queue(dev);
1905
1906         napi_disable(&priv->napi);
1907
1908         del_timer_sync(&priv->txtimer);
1909
1910         /* Free the IRQ lines */
1911         free_irq(dev->irq, dev);
1912         if (priv->wol_irq != dev->irq)
1913                 free_irq(priv->wol_irq, dev);
1914         if (priv->lpi_irq > 0)
1915                 free_irq(priv->lpi_irq, dev);
1916
1917         /* Stop TX/RX DMA and clear the descriptors */
1918         priv->hw->dma->stop_tx(priv->ioaddr);
1919         priv->hw->dma->stop_rx(priv->ioaddr);
1920
1921         /* Release and free the Rx/Tx resources */
1922         free_dma_desc_resources(priv);
1923
1924         /* Disable the MAC Rx/Tx */
1925         stmmac_set_mac(priv->ioaddr, false);
1926
1927         netif_carrier_off(dev);
1928
1929 #ifdef CONFIG_DEBUG_FS
1930         stmmac_exit_fs(dev);
1931 #endif
1932
1933         stmmac_release_ptp(priv);
1934
1935         return 0;
1936 }
1937
1938 /**
1939  *  stmmac_xmit - Tx entry point of the driver
1940  *  @skb : the socket buffer
1941  *  @dev : device pointer
1942  *  Description : this is the tx entry point of the driver.
1943  *  It programs the chain or the ring and supports oversized frames
1944  *  and SG feature.
1945  */
1946 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1947 {
1948         struct stmmac_priv *priv = netdev_priv(dev);
1949         unsigned int nopaged_len = skb_headlen(skb);
1950         int i, csum_insertion = 0, is_jumbo = 0;
1951         int nfrags = skb_shinfo(skb)->nr_frags;
1952         unsigned int entry, first_entry;
1953         struct dma_desc *desc, *first;
1954         unsigned int enh_desc;
1955
1956         spin_lock(&priv->tx_lock);
1957
1958         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1959                 spin_unlock(&priv->tx_lock);
1960                 if (!netif_queue_stopped(dev)) {
1961                         netif_stop_queue(dev);
1962                         /* This is a hard error, log it. */
1963                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1964                 }
1965                 return NETDEV_TX_BUSY;
1966         }
1967
1968         if (priv->tx_path_in_lpi_mode)
1969                 stmmac_disable_eee_mode(priv);
1970
1971         entry = priv->cur_tx;
1972         first_entry = entry;
1973
1974         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1975
1976         if (likely(priv->extend_desc))
1977                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1978         else
1979                 desc = priv->dma_tx + entry;
1980
1981         first = desc;
1982
1983         priv->tx_skbuff[first_entry] = skb;
1984
1985         enh_desc = priv->plat->enh_desc;
1986         /* To program the descriptors according to the size of the frame */
1987         if (enh_desc)
1988                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1989
1990         if (unlikely(is_jumbo)) {
1991                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1992                 if (unlikely(entry < 0))
1993                         goto dma_map_err;
1994         }
1995
1996         for (i = 0; i < nfrags; i++) {
1997                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1998                 int len = skb_frag_size(frag);
1999                 bool last_segment = (i == (nfrags - 1));
2000
2001                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2002
2003                 if (likely(priv->extend_desc))
2004                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2005                 else
2006                         desc = priv->dma_tx + entry;
2007
2008                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2009                                               DMA_TO_DEVICE);
2010                 if (dma_mapping_error(priv->device, desc->des2))
2011                         goto dma_map_err; /* should reuse desc w/o issues */
2012
2013                 priv->tx_skbuff[entry] = NULL;
2014                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2015                 priv->tx_skbuff_dma[entry].map_as_page = true;
2016                 priv->tx_skbuff_dma[entry].len = len;
2017                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2018
2019                 /* Prepare the descriptor and set the own bit too */
2020                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2021                                                 priv->mode, 1, last_segment);
2022         }
2023
2024         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2025
2026         priv->cur_tx = entry;
2027
2028         if (netif_msg_pktdata(priv)) {
2029                 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2030                          __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2031                          entry, first, nfrags);
2032
2033                 if (priv->extend_desc)
2034                         stmmac_display_ring((void *)priv->dma_etx,
2035                                             DMA_TX_SIZE, 1);
2036                 else
2037                         stmmac_display_ring((void *)priv->dma_tx,
2038                                             DMA_TX_SIZE, 0);
2039
2040                 pr_debug(">>> frame to be transmitted: ");
2041                 print_pkt(skb->data, skb->len);
2042         }
2043
2044         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2045                 if (netif_msg_hw(priv))
2046                         pr_debug("%s: stop transmitted packets\n", __func__);
2047                 netif_stop_queue(dev);
2048         }
2049
2050         dev->stats.tx_bytes += skb->len;
2051
2052         /* According to the coalesce parameter the IC bit for the latest
2053          * segment is reset and the timer re-started to clean the tx status.
2054          * This approach takes care about the fragments: desc is the first
2055          * element in case of no SG.
2056          */
2057         priv->tx_count_frames += nfrags + 1;
2058         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2059                 mod_timer(&priv->txtimer,
2060                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2061         } else {
2062                 priv->tx_count_frames = 0;
2063                 priv->hw->desc->set_tx_ic(desc);
2064                 priv->xstats.tx_set_ic_bit++;
2065         }
2066
2067         if (!priv->hwts_tx_en)
2068                 skb_tx_timestamp(skb);
2069
2070         /* Ready to fill the first descriptor and set the OWN bit w/o any
2071          * problems because all the descriptors are actually ready to be
2072          * passed to the DMA engine.
2073          */
2074         if (likely(!is_jumbo)) {
2075                 bool last_segment = (nfrags == 0);
2076
2077                 first->des2 = dma_map_single(priv->device, skb->data,
2078                                              nopaged_len, DMA_TO_DEVICE);
2079                 if (dma_mapping_error(priv->device, first->des2))
2080                         goto dma_map_err;
2081
2082                 priv->tx_skbuff_dma[first_entry].buf = first->des2;
2083                 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2084                 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2085
2086                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2087                              priv->hwts_tx_en)) {
2088                         /* declare that device is doing timestamping */
2089                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2090                         priv->hw->desc->enable_tx_timestamp(first);
2091                 }
2092
2093                 /* Prepare the first descriptor setting the OWN bit too */
2094                 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2095                                                 csum_insertion, priv->mode, 1,
2096                                                 last_segment);
2097
2098                 /* The own bit must be the latest setting done when prepare the
2099                  * descriptor and then barrier is needed to make sure that
2100                  * all is coherent before granting the DMA engine.
2101                  */
2102                 smp_wmb();
2103         }
2104
2105         netdev_sent_queue(dev, skb->len);
2106         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2107
2108         spin_unlock(&priv->tx_lock);
2109         return NETDEV_TX_OK;
2110
2111 dma_map_err:
2112         spin_unlock(&priv->tx_lock);
2113         dev_err(priv->device, "Tx dma map failed\n");
2114         dev_kfree_skb(skb);
2115         priv->dev->stats.tx_dropped++;
2116         return NETDEV_TX_OK;
2117 }
2118
2119 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2120 {
2121         struct ethhdr *ehdr;
2122         u16 vlanid;
2123
2124         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2125             NETIF_F_HW_VLAN_CTAG_RX &&
2126             !__vlan_get_tag(skb, &vlanid)) {
2127                 /* pop the vlan tag */
2128                 ehdr = (struct ethhdr *)skb->data;
2129                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2130                 skb_pull(skb, VLAN_HLEN);
2131                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2132         }
2133 }
2134
2135
2136 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2137 {
2138         if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2139                 return 0;
2140
2141         return 1;
2142 }
2143
2144 /**
2145  * stmmac_rx_refill - refill used skb preallocated buffers
2146  * @priv: driver private structure
2147  * Description : this is to reallocate the skb for the reception process
2148  * that is based on zero-copy.
2149  */
2150 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2151 {
2152         int bfsize = priv->dma_buf_sz;
2153         unsigned int entry = priv->dirty_rx;
2154         int dirty = stmmac_rx_dirty(priv);
2155
2156         while (dirty-- > 0) {
2157                 struct dma_desc *p;
2158
2159                 if (priv->extend_desc)
2160                         p = (struct dma_desc *)(priv->dma_erx + entry);
2161                 else
2162                         p = priv->dma_rx + entry;
2163
2164                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2165                         struct sk_buff *skb;
2166
2167                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2168                         if (unlikely(!skb)) {
2169                                 /* so for a while no zero-copy! */
2170                                 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2171                                 if (unlikely(net_ratelimit()))
2172                                         dev_err(priv->device,
2173                                                 "fail to alloc skb entry %d\n",
2174                                                 entry);
2175                                 break;
2176                         }
2177
2178                         priv->rx_skbuff[entry] = skb;
2179                         priv->rx_skbuff_dma[entry] =
2180                             dma_map_single(priv->device, skb->data, bfsize,
2181                                            DMA_FROM_DEVICE);
2182                         if (dma_mapping_error(priv->device,
2183                                               priv->rx_skbuff_dma[entry])) {
2184                                 dev_err(priv->device, "Rx dma map failed\n");
2185                                 dev_kfree_skb(skb);
2186                                 break;
2187                         }
2188                         p->des2 = priv->rx_skbuff_dma[entry];
2189
2190                         priv->hw->mode->refill_desc3(priv, p);
2191
2192                         if (priv->rx_zeroc_thresh > 0)
2193                                 priv->rx_zeroc_thresh--;
2194
2195                         if (netif_msg_rx_status(priv))
2196                                 pr_debug("\trefill entry #%d\n", entry);
2197                 }
2198
2199                 wmb();
2200                 priv->hw->desc->set_rx_owner(p);
2201                 wmb();
2202
2203                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2204         }
2205         priv->dirty_rx = entry;
2206 }
2207
2208 /**
2209  * stmmac_rx - manage the receive process
2210  * @priv: driver private structure
2211  * @limit: napi bugget.
2212  * Description :  this the function called by the napi poll method.
2213  * It gets all the frames inside the ring.
2214  */
2215 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2216 {
2217         unsigned int entry = priv->cur_rx;
2218         unsigned int next_entry;
2219         unsigned int count = 0;
2220         int coe = priv->hw->rx_csum;
2221
2222         if (netif_msg_rx_status(priv)) {
2223                 pr_debug("%s: descriptor ring:\n", __func__);
2224                 if (priv->extend_desc)
2225                         stmmac_display_ring((void *)priv->dma_erx,
2226                                             DMA_RX_SIZE, 1);
2227                 else
2228                         stmmac_display_ring((void *)priv->dma_rx,
2229                                             DMA_RX_SIZE, 0);
2230         }
2231         while (count < limit) {
2232                 int status;
2233                 struct dma_desc *p;
2234
2235                 if (priv->extend_desc)
2236                         p = (struct dma_desc *)(priv->dma_erx + entry);
2237                 else
2238                         p = priv->dma_rx + entry;
2239
2240                 /* read the status of the incoming frame */
2241                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2242                                                    &priv->xstats, p);
2243                 /* check if managed by the DMA otherwise go ahead */
2244                 if (unlikely(status & dma_own))
2245                         break;
2246
2247                 count++;
2248
2249                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2250                 next_entry = priv->cur_rx;
2251
2252                 if (priv->extend_desc)
2253                         prefetch(priv->dma_erx + next_entry);
2254                 else
2255                         prefetch(priv->dma_rx + next_entry);
2256
2257                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2258                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2259                                                            &priv->xstats,
2260                                                            priv->dma_erx +
2261                                                            entry);
2262                 if (unlikely(status == discard_frame)) {
2263                         priv->dev->stats.rx_errors++;
2264                         if (priv->hwts_rx_en && !priv->extend_desc) {
2265                                 /* DESC2 & DESC3 will be overwitten by device
2266                                  * with timestamp value, hence reinitialize
2267                                  * them in stmmac_rx_refill() function so that
2268                                  * device can reuse it.
2269                                  */
2270                                 priv->rx_skbuff[entry] = NULL;
2271                                 dma_unmap_single(priv->device,
2272                                                  priv->rx_skbuff_dma[entry],
2273                                                  priv->dma_buf_sz,
2274                                                  DMA_FROM_DEVICE);
2275                         }
2276                 } else {
2277                         struct sk_buff *skb;
2278                         int frame_len;
2279
2280                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2281
2282                         /*  check if frame_len fits the preallocated memory */
2283                         if (frame_len > priv->dma_buf_sz) {
2284                                 priv->dev->stats.rx_length_errors++;
2285                                 break;
2286                         }
2287
2288                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2289                          * Type frames (LLC/LLC-SNAP)
2290                          */
2291                         if (unlikely(status != llc_snap))
2292                                 frame_len -= ETH_FCS_LEN;
2293
2294                         if (netif_msg_rx_status(priv)) {
2295                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2296                                          p, entry, p->des2);
2297                                 if (frame_len > ETH_FRAME_LEN)
2298                                         pr_debug("\tframe size %d, COE: %d\n",
2299                                                  frame_len, status);
2300                         }
2301
2302                         if (unlikely((frame_len < priv->rx_copybreak) ||
2303                                      stmmac_rx_threshold_count(priv))) {
2304                                 skb = netdev_alloc_skb_ip_align(priv->dev,
2305                                                                 frame_len);
2306                                 if (unlikely(!skb)) {
2307                                         if (net_ratelimit())
2308                                                 dev_warn(priv->device,
2309                                                          "packet dropped\n");
2310                                         priv->dev->stats.rx_dropped++;
2311                                         break;
2312                                 }
2313
2314                                 dma_sync_single_for_cpu(priv->device,
2315                                                         priv->rx_skbuff_dma
2316                                                         [entry], frame_len,
2317                                                         DMA_FROM_DEVICE);
2318                                 skb_copy_to_linear_data(skb,
2319                                                         priv->
2320                                                         rx_skbuff[entry]->data,
2321                                                         frame_len);
2322
2323                                 skb_put(skb, frame_len);
2324                                 dma_sync_single_for_device(priv->device,
2325                                                            priv->rx_skbuff_dma
2326                                                            [entry], frame_len,
2327                                                            DMA_FROM_DEVICE);
2328                         } else {
2329                                 skb = priv->rx_skbuff[entry];
2330                                 if (unlikely(!skb)) {
2331                                         pr_err("%s: Inconsistent Rx chain\n",
2332                                                priv->dev->name);
2333                                         priv->dev->stats.rx_dropped++;
2334                                         break;
2335                                 }
2336                                 prefetch(skb->data - NET_IP_ALIGN);
2337                                 priv->rx_skbuff[entry] = NULL;
2338                                 priv->rx_zeroc_thresh++;
2339
2340                                 skb_put(skb, frame_len);
2341                                 dma_unmap_single(priv->device,
2342                                                  priv->rx_skbuff_dma[entry],
2343                                                  priv->dma_buf_sz,
2344                                                  DMA_FROM_DEVICE);
2345                         }
2346
2347                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2348
2349                         if (netif_msg_pktdata(priv)) {
2350                                 pr_debug("frame received (%dbytes)", frame_len);
2351                                 print_pkt(skb->data, frame_len);
2352                         }
2353
2354                         stmmac_rx_vlan(priv->dev, skb);
2355
2356                         skb->protocol = eth_type_trans(skb, priv->dev);
2357
2358                         if (unlikely(!coe))
2359                                 skb_checksum_none_assert(skb);
2360                         else
2361                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2362
2363                         napi_gro_receive(&priv->napi, skb);
2364
2365                         priv->dev->stats.rx_packets++;
2366                         priv->dev->stats.rx_bytes += frame_len;
2367                 }
2368                 entry = next_entry;
2369         }
2370
2371         stmmac_rx_refill(priv);
2372
2373         priv->xstats.rx_pkt_n += count;
2374
2375         return count;
2376 }
2377
2378 /**
2379  *  stmmac_poll - stmmac poll method (NAPI)
2380  *  @napi : pointer to the napi structure.
2381  *  @budget : maximum number of packets that the current CPU can receive from
2382  *            all interfaces.
2383  *  Description :
2384  *  To look at the incoming frames and clear the tx resources.
2385  */
2386 static int stmmac_poll(struct napi_struct *napi, int budget)
2387 {
2388         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2389         int work_done = 0;
2390
2391         priv->xstats.napi_poll++;
2392         stmmac_tx_clean(priv);
2393
2394         work_done = stmmac_rx(priv, budget);
2395         if (work_done < budget) {
2396                 napi_complete(napi);
2397                 stmmac_enable_dma_irq(priv);
2398         }
2399         return work_done;
2400 }
2401
2402 /**
2403  *  stmmac_tx_timeout
2404  *  @dev : Pointer to net device structure
2405  *  Description: this function is called when a packet transmission fails to
2406  *   complete within a reasonable time. The driver will mark the error in the
2407  *   netdev structure and arrange for the device to be reset to a sane state
2408  *   in order to transmit a new packet.
2409  */
2410 static void stmmac_tx_timeout(struct net_device *dev)
2411 {
2412         struct stmmac_priv *priv = netdev_priv(dev);
2413
2414         /* Clear Tx resources and restart transmitting again */
2415         stmmac_tx_err(priv);
2416 }
2417
2418 /**
2419  *  stmmac_set_rx_mode - entry point for multicast addressing
2420  *  @dev : pointer to the device structure
2421  *  Description:
2422  *  This function is a driver entry point which gets called by the kernel
2423  *  whenever multicast addresses must be enabled/disabled.
2424  *  Return value:
2425  *  void.
2426  */
2427 static void stmmac_set_rx_mode(struct net_device *dev)
2428 {
2429         struct stmmac_priv *priv = netdev_priv(dev);
2430
2431         priv->hw->mac->set_filter(priv->hw, dev);
2432 }
2433
2434 /**
2435  *  stmmac_change_mtu - entry point to change MTU size for the device.
2436  *  @dev : device pointer.
2437  *  @new_mtu : the new MTU size for the device.
2438  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2439  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2440  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2441  *  Return value:
2442  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2443  *  file on failure.
2444  */
2445 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2446 {
2447         struct stmmac_priv *priv = netdev_priv(dev);
2448         int max_mtu;
2449
2450         if (netif_running(dev)) {
2451                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2452                 return -EBUSY;
2453         }
2454
2455         if (priv->plat->enh_desc)
2456                 max_mtu = JUMBO_LEN;
2457         else
2458                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2459
2460         if (priv->plat->maxmtu < max_mtu)
2461                 max_mtu = priv->plat->maxmtu;
2462
2463         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2464                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2465                 return -EINVAL;
2466         }
2467
2468         dev->mtu = new_mtu;
2469         netdev_update_features(dev);
2470
2471         return 0;
2472 }
2473
2474 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2475                                              netdev_features_t features)
2476 {
2477         struct stmmac_priv *priv = netdev_priv(dev);
2478
2479         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2480                 features &= ~NETIF_F_RXCSUM;
2481
2482         if (!priv->plat->tx_coe)
2483                 features &= ~NETIF_F_CSUM_MASK;
2484
2485         /* Some GMAC devices have a bugged Jumbo frame support that
2486          * needs to have the Tx COE disabled for oversized frames
2487          * (due to limited buffer sizes). In this case we disable
2488          * the TX csum insertionin the TDES and not use SF.
2489          */
2490         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2491                 features &= ~NETIF_F_CSUM_MASK;
2492
2493         return features;
2494 }
2495
2496 static int stmmac_set_features(struct net_device *netdev,
2497                                netdev_features_t features)
2498 {
2499         struct stmmac_priv *priv = netdev_priv(netdev);
2500
2501         /* Keep the COE Type in case of csum is supporting */
2502         if (features & NETIF_F_RXCSUM)
2503                 priv->hw->rx_csum = priv->plat->rx_coe;
2504         else
2505                 priv->hw->rx_csum = 0;
2506         /* No check needed because rx_coe has been set before and it will be
2507          * fixed in case of issue.
2508          */
2509         priv->hw->mac->rx_ipc(priv->hw);
2510
2511         return 0;
2512 }
2513
2514 /**
2515  *  stmmac_interrupt - main ISR
2516  *  @irq: interrupt number.
2517  *  @dev_id: to pass the net device pointer.
2518  *  Description: this is the main driver interrupt service routine.
2519  *  It can call:
2520  *  o DMA service routine (to manage incoming frame reception and transmission
2521  *    status)
2522  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2523  *    interrupts.
2524  */
2525 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2526 {
2527         struct net_device *dev = (struct net_device *)dev_id;
2528         struct stmmac_priv *priv = netdev_priv(dev);
2529
2530         if (priv->irq_wake)
2531                 pm_wakeup_event(priv->device, 0);
2532
2533         if (unlikely(!dev)) {
2534                 pr_err("%s: invalid dev pointer\n", __func__);
2535                 return IRQ_NONE;
2536         }
2537
2538         /* To handle GMAC own interrupts */
2539         if (priv->plat->has_gmac) {
2540                 int status = priv->hw->mac->host_irq_status(priv->hw,
2541                                                             &priv->xstats);
2542                 if (unlikely(status)) {
2543                         /* For LPI we need to save the tx status */
2544                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2545                                 priv->tx_path_in_lpi_mode = true;
2546                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2547                                 priv->tx_path_in_lpi_mode = false;
2548                 }
2549         }
2550
2551         /* To handle DMA interrupts */
2552         stmmac_dma_interrupt(priv);
2553
2554         return IRQ_HANDLED;
2555 }
2556
2557 #ifdef CONFIG_NET_POLL_CONTROLLER
2558 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2559  * to allow network I/O with interrupts disabled.
2560  */
2561 static void stmmac_poll_controller(struct net_device *dev)
2562 {
2563         disable_irq(dev->irq);
2564         stmmac_interrupt(dev->irq, dev);
2565         enable_irq(dev->irq);
2566 }
2567 #endif
2568
2569 /**
2570  *  stmmac_ioctl - Entry point for the Ioctl
2571  *  @dev: Device pointer.
2572  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2573  *  a proprietary structure used to pass information to the driver.
2574  *  @cmd: IOCTL command
2575  *  Description:
2576  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2577  */
2578 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2579 {
2580         struct stmmac_priv *priv = netdev_priv(dev);
2581         int ret = -EOPNOTSUPP;
2582
2583         if (!netif_running(dev))
2584                 return -EINVAL;
2585
2586         switch (cmd) {
2587         case SIOCGMIIPHY:
2588         case SIOCGMIIREG:
2589         case SIOCSMIIREG:
2590                 if (!priv->phydev)
2591                         return -EINVAL;
2592                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2593                 break;
2594         case SIOCSHWTSTAMP:
2595                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2596                 break;
2597         default:
2598                 break;
2599         }
2600
2601         return ret;
2602 }
2603
2604 #ifdef CONFIG_DEBUG_FS
2605 static struct dentry *stmmac_fs_dir;
2606
2607 static void sysfs_display_ring(void *head, int size, int extend_desc,
2608                                struct seq_file *seq)
2609 {
2610         int i;
2611         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2612         struct dma_desc *p = (struct dma_desc *)head;
2613
2614         for (i = 0; i < size; i++) {
2615                 u64 x;
2616                 if (extend_desc) {
2617                         x = *(u64 *) ep;
2618                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2619                                    i, (unsigned int)virt_to_phys(ep),
2620                                    (unsigned int)x, (unsigned int)(x >> 32),
2621                                    ep->basic.des2, ep->basic.des3);
2622                         ep++;
2623                 } else {
2624                         x = *(u64 *) p;
2625                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2626                                    i, (unsigned int)virt_to_phys(ep),
2627                                    (unsigned int)x, (unsigned int)(x >> 32),
2628                                    p->des2, p->des3);
2629                         p++;
2630                 }
2631                 seq_printf(seq, "\n");
2632         }
2633 }
2634
2635 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2636 {
2637         struct net_device *dev = seq->private;
2638         struct stmmac_priv *priv = netdev_priv(dev);
2639
2640         if (priv->extend_desc) {
2641                 seq_printf(seq, "Extended RX descriptor ring:\n");
2642                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2643                 seq_printf(seq, "Extended TX descriptor ring:\n");
2644                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2645         } else {
2646                 seq_printf(seq, "RX descriptor ring:\n");
2647                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2648                 seq_printf(seq, "TX descriptor ring:\n");
2649                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2656 {
2657         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2658 }
2659
2660 static const struct file_operations stmmac_rings_status_fops = {
2661         .owner = THIS_MODULE,
2662         .open = stmmac_sysfs_ring_open,
2663         .read = seq_read,
2664         .llseek = seq_lseek,
2665         .release = single_release,
2666 };
2667
2668 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2669 {
2670         struct net_device *dev = seq->private;
2671         struct stmmac_priv *priv = netdev_priv(dev);
2672
2673         if (!priv->hw_cap_support) {
2674                 seq_printf(seq, "DMA HW features not supported\n");
2675                 return 0;
2676         }
2677
2678         seq_printf(seq, "==============================\n");
2679         seq_printf(seq, "\tDMA HW features\n");
2680         seq_printf(seq, "==============================\n");
2681
2682         seq_printf(seq, "\t10/100 Mbps %s\n",
2683                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2684         seq_printf(seq, "\t1000 Mbps %s\n",
2685                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2686         seq_printf(seq, "\tHalf duple %s\n",
2687                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2688         seq_printf(seq, "\tHash Filter: %s\n",
2689                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2690         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2691                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2692         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2693                    (priv->dma_cap.pcs) ? "Y" : "N");
2694         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2695                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2696         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2697                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2698         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2699                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2700         seq_printf(seq, "\tRMON module: %s\n",
2701                    (priv->dma_cap.rmon) ? "Y" : "N");
2702         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2703                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2704         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2705                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2706         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2707                    (priv->dma_cap.eee) ? "Y" : "N");
2708         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2709         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2710                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2711         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2712                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2713         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2714                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2715         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2716                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2717         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2718                    priv->dma_cap.number_rx_channel);
2719         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2720                    priv->dma_cap.number_tx_channel);
2721         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2722                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2723
2724         return 0;
2725 }
2726
2727 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2728 {
2729         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2730 }
2731
2732 static const struct file_operations stmmac_dma_cap_fops = {
2733         .owner = THIS_MODULE,
2734         .open = stmmac_sysfs_dma_cap_open,
2735         .read = seq_read,
2736         .llseek = seq_lseek,
2737         .release = single_release,
2738 };
2739
2740 static int stmmac_init_fs(struct net_device *dev)
2741 {
2742         struct stmmac_priv *priv = netdev_priv(dev);
2743
2744         /* Create per netdev entries */
2745         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2746
2747         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2748                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2749                        STMMAC_RESOURCE_NAME, dev->name);
2750
2751                 return -ENOMEM;
2752         }
2753
2754         /* Entry to report DMA RX/TX rings */
2755         priv->dbgfs_rings_status =
2756                 debugfs_create_file("descriptors_status", S_IRUGO,
2757                                     priv->dbgfs_dir, dev,
2758                                     &stmmac_rings_status_fops);
2759
2760         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2761                 pr_info("ERROR creating stmmac ring debugfs file\n");
2762                 debugfs_remove_recursive(priv->dbgfs_dir);
2763
2764                 return -ENOMEM;
2765         }
2766
2767         /* Entry to report the DMA HW features */
2768         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2769                                             priv->dbgfs_dir,
2770                                             dev, &stmmac_dma_cap_fops);
2771
2772         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2773                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2774                 debugfs_remove_recursive(priv->dbgfs_dir);
2775
2776                 return -ENOMEM;
2777         }
2778
2779         return 0;
2780 }
2781
2782 static void stmmac_exit_fs(struct net_device *dev)
2783 {
2784         struct stmmac_priv *priv = netdev_priv(dev);
2785
2786         debugfs_remove_recursive(priv->dbgfs_dir);
2787 }
2788 #endif /* CONFIG_DEBUG_FS */
2789
2790 static const struct net_device_ops stmmac_netdev_ops = {
2791         .ndo_open = stmmac_open,
2792         .ndo_start_xmit = stmmac_xmit,
2793         .ndo_stop = stmmac_release,
2794         .ndo_change_mtu = stmmac_change_mtu,
2795         .ndo_fix_features = stmmac_fix_features,
2796         .ndo_set_features = stmmac_set_features,
2797         .ndo_set_rx_mode = stmmac_set_rx_mode,
2798         .ndo_tx_timeout = stmmac_tx_timeout,
2799         .ndo_do_ioctl = stmmac_ioctl,
2800 #ifdef CONFIG_NET_POLL_CONTROLLER
2801         .ndo_poll_controller = stmmac_poll_controller,
2802 #endif
2803         .ndo_set_mac_address = eth_mac_addr,
2804 };
2805
2806 /**
2807  *  stmmac_hw_init - Init the MAC device
2808  *  @priv: driver private structure
2809  *  Description: this function is to configure the MAC device according to
2810  *  some platform parameters or the HW capability register. It prepares the
2811  *  driver to use either ring or chain modes and to setup either enhanced or
2812  *  normal descriptors.
2813  */
2814 static int stmmac_hw_init(struct stmmac_priv *priv)
2815 {
2816         struct mac_device_info *mac;
2817
2818         /* Identify the MAC HW device */
2819         if (priv->plat->has_gmac) {
2820                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2821                 mac = dwmac1000_setup(priv->ioaddr,
2822                                       priv->plat->multicast_filter_bins,
2823                                       priv->plat->unicast_filter_entries);
2824         } else {
2825                 mac = dwmac100_setup(priv->ioaddr);
2826         }
2827         if (!mac)
2828                 return -ENOMEM;
2829
2830         priv->hw = mac;
2831
2832         /* Get and dump the chip ID */
2833         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2834
2835         /* To use the chained or ring mode */
2836         if (chain_mode) {
2837                 priv->hw->mode = &chain_mode_ops;
2838                 pr_info(" Chain mode enabled\n");
2839                 priv->mode = STMMAC_CHAIN_MODE;
2840         } else {
2841                 priv->hw->mode = &ring_mode_ops;
2842                 pr_info(" Ring mode enabled\n");
2843                 priv->mode = STMMAC_RING_MODE;
2844         }
2845
2846         /* Get the HW capability (new GMAC newer than 3.50a) */
2847         priv->hw_cap_support = stmmac_get_hw_features(priv);
2848         if (priv->hw_cap_support) {
2849                 pr_info(" DMA HW capability register supported");
2850
2851                 /* We can override some gmac/dma configuration fields: e.g.
2852                  * enh_desc, tx_coe (e.g. that are passed through the
2853                  * platform) with the values from the HW capability
2854                  * register (if supported).
2855                  */
2856                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2857                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2858
2859                 /* TXCOE doesn't work in thresh DMA mode */
2860                 if (priv->plat->force_thresh_dma_mode)
2861                         priv->plat->tx_coe = 0;
2862                 else
2863                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2864
2865                 if (priv->dma_cap.rx_coe_type2)
2866                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2867                 else if (priv->dma_cap.rx_coe_type1)
2868                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2869
2870         } else
2871                 pr_info(" No HW DMA feature register supported");
2872
2873         /* To use alternate (extended) or normal descriptor structures */
2874         stmmac_selec_desc_mode(priv);
2875
2876         if (priv->plat->rx_coe) {
2877                 priv->hw->rx_csum = priv->plat->rx_coe;
2878                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2879                         priv->plat->rx_coe);
2880         }
2881         if (priv->plat->tx_coe)
2882                 pr_info(" TX Checksum insertion supported\n");
2883
2884         if (priv->plat->pmt) {
2885                 pr_info(" Wake-Up On Lan supported\n");
2886                 device_set_wakeup_capable(priv->device, 1);
2887         }
2888
2889         return 0;
2890 }
2891
2892 /**
2893  * stmmac_dvr_probe
2894  * @device: device pointer
2895  * @plat_dat: platform data pointer
2896  * @res: stmmac resource pointer
2897  * Description: this is the main probe function used to
2898  * call the alloc_etherdev, allocate the priv structure.
2899  * Return:
2900  * returns 0 on success, otherwise errno.
2901  */
2902 int stmmac_dvr_probe(struct device *device,
2903                      struct plat_stmmacenet_data *plat_dat,
2904                      struct stmmac_resources *res)
2905 {
2906         int ret = 0;
2907         struct net_device *ndev = NULL;
2908         struct stmmac_priv *priv;
2909
2910         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2911         if (!ndev)
2912                 return -ENOMEM;
2913
2914         SET_NETDEV_DEV(ndev, device);
2915
2916         priv = netdev_priv(ndev);
2917         priv->device = device;
2918         priv->dev = ndev;
2919
2920         stmmac_set_ethtool_ops(ndev);
2921         priv->pause = pause;
2922         priv->plat = plat_dat;
2923         priv->ioaddr = res->addr;
2924         priv->dev->base_addr = (unsigned long)res->addr;
2925
2926         priv->dev->irq = res->irq;
2927         priv->wol_irq = res->wol_irq;
2928         priv->lpi_irq = res->lpi_irq;
2929
2930         if (res->mac)
2931                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2932
2933         dev_set_drvdata(device, priv->dev);
2934
2935         /* Verify driver arguments */
2936         stmmac_verify_args();
2937
2938         /* Override with kernel parameters if supplied XXX CRS XXX
2939          * this needs to have multiple instances
2940          */
2941         if ((phyaddr >= 0) && (phyaddr <= 31))
2942                 priv->plat->phy_addr = phyaddr;
2943
2944         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2945         if (IS_ERR(priv->stmmac_clk)) {
2946                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2947                          __func__);
2948                 /* If failed to obtain stmmac_clk and specific clk_csr value
2949                  * is NOT passed from the platform, probe fail.
2950                  */
2951                 if (!priv->plat->clk_csr) {
2952                         ret = PTR_ERR(priv->stmmac_clk);
2953                         goto error_clk_get;
2954                 } else {
2955                         priv->stmmac_clk = NULL;
2956                 }
2957         }
2958         clk_prepare_enable(priv->stmmac_clk);
2959
2960         priv->pclk = devm_clk_get(priv->device, "pclk");
2961         if (IS_ERR(priv->pclk)) {
2962                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2963                         ret = -EPROBE_DEFER;
2964                         goto error_pclk_get;
2965                 }
2966                 priv->pclk = NULL;
2967         }
2968         clk_prepare_enable(priv->pclk);
2969
2970         priv->stmmac_rst = devm_reset_control_get(priv->device,
2971                                                   STMMAC_RESOURCE_NAME);
2972         if (IS_ERR(priv->stmmac_rst)) {
2973                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2974                         ret = -EPROBE_DEFER;
2975                         goto error_hw_init;
2976                 }
2977                 dev_info(priv->device, "no reset control found\n");
2978                 priv->stmmac_rst = NULL;
2979         }
2980         if (priv->stmmac_rst)
2981                 reset_control_deassert(priv->stmmac_rst);
2982
2983         /* Init MAC and get the capabilities */
2984         ret = stmmac_hw_init(priv);
2985         if (ret)
2986                 goto error_hw_init;
2987
2988         ndev->netdev_ops = &stmmac_netdev_ops;
2989
2990         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2991                             NETIF_F_RXCSUM;
2992         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2993         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2994 #ifdef STMMAC_VLAN_TAG_USED
2995         /* Both mac100 and gmac support receive VLAN tag detection */
2996         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2997 #endif
2998         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2999
3000         if (flow_ctrl)
3001                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
3002
3003         /* Rx Watchdog is available in the COREs newer than the 3.40.
3004          * In some case, for example on bugged HW this feature
3005          * has to be disable and this can be done by passing the
3006          * riwt_off field from the platform.
3007          */
3008         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3009                 priv->use_riwt = 1;
3010                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3011         }
3012
3013         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3014
3015         spin_lock_init(&priv->lock);
3016         spin_lock_init(&priv->tx_lock);
3017
3018         ret = register_netdev(ndev);
3019         if (ret) {
3020                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3021                 goto error_netdev_register;
3022         }
3023
3024         /* If a specific clk_csr value is passed from the platform
3025          * this means that the CSR Clock Range selection cannot be
3026          * changed at run-time and it is fixed. Viceversa the driver'll try to
3027          * set the MDC clock dynamically according to the csr actual
3028          * clock input.
3029          */
3030         if (!priv->plat->clk_csr)
3031                 stmmac_clk_csr_set(priv);
3032         else
3033                 priv->clk_csr = priv->plat->clk_csr;
3034
3035         stmmac_check_pcs_mode(priv);
3036
3037         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3038             priv->pcs != STMMAC_PCS_RTBI) {
3039                 /* MDIO bus Registration */
3040                 ret = stmmac_mdio_register(ndev);
3041                 if (ret < 0) {
3042                         pr_debug("%s: MDIO bus (id: %d) registration failed",
3043                                  __func__, priv->plat->bus_id);
3044                         goto error_mdio_register;
3045                 }
3046         }
3047
3048         return 0;
3049
3050 error_mdio_register:
3051         unregister_netdev(ndev);
3052 error_netdev_register:
3053         netif_napi_del(&priv->napi);
3054 error_hw_init:
3055         clk_disable_unprepare(priv->pclk);
3056 error_pclk_get:
3057         clk_disable_unprepare(priv->stmmac_clk);
3058 error_clk_get:
3059         free_netdev(ndev);
3060
3061         return ret;
3062 }
3063 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3064
3065 /**
3066  * stmmac_dvr_remove
3067  * @ndev: net device pointer
3068  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3069  * changes the link status, releases the DMA descriptor rings.
3070  */
3071 int stmmac_dvr_remove(struct net_device *ndev)
3072 {
3073         struct stmmac_priv *priv = netdev_priv(ndev);
3074
3075         pr_info("%s:\n\tremoving driver", __func__);
3076
3077         priv->hw->dma->stop_rx(priv->ioaddr);
3078         priv->hw->dma->stop_tx(priv->ioaddr);
3079
3080         stmmac_set_mac(priv->ioaddr, false);
3081         netif_carrier_off(ndev);
3082         unregister_netdev(ndev);
3083         if (priv->stmmac_rst)
3084                 reset_control_assert(priv->stmmac_rst);
3085         clk_disable_unprepare(priv->pclk);
3086         clk_disable_unprepare(priv->stmmac_clk);
3087         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3088             priv->pcs != STMMAC_PCS_RTBI)
3089                 stmmac_mdio_unregister(ndev);
3090         free_netdev(ndev);
3091
3092         return 0;
3093 }
3094 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3095
3096 /**
3097  * stmmac_suspend - suspend callback
3098  * @ndev: net device pointer
3099  * Description: this is the function to suspend the device and it is called
3100  * by the platform driver to stop the network queue, release the resources,
3101  * program the PMT register (for WoL), clean and release driver resources.
3102  */
3103 int stmmac_suspend(struct net_device *ndev)
3104 {
3105         struct stmmac_priv *priv = netdev_priv(ndev);
3106         unsigned long flags;
3107
3108         if (!ndev || !netif_running(ndev))
3109                 return 0;
3110
3111         if (priv->phydev)
3112                 phy_stop(priv->phydev);
3113
3114         spin_lock_irqsave(&priv->lock, flags);
3115
3116         netif_device_detach(ndev);
3117         netif_stop_queue(ndev);
3118
3119         napi_disable(&priv->napi);
3120
3121         /* Stop TX/RX DMA */
3122         priv->hw->dma->stop_tx(priv->ioaddr);
3123         priv->hw->dma->stop_rx(priv->ioaddr);
3124
3125         /* Enable Power down mode by programming the PMT regs */
3126         if (device_may_wakeup(priv->device)) {
3127                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3128                 priv->irq_wake = 1;
3129         } else {
3130                 stmmac_set_mac(priv->ioaddr, false);
3131                 pinctrl_pm_select_sleep_state(priv->device);
3132                 /* Disable clock in case of PWM is off */
3133                 clk_disable(priv->pclk);
3134                 clk_disable(priv->stmmac_clk);
3135         }
3136         spin_unlock_irqrestore(&priv->lock, flags);
3137
3138         priv->oldlink = 0;
3139         priv->speed = 0;
3140         priv->oldduplex = -1;
3141         return 0;
3142 }
3143 EXPORT_SYMBOL_GPL(stmmac_suspend);
3144
3145 /**
3146  * stmmac_resume - resume callback
3147  * @ndev: net device pointer
3148  * Description: when resume this function is invoked to setup the DMA and CORE
3149  * in a usable state.
3150  */
3151 int stmmac_resume(struct net_device *ndev)
3152 {
3153         struct stmmac_priv *priv = netdev_priv(ndev);
3154         unsigned long flags;
3155
3156         if (!netif_running(ndev))
3157                 return 0;
3158
3159         spin_lock_irqsave(&priv->lock, flags);
3160
3161         /* Power Down bit, into the PM register, is cleared
3162          * automatically as soon as a magic packet or a Wake-up frame
3163          * is received. Anyway, it's better to manually clear
3164          * this bit because it can generate problems while resuming
3165          * from another devices (e.g. serial console).
3166          */
3167         if (device_may_wakeup(priv->device)) {
3168                 priv->hw->mac->pmt(priv->hw, 0);
3169                 priv->irq_wake = 0;
3170         } else {
3171                 pinctrl_pm_select_default_state(priv->device);
3172                 /* enable the clk prevously disabled */
3173                 clk_enable(priv->stmmac_clk);
3174                 clk_enable(priv->pclk);
3175                 /* reset the phy so that it's ready */
3176                 if (priv->mii)
3177                         stmmac_mdio_reset(priv->mii);
3178         }
3179
3180         netif_device_attach(ndev);
3181
3182         priv->cur_rx = 0;
3183         priv->dirty_rx = 0;
3184         priv->dirty_tx = 0;
3185         priv->cur_tx = 0;
3186         stmmac_clear_descriptors(priv);
3187
3188         stmmac_hw_setup(ndev, false);
3189         stmmac_init_tx_coalesce(priv);
3190         stmmac_set_rx_mode(ndev);
3191
3192         napi_enable(&priv->napi);
3193
3194         netif_start_queue(ndev);
3195
3196         spin_unlock_irqrestore(&priv->lock, flags);
3197
3198         if (priv->phydev)
3199                 phy_start(priv->phydev);
3200
3201         return 0;
3202 }
3203 EXPORT_SYMBOL_GPL(stmmac_resume);
3204
3205 #ifndef MODULE
3206 static int __init stmmac_cmdline_opt(char *str)
3207 {
3208         char *opt;
3209
3210         if (!str || !*str)
3211                 return -EINVAL;
3212         while ((opt = strsep(&str, ",")) != NULL) {
3213                 if (!strncmp(opt, "debug:", 6)) {
3214                         if (kstrtoint(opt + 6, 0, &debug))
3215                                 goto err;
3216                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3217                         if (kstrtoint(opt + 8, 0, &phyaddr))
3218                                 goto err;
3219                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3220                         if (kstrtoint(opt + 7, 0, &buf_sz))
3221                                 goto err;
3222                 } else if (!strncmp(opt, "tc:", 3)) {
3223                         if (kstrtoint(opt + 3, 0, &tc))
3224                                 goto err;
3225                 } else if (!strncmp(opt, "watchdog:", 9)) {
3226                         if (kstrtoint(opt + 9, 0, &watchdog))
3227                                 goto err;
3228                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3229                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3230                                 goto err;
3231                 } else if (!strncmp(opt, "pause:", 6)) {
3232                         if (kstrtoint(opt + 6, 0, &pause))
3233                                 goto err;
3234                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3235                         if (kstrtoint(opt + 10, 0, &eee_timer))
3236                                 goto err;
3237                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3238                         if (kstrtoint(opt + 11, 0, &chain_mode))
3239                                 goto err;
3240                 }
3241         }
3242         return 0;
3243
3244 err:
3245         pr_err("%s: ERROR broken module parameter conversion", __func__);
3246         return -EINVAL;
3247 }
3248
3249 __setup("stmmaceth=", stmmac_cmdline_opt);
3250 #endif /* MODULE */
3251
3252 static int __init stmmac_init(void)
3253 {
3254 #ifdef CONFIG_DEBUG_FS
3255         /* Create debugfs main directory if it doesn't exist yet */
3256         if (!stmmac_fs_dir) {
3257                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3258
3259                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3260                         pr_err("ERROR %s, debugfs create directory failed\n",
3261                                STMMAC_RESOURCE_NAME);
3262
3263                         return -ENOMEM;
3264                 }
3265         }
3266 #endif
3267
3268         return 0;
3269 }
3270
3271 static void __exit stmmac_exit(void)
3272 {
3273 #ifdef CONFIG_DEBUG_FS
3274         debugfs_remove_recursive(stmmac_fs_dir);
3275 #endif
3276 }
3277
3278 module_init(stmmac_init)
3279 module_exit(stmmac_exit)
3280
3281 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3282 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3283 MODULE_LICENSE("GPL");