drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <linux/udp.h>
  40 #include <net/pkt_cls.h>
  41 #include "stmmac_ptp.h"
  42 #include "stmmac.h"
  43 #include <linux/reset.h>
  44 #include <linux/of_mdio.h>
  45 #include "dwmac1000.h"
  46 #include "dwxgmac2.h"
  47 #include "hwif.h"
  48
  49 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  50 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  51
  52 /* Module parameters */
  53 #define TX_TIMEO        5000
  54 static int watchdog = TX_TIMEO;
  55 module_param(watchdog, int, 0644);
  56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  57
  58 static int debug = -1;
  59 module_param(debug, int, 0644);
  60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  61
  62 static int phyaddr = -1;
  63 module_param(phyaddr, int, 0444);
  64 MODULE_PARM_DESC(phyaddr, "Physical device address");
  65
  66 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  67 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  68
  69 static int flow_ctrl = FLOW_AUTO;
  70 module_param(flow_ctrl, int, 0644);
  71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  72
  73 static int pause = PAUSE_TIME;
  74 module_param(pause, int, 0644);
  75 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  76
  77 #define TC_DEFAULT 64
  78 static int tc = TC_DEFAULT;
  79 module_param(tc, int, 0644);
  80 MODULE_PARM_DESC(tc, "DMA threshold control value");
  81
  82 #define DEFAULT_BUFSIZE 1536
  83 static int buf_sz = DEFAULT_BUFSIZE;
  84 module_param(buf_sz, int, 0644);
  85 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  86
  87 #define STMMAC_RX_COPYBREAK     256
  88
  89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  90                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  91                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  92
  93 #define STMMAC_DEFAULT_LPI_TIMER        1000
  94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  95 module_param(eee_timer, int, 0644);
  96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  98
  99 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 100  * but allow user to force to use the chain instead of the ring
 101  */
 102 static unsigned int chain_mode;
 103 module_param(chain_mode, int, 0444);
 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 105
 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 107
 108 #ifdef CONFIG_DEBUG_FS
 109 static const struct net_device_ops stmmac_netdev_ops;
 110 static void stmmac_init_fs(struct net_device *dev);
 111 static void stmmac_exit_fs(struct net_device *dev);
 112 #endif
 113
 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 115
 116 /**
 117  * stmmac_verify_args - verify the driver parameters.
 118  * Description: it checks the driver parameters and set a default in case of
 119  * errors.
 120  */
 121 static void stmmac_verify_args(void)
 122 {
 123         if (unlikely(watchdog < 0))
 124                 watchdog = TX_TIMEO;
 125         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 126                 buf_sz = DEFAULT_BUFSIZE;
 127         if (unlikely(flow_ctrl > 1))
 128                 flow_ctrl = FLOW_AUTO;
 129         else if (likely(flow_ctrl < 0))
 130                 flow_ctrl = FLOW_OFF;
 131         if (unlikely((pause < 0) || (pause > 0xffff)))
 132                 pause = PAUSE_TIME;
 133         if (eee_timer < 0)
 134                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 135 }
 136
 137 /**
 138  * stmmac_disable_all_queues - Disable all queues
 139  * @priv: driver private structure
 140  */
 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 142 {
 143         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 144         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 145         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 146         u32 queue;
 147
 148         for (queue = 0; queue < maxq; queue++) {
 149                 struct stmmac_channel *ch = &priv->channel[queue];
 150
 151                 if (queue < rx_queues_cnt)
 152                         napi_disable(&ch->rx_napi);
 153                 if (queue < tx_queues_cnt)
 154                         napi_disable(&ch->tx_napi);
 155         }
 156 }
 157
 158 /**
 159  * stmmac_enable_all_queues - Enable all queues
 160  * @priv: driver private structure
 161  */
 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 163 {
 164         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 165         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 166         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 167         u32 queue;
 168
 169         for (queue = 0; queue < maxq; queue++) {
 170                 struct stmmac_channel *ch = &priv->channel[queue];
 171
 172                 if (queue < rx_queues_cnt)
 173                         napi_enable(&ch->rx_napi);
 174                 if (queue < tx_queues_cnt)
 175                         napi_enable(&ch->tx_napi);
 176         }
 177 }
 178
 179 /**
 180  * stmmac_stop_all_queues - Stop all queues
 181  * @priv: driver private structure
 182  */
 183 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 184 {
 185         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 186         u32 queue;
 187
 188         for (queue = 0; queue < tx_queues_cnt; queue++)
 189                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 190 }
 191
 192 /**
 193  * stmmac_start_all_queues - Start all queues
 194  * @priv: driver private structure
 195  */
 196 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 197 {
 198         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 199         u32 queue;
 200
 201         for (queue = 0; queue < tx_queues_cnt; queue++)
 202                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 203 }
 204
 205 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 206 {
 207         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 208             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 209                 queue_work(priv->wq, &priv->service_task);
 210 }
 211
 212 static void stmmac_global_err(struct stmmac_priv *priv)
 213 {
 214         netif_carrier_off(priv->dev);
 215         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 216         stmmac_service_event_schedule(priv);
 217 }
 218
 219 /**
 220  * stmmac_clk_csr_set - dynamically set the MDC clock
 221  * @priv: driver private structure
 222  * Description: this is to dynamically set the MDC clock according to the csr
 223  * clock input.
 224  * Note:
 225  *      If a specific clk_csr value is passed from the platform
 226  *      this means that the CSR Clock Range selection cannot be
 227  *      changed at run-time and it is fixed (as reported in the driver
 228  *      documentation). Viceversa the driver will try to set the MDC
 229  *      clock dynamically according to the actual clock input.
 230  */
 231 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 232 {
 233         u32 clk_rate;
 234
 235         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 236
 237         /* Platform provided default clk_csr would be assumed valid
 238          * for all other cases except for the below mentioned ones.
 239          * For values higher than the IEEE 802.3 specified frequency
 240          * we can not estimate the proper divider as it is not known
 241          * the frequency of clk_csr_i. So we do not change the default
 242          * divider.
 243          */
 244         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 245                 if (clk_rate < CSR_F_35M)
 246                         priv->clk_csr = STMMAC_CSR_20_35M;
 247                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 248                         priv->clk_csr = STMMAC_CSR_35_60M;
 249                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 250                         priv->clk_csr = STMMAC_CSR_60_100M;
 251                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 252                         priv->clk_csr = STMMAC_CSR_100_150M;
 253                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 254                         priv->clk_csr = STMMAC_CSR_150_250M;
 255                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 256                         priv->clk_csr = STMMAC_CSR_250_300M;
 257         }
 258
 259         if (priv->plat->has_sun8i) {
 260                 if (clk_rate > 160000000)
 261                         priv->clk_csr = 0x03;
 262                 else if (clk_rate > 80000000)
 263                         priv->clk_csr = 0x02;
 264                 else if (clk_rate > 40000000)
 265                         priv->clk_csr = 0x01;
 266                 else
 267                         priv->clk_csr = 0;
 268         }
 269
 270         if (priv->plat->has_xgmac) {
 271                 if (clk_rate > 400000000)
 272                         priv->clk_csr = 0x5;
 273                 else if (clk_rate > 350000000)
 274                         priv->clk_csr = 0x4;
 275                 else if (clk_rate > 300000000)
 276                         priv->clk_csr = 0x3;
 277                 else if (clk_rate > 250000000)
 278                         priv->clk_csr = 0x2;
 279                 else if (clk_rate > 150000000)
 280                         priv->clk_csr = 0x1;
 281                 else
 282                         priv->clk_csr = 0x0;
 283         }
 284 }
 285
 286 static void print_pkt(unsigned char *buf, int len)
 287 {
 288         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 289         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 290 }
 291
 292 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 293 {
 294         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 295         u32 avail;
 296
 297         if (tx_q->dirty_tx > tx_q->cur_tx)
 298                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 299         else
 300                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 301
 302         return avail;
 303 }
 304
 305 /**
 306  * stmmac_rx_dirty - Get RX queue dirty
 307  * @priv: driver private structure
 308  * @queue: RX queue index
 309  */
 310 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 311 {
 312         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 313         u32 dirty;
 314
 315         if (rx_q->dirty_rx <= rx_q->cur_rx)
 316                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 317         else
 318                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 319
 320         return dirty;
 321 }
 322
 323 /**
 324  * stmmac_enable_eee_mode - check and enter in LPI mode
 325  * @priv: driver private structure
 326  * Description: this function is to verify and enter in LPI mode in case of
 327  * EEE.
 328  */
 329 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 330 {
 331         u32 tx_cnt = priv->plat->tx_queues_to_use;
 332         u32 queue;
 333
 334         /* check if all TX queues have the work finished */
 335         for (queue = 0; queue < tx_cnt; queue++) {
 336                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 337
 338                 if (tx_q->dirty_tx != tx_q->cur_tx)
 339                         return; /* still unfinished work */
 340         }
 341
 342         /* Check and enter in LPI mode */
 343         if (!priv->tx_path_in_lpi_mode)
 344                 stmmac_set_eee_mode(priv, priv->hw,
 345                                 priv->plat->en_tx_lpi_clockgating);
 346 }
 347
 348 /**
 349  * stmmac_disable_eee_mode - disable and exit from LPI mode
 350  * @priv: driver private structure
 351  * Description: this function is to exit and disable EEE in case of
 352  * LPI state is true. This is called by the xmit.
 353  */
 354 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 355 {
 356         stmmac_reset_eee_mode(priv, priv->hw);
 357         del_timer_sync(&priv->eee_ctrl_timer);
 358         priv->tx_path_in_lpi_mode = false;
 359 }
 360
 361 /**
 362  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 363  * @arg : data hook
 364  * Description:
 365  *  if there is no data transfer and if we are not in LPI state,
 366  *  then MAC Transmitter can be moved to LPI state.
 367  */
 368 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 369 {
 370         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 371
 372         stmmac_enable_eee_mode(priv);
 373         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 374 }
 375
 376 /**
 377  * stmmac_eee_init - init EEE
 378  * @priv: driver private structure
 379  * Description:
 380  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 381  *  can also manage EEE, this function enable the LPI state and start related
 382  *  timer.
 383  */
 384 bool stmmac_eee_init(struct stmmac_priv *priv)
 385 {
 386         int tx_lpi_timer = priv->tx_lpi_timer;
 387
 388         /* Using PCS we cannot dial with the phy registers at this stage
 389          * so we do not support extra feature like EEE.
 390          */
 391         if (priv->hw->pcs == STMMAC_PCS_TBI ||
 392             priv->hw->pcs == STMMAC_PCS_RTBI)
 393                 return false;
 394
 395         /* Check if MAC core supports the EEE feature. */
 396         if (!priv->dma_cap.eee)
 397                 return false;
 398
 399         mutex_lock(&priv->lock);
 400
 401         /* Check if it needs to be deactivated */
 402         if (!priv->eee_active) {
 403                 if (priv->eee_enabled) {
 404                         netdev_dbg(priv->dev, "disable EEE\n");
 405                         del_timer_sync(&priv->eee_ctrl_timer);
 406                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 407                 }
 408                 mutex_unlock(&priv->lock);
 409                 return false;
 410         }
 411
 412         if (priv->eee_active && !priv->eee_enabled) {
 413                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 414                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 415                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 416                                      tx_lpi_timer);
 417         }
 418
 419         mutex_unlock(&priv->lock);
 420         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 421         return true;
 422 }
 423
 424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 425  * @priv: driver private structure
 426  * @p : descriptor pointer
 427  * @skb : the socket buffer
 428  * Description :
 429  * This function will read timestamp from the descriptor & pass it to stack.
 430  * and also perform some sanity checks.
 431  */
 432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 433                                    struct dma_desc *p, struct sk_buff *skb)
 434 {
 435         struct skb_shared_hwtstamps shhwtstamp;
 436         bool found = false;
 437         u64 ns = 0;
 438
 439         if (!priv->hwts_tx_en)
 440                 return;
 441
 442         /* exit if skb doesn't support hw tstamp */
 443         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 444                 return;
 445
 446         /* check tx tstamp status */
 447         if (stmmac_get_tx_timestamp_status(priv, p)) {
 448                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 449                 found = true;
 450         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 451                 found = true;
 452         }
 453
 454         if (found) {
 455                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 456                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 457
 458                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 459                 /* pass tstamp to stack */
 460                 skb_tstamp_tx(skb, &shhwtstamp);
 461         }
 462 }
 463
 464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 465  * @priv: driver private structure
 466  * @p : descriptor pointer
 467  * @np : next descriptor pointer
 468  * @skb : the socket buffer
 469  * Description :
 470  * This function will read received packet's timestamp from the descriptor
 471  * and pass it to stack. It also perform some sanity checks.
 472  */
 473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 474                                    struct dma_desc *np, struct sk_buff *skb)
 475 {
 476         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 477         struct dma_desc *desc = p;
 478         u64 ns = 0;
 479
 480         if (!priv->hwts_rx_en)
 481                 return;
 482         /* For GMAC4, the valid timestamp is from CTX next desc. */
 483         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 484                 desc = np;
 485
 486         /* Check if timestamp is available */
 487         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 488                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 489                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 490                 shhwtstamp = skb_hwtstamps(skb);
 491                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 492                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 493         } else  {
 494                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 495         }
 496 }
 497
 498 /**
 499  *  stmmac_hwtstamp_set - control hardware timestamping.
 500  *  @dev: device pointer.
 501  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 502  *  a proprietary structure used to pass information to the driver.
 503  *  Description:
 504  *  This function configures the MAC to enable/disable both outgoing(TX)
 505  *  and incoming(RX) packets time stamping based on user input.
 506  *  Return Value:
 507  *  0 on success and an appropriate -ve integer on failure.
 508  */
 509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 510 {
 511         struct stmmac_priv *priv = netdev_priv(dev);
 512         struct hwtstamp_config config;
 513         struct timespec64 now;
 514         u64 temp = 0;
 515         u32 ptp_v2 = 0;
 516         u32 tstamp_all = 0;
 517         u32 ptp_over_ipv4_udp = 0;
 518         u32 ptp_over_ipv6_udp = 0;
 519         u32 ptp_over_ethernet = 0;
 520         u32 snap_type_sel = 0;
 521         u32 ts_master_en = 0;
 522         u32 ts_event_en = 0;
 523         u32 sec_inc = 0;
 524         u32 value = 0;
 525         bool xmac;
 526
 527         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 528
 529         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 530                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 531                 priv->hwts_tx_en = 0;
 532                 priv->hwts_rx_en = 0;
 533
 534                 return -EOPNOTSUPP;
 535         }
 536
 537         if (copy_from_user(&config, ifr->ifr_data,
 538                            sizeof(config)))
 539                 return -EFAULT;
 540
 541         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 542                    __func__, config.flags, config.tx_type, config.rx_filter);
 543
 544         /* reserved for future extensions */
 545         if (config.flags)
 546                 return -EINVAL;
 547
 548         if (config.tx_type != HWTSTAMP_TX_OFF &&
 549             config.tx_type != HWTSTAMP_TX_ON)
 550                 return -ERANGE;
 551
 552         if (priv->adv_ts) {
 553                 switch (config.rx_filter) {
 554                 case HWTSTAMP_FILTER_NONE:
 555                         /* time stamp no incoming packet at all */
 556                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 557                         break;
 558
 559                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 560                         /* PTP v1, UDP, any kind of event packet */
 561                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 562                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 563                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 564                          * This leaves Delay_Req timestamps out.
 565                          * Enable all events *and* general purpose message
 566                          * timestamping
 567                          */
 568                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 569                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 570                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 571                         break;
 572
 573                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 574                         /* PTP v1, UDP, Sync packet */
 575                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 576                         /* take time stamp for SYNC messages only */
 577                         ts_event_en = PTP_TCR_TSEVNTENA;
 578
 579                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 580                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 581                         break;
 582
 583                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 584                         /* PTP v1, UDP, Delay_req packet */
 585                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 586                         /* take time stamp for Delay_Req messages only */
 587                         ts_master_en = PTP_TCR_TSMSTRENA;
 588                         ts_event_en = PTP_TCR_TSEVNTENA;
 589
 590                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 591                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 592                         break;
 593
 594                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 595                         /* PTP v2, UDP, any kind of event packet */
 596                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 597                         ptp_v2 = PTP_TCR_TSVER2ENA;
 598                         /* take time stamp for all event messages */
 599                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 600
 601                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 602                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 603                         break;
 604
 605                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 606                         /* PTP v2, UDP, Sync packet */
 607                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 608                         ptp_v2 = PTP_TCR_TSVER2ENA;
 609                         /* take time stamp for SYNC messages only */
 610                         ts_event_en = PTP_TCR_TSEVNTENA;
 611
 612                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 613                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 614                         break;
 615
 616                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 617                         /* PTP v2, UDP, Delay_req packet */
 618                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 619                         ptp_v2 = PTP_TCR_TSVER2ENA;
 620                         /* take time stamp for Delay_Req messages only */
 621                         ts_master_en = PTP_TCR_TSMSTRENA;
 622                         ts_event_en = PTP_TCR_TSEVNTENA;
 623
 624                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 625                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 626                         break;
 627
 628                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 629                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 630                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 631                         ptp_v2 = PTP_TCR_TSVER2ENA;
 632                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 633                         if (priv->synopsys_id != DWMAC_CORE_5_10)
 634                                 ts_event_en = PTP_TCR_TSEVNTENA;
 635                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 636                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 637                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 638                         break;
 639
 640                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 641                         /* PTP v2/802.AS1, any layer, Sync packet */
 642                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 643                         ptp_v2 = PTP_TCR_TSVER2ENA;
 644                         /* take time stamp for SYNC messages only */
 645                         ts_event_en = PTP_TCR_TSEVNTENA;
 646
 647                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 648                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 649                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 650                         break;
 651
 652                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 653                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 654                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 655                         ptp_v2 = PTP_TCR_TSVER2ENA;
 656                         /* take time stamp for Delay_Req messages only */
 657                         ts_master_en = PTP_TCR_TSMSTRENA;
 658                         ts_event_en = PTP_TCR_TSEVNTENA;
 659
 660                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 661                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 662                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 663                         break;
 664
 665                 case HWTSTAMP_FILTER_NTP_ALL:
 666                 case HWTSTAMP_FILTER_ALL:
 667                         /* time stamp any incoming packet */
 668                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 669                         tstamp_all = PTP_TCR_TSENALL;
 670                         break;
 671
 672                 default:
 673                         return -ERANGE;
 674                 }
 675         } else {
 676                 switch (config.rx_filter) {
 677                 case HWTSTAMP_FILTER_NONE:
 678                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 679                         break;
 680                 default:
 681                         /* PTP v1, UDP, any kind of event packet */
 682                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 683                         break;
 684                 }
 685         }
 686         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 687         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 688
 689         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 690                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 691         else {
 692                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 693                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 694                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 695                          ts_master_en | snap_type_sel);
 696                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 697
 698                 /* program Sub Second Increment reg */
 699                 stmmac_config_sub_second_increment(priv,
 700                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 701                                 xmac, &sec_inc);
 702                 temp = div_u64(1000000000ULL, sec_inc);
 703
 704                 /* Store sub second increment and flags for later use */
 705                 priv->sub_second_inc = sec_inc;
 706                 priv->systime_flags = value;
 707
 708                 /* calculate default added value:
 709                  * formula is :
 710                  * addend = (2^32)/freq_div_ratio;
 711                  * where, freq_div_ratio = 1e9ns/sec_inc
 712                  */
 713                 temp = (u64)(temp << 32);
 714                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 715                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 716
 717                 /* initialize system time */
 718                 ktime_get_real_ts64(&now);
 719
 720                 /* lower 32 bits of tv_sec are safe until y2106 */
 721                 stmmac_init_systime(priv, priv->ptpaddr,
 722                                 (u32)now.tv_sec, now.tv_nsec);
 723         }
 724
 725         memcpy(&priv->tstamp_config, &config, sizeof(config));
 726
 727         return copy_to_user(ifr->ifr_data, &config,
 728                             sizeof(config)) ? -EFAULT : 0;
 729 }
 730
 731 /**
 732  *  stmmac_hwtstamp_get - read hardware timestamping.
 733  *  @dev: device pointer.
 734  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 735  *  a proprietary structure used to pass information to the driver.
 736  *  Description:
 737  *  This function obtain the current hardware timestamping settings
 738     as requested.
 739  */
 740 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 741 {
 742         struct stmmac_priv *priv = netdev_priv(dev);
 743         struct hwtstamp_config *config = &priv->tstamp_config;
 744
 745         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 746                 return -EOPNOTSUPP;
 747
 748         return copy_to_user(ifr->ifr_data, config,
 749                             sizeof(*config)) ? -EFAULT : 0;
 750 }
 751
 752 /**
 753  * stmmac_init_ptp - init PTP
 754  * @priv: driver private structure
 755  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 756  * This is done by looking at the HW cap. register.
 757  * This function also registers the ptp driver.
 758  */
 759 static int stmmac_init_ptp(struct stmmac_priv *priv)
 760 {
 761         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 762
 763         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 764                 return -EOPNOTSUPP;
 765
 766         priv->adv_ts = 0;
 767         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 768         if (xmac && priv->dma_cap.atime_stamp)
 769                 priv->adv_ts = 1;
 770         /* Dwmac 3.x core with extend_desc can support adv_ts */
 771         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 772                 priv->adv_ts = 1;
 773
 774         if (priv->dma_cap.time_stamp)
 775                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 776
 777         if (priv->adv_ts)
 778                 netdev_info(priv->dev,
 779                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 780
 781         priv->hwts_tx_en = 0;
 782         priv->hwts_rx_en = 0;
 783
 784         stmmac_ptp_register(priv);
 785
 786         return 0;
 787 }
 788
 789 static void stmmac_release_ptp(struct stmmac_priv *priv)
 790 {
 791         if (priv->plat->clk_ptp_ref)
 792                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 793         stmmac_ptp_unregister(priv);
 794 }
 795
 796 /**
 797  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 798  *  @priv: driver private structure
 799  *  Description: It is used for configuring the flow control in all queues
 800  */
 801 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 802 {
 803         u32 tx_cnt = priv->plat->tx_queues_to_use;
 804
 805         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 806                         priv->pause, tx_cnt);
 807 }
 808
 809 static void stmmac_validate(struct phylink_config *config,
 810                             unsigned long *supported,
 811                             struct phylink_link_state *state)
 812 {
 813         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 814         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 815         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 816         int tx_cnt = priv->plat->tx_queues_to_use;
 817         int max_speed = priv->plat->max_speed;
 818
 819         phylink_set(mac_supported, 10baseT_Half);
 820         phylink_set(mac_supported, 10baseT_Full);
 821         phylink_set(mac_supported, 100baseT_Half);
 822         phylink_set(mac_supported, 100baseT_Full);
 823         phylink_set(mac_supported, 1000baseT_Half);
 824         phylink_set(mac_supported, 1000baseT_Full);
 825         phylink_set(mac_supported, 1000baseKX_Full);
 826
 827         phylink_set(mac_supported, Autoneg);
 828         phylink_set(mac_supported, Pause);
 829         phylink_set(mac_supported, Asym_Pause);
 830         phylink_set_port_modes(mac_supported);
 831
 832         /* Cut down 1G if asked to */
 833         if ((max_speed > 0) && (max_speed < 1000)) {
 834                 phylink_set(mask, 1000baseT_Full);
 835                 phylink_set(mask, 1000baseX_Full);
 836         } else if (priv->plat->has_xgmac) {
 837                 if (!max_speed || (max_speed >= 2500)) {
 838                         phylink_set(mac_supported, 2500baseT_Full);
 839                         phylink_set(mac_supported, 2500baseX_Full);
 840                 }
 841                 if (!max_speed || (max_speed >= 5000)) {
 842                         phylink_set(mac_supported, 5000baseT_Full);
 843                 }
 844                 if (!max_speed || (max_speed >= 10000)) {
 845                         phylink_set(mac_supported, 10000baseSR_Full);
 846                         phylink_set(mac_supported, 10000baseLR_Full);
 847                         phylink_set(mac_supported, 10000baseER_Full);
 848                         phylink_set(mac_supported, 10000baseLRM_Full);
 849                         phylink_set(mac_supported, 10000baseT_Full);
 850                         phylink_set(mac_supported, 10000baseKX4_Full);
 851                         phylink_set(mac_supported, 10000baseKR_Full);
 852                 }
 853                 if (!max_speed || (max_speed >= 25000)) {
 854                         phylink_set(mac_supported, 25000baseCR_Full);
 855                         phylink_set(mac_supported, 25000baseKR_Full);
 856                         phylink_set(mac_supported, 25000baseSR_Full);
 857                 }
 858                 if (!max_speed || (max_speed >= 40000)) {
 859                         phylink_set(mac_supported, 40000baseKR4_Full);
 860                         phylink_set(mac_supported, 40000baseCR4_Full);
 861                         phylink_set(mac_supported, 40000baseSR4_Full);
 862                         phylink_set(mac_supported, 40000baseLR4_Full);
 863                 }
 864                 if (!max_speed || (max_speed >= 50000)) {
 865                         phylink_set(mac_supported, 50000baseCR2_Full);
 866                         phylink_set(mac_supported, 50000baseKR2_Full);
 867                         phylink_set(mac_supported, 50000baseSR2_Full);
 868                         phylink_set(mac_supported, 50000baseKR_Full);
 869                         phylink_set(mac_supported, 50000baseSR_Full);
 870                         phylink_set(mac_supported, 50000baseCR_Full);
 871                         phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
 872                         phylink_set(mac_supported, 50000baseDR_Full);
 873                 }
 874                 if (!max_speed || (max_speed >= 100000)) {
 875                         phylink_set(mac_supported, 100000baseKR4_Full);
 876                         phylink_set(mac_supported, 100000baseSR4_Full);
 877                         phylink_set(mac_supported, 100000baseCR4_Full);
 878                         phylink_set(mac_supported, 100000baseLR4_ER4_Full);
 879                         phylink_set(mac_supported, 100000baseKR2_Full);
 880                         phylink_set(mac_supported, 100000baseSR2_Full);
 881                         phylink_set(mac_supported, 100000baseCR2_Full);
 882                         phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
 883                         phylink_set(mac_supported, 100000baseDR2_Full);
 884                 }
 885         }
 886
 887         /* Half-Duplex can only work with single queue */
 888         if (tx_cnt > 1) {
 889                 phylink_set(mask, 10baseT_Half);
 890                 phylink_set(mask, 100baseT_Half);
 891                 phylink_set(mask, 1000baseT_Half);
 892         }
 893
 894         linkmode_and(supported, supported, mac_supported);
 895         linkmode_andnot(supported, supported, mask);
 896
 897         linkmode_and(state->advertising, state->advertising, mac_supported);
 898         linkmode_andnot(state->advertising, state->advertising, mask);
 899
 900         /* If PCS is supported, check which modes it supports. */
 901         stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state);
 902 }
 903
 904 static void stmmac_mac_pcs_get_state(struct phylink_config *config,
 905                                      struct phylink_link_state *state)
 906 {
 907         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 908
 909         state->link = 0;
 910         stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state);
 911 }
 912
 913 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 914                               const struct phylink_link_state *state)
 915 {
 916         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 917
 918         stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state);
 919 }
 920
 921 static void stmmac_mac_an_restart(struct phylink_config *config)
 922 {
 923         /* Not Supported */
 924 }
 925
 926 static void stmmac_mac_link_down(struct phylink_config *config,
 927                                  unsigned int mode, phy_interface_t interface)
 928 {
 929         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 930
 931         stmmac_mac_set(priv, priv->ioaddr, false);
 932         priv->eee_active = false;
 933         stmmac_eee_init(priv);
 934         stmmac_set_eee_pls(priv, priv->hw, false);
 935 }
 936
 937 static void stmmac_mac_link_up(struct phylink_config *config,
 938                                struct phy_device *phy,
 939                                unsigned int mode, phy_interface_t interface,
 940                                int speed, int duplex,
 941                                bool tx_pause, bool rx_pause)
 942 {
 943         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 944         u32 ctrl;
 945
 946         stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface);
 947
 948         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 949         ctrl &= ~priv->hw->link.speed_mask;
 950
 951         if (interface == PHY_INTERFACE_MODE_USXGMII) {
 952                 switch (speed) {
 953                 case SPEED_10000:
 954                         ctrl |= priv->hw->link.xgmii.speed10000;
 955                         break;
 956                 case SPEED_5000:
 957                         ctrl |= priv->hw->link.xgmii.speed5000;
 958                         break;
 959                 case SPEED_2500:
 960                         ctrl |= priv->hw->link.xgmii.speed2500;
 961                         break;
 962                 default:
 963                         return;
 964                 }
 965         } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
 966                 switch (speed) {
 967                 case SPEED_100000:
 968                         ctrl |= priv->hw->link.xlgmii.speed100000;
 969                         break;
 970                 case SPEED_50000:
 971                         ctrl |= priv->hw->link.xlgmii.speed50000;
 972                         break;
 973                 case SPEED_40000:
 974                         ctrl |= priv->hw->link.xlgmii.speed40000;
 975                         break;
 976                 case SPEED_25000:
 977                         ctrl |= priv->hw->link.xlgmii.speed25000;
 978                         break;
 979                 case SPEED_10000:
 980                         ctrl |= priv->hw->link.xgmii.speed10000;
 981                         break;
 982                 case SPEED_2500:
 983                         ctrl |= priv->hw->link.speed2500;
 984                         break;
 985                 case SPEED_1000:
 986                         ctrl |= priv->hw->link.speed1000;
 987                         break;
 988                 default:
 989                         return;
 990                 }
 991         } else {
 992                 switch (speed) {
 993                 case SPEED_2500:
 994                         ctrl |= priv->hw->link.speed2500;
 995                         break;
 996                 case SPEED_1000:
 997                         ctrl |= priv->hw->link.speed1000;
 998                         break;
 999                 case SPEED_100:
1000                         ctrl |= priv->hw->link.speed100;
1001                         break;
1002                 case SPEED_10:
1003                         ctrl |= priv->hw->link.speed10;
1004                         break;
1005                 default:
1006                         return;
1007                 }
1008         }
1009
1010         priv->speed = speed;
1011
1012         if (priv->plat->fix_mac_speed)
1013                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1014
1015         if (!duplex)
1016                 ctrl &= ~priv->hw->link.duplex;
1017         else
1018                 ctrl |= priv->hw->link.duplex;
1019
1020         /* Flow Control operation */
1021         if (tx_pause && rx_pause)
1022                 stmmac_mac_flow_ctrl(priv, duplex);
1023
1024         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1025
1026         stmmac_mac_set(priv, priv->ioaddr, true);
1027         if (phy && priv->dma_cap.eee) {
1028                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1029                 priv->eee_enabled = stmmac_eee_init(priv);
1030                 stmmac_set_eee_pls(priv, priv->hw, true);
1031         }
1032 }
1033
1034 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1035         .validate = stmmac_validate,
1036         .mac_pcs_get_state = stmmac_mac_pcs_get_state,
1037         .mac_config = stmmac_mac_config,
1038         .mac_an_restart = stmmac_mac_an_restart,
1039         .mac_link_down = stmmac_mac_link_down,
1040         .mac_link_up = stmmac_mac_link_up,
1041 };
1042
1043 /**
1044  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1045  * @priv: driver private structure
1046  * Description: this is to verify if the HW supports the PCS.
1047  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1048  * configured for the TBI, RTBI, or SGMII PHY interface.
1049  */
1050 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1051 {
1052         int interface = priv->plat->interface;
1053
1054         if (priv->dma_cap.pcs) {
1055                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1056                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1057                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1058                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1059                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1060                         priv->hw->pcs = STMMAC_PCS_RGMII;
1061                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1062                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1063                         priv->hw->pcs = STMMAC_PCS_SGMII;
1064                 }
1065         }
1066 }
1067
1068 /**
1069  * stmmac_init_phy - PHY initialization
1070  * @dev: net device structure
1071  * Description: it initializes the driver's PHY state, and attaches the PHY
1072  * to the mac driver.
1073  *  Return value:
1074  *  0 on success
1075  */
1076 static int stmmac_init_phy(struct net_device *dev)
1077 {
1078         struct stmmac_priv *priv = netdev_priv(dev);
1079         struct device_node *node;
1080         int ret;
1081
1082         node = priv->plat->phylink_node;
1083
1084         if (node)
1085                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1086
1087         /* Some DT bindings do not set-up the PHY handle. Let's try to
1088          * manually parse it
1089          */
1090         if (!node || ret) {
1091                 int addr = priv->plat->phy_addr;
1092                 struct phy_device *phydev;
1093
1094                 phydev = mdiobus_get_phy(priv->mii, addr);
1095                 if (!phydev) {
1096                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1097                         return -ENODEV;
1098                 }
1099
1100                 ret = phylink_connect_phy(priv->phylink, phydev);
1101         }
1102
1103         return ret;
1104 }
1105
1106 static int stmmac_phy_setup(struct stmmac_priv *priv)
1107 {
1108         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1109         int mode = priv->plat->phy_interface;
1110         struct phylink *phylink;
1111
1112         priv->phylink_config.dev = &priv->dev->dev;
1113         priv->phylink_config.type = PHYLINK_NETDEV;
1114         priv->phylink_config.pcs_poll = true;
1115
1116         if (!fwnode)
1117                 fwnode = dev_fwnode(priv->device);
1118
1119         phylink = phylink_create(&priv->phylink_config, fwnode,
1120                                  mode, &stmmac_phylink_mac_ops);
1121         if (IS_ERR(phylink))
1122                 return PTR_ERR(phylink);
1123
1124         priv->phylink = phylink;
1125         return 0;
1126 }
1127
1128 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1129 {
1130         u32 rx_cnt = priv->plat->rx_queues_to_use;
1131         void *head_rx;
1132         u32 queue;
1133
1134         /* Display RX rings */
1135         for (queue = 0; queue < rx_cnt; queue++) {
1136                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1137
1138                 pr_info("\tRX Queue %u rings\n", queue);
1139
1140                 if (priv->extend_desc)
1141                         head_rx = (void *)rx_q->dma_erx;
1142                 else
1143                         head_rx = (void *)rx_q->dma_rx;
1144
1145                 /* Display RX ring */
1146                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1147         }
1148 }
1149
1150 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1151 {
1152         u32 tx_cnt = priv->plat->tx_queues_to_use;
1153         void *head_tx;
1154         u32 queue;
1155
1156         /* Display TX rings */
1157         for (queue = 0; queue < tx_cnt; queue++) {
1158                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1159
1160                 pr_info("\tTX Queue %d rings\n", queue);
1161
1162                 if (priv->extend_desc)
1163                         head_tx = (void *)tx_q->dma_etx;
1164                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1165                         head_tx = (void *)tx_q->dma_entx;
1166                 else
1167                         head_tx = (void *)tx_q->dma_tx;
1168
1169                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1170         }
1171 }
1172
1173 static void stmmac_display_rings(struct stmmac_priv *priv)
1174 {
1175         /* Display RX ring */
1176         stmmac_display_rx_rings(priv);
1177
1178         /* Display TX ring */
1179         stmmac_display_tx_rings(priv);
1180 }
1181
1182 static int stmmac_set_bfsize(int mtu, int bufsize)
1183 {
1184         int ret = bufsize;
1185
1186         if (mtu >= BUF_SIZE_8KiB)
1187                 ret = BUF_SIZE_16KiB;
1188         else if (mtu >= BUF_SIZE_4KiB)
1189                 ret = BUF_SIZE_8KiB;
1190         else if (mtu >= BUF_SIZE_2KiB)
1191                 ret = BUF_SIZE_4KiB;
1192         else if (mtu > DEFAULT_BUFSIZE)
1193                 ret = BUF_SIZE_2KiB;
1194         else
1195                 ret = DEFAULT_BUFSIZE;
1196
1197         return ret;
1198 }
1199
1200 /**
1201  * stmmac_clear_rx_descriptors - clear RX descriptors
1202  * @priv: driver private structure
1203  * @queue: RX queue index
1204  * Description: this function is called to clear the RX descriptors
1205  * in case of both basic and extended descriptors are used.
1206  */
1207 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1208 {
1209         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1210         int i;
1211
1212         /* Clear the RX descriptors */
1213         for (i = 0; i < DMA_RX_SIZE; i++)
1214                 if (priv->extend_desc)
1215                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1216                                         priv->use_riwt, priv->mode,
1217                                         (i == DMA_RX_SIZE - 1),
1218                                         priv->dma_buf_sz);
1219                 else
1220                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1221                                         priv->use_riwt, priv->mode,
1222                                         (i == DMA_RX_SIZE - 1),
1223                                         priv->dma_buf_sz);
1224 }
1225
1226 /**
1227  * stmmac_clear_tx_descriptors - clear tx descriptors
1228  * @priv: driver private structure
1229  * @queue: TX queue index.
1230  * Description: this function is called to clear the TX descriptors
1231  * in case of both basic and extended descriptors are used.
1232  */
1233 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1234 {
1235         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1236         int i;
1237
1238         /* Clear the TX descriptors */
1239         for (i = 0; i < DMA_TX_SIZE; i++) {
1240                 int last = (i == (DMA_TX_SIZE - 1));
1241                 struct dma_desc *p;
1242
1243                 if (priv->extend_desc)
1244                         p = &tx_q->dma_etx[i].basic;
1245                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1246                         p = &tx_q->dma_entx[i].basic;
1247                 else
1248                         p = &tx_q->dma_tx[i];
1249
1250                 stmmac_init_tx_desc(priv, p, priv->mode, last);
1251         }
1252 }
1253
1254 /**
1255  * stmmac_clear_descriptors - clear descriptors
1256  * @priv: driver private structure
1257  * Description: this function is called to clear the TX and RX descriptors
1258  * in case of both basic and extended descriptors are used.
1259  */
1260 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1261 {
1262         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1263         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1264         u32 queue;
1265
1266         /* Clear the RX descriptors */
1267         for (queue = 0; queue < rx_queue_cnt; queue++)
1268                 stmmac_clear_rx_descriptors(priv, queue);
1269
1270         /* Clear the TX descriptors */
1271         for (queue = 0; queue < tx_queue_cnt; queue++)
1272                 stmmac_clear_tx_descriptors(priv, queue);
1273 }
1274
1275 /**
1276  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1277  * @priv: driver private structure
1278  * @p: descriptor pointer
1279  * @i: descriptor index
1280  * @flags: gfp flag
1281  * @queue: RX queue index
1282  * Description: this function is called to allocate a receive buffer, perform
1283  * the DMA mapping and init the descriptor.
1284  */
1285 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1286                                   int i, gfp_t flags, u32 queue)
1287 {
1288         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1289         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1290
1291         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1292         if (!buf->page)
1293                 return -ENOMEM;
1294
1295         if (priv->sph) {
1296                 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1297                 if (!buf->sec_page)
1298                         return -ENOMEM;
1299
1300                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1301                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
1302         } else {
1303                 buf->sec_page = NULL;
1304         }
1305
1306         buf->addr = page_pool_get_dma_addr(buf->page);
1307         stmmac_set_desc_addr(priv, p, buf->addr);
1308         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1309                 stmmac_init_desc3(priv, p);
1310
1311         return 0;
1312 }
1313
1314 /**
1315  * stmmac_free_rx_buffer - free RX dma buffers
1316  * @priv: private structure
1317  * @queue: RX queue index
1318  * @i: buffer index.
1319  */
1320 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1321 {
1322         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1323         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1324
1325         if (buf->page)
1326                 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1327         buf->page = NULL;
1328
1329         if (buf->sec_page)
1330                 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1331         buf->sec_page = NULL;
1332 }
1333
1334 /**
1335  * stmmac_free_tx_buffer - free RX dma buffers
1336  * @priv: private structure
1337  * @queue: RX queue index
1338  * @i: buffer index.
1339  */
1340 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1341 {
1342         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1343
1344         if (tx_q->tx_skbuff_dma[i].buf) {
1345                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1346                         dma_unmap_page(priv->device,
1347                                        tx_q->tx_skbuff_dma[i].buf,
1348                                        tx_q->tx_skbuff_dma[i].len,
1349                                        DMA_TO_DEVICE);
1350                 else
1351                         dma_unmap_single(priv->device,
1352                                          tx_q->tx_skbuff_dma[i].buf,
1353                                          tx_q->tx_skbuff_dma[i].len,
1354                                          DMA_TO_DEVICE);
1355         }
1356
1357         if (tx_q->tx_skbuff[i]) {
1358                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1359                 tx_q->tx_skbuff[i] = NULL;
1360                 tx_q->tx_skbuff_dma[i].buf = 0;
1361                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1362         }
1363 }
1364
1365 /**
1366  * init_dma_rx_desc_rings - init the RX descriptor rings
1367  * @dev: net device structure
1368  * @flags: gfp flag.
1369  * Description: this function initializes the DMA RX descriptors
1370  * and allocates the socket buffers. It supports the chained and ring
1371  * modes.
1372  */
1373 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1374 {
1375         struct stmmac_priv *priv = netdev_priv(dev);
1376         u32 rx_count = priv->plat->rx_queues_to_use;
1377         int ret = -ENOMEM;
1378         int queue;
1379         int i;
1380
1381         /* RX INITIALIZATION */
1382         netif_dbg(priv, probe, priv->dev,
1383                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1384
1385         for (queue = 0; queue < rx_count; queue++) {
1386                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1387
1388                 netif_dbg(priv, probe, priv->dev,
1389                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1390                           (u32)rx_q->dma_rx_phy);
1391
1392                 stmmac_clear_rx_descriptors(priv, queue);
1393
1394                 for (i = 0; i < DMA_RX_SIZE; i++) {
1395                         struct dma_desc *p;
1396
1397                         if (priv->extend_desc)
1398                                 p = &((rx_q->dma_erx + i)->basic);
1399                         else
1400                                 p = rx_q->dma_rx + i;
1401
1402                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1403                                                      queue);
1404                         if (ret)
1405                                 goto err_init_rx_buffers;
1406                 }
1407
1408                 rx_q->cur_rx = 0;
1409                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1410
1411                 /* Setup the chained descriptor addresses */
1412                 if (priv->mode == STMMAC_CHAIN_MODE) {
1413                         if (priv->extend_desc)
1414                                 stmmac_mode_init(priv, rx_q->dma_erx,
1415                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1416                         else
1417                                 stmmac_mode_init(priv, rx_q->dma_rx,
1418                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1419                 }
1420         }
1421
1422         return 0;
1423
1424 err_init_rx_buffers:
1425         while (queue >= 0) {
1426                 while (--i >= 0)
1427                         stmmac_free_rx_buffer(priv, queue, i);
1428
1429                 if (queue == 0)
1430                         break;
1431
1432                 i = DMA_RX_SIZE;
1433                 queue--;
1434         }
1435
1436         return ret;
1437 }
1438
1439 /**
1440  * init_dma_tx_desc_rings - init the TX descriptor rings
1441  * @dev: net device structure.
1442  * Description: this function initializes the DMA TX descriptors
1443  * and allocates the socket buffers. It supports the chained and ring
1444  * modes.
1445  */
1446 static int init_dma_tx_desc_rings(struct net_device *dev)
1447 {
1448         struct stmmac_priv *priv = netdev_priv(dev);
1449         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1450         u32 queue;
1451         int i;
1452
1453         for (queue = 0; queue < tx_queue_cnt; queue++) {
1454                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1455
1456                 netif_dbg(priv, probe, priv->dev,
1457                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1458                          (u32)tx_q->dma_tx_phy);
1459
1460                 /* Setup the chained descriptor addresses */
1461                 if (priv->mode == STMMAC_CHAIN_MODE) {
1462                         if (priv->extend_desc)
1463                                 stmmac_mode_init(priv, tx_q->dma_etx,
1464                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1465                         else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1466                                 stmmac_mode_init(priv, tx_q->dma_tx,
1467                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1468                 }
1469
1470                 for (i = 0; i < DMA_TX_SIZE; i++) {
1471                         struct dma_desc *p;
1472                         if (priv->extend_desc)
1473                                 p = &((tx_q->dma_etx + i)->basic);
1474                         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1475                                 p = &((tx_q->dma_entx + i)->basic);
1476                         else
1477                                 p = tx_q->dma_tx + i;
1478
1479                         stmmac_clear_desc(priv, p);
1480
1481                         tx_q->tx_skbuff_dma[i].buf = 0;
1482                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1483                         tx_q->tx_skbuff_dma[i].len = 0;
1484                         tx_q->tx_skbuff_dma[i].last_segment = false;
1485                         tx_q->tx_skbuff[i] = NULL;
1486                 }
1487
1488                 tx_q->dirty_tx = 0;
1489                 tx_q->cur_tx = 0;
1490                 tx_q->mss = 0;
1491
1492                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1493         }
1494
1495         return 0;
1496 }
1497
1498 /**
1499  * init_dma_desc_rings - init the RX/TX descriptor rings
1500  * @dev: net device structure
1501  * @flags: gfp flag.
1502  * Description: this function initializes the DMA RX/TX descriptors
1503  * and allocates the socket buffers. It supports the chained and ring
1504  * modes.
1505  */
1506 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1507 {
1508         struct stmmac_priv *priv = netdev_priv(dev);
1509         int ret;
1510
1511         ret = init_dma_rx_desc_rings(dev, flags);
1512         if (ret)
1513                 return ret;
1514
1515         ret = init_dma_tx_desc_rings(dev);
1516
1517         stmmac_clear_descriptors(priv);
1518
1519         if (netif_msg_hw(priv))
1520                 stmmac_display_rings(priv);
1521
1522         return ret;
1523 }
1524
1525 /**
1526  * dma_free_rx_skbufs - free RX dma buffers
1527  * @priv: private structure
1528  * @queue: RX queue index
1529  */
1530 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1531 {
1532         int i;
1533
1534         for (i = 0; i < DMA_RX_SIZE; i++)
1535                 stmmac_free_rx_buffer(priv, queue, i);
1536 }
1537
1538 /**
1539  * dma_free_tx_skbufs - free TX dma buffers
1540  * @priv: private structure
1541  * @queue: TX queue index
1542  */
1543 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1544 {
1545         int i;
1546
1547         for (i = 0; i < DMA_TX_SIZE; i++)
1548                 stmmac_free_tx_buffer(priv, queue, i);
1549 }
1550
1551 /**
1552  * free_dma_rx_desc_resources - free RX dma desc resources
1553  * @priv: private structure
1554  */
1555 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1556 {
1557         u32 rx_count = priv->plat->rx_queues_to_use;
1558         u32 queue;
1559
1560         /* Free RX queue resources */
1561         for (queue = 0; queue < rx_count; queue++) {
1562                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1563
1564                 /* Release the DMA RX socket buffers */
1565                 dma_free_rx_skbufs(priv, queue);
1566
1567                 /* Free DMA regions of consistent memory previously allocated */
1568                 if (!priv->extend_desc)
1569                         dma_free_coherent(priv->device,
1570                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1571                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1572                 else
1573                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1574                                           sizeof(struct dma_extended_desc),
1575                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1576
1577                 kfree(rx_q->buf_pool);
1578                 if (rx_q->page_pool)
1579                         page_pool_destroy(rx_q->page_pool);
1580         }
1581 }
1582
1583 /**
1584  * free_dma_tx_desc_resources - free TX dma desc resources
1585  * @priv: private structure
1586  */
1587 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1588 {
1589         u32 tx_count = priv->plat->tx_queues_to_use;
1590         u32 queue;
1591
1592         /* Free TX queue resources */
1593         for (queue = 0; queue < tx_count; queue++) {
1594                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1595                 size_t size;
1596                 void *addr;
1597
1598                 /* Release the DMA TX socket buffers */
1599                 dma_free_tx_skbufs(priv, queue);
1600
1601                 if (priv->extend_desc) {
1602                         size = sizeof(struct dma_extended_desc);
1603                         addr = tx_q->dma_etx;
1604                 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1605                         size = sizeof(struct dma_edesc);
1606                         addr = tx_q->dma_entx;
1607                 } else {
1608                         size = sizeof(struct dma_desc);
1609                         addr = tx_q->dma_tx;
1610                 }
1611
1612                 size *= DMA_TX_SIZE;
1613
1614                 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1615
1616                 kfree(tx_q->tx_skbuff_dma);
1617                 kfree(tx_q->tx_skbuff);
1618         }
1619 }
1620
1621 /**
1622  * alloc_dma_rx_desc_resources - alloc RX resources.
1623  * @priv: private structure
1624  * Description: according to which descriptor can be used (extend or basic)
1625  * this function allocates the resources for TX and RX paths. In case of
1626  * reception, for example, it pre-allocated the RX socket buffer in order to
1627  * allow zero-copy mechanism.
1628  */
1629 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1630 {
1631         u32 rx_count = priv->plat->rx_queues_to_use;
1632         int ret = -ENOMEM;
1633         u32 queue;
1634
1635         /* RX queues buffers and DMA */
1636         for (queue = 0; queue < rx_count; queue++) {
1637                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1638                 struct page_pool_params pp_params = { 0 };
1639                 unsigned int num_pages;
1640
1641                 rx_q->queue_index = queue;
1642                 rx_q->priv_data = priv;
1643
1644                 pp_params.flags = PP_FLAG_DMA_MAP;
1645                 pp_params.pool_size = DMA_RX_SIZE;
1646                 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1647                 pp_params.order = ilog2(num_pages);
1648                 pp_params.nid = dev_to_node(priv->device);
1649                 pp_params.dev = priv->device;
1650                 pp_params.dma_dir = DMA_FROM_DEVICE;
1651
1652                 rx_q->page_pool = page_pool_create(&pp_params);
1653                 if (IS_ERR(rx_q->page_pool)) {
1654                         ret = PTR_ERR(rx_q->page_pool);
1655                         rx_q->page_pool = NULL;
1656                         goto err_dma;
1657                 }
1658
1659                 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1660                                          GFP_KERNEL);
1661                 if (!rx_q->buf_pool)
1662                         goto err_dma;
1663
1664                 if (priv->extend_desc) {
1665                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1666                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1667                                                            &rx_q->dma_rx_phy,
1668                                                            GFP_KERNEL);
1669                         if (!rx_q->dma_erx)
1670                                 goto err_dma;
1671
1672                 } else {
1673                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1674                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1675                                                           &rx_q->dma_rx_phy,
1676                                                           GFP_KERNEL);
1677                         if (!rx_q->dma_rx)
1678                                 goto err_dma;
1679                 }
1680         }
1681
1682         return 0;
1683
1684 err_dma:
1685         free_dma_rx_desc_resources(priv);
1686
1687         return ret;
1688 }
1689
1690 /**
1691  * alloc_dma_tx_desc_resources - alloc TX resources.
1692  * @priv: private structure
1693  * Description: according to which descriptor can be used (extend or basic)
1694  * this function allocates the resources for TX and RX paths. In case of
1695  * reception, for example, it pre-allocated the RX socket buffer in order to
1696  * allow zero-copy mechanism.
1697  */
1698 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1699 {
1700         u32 tx_count = priv->plat->tx_queues_to_use;
1701         int ret = -ENOMEM;
1702         u32 queue;
1703
1704         /* TX queues buffers and DMA */
1705         for (queue = 0; queue < tx_count; queue++) {
1706                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1707                 size_t size;
1708                 void *addr;
1709
1710                 tx_q->queue_index = queue;
1711                 tx_q->priv_data = priv;
1712
1713                 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1714                                               sizeof(*tx_q->tx_skbuff_dma),
1715                                               GFP_KERNEL);
1716                 if (!tx_q->tx_skbuff_dma)
1717                         goto err_dma;
1718
1719                 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1720                                           sizeof(struct sk_buff *),
1721                                           GFP_KERNEL);
1722                 if (!tx_q->tx_skbuff)
1723                         goto err_dma;
1724
1725                 if (priv->extend_desc)
1726                         size = sizeof(struct dma_extended_desc);
1727                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1728                         size = sizeof(struct dma_edesc);
1729                 else
1730                         size = sizeof(struct dma_desc);
1731
1732                 size *= DMA_TX_SIZE;
1733
1734                 addr = dma_alloc_coherent(priv->device, size,
1735                                           &tx_q->dma_tx_phy, GFP_KERNEL);
1736                 if (!addr)
1737                         goto err_dma;
1738
1739                 if (priv->extend_desc)
1740                         tx_q->dma_etx = addr;
1741                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1742                         tx_q->dma_entx = addr;
1743                 else
1744                         tx_q->dma_tx = addr;
1745         }
1746
1747         return 0;
1748
1749 err_dma:
1750         free_dma_tx_desc_resources(priv);
1751         return ret;
1752 }
1753
1754 /**
1755  * alloc_dma_desc_resources - alloc TX/RX resources.
1756  * @priv: private structure
1757  * Description: according to which descriptor can be used (extend or basic)
1758  * this function allocates the resources for TX and RX paths. In case of
1759  * reception, for example, it pre-allocated the RX socket buffer in order to
1760  * allow zero-copy mechanism.
1761  */
1762 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1763 {
1764         /* RX Allocation */
1765         int ret = alloc_dma_rx_desc_resources(priv);
1766
1767         if (ret)
1768                 return ret;
1769
1770         ret = alloc_dma_tx_desc_resources(priv);
1771
1772         return ret;
1773 }
1774
1775 /**
1776  * free_dma_desc_resources - free dma desc resources
1777  * @priv: private structure
1778  */
1779 static void free_dma_desc_resources(struct stmmac_priv *priv)
1780 {
1781         /* Release the DMA RX socket buffers */
1782         free_dma_rx_desc_resources(priv);
1783
1784         /* Release the DMA TX socket buffers */
1785         free_dma_tx_desc_resources(priv);
1786 }
1787
1788 /**
1789  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1790  *  @priv: driver private structure
1791  *  Description: It is used for enabling the rx queues in the MAC
1792  */
1793 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1794 {
1795         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1796         int queue;
1797         u8 mode;
1798
1799         for (queue = 0; queue < rx_queues_count; queue++) {
1800                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1801                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1802         }
1803 }
1804
1805 /**
1806  * stmmac_start_rx_dma - start RX DMA channel
1807  * @priv: driver private structure
1808  * @chan: RX channel index
1809  * Description:
1810  * This starts a RX DMA channel
1811  */
1812 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1813 {
1814         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1815         stmmac_start_rx(priv, priv->ioaddr, chan);
1816 }
1817
1818 /**
1819  * stmmac_start_tx_dma - start TX DMA channel
1820  * @priv: driver private structure
1821  * @chan: TX channel index
1822  * Description:
1823  * This starts a TX DMA channel
1824  */
1825 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1826 {
1827         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1828         stmmac_start_tx(priv, priv->ioaddr, chan);
1829 }
1830
1831 /**
1832  * stmmac_stop_rx_dma - stop RX DMA channel
1833  * @priv: driver private structure
1834  * @chan: RX channel index
1835  * Description:
1836  * This stops a RX DMA channel
1837  */
1838 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1839 {
1840         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1841         stmmac_stop_rx(priv, priv->ioaddr, chan);
1842 }
1843
1844 /**
1845  * stmmac_stop_tx_dma - stop TX DMA channel
1846  * @priv: driver private structure
1847  * @chan: TX channel index
1848  * Description:
1849  * This stops a TX DMA channel
1850  */
1851 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1852 {
1853         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1854         stmmac_stop_tx(priv, priv->ioaddr, chan);
1855 }
1856
1857 /**
1858  * stmmac_start_all_dma - start all RX and TX DMA channels
1859  * @priv: driver private structure
1860  * Description:
1861  * This starts all the RX and TX DMA channels
1862  */
1863 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1864 {
1865         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1866         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1867         u32 chan = 0;
1868
1869         for (chan = 0; chan < rx_channels_count; chan++)
1870                 stmmac_start_rx_dma(priv, chan);
1871
1872         for (chan = 0; chan < tx_channels_count; chan++)
1873                 stmmac_start_tx_dma(priv, chan);
1874 }
1875
1876 /**
1877  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1878  * @priv: driver private structure
1879  * Description:
1880  * This stops the RX and TX DMA channels
1881  */
1882 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1883 {
1884         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1885         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1886         u32 chan = 0;
1887
1888         for (chan = 0; chan < rx_channels_count; chan++)
1889                 stmmac_stop_rx_dma(priv, chan);
1890
1891         for (chan = 0; chan < tx_channels_count; chan++)
1892                 stmmac_stop_tx_dma(priv, chan);
1893 }
1894
1895 /**
1896  *  stmmac_dma_operation_mode - HW DMA operation mode
1897  *  @priv: driver private structure
1898  *  Description: it is used for configuring the DMA operation mode register in
1899  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1900  */
1901 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1902 {
1903         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1904         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1905         int rxfifosz = priv->plat->rx_fifo_size;
1906         int txfifosz = priv->plat->tx_fifo_size;
1907         u32 txmode = 0;
1908         u32 rxmode = 0;
1909         u32 chan = 0;
1910         u8 qmode = 0;
1911
1912         if (rxfifosz == 0)
1913                 rxfifosz = priv->dma_cap.rx_fifo_size;
1914         if (txfifosz == 0)
1915                 txfifosz = priv->dma_cap.tx_fifo_size;
1916
1917         /* Adjust for real per queue fifo size */
1918         rxfifosz /= rx_channels_count;
1919         txfifosz /= tx_channels_count;
1920
1921         if (priv->plat->force_thresh_dma_mode) {
1922                 txmode = tc;
1923                 rxmode = tc;
1924         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1925                 /*
1926                  * In case of GMAC, SF mode can be enabled
1927                  * to perform the TX COE in HW. This depends on:
1928                  * 1) TX COE if actually supported
1929                  * 2) There is no bugged Jumbo frame support
1930                  *    that needs to not insert csum in the TDES.
1931                  */
1932                 txmode = SF_DMA_MODE;
1933                 rxmode = SF_DMA_MODE;
1934                 priv->xstats.threshold = SF_DMA_MODE;
1935         } else {
1936                 txmode = tc;
1937                 rxmode = SF_DMA_MODE;
1938         }
1939
1940         /* configure all channels */
1941         for (chan = 0; chan < rx_channels_count; chan++) {
1942                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1943
1944                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1945                                 rxfifosz, qmode);
1946                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1947                                 chan);
1948         }
1949
1950         for (chan = 0; chan < tx_channels_count; chan++) {
1951                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1952
1953                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1954                                 txfifosz, qmode);
1955         }
1956 }
1957
1958 /**
1959  * stmmac_tx_clean - to manage the transmission completion
1960  * @priv: driver private structure
1961  * @queue: TX queue index
1962  * Description: it reclaims the transmit resources after transmission completes.
1963  */
1964 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1965 {
1966         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1967         unsigned int bytes_compl = 0, pkts_compl = 0;
1968         unsigned int entry, count = 0;
1969
1970         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1971
1972         priv->xstats.tx_clean++;
1973
1974         entry = tx_q->dirty_tx;
1975         while ((entry != tx_q->cur_tx) && (count < budget)) {
1976                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1977                 struct dma_desc *p;
1978                 int status;
1979
1980                 if (priv->extend_desc)
1981                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1982                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1983                         p = &tx_q->dma_entx[entry].basic;
1984                 else
1985                         p = tx_q->dma_tx + entry;
1986
1987                 status = stmmac_tx_status(priv, &priv->dev->stats,
1988                                 &priv->xstats, p, priv->ioaddr);
1989                 /* Check if the descriptor is owned by the DMA */
1990                 if (unlikely(status & tx_dma_own))
1991                         break;
1992
1993                 count++;
1994
1995                 /* Make sure descriptor fields are read after reading
1996                  * the own bit.
1997                  */
1998                 dma_rmb();
1999
2000                 /* Just consider the last segment and ...*/
2001                 if (likely(!(status & tx_not_ls))) {
2002                         /* ... verify the status error condition */
2003                         if (unlikely(status & tx_err)) {
2004                                 priv->dev->stats.tx_errors++;
2005                         } else {
2006                                 priv->dev->stats.tx_packets++;
2007                                 priv->xstats.tx_pkt_n++;
2008                         }
2009                         stmmac_get_tx_hwtstamp(priv, p, skb);
2010                 }
2011
2012                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
2013                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
2014                                 dma_unmap_page(priv->device,
2015                                                tx_q->tx_skbuff_dma[entry].buf,
2016                                                tx_q->tx_skbuff_dma[entry].len,
2017                                                DMA_TO_DEVICE);
2018                         else
2019                                 dma_unmap_single(priv->device,
2020                                                  tx_q->tx_skbuff_dma[entry].buf,
2021                                                  tx_q->tx_skbuff_dma[entry].len,
2022                                                  DMA_TO_DEVICE);
2023                         tx_q->tx_skbuff_dma[entry].buf = 0;
2024                         tx_q->tx_skbuff_dma[entry].len = 0;
2025                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
2026                 }
2027
2028                 stmmac_clean_desc3(priv, tx_q, p);
2029
2030                 tx_q->tx_skbuff_dma[entry].last_segment = false;
2031                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2032
2033                 if (likely(skb != NULL)) {
2034                         pkts_compl++;
2035                         bytes_compl += skb->len;
2036                         dev_consume_skb_any(skb);
2037                         tx_q->tx_skbuff[entry] = NULL;
2038                 }
2039
2040                 stmmac_release_tx_desc(priv, p, priv->mode);
2041
2042                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2043         }
2044         tx_q->dirty_tx = entry;
2045
2046         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2047                                   pkts_compl, bytes_compl);
2048
2049         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2050                                                                 queue))) &&
2051             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
2052
2053                 netif_dbg(priv, tx_done, priv->dev,
2054                           "%s: restart transmit\n", __func__);
2055                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2056         }
2057
2058         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
2059                 stmmac_enable_eee_mode(priv);
2060                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
2061         }
2062
2063         /* We still have pending packets, let's call for a new scheduling */
2064         if (tx_q->dirty_tx != tx_q->cur_tx)
2065                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2066
2067         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2068
2069         return count;
2070 }
2071
2072 /**
2073  * stmmac_tx_err - to manage the tx error
2074  * @priv: driver private structure
2075  * @chan: channel index
2076  * Description: it cleans the descriptors and restarts the transmission
2077  * in case of transmission errors.
2078  */
2079 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2080 {
2081         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2082
2083         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2084
2085         stmmac_stop_tx_dma(priv, chan);
2086         dma_free_tx_skbufs(priv, chan);
2087         stmmac_clear_tx_descriptors(priv, chan);
2088         tx_q->dirty_tx = 0;
2089         tx_q->cur_tx = 0;
2090         tx_q->mss = 0;
2091         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2092         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2093                             tx_q->dma_tx_phy, chan);
2094         stmmac_start_tx_dma(priv, chan);
2095
2096         priv->dev->stats.tx_errors++;
2097         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2098 }
2099
2100 /**
2101  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2102  *  @priv: driver private structure
2103  *  @txmode: TX operating mode
2104  *  @rxmode: RX operating mode
2105  *  @chan: channel index
2106  *  Description: it is used for configuring of the DMA operation mode in
2107  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2108  *  mode.
2109  */
2110 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2111                                           u32 rxmode, u32 chan)
2112 {
2113         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2114         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2115         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2116         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2117         int rxfifosz = priv->plat->rx_fifo_size;
2118         int txfifosz = priv->plat->tx_fifo_size;
2119
2120         if (rxfifosz == 0)
2121                 rxfifosz = priv->dma_cap.rx_fifo_size;
2122         if (txfifosz == 0)
2123                 txfifosz = priv->dma_cap.tx_fifo_size;
2124
2125         /* Adjust for real per queue fifo size */
2126         rxfifosz /= rx_channels_count;
2127         txfifosz /= tx_channels_count;
2128
2129         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2130         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2131 }
2132
2133 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2134 {
2135         int ret;
2136
2137         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2138                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2139         if (ret && (ret != -EINVAL)) {
2140                 stmmac_global_err(priv);
2141                 return true;
2142         }
2143
2144         return false;
2145 }
2146
2147 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2148 {
2149         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2150                                                  &priv->xstats, chan);
2151         struct stmmac_channel *ch = &priv->channel[chan];
2152         unsigned long flags;
2153
2154         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2155                 if (napi_schedule_prep(&ch->rx_napi)) {
2156                         spin_lock_irqsave(&ch->lock, flags);
2157                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2158                         spin_unlock_irqrestore(&ch->lock, flags);
2159                         __napi_schedule_irqoff(&ch->rx_napi);
2160                 }
2161         }
2162
2163         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2164                 if (napi_schedule_prep(&ch->tx_napi)) {
2165                         spin_lock_irqsave(&ch->lock, flags);
2166                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2167                         spin_unlock_irqrestore(&ch->lock, flags);
2168                         __napi_schedule_irqoff(&ch->tx_napi);
2169                 }
2170         }
2171
2172         return status;
2173 }
2174
2175 /**
2176  * stmmac_dma_interrupt - DMA ISR
2177  * @priv: driver private structure
2178  * Description: this is the DMA ISR. It is called by the main ISR.
2179  * It calls the dwmac dma routine and schedule poll method in case of some
2180  * work can be done.
2181  */
2182 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2183 {
2184         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2185         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2186         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2187                                 tx_channel_count : rx_channel_count;
2188         u32 chan;
2189         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2190
2191         /* Make sure we never check beyond our status buffer. */
2192         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2193                 channels_to_check = ARRAY_SIZE(status);
2194
2195         for (chan = 0; chan < channels_to_check; chan++)
2196                 status[chan] = stmmac_napi_check(priv, chan);
2197
2198         for (chan = 0; chan < tx_channel_count; chan++) {
2199                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2200                         /* Try to bump up the dma threshold on this failure */
2201                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2202                             (tc <= 256)) {
2203                                 tc += 64;
2204                                 if (priv->plat->force_thresh_dma_mode)
2205                                         stmmac_set_dma_operation_mode(priv,
2206                                                                       tc,
2207                                                                       tc,
2208                                                                       chan);
2209                                 else
2210                                         stmmac_set_dma_operation_mode(priv,
2211                                                                     tc,
2212                                                                     SF_DMA_MODE,
2213                                                                     chan);
2214                                 priv->xstats.threshold = tc;
2215                         }
2216                 } else if (unlikely(status[chan] == tx_hard_error)) {
2217                         stmmac_tx_err(priv, chan);
2218                 }
2219         }
2220 }
2221
2222 /**
2223  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2224  * @priv: driver private structure
2225  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2226  */
2227 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2228 {
2229         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2230                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2231
2232         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2233
2234         if (priv->dma_cap.rmon) {
2235                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2236                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2237         } else
2238                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2239 }
2240
2241 /**
2242  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2243  * @priv: driver private structure
2244  * Description:
2245  *  new GMAC chip generations have a new register to indicate the
2246  *  presence of the optional feature/functions.
2247  *  This can be also used to override the value passed through the
2248  *  platform and necessary for old MAC10/100 and GMAC chips.
2249  */
2250 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2251 {
2252         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2253 }
2254
2255 /**
2256  * stmmac_check_ether_addr - check if the MAC addr is valid
2257  * @priv: driver private structure
2258  * Description:
2259  * it is to verify if the MAC address is valid, in case of failures it
2260  * generates a random MAC address
2261  */
2262 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2263 {
2264         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2265                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2266                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2267                         eth_hw_addr_random(priv->dev);
2268                 dev_info(priv->device, "device MAC address %pM\n",
2269                          priv->dev->dev_addr);
2270         }
2271 }
2272
2273 /**
2274  * stmmac_init_dma_engine - DMA init.
2275  * @priv: driver private structure
2276  * Description:
2277  * It inits the DMA invoking the specific MAC/GMAC callback.
2278  * Some DMA parameters can be passed from the platform;
2279  * in case of these are not passed a default is kept for the MAC or GMAC.
2280  */
2281 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2282 {
2283         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2284         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2285         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2286         struct stmmac_rx_queue *rx_q;
2287         struct stmmac_tx_queue *tx_q;
2288         u32 chan = 0;
2289         int atds = 0;
2290         int ret = 0;
2291
2292         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2293                 dev_err(priv->device, "Invalid DMA configuration\n");
2294                 return -EINVAL;
2295         }
2296
2297         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2298                 atds = 1;
2299
2300         ret = stmmac_reset(priv, priv->ioaddr);
2301         if (ret) {
2302                 dev_err(priv->device, "Failed to reset the dma\n");
2303                 return ret;
2304         }
2305
2306         /* DMA Configuration */
2307         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2308
2309         if (priv->plat->axi)
2310                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2311
2312         /* DMA CSR Channel configuration */
2313         for (chan = 0; chan < dma_csr_ch; chan++)
2314                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2315
2316         /* DMA RX Channel Configuration */
2317         for (chan = 0; chan < rx_channels_count; chan++) {
2318                 rx_q = &priv->rx_queue[chan];
2319
2320                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2321                                     rx_q->dma_rx_phy, chan);
2322
2323                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2324                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2325                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2326                                        rx_q->rx_tail_addr, chan);
2327         }
2328
2329         /* DMA TX Channel Configuration */
2330         for (chan = 0; chan < tx_channels_count; chan++) {
2331                 tx_q = &priv->tx_queue[chan];
2332
2333                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2334                                     tx_q->dma_tx_phy, chan);
2335
2336                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2337                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2338                                        tx_q->tx_tail_addr, chan);
2339         }
2340
2341         return ret;
2342 }
2343
2344 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2345 {
2346         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2347
2348         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2349 }
2350
2351 /**
2352  * stmmac_tx_timer - mitigation sw timer for tx.
2353  * @data: data pointer
2354  * Description:
2355  * This is the timer handler to directly invoke the stmmac_tx_clean.
2356  */
2357 static void stmmac_tx_timer(struct timer_list *t)
2358 {
2359         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2360         struct stmmac_priv *priv = tx_q->priv_data;
2361         struct stmmac_channel *ch;
2362
2363         ch = &priv->channel[tx_q->queue_index];
2364
2365         if (likely(napi_schedule_prep(&ch->tx_napi))) {
2366                 unsigned long flags;
2367
2368                 spin_lock_irqsave(&ch->lock, flags);
2369                 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2370                 spin_unlock_irqrestore(&ch->lock, flags);
2371                 __napi_schedule(&ch->tx_napi);
2372         }
2373 }
2374
2375 /**
2376  * stmmac_init_coalesce - init mitigation options.
2377  * @priv: driver private structure
2378  * Description:
2379  * This inits the coalesce parameters: i.e. timer rate,
2380  * timer handler and default threshold used for enabling the
2381  * interrupt on completion bit.
2382  */
2383 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2384 {
2385         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2386         u32 chan;
2387
2388         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2389         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2390         priv->rx_coal_frames = STMMAC_RX_FRAMES;
2391
2392         for (chan = 0; chan < tx_channel_count; chan++) {
2393                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2394
2395                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2396         }
2397 }
2398
2399 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2400 {
2401         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2402         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2403         u32 chan;
2404
2405         /* set TX ring length */
2406         for (chan = 0; chan < tx_channels_count; chan++)
2407                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2408                                 (DMA_TX_SIZE - 1), chan);
2409
2410         /* set RX ring length */
2411         for (chan = 0; chan < rx_channels_count; chan++)
2412                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2413                                 (DMA_RX_SIZE - 1), chan);
2414 }
2415
2416 /**
2417  *  stmmac_set_tx_queue_weight - Set TX queue weight
2418  *  @priv: driver private structure
2419  *  Description: It is used for setting TX queues weight
2420  */
2421 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2422 {
2423         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2424         u32 weight;
2425         u32 queue;
2426
2427         for (queue = 0; queue < tx_queues_count; queue++) {
2428                 weight = priv->plat->tx_queues_cfg[queue].weight;
2429                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2430         }
2431 }
2432
2433 /**
2434  *  stmmac_configure_cbs - Configure CBS in TX queue
2435  *  @priv: driver private structure
2436  *  Description: It is used for configuring CBS in AVB TX queues
2437  */
2438 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2439 {
2440         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2441         u32 mode_to_use;
2442         u32 queue;
2443
2444         /* queue 0 is reserved for legacy traffic */
2445         for (queue = 1; queue < tx_queues_count; queue++) {
2446                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2447                 if (mode_to_use == MTL_QUEUE_DCB)
2448                         continue;
2449
2450                 stmmac_config_cbs(priv, priv->hw,
2451                                 priv->plat->tx_queues_cfg[queue].send_slope,
2452                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2453                                 priv->plat->tx_queues_cfg[queue].high_credit,
2454                                 priv->plat->tx_queues_cfg[queue].low_credit,
2455                                 queue);
2456         }
2457 }
2458
2459 /**
2460  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2461  *  @priv: driver private structure
2462  *  Description: It is used for mapping RX queues to RX dma channels
2463  */
2464 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2465 {
2466         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2467         u32 queue;
2468         u32 chan;
2469
2470         for (queue = 0; queue < rx_queues_count; queue++) {
2471                 chan = priv->plat->rx_queues_cfg[queue].chan;
2472                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2473         }
2474 }
2475
2476 /**
2477  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2478  *  @priv: driver private structure
2479  *  Description: It is used for configuring the RX Queue Priority
2480  */
2481 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2482 {
2483         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2484         u32 queue;
2485         u32 prio;
2486
2487         for (queue = 0; queue < rx_queues_count; queue++) {
2488                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2489                         continue;
2490
2491                 prio = priv->plat->rx_queues_cfg[queue].prio;
2492                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2493         }
2494 }
2495
2496 /**
2497  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2498  *  @priv: driver private structure
2499  *  Description: It is used for configuring the TX Queue Priority
2500  */
2501 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2502 {
2503         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2504         u32 queue;
2505         u32 prio;
2506
2507         for (queue = 0; queue < tx_queues_count; queue++) {
2508                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2509                         continue;
2510
2511                 prio = priv->plat->tx_queues_cfg[queue].prio;
2512                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2513         }
2514 }
2515
2516 /**
2517  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2518  *  @priv: driver private structure
2519  *  Description: It is used for configuring the RX queue routing
2520  */
2521 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2522 {
2523         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2524         u32 queue;
2525         u8 packet;
2526
2527         for (queue = 0; queue < rx_queues_count; queue++) {
2528                 /* no specific packet type routing specified for the queue */
2529                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2530                         continue;
2531
2532                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2533                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2534         }
2535 }
2536
2537 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
2538 {
2539         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
2540                 priv->rss.enable = false;
2541                 return;
2542         }
2543
2544         if (priv->dev->features & NETIF_F_RXHASH)
2545                 priv->rss.enable = true;
2546         else
2547                 priv->rss.enable = false;
2548
2549         stmmac_rss_configure(priv, priv->hw, &priv->rss,
2550                              priv->plat->rx_queues_to_use);
2551 }
2552
2553 /**
2554  *  stmmac_mtl_configuration - Configure MTL
2555  *  @priv: driver private structure
2556  *  Description: It is used for configurring MTL
2557  */
2558 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2559 {
2560         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2561         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2562
2563         if (tx_queues_count > 1)
2564                 stmmac_set_tx_queue_weight(priv);
2565
2566         /* Configure MTL RX algorithms */
2567         if (rx_queues_count > 1)
2568                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2569                                 priv->plat->rx_sched_algorithm);
2570
2571         /* Configure MTL TX algorithms */
2572         if (tx_queues_count > 1)
2573                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2574                                 priv->plat->tx_sched_algorithm);
2575
2576         /* Configure CBS in AVB TX queues */
2577         if (tx_queues_count > 1)
2578                 stmmac_configure_cbs(priv);
2579
2580         /* Map RX MTL to DMA channels */
2581         stmmac_rx_queue_dma_chan_map(priv);
2582
2583         /* Enable MAC RX Queues */
2584         stmmac_mac_enable_rx_queues(priv);
2585
2586         /* Set RX priorities */
2587         if (rx_queues_count > 1)
2588                 stmmac_mac_config_rx_queues_prio(priv);
2589
2590         /* Set TX priorities */
2591         if (tx_queues_count > 1)
2592                 stmmac_mac_config_tx_queues_prio(priv);
2593
2594         /* Set RX routing */
2595         if (rx_queues_count > 1)
2596                 stmmac_mac_config_rx_queues_routing(priv);
2597
2598         /* Receive Side Scaling */
2599         if (rx_queues_count > 1)
2600                 stmmac_mac_config_rss(priv);
2601 }
2602
2603 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2604 {
2605         if (priv->dma_cap.asp) {
2606                 netdev_info(priv->dev, "Enabling Safety Features\n");
2607                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2608         } else {
2609                 netdev_info(priv->dev, "No Safety Features support found\n");
2610         }
2611 }
2612
2613 /**
2614  * stmmac_hw_setup - setup mac in a usable state.
2615  *  @dev : pointer to the device structure.
2616  *  Description:
2617  *  this is the main function to setup the HW in a usable state because the
2618  *  dma engine is reset, the core registers are configured (e.g. AXI,
2619  *  Checksum features, timers). The DMA is ready to start receiving and
2620  *  transmitting.
2621  *  Return value:
2622  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2623  *  file on failure.
2624  */
2625 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2626 {
2627         struct stmmac_priv *priv = netdev_priv(dev);
2628         u32 rx_cnt = priv->plat->rx_queues_to_use;
2629         u32 tx_cnt = priv->plat->tx_queues_to_use;
2630         u32 chan;
2631         int ret;
2632
2633         /* DMA initialization and SW reset */
2634         ret = stmmac_init_dma_engine(priv);
2635         if (ret < 0) {
2636                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2637                            __func__);
2638                 return ret;
2639         }
2640
2641         /* Copy the MAC addr into the HW  */
2642         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2643
2644         /* PS and related bits will be programmed according to the speed */
2645         if (priv->hw->pcs) {
2646                 int speed = priv->plat->mac_port_sel_speed;
2647
2648                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2649                     (speed == SPEED_1000)) {
2650                         priv->hw->ps = speed;
2651                 } else {
2652                         dev_warn(priv->device, "invalid port speed\n");
2653                         priv->hw->ps = 0;
2654                 }
2655         }
2656
2657         /* Initialize the MAC Core */
2658         stmmac_core_init(priv, priv->hw, dev);
2659
2660         /* Initialize MTL*/
2661         stmmac_mtl_configuration(priv);
2662
2663         /* Initialize Safety Features */
2664         stmmac_safety_feat_configuration(priv);
2665
2666         ret = stmmac_rx_ipc(priv, priv->hw);
2667         if (!ret) {
2668                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2669                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2670                 priv->hw->rx_csum = 0;
2671         }
2672
2673         /* Enable the MAC Rx/Tx */
2674         stmmac_mac_set(priv, priv->ioaddr, true);
2675
2676         /* Set the HW DMA mode and the COE */
2677         stmmac_dma_operation_mode(priv);
2678
2679         stmmac_mmc_setup(priv);
2680
2681         if (init_ptp) {
2682                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2683                 if (ret < 0)
2684                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2685
2686                 ret = stmmac_init_ptp(priv);
2687                 if (ret == -EOPNOTSUPP)
2688                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2689                 else if (ret)
2690                         netdev_warn(priv->dev, "PTP init failed\n");
2691         }
2692
2693         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2694
2695         if (priv->use_riwt) {
2696                 if (!priv->rx_riwt)
2697                         priv->rx_riwt = DEF_DMA_RIWT;
2698
2699                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
2700         }
2701
2702         if (priv->hw->pcs)
2703                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
2704
2705         /* set TX and RX rings length */
2706         stmmac_set_rings_length(priv);
2707
2708         /* Enable TSO */
2709         if (priv->tso) {
2710                 for (chan = 0; chan < tx_cnt; chan++)
2711                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2712         }
2713
2714         /* Enable Split Header */
2715         if (priv->sph && priv->hw->rx_csum) {
2716                 for (chan = 0; chan < rx_cnt; chan++)
2717                         stmmac_enable_sph(priv, priv->ioaddr, 1, chan);
2718         }
2719
2720         /* VLAN Tag Insertion */
2721         if (priv->dma_cap.vlins)
2722                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
2723
2724         /* TBS */
2725         for (chan = 0; chan < tx_cnt; chan++) {
2726                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2727                 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
2728
2729                 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
2730         }
2731
2732         /* Start the ball rolling... */
2733         stmmac_start_all_dma(priv);
2734
2735         return 0;
2736 }
2737
2738 static void stmmac_hw_teardown(struct net_device *dev)
2739 {
2740         struct stmmac_priv *priv = netdev_priv(dev);
2741
2742         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2743 }
2744
2745 /**
2746  *  stmmac_open - open entry point of the driver
2747  *  @dev : pointer to the device structure.
2748  *  Description:
2749  *  This function is the open entry point of the driver.
2750  *  Return value:
2751  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2752  *  file on failure.
2753  */
2754 static int stmmac_open(struct net_device *dev)
2755 {
2756         struct stmmac_priv *priv = netdev_priv(dev);
2757         int bfsize = 0;
2758         u32 chan;
2759         int ret;
2760
2761         if (priv->hw->pcs != STMMAC_PCS_TBI &&
2762             priv->hw->pcs != STMMAC_PCS_RTBI &&
2763             priv->hw->xpcs == NULL) {
2764                 ret = stmmac_init_phy(dev);
2765                 if (ret) {
2766                         netdev_err(priv->dev,
2767                                    "%s: Cannot attach to PHY (error: %d)\n",
2768                                    __func__, ret);
2769                         return ret;
2770                 }
2771         }
2772
2773         /* Extra statistics */
2774         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2775         priv->xstats.threshold = tc;
2776
2777         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
2778         if (bfsize < 0)
2779                 bfsize = 0;
2780
2781         if (bfsize < BUF_SIZE_16KiB)
2782                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
2783
2784         priv->dma_buf_sz = bfsize;
2785         buf_sz = bfsize;
2786
2787         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2788
2789         /* Earlier check for TBS */
2790         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
2791                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2792                 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
2793
2794                 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
2795                 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan))
2796                         tx_q->tbs &= ~STMMAC_TBS_AVAIL;
2797         }
2798
2799         ret = alloc_dma_desc_resources(priv);
2800         if (ret < 0) {
2801                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2802                            __func__);
2803                 goto dma_desc_error;
2804         }
2805
2806         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2807         if (ret < 0) {
2808                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2809                            __func__);
2810                 goto init_error;
2811         }
2812
2813         ret = stmmac_hw_setup(dev, true);
2814         if (ret < 0) {
2815                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2816                 goto init_error;
2817         }
2818
2819         stmmac_init_coalesce(priv);
2820
2821         phylink_start(priv->phylink);
2822
2823         /* Request the IRQ lines */
2824         ret = request_irq(dev->irq, stmmac_interrupt,
2825                           IRQF_SHARED, dev->name, dev);
2826         if (unlikely(ret < 0)) {
2827                 netdev_err(priv->dev,
2828                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2829                            __func__, dev->irq, ret);
2830                 goto irq_error;
2831         }
2832
2833         /* Request the Wake IRQ in case of another line is used for WoL */
2834         if (priv->wol_irq != dev->irq) {
2835                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2836                                   IRQF_SHARED, dev->name, dev);
2837                 if (unlikely(ret < 0)) {
2838                         netdev_err(priv->dev,
2839                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2840                                    __func__, priv->wol_irq, ret);
2841                         goto wolirq_error;
2842                 }
2843         }
2844
2845         /* Request the IRQ lines */
2846         if (priv->lpi_irq > 0) {
2847                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2848                                   dev->name, dev);
2849                 if (unlikely(ret < 0)) {
2850                         netdev_err(priv->dev,
2851                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2852                                    __func__, priv->lpi_irq, ret);
2853                         goto lpiirq_error;
2854                 }
2855         }
2856
2857         stmmac_enable_all_queues(priv);
2858         stmmac_start_all_queues(priv);
2859
2860         return 0;
2861
2862 lpiirq_error:
2863         if (priv->wol_irq != dev->irq)
2864                 free_irq(priv->wol_irq, dev);
2865 wolirq_error:
2866         free_irq(dev->irq, dev);
2867 irq_error:
2868         phylink_stop(priv->phylink);
2869
2870         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2871                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2872
2873         stmmac_hw_teardown(dev);
2874 init_error:
2875         free_dma_desc_resources(priv);
2876 dma_desc_error:
2877         phylink_disconnect_phy(priv->phylink);
2878         return ret;
2879 }
2880
2881 /**
2882  *  stmmac_release - close entry point of the driver
2883  *  @dev : device pointer.
2884  *  Description:
2885  *  This is the stop entry point of the driver.
2886  */
2887 static int stmmac_release(struct net_device *dev)
2888 {
2889         struct stmmac_priv *priv = netdev_priv(dev);
2890         u32 chan;
2891
2892         if (priv->eee_enabled)
2893                 del_timer_sync(&priv->eee_ctrl_timer);
2894
2895         /* Stop and disconnect the PHY */
2896         phylink_stop(priv->phylink);
2897         phylink_disconnect_phy(priv->phylink);
2898
2899         stmmac_stop_all_queues(priv);
2900
2901         stmmac_disable_all_queues(priv);
2902
2903         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2904                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2905
2906         /* Free the IRQ lines */
2907         free_irq(dev->irq, dev);
2908         if (priv->wol_irq != dev->irq)
2909                 free_irq(priv->wol_irq, dev);
2910         if (priv->lpi_irq > 0)
2911                 free_irq(priv->lpi_irq, dev);
2912
2913         /* Stop TX/RX DMA and clear the descriptors */
2914         stmmac_stop_all_dma(priv);
2915
2916         /* Release and free the Rx/Tx resources */
2917         free_dma_desc_resources(priv);
2918
2919         /* Disable the MAC Rx/Tx */
2920         stmmac_mac_set(priv, priv->ioaddr, false);
2921
2922         netif_carrier_off(dev);
2923
2924         stmmac_release_ptp(priv);
2925
2926         return 0;
2927 }
2928
2929 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
2930                                struct stmmac_tx_queue *tx_q)
2931 {
2932         u16 tag = 0x0, inner_tag = 0x0;
2933         u32 inner_type = 0x0;
2934         struct dma_desc *p;
2935
2936         if (!priv->dma_cap.vlins)
2937                 return false;
2938         if (!skb_vlan_tag_present(skb))
2939                 return false;
2940         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
2941                 inner_tag = skb_vlan_tag_get(skb);
2942                 inner_type = STMMAC_VLAN_INSERT;
2943         }
2944
2945         tag = skb_vlan_tag_get(skb);
2946
2947         if (tx_q->tbs & STMMAC_TBS_AVAIL)
2948                 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
2949         else
2950                 p = &tx_q->dma_tx[tx_q->cur_tx];
2951
2952         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
2953                 return false;
2954
2955         stmmac_set_tx_owner(priv, p);
2956         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2957         return true;
2958 }
2959
2960 /**
2961  *  stmmac_tso_allocator - close entry point of the driver
2962  *  @priv: driver private structure
2963  *  @des: buffer start address
2964  *  @total_len: total length to fill in descriptors
2965  *  @last_segmant: condition for the last descriptor
2966  *  @queue: TX queue index
2967  *  Description:
2968  *  This function fills descriptor and request new descriptors according to
2969  *  buffer length to fill
2970  */
2971 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2972                                  int total_len, bool last_segment, u32 queue)
2973 {
2974         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2975         struct dma_desc *desc;
2976         u32 buff_size;
2977         int tmp_len;
2978
2979         tmp_len = total_len;
2980
2981         while (tmp_len > 0) {
2982                 dma_addr_t curr_addr;
2983
2984                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2985                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2986
2987                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
2988                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
2989                 else
2990                         desc = &tx_q->dma_tx[tx_q->cur_tx];
2991
2992                 curr_addr = des + (total_len - tmp_len);
2993                 if (priv->dma_cap.addr64 <= 32)
2994                         desc->des0 = cpu_to_le32(curr_addr);
2995                 else
2996                         stmmac_set_desc_addr(priv, desc, curr_addr);
2997
2998                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2999                             TSO_MAX_BUFF_SIZE : tmp_len;
3000
3001                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3002                                 0, 1,
3003                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3004                                 0, 0);
3005
3006                 tmp_len -= TSO_MAX_BUFF_SIZE;
3007         }
3008 }
3009
3010 /**
3011  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3012  *  @skb : the socket buffer
3013  *  @dev : device pointer
3014  *  Description: this is the transmit function that is called on TSO frames
3015  *  (support available on GMAC4 and newer chips).
3016  *  Diagram below show the ring programming in case of TSO frames:
3017  *
3018  *  First Descriptor
3019  *   --------
3020  *   | DES0 |---> buffer1 = L2/L3/L4 header
3021  *   | DES1 |---> TCP Payload (can continue on next descr...)
3022  *   | DES2 |---> buffer 1 and 2 len
3023  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3024  *   --------
3025  *      |
3026  *     ...
3027  *      |
3028  *   --------
3029  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
3030  *   | DES1 | --|
3031  *   | DES2 | --> buffer 1 and 2 len
3032  *   | DES3 |
3033  *   --------
3034  *
3035  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3036  */
3037 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3038 {
3039         struct dma_desc *desc, *first, *mss_desc = NULL;
3040         struct stmmac_priv *priv = netdev_priv(dev);
3041         int desc_size, tmp_pay_len = 0, first_tx;
3042         int nfrags = skb_shinfo(skb)->nr_frags;
3043         u32 queue = skb_get_queue_mapping(skb);
3044         unsigned int first_entry, tx_packets;
3045         struct stmmac_tx_queue *tx_q;
3046         bool has_vlan, set_ic;
3047         u8 proto_hdr_len, hdr;
3048         u32 pay_len, mss;
3049         dma_addr_t des;
3050         int i;
3051
3052         tx_q = &priv->tx_queue[queue];
3053         first_tx = tx_q->cur_tx;
3054
3055         /* Compute header lengths */
3056         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3057                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3058                 hdr = sizeof(struct udphdr);
3059         } else {
3060                 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3061                 hdr = tcp_hdrlen(skb);
3062         }
3063
3064         /* Desc availability based on threshold should be enough safe */
3065         if (unlikely(stmmac_tx_avail(priv, queue) <
3066                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3067                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3068                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3069                                                                 queue));
3070                         /* This is a hard error, log it. */
3071                         netdev_err(priv->dev,
3072                                    "%s: Tx Ring full when queue awake\n",
3073                                    __func__);
3074                 }
3075                 return NETDEV_TX_BUSY;
3076         }
3077
3078         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3079
3080         mss = skb_shinfo(skb)->gso_size;
3081
3082         /* set new MSS value if needed */
3083         if (mss != tx_q->mss) {
3084                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3085                         mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3086                 else
3087                         mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3088
3089                 stmmac_set_mss(priv, mss_desc, mss);
3090                 tx_q->mss = mss;
3091                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
3092                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3093         }
3094
3095         if (netif_msg_tx_queued(priv)) {
3096                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
3097                         __func__, hdr, proto_hdr_len, pay_len, mss);
3098                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
3099                         skb->data_len);
3100         }
3101
3102         /* Check if VLAN can be inserted by HW */
3103         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3104
3105         first_entry = tx_q->cur_tx;
3106         WARN_ON(tx_q->tx_skbuff[first_entry]);
3107
3108         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3109                 desc = &tx_q->dma_entx[first_entry].basic;
3110         else
3111                 desc = &tx_q->dma_tx[first_entry];
3112         first = desc;
3113
3114         if (has_vlan)
3115                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3116
3117         /* first descriptor: fill Headers on Buf1 */
3118         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
3119                              DMA_TO_DEVICE);
3120         if (dma_mapping_error(priv->device, des))
3121                 goto dma_map_err;
3122
3123         tx_q->tx_skbuff_dma[first_entry].buf = des;
3124         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
3125
3126         if (priv->dma_cap.addr64 <= 32) {
3127                 first->des0 = cpu_to_le32(des);
3128
3129                 /* Fill start of payload in buff2 of first descriptor */
3130                 if (pay_len)
3131                         first->des1 = cpu_to_le32(des + proto_hdr_len);
3132
3133                 /* If needed take extra descriptors to fill the remaining payload */
3134                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
3135         } else {
3136                 stmmac_set_desc_addr(priv, first, des);
3137                 tmp_pay_len = pay_len;
3138                 des += proto_hdr_len;
3139                 pay_len = 0;
3140         }
3141
3142         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
3143
3144         /* Prepare fragments */
3145         for (i = 0; i < nfrags; i++) {
3146                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3147
3148                 des = skb_frag_dma_map(priv->device, frag, 0,
3149                                        skb_frag_size(frag),
3150                                        DMA_TO_DEVICE);
3151                 if (dma_mapping_error(priv->device, des))
3152                         goto dma_map_err;
3153
3154                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
3155                                      (i == nfrags - 1), queue);
3156
3157                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
3158                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
3159                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
3160         }
3161
3162         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
3163
3164         /* Only the last descriptor gets to point to the skb. */
3165         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
3166
3167         /* Manage tx mitigation */
3168         tx_packets = (tx_q->cur_tx + 1) - first_tx;
3169         tx_q->tx_count_frames += tx_packets;
3170
3171         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3172                 set_ic = true;
3173         else if (!priv->tx_coal_frames)
3174                 set_ic = false;
3175         else if (tx_packets > priv->tx_coal_frames)
3176                 set_ic = true;
3177         else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3178                 set_ic = true;
3179         else
3180                 set_ic = false;
3181
3182         if (set_ic) {
3183                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3184                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3185                 else
3186                         desc = &tx_q->dma_tx[tx_q->cur_tx];
3187
3188                 tx_q->tx_count_frames = 0;
3189                 stmmac_set_tx_ic(priv, desc);
3190                 priv->xstats.tx_set_ic_bit++;
3191         }
3192
3193         /* We've used all descriptors we need for this skb, however,
3194          * advance cur_tx so that it references a fresh descriptor.
3195          * ndo_start_xmit will fill this descriptor the next time it's
3196          * called and stmmac_tx_clean may clean up to this descriptor.
3197          */
3198         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
3199
3200         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3201                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3202                           __func__);
3203                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3204         }
3205
3206         dev->stats.tx_bytes += skb->len;
3207         priv->xstats.tx_tso_frames++;
3208         priv->xstats.tx_tso_nfrags += nfrags;
3209
3210         if (priv->sarc_type)
3211                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3212
3213         skb_tx_timestamp(skb);
3214
3215         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3216                      priv->hwts_tx_en)) {
3217                 /* declare that device is doing timestamping */
3218                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3219                 stmmac_enable_tx_timestamp(priv, first);
3220         }
3221
3222         /* Complete the first descriptor before granting the DMA */
3223         stmmac_prepare_tso_tx_desc(priv, first, 1,
3224                         proto_hdr_len,
3225                         pay_len,
3226                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
3227                         hdr / 4, (skb->len - proto_hdr_len));
3228
3229         /* If context desc is used to change MSS */
3230         if (mss_desc) {
3231                 /* Make sure that first descriptor has been completely
3232                  * written, including its own bit. This is because MSS is
3233                  * actually before first descriptor, so we need to make
3234                  * sure that MSS's own bit is the last thing written.
3235                  */
3236                 dma_wmb();
3237                 stmmac_set_tx_owner(priv, mss_desc);
3238         }
3239
3240         /* The own bit must be the latest setting done when prepare the
3241          * descriptor and then barrier is needed to make sure that
3242          * all is coherent before granting the DMA engine.
3243          */
3244         wmb();
3245
3246         if (netif_msg_pktdata(priv)) {
3247                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3248                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3249                         tx_q->cur_tx, first, nfrags);
3250                 pr_info(">>> frame to be transmitted: ");
3251                 print_pkt(skb->data, skb_headlen(skb));
3252         }
3253
3254         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3255
3256         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3257                 desc_size = sizeof(struct dma_edesc);
3258         else
3259                 desc_size = sizeof(struct dma_desc);
3260
3261         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3262         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3263         stmmac_tx_timer_arm(priv, queue);
3264
3265         return NETDEV_TX_OK;
3266
3267 dma_map_err:
3268         dev_err(priv->device, "Tx dma map failed\n");
3269         dev_kfree_skb(skb);
3270         priv->dev->stats.tx_dropped++;
3271         return NETDEV_TX_OK;
3272 }
3273
3274 /**
3275  *  stmmac_xmit - Tx entry point of the driver
3276  *  @skb : the socket buffer
3277  *  @dev : device pointer
3278  *  Description : this is the tx entry point of the driver.
3279  *  It programs the chain or the ring and supports oversized frames
3280  *  and SG feature.
3281  */
3282 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3283 {
3284         unsigned int first_entry, tx_packets, enh_desc;
3285         struct stmmac_priv *priv = netdev_priv(dev);
3286         unsigned int nopaged_len = skb_headlen(skb);
3287         int i, csum_insertion = 0, is_jumbo = 0;
3288         u32 queue = skb_get_queue_mapping(skb);
3289         int nfrags = skb_shinfo(skb)->nr_frags;
3290         int gso = skb_shinfo(skb)->gso_type;
3291         struct dma_edesc *tbs_desc = NULL;
3292         int entry, desc_size, first_tx;
3293         struct dma_desc *desc, *first;
3294         struct stmmac_tx_queue *tx_q;
3295         bool has_vlan, set_ic;
3296         dma_addr_t des;
3297
3298         tx_q = &priv->tx_queue[queue];
3299         first_tx = tx_q->cur_tx;
3300
3301         if (priv->tx_path_in_lpi_mode)
3302                 stmmac_disable_eee_mode(priv);
3303
3304         /* Manage oversized TCP frames for GMAC4 device */
3305         if (skb_is_gso(skb) && priv->tso) {
3306                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3307                         return stmmac_tso_xmit(skb, dev);
3308                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
3309                         return stmmac_tso_xmit(skb, dev);
3310         }
3311
3312         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3313                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3314                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3315                                                                 queue));
3316                         /* This is a hard error, log it. */
3317                         netdev_err(priv->dev,
3318                                    "%s: Tx Ring full when queue awake\n",
3319                                    __func__);
3320                 }
3321                 return NETDEV_TX_BUSY;
3322         }
3323
3324         /* Check if VLAN can be inserted by HW */
3325         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3326
3327         entry = tx_q->cur_tx;
3328         first_entry = entry;
3329         WARN_ON(tx_q->tx_skbuff[first_entry]);
3330
3331         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3332
3333         if (likely(priv->extend_desc))
3334                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3335         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3336                 desc = &tx_q->dma_entx[entry].basic;
3337         else
3338                 desc = tx_q->dma_tx + entry;
3339
3340         first = desc;
3341
3342         if (has_vlan)
3343                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3344
3345         enh_desc = priv->plat->enh_desc;
3346         /* To program the descriptors according to the size of the frame */
3347         if (enh_desc)
3348                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3349
3350         if (unlikely(is_jumbo)) {
3351                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3352                 if (unlikely(entry < 0) && (entry != -EINVAL))
3353                         goto dma_map_err;
3354         }
3355
3356         for (i = 0; i < nfrags; i++) {
3357                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3358                 int len = skb_frag_size(frag);
3359                 bool last_segment = (i == (nfrags - 1));
3360
3361                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3362                 WARN_ON(tx_q->tx_skbuff[entry]);
3363
3364                 if (likely(priv->extend_desc))
3365                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3366                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3367                         desc = &tx_q->dma_entx[entry].basic;
3368                 else
3369                         desc = tx_q->dma_tx + entry;
3370
3371                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3372                                        DMA_TO_DEVICE);
3373                 if (dma_mapping_error(priv->device, des))
3374                         goto dma_map_err; /* should reuse desc w/o issues */
3375
3376                 tx_q->tx_skbuff_dma[entry].buf = des;
3377
3378                 stmmac_set_desc_addr(priv, desc, des);
3379
3380                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3381                 tx_q->tx_skbuff_dma[entry].len = len;
3382                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3383
3384                 /* Prepare the descriptor and set the own bit too */
3385                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3386                                 priv->mode, 1, last_segment, skb->len);
3387         }
3388
3389         /* Only the last descriptor gets to point to the skb. */
3390         tx_q->tx_skbuff[entry] = skb;
3391
3392         /* According to the coalesce parameter the IC bit for the latest
3393          * segment is reset and the timer re-started to clean the tx status.
3394          * This approach takes care about the fragments: desc is the first
3395          * element in case of no SG.
3396          */
3397         tx_packets = (entry + 1) - first_tx;
3398         tx_q->tx_count_frames += tx_packets;
3399
3400         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3401                 set_ic = true;
3402         else if (!priv->tx_coal_frames)
3403                 set_ic = false;
3404         else if (tx_packets > priv->tx_coal_frames)
3405                 set_ic = true;
3406         else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3407                 set_ic = true;
3408         else
3409                 set_ic = false;
3410
3411         if (set_ic) {
3412                 if (likely(priv->extend_desc))
3413                         desc = &tx_q->dma_etx[entry].basic;
3414                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3415                         desc = &tx_q->dma_entx[entry].basic;
3416                 else
3417                         desc = &tx_q->dma_tx[entry];
3418
3419                 tx_q->tx_count_frames = 0;
3420                 stmmac_set_tx_ic(priv, desc);
3421                 priv->xstats.tx_set_ic_bit++;
3422         }
3423
3424         /* We've used all descriptors we need for this skb, however,
3425          * advance cur_tx so that it references a fresh descriptor.
3426          * ndo_start_xmit will fill this descriptor the next time it's
3427          * called and stmmac_tx_clean may clean up to this descriptor.
3428          */
3429         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3430         tx_q->cur_tx = entry;
3431
3432         if (netif_msg_pktdata(priv)) {
3433                 netdev_dbg(priv->dev,
3434                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3435                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3436                            entry, first, nfrags);
3437
3438                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3439                 print_pkt(skb->data, skb->len);
3440         }
3441
3442         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3443                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3444                           __func__);
3445                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3446         }
3447
3448         dev->stats.tx_bytes += skb->len;
3449
3450         if (priv->sarc_type)
3451                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3452
3453         skb_tx_timestamp(skb);
3454
3455         /* Ready to fill the first descriptor and set the OWN bit w/o any
3456          * problems because all the descriptors are actually ready to be
3457          * passed to the DMA engine.
3458          */
3459         if (likely(!is_jumbo)) {
3460                 bool last_segment = (nfrags == 0);
3461
3462                 des = dma_map_single(priv->device, skb->data,
3463                                      nopaged_len, DMA_TO_DEVICE);
3464                 if (dma_mapping_error(priv->device, des))
3465                         goto dma_map_err;
3466
3467                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3468
3469                 stmmac_set_desc_addr(priv, first, des);
3470
3471                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3472                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3473
3474                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3475                              priv->hwts_tx_en)) {
3476                         /* declare that device is doing timestamping */
3477                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3478                         stmmac_enable_tx_timestamp(priv, first);
3479                 }
3480
3481                 /* Prepare the first descriptor setting the OWN bit too */
3482                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3483                                 csum_insertion, priv->mode, 0, last_segment,
3484                                 skb->len);
3485         }
3486
3487         if (tx_q->tbs & STMMAC_TBS_EN) {
3488                 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
3489
3490                 tbs_desc = &tx_q->dma_entx[first_entry];
3491                 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
3492         }
3493
3494         stmmac_set_tx_owner(priv, first);
3495
3496         /* The own bit must be the latest setting done when prepare the
3497          * descriptor and then barrier is needed to make sure that
3498          * all is coherent before granting the DMA engine.
3499          */
3500         wmb();
3501
3502         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3503
3504         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3505
3506         if (likely(priv->extend_desc))
3507                 desc_size = sizeof(struct dma_extended_desc);
3508         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3509                 desc_size = sizeof(struct dma_edesc);
3510         else
3511                 desc_size = sizeof(struct dma_desc);
3512
3513         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3514         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3515         stmmac_tx_timer_arm(priv, queue);
3516
3517         return NETDEV_TX_OK;
3518
3519 dma_map_err:
3520         netdev_err(priv->dev, "Tx DMA map failed\n");
3521         dev_kfree_skb(skb);
3522         priv->dev->stats.tx_dropped++;
3523         return NETDEV_TX_OK;
3524 }
3525
3526 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3527 {
3528         struct vlan_ethhdr *veth;
3529         __be16 vlan_proto;
3530         u16 vlanid;
3531
3532         veth = (struct vlan_ethhdr *)skb->data;
3533         vlan_proto = veth->h_vlan_proto;
3534
3535         if ((vlan_proto == htons(ETH_P_8021Q) &&
3536              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3537             (vlan_proto == htons(ETH_P_8021AD) &&
3538              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3539                 /* pop the vlan tag */
3540                 vlanid = ntohs(veth->h_vlan_TCI);
3541                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3542                 skb_pull(skb, VLAN_HLEN);
3543                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3544         }
3545 }
3546
3547 /**
3548  * stmmac_rx_refill - refill used skb preallocated buffers
3549  * @priv: driver private structure
3550  * @queue: RX queue index
3551  * Description : this is to reallocate the skb for the reception process
3552  * that is based on zero-copy.
3553  */
3554 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3555 {
3556         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3557         int len, dirty = stmmac_rx_dirty(priv, queue);
3558         unsigned int entry = rx_q->dirty_rx;
3559
3560         len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3561
3562         while (dirty-- > 0) {
3563                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
3564                 struct dma_desc *p;
3565                 bool use_rx_wd;
3566
3567                 if (priv->extend_desc)
3568                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3569                 else
3570                         p = rx_q->dma_rx + entry;
3571
3572                 if (!buf->page) {
3573                         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3574                         if (!buf->page)
3575                                 break;
3576                 }
3577
3578                 if (priv->sph && !buf->sec_page) {
3579                         buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
3580                         if (!buf->sec_page)
3581                                 break;
3582
3583                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
3584
3585                         dma_sync_single_for_device(priv->device, buf->sec_addr,
3586                                                    len, DMA_FROM_DEVICE);
3587                 }
3588
3589                 buf->addr = page_pool_get_dma_addr(buf->page);
3590
3591                 /* Sync whole allocation to device. This will invalidate old
3592                  * data.
3593                  */
3594                 dma_sync_single_for_device(priv->device, buf->addr, len,
3595                                            DMA_FROM_DEVICE);
3596
3597                 stmmac_set_desc_addr(priv, p, buf->addr);
3598                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
3599                 stmmac_refill_desc3(priv, rx_q, p);
3600
3601                 rx_q->rx_count_frames++;
3602                 rx_q->rx_count_frames += priv->rx_coal_frames;
3603                 if (rx_q->rx_count_frames > priv->rx_coal_frames)
3604                         rx_q->rx_count_frames = 0;
3605
3606                 use_rx_wd = !priv->rx_coal_frames;
3607                 use_rx_wd |= rx_q->rx_count_frames > 0;
3608                 if (!priv->use_riwt)
3609                         use_rx_wd = false;
3610
3611                 dma_wmb();
3612                 stmmac_set_rx_owner(priv, p, use_rx_wd);
3613
3614                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3615         }
3616         rx_q->dirty_rx = entry;
3617         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3618                             (rx_q->dirty_rx * sizeof(struct dma_desc));
3619         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3620 }
3621
3622 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
3623                                        struct dma_desc *p,
3624                                        int status, unsigned int len)
3625 {
3626         int ret, coe = priv->hw->rx_csum;
3627         unsigned int plen = 0, hlen = 0;
3628
3629         /* Not first descriptor, buffer is always zero */
3630         if (priv->sph && len)
3631                 return 0;
3632
3633         /* First descriptor, get split header length */
3634         ret = stmmac_get_rx_header_len(priv, p, &hlen);
3635         if (priv->sph && hlen) {
3636                 priv->xstats.rx_split_hdr_pkt_n++;
3637                 return hlen;
3638         }
3639
3640         /* First descriptor, not last descriptor and not split header */
3641         if (status & rx_not_ls)
3642                 return priv->dma_buf_sz;
3643
3644         plen = stmmac_get_rx_frame_len(priv, p, coe);
3645
3646         /* First descriptor and last descriptor and not split header */
3647         return min_t(unsigned int, priv->dma_buf_sz, plen);
3648 }
3649
3650 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
3651                                        struct dma_desc *p,
3652                                        int status, unsigned int len)
3653 {
3654         int coe = priv->hw->rx_csum;
3655         unsigned int plen = 0;
3656
3657         /* Not split header, buffer is not available */
3658         if (!priv->sph)
3659                 return 0;
3660
3661         /* Not last descriptor */
3662         if (status & rx_not_ls)
3663                 return priv->dma_buf_sz;
3664
3665         plen = stmmac_get_rx_frame_len(priv, p, coe);
3666
3667         /* Last descriptor */
3668         return plen - len;
3669 }
3670
3671 /**
3672  * stmmac_rx - manage the receive process
3673  * @priv: driver private structure
3674  * @limit: napi bugget
3675  * @queue: RX queue index.
3676  * Description :  this the function called by the napi poll method.
3677  * It gets all the frames inside the ring.
3678  */
3679 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3680 {
3681         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3682         struct stmmac_channel *ch = &priv->channel[queue];
3683         unsigned int count = 0, error = 0, len = 0;
3684         int status = 0, coe = priv->hw->rx_csum;
3685         unsigned int next_entry = rx_q->cur_rx;
3686         struct sk_buff *skb = NULL;
3687
3688         if (netif_msg_rx_status(priv)) {
3689                 void *rx_head;
3690
3691                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3692                 if (priv->extend_desc)
3693                         rx_head = (void *)rx_q->dma_erx;
3694                 else
3695                         rx_head = (void *)rx_q->dma_rx;
3696
3697                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3698         }
3699         while (count < limit) {
3700                 unsigned int buf1_len = 0, buf2_len = 0;
3701                 enum pkt_hash_types hash_type;
3702                 struct stmmac_rx_buffer *buf;
3703                 struct dma_desc *np, *p;
3704                 int entry;
3705                 u32 hash;
3706
3707                 if (!count && rx_q->state_saved) {
3708                         skb = rx_q->state.skb;
3709                         error = rx_q->state.error;
3710                         len = rx_q->state.len;
3711                 } else {
3712                         rx_q->state_saved = false;
3713                         skb = NULL;
3714                         error = 0;
3715                         len = 0;
3716                 }
3717
3718                 if (count >= limit)
3719                         break;
3720
3721 read_again:
3722                 buf1_len = 0;
3723                 buf2_len = 0;
3724                 entry = next_entry;
3725                 buf = &rx_q->buf_pool[entry];
3726
3727                 if (priv->extend_desc)
3728                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3729                 else
3730                         p = rx_q->dma_rx + entry;
3731
3732                 /* read the status of the incoming frame */
3733                 status = stmmac_rx_status(priv, &priv->dev->stats,
3734                                 &priv->xstats, p);
3735                 /* check if managed by the DMA otherwise go ahead */
3736                 if (unlikely(status & dma_own))
3737                         break;
3738
3739                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3740                 next_entry = rx_q->cur_rx;
3741
3742                 if (priv->extend_desc)
3743                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3744                 else
3745                         np = rx_q->dma_rx + next_entry;
3746
3747                 prefetch(np);
3748
3749                 if (priv->extend_desc)
3750                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3751                                         &priv->xstats, rx_q->dma_erx + entry);
3752                 if (unlikely(status == discard_frame)) {
3753                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3754                         buf->page = NULL;
3755                         error = 1;
3756                         if (!priv->hwts_rx_en)
3757                                 priv->dev->stats.rx_errors++;
3758                 }
3759
3760                 if (unlikely(error && (status & rx_not_ls)))
3761                         goto read_again;
3762                 if (unlikely(error)) {
3763                         dev_kfree_skb(skb);
3764                         skb = NULL;
3765                         count++;
3766                         continue;
3767                 }
3768
3769                 /* Buffer is good. Go on. */
3770
3771                 prefetch(page_address(buf->page));
3772                 if (buf->sec_page)
3773                         prefetch(page_address(buf->sec_page));
3774
3775                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
3776                 len += buf1_len;
3777                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
3778                 len += buf2_len;
3779
3780                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3781                  * Type frames (LLC/LLC-SNAP)
3782                  *
3783                  * llc_snap is never checked in GMAC >= 4, so this ACS
3784                  * feature is always disabled and packets need to be
3785                  * stripped manually.
3786                  */
3787                 if (likely(!(status & rx_not_ls)) &&
3788                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3789                      unlikely(status != llc_snap))) {
3790                         if (buf2_len)
3791                                 buf2_len -= ETH_FCS_LEN;
3792                         else
3793                                 buf1_len -= ETH_FCS_LEN;
3794
3795                         len -= ETH_FCS_LEN;
3796                 }
3797
3798                 if (!skb) {
3799                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
3800                         if (!skb) {
3801                                 priv->dev->stats.rx_dropped++;
3802                                 count++;
3803                                 goto drain_data;
3804                         }
3805
3806                         dma_sync_single_for_cpu(priv->device, buf->addr,
3807                                                 buf1_len, DMA_FROM_DEVICE);
3808                         skb_copy_to_linear_data(skb, page_address(buf->page),
3809                                                 buf1_len);
3810                         skb_put(skb, buf1_len);
3811
3812                         /* Data payload copied into SKB, page ready for recycle */
3813                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3814                         buf->page = NULL;
3815                 } else if (buf1_len) {
3816                         dma_sync_single_for_cpu(priv->device, buf->addr,
3817                                                 buf1_len, DMA_FROM_DEVICE);
3818                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3819                                         buf->page, 0, buf1_len,
3820                                         priv->dma_buf_sz);
3821
3822                         /* Data payload appended into SKB */
3823                         page_pool_release_page(rx_q->page_pool, buf->page);
3824                         buf->page = NULL;
3825                 }
3826
3827                 if (buf2_len) {
3828                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
3829                                                 buf2_len, DMA_FROM_DEVICE);
3830                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3831                                         buf->sec_page, 0, buf2_len,
3832                                         priv->dma_buf_sz);
3833
3834                         /* Data payload appended into SKB */
3835                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
3836                         buf->sec_page = NULL;
3837                 }
3838
3839 drain_data:
3840                 if (likely(status & rx_not_ls))
3841                         goto read_again;
3842                 if (!skb)
3843                         continue;
3844
3845                 /* Got entire packet into SKB. Finish it. */
3846
3847                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3848                 stmmac_rx_vlan(priv->dev, skb);
3849                 skb->protocol = eth_type_trans(skb, priv->dev);
3850
3851                 if (unlikely(!coe))
3852                         skb_checksum_none_assert(skb);
3853                 else
3854                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3855
3856                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
3857                         skb_set_hash(skb, hash, hash_type);
3858
3859                 skb_record_rx_queue(skb, queue);
3860                 napi_gro_receive(&ch->rx_napi, skb);
3861                 skb = NULL;
3862
3863                 priv->dev->stats.rx_packets++;
3864                 priv->dev->stats.rx_bytes += len;
3865                 count++;
3866         }
3867
3868         if (status & rx_not_ls || skb) {
3869                 rx_q->state_saved = true;
3870                 rx_q->state.skb = skb;
3871                 rx_q->state.error = error;
3872                 rx_q->state.len = len;
3873         }
3874
3875         stmmac_rx_refill(priv, queue);
3876
3877         priv->xstats.rx_pkt_n += count;
3878
3879         return count;
3880 }
3881
3882 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3883 {
3884         struct stmmac_channel *ch =
3885                 container_of(napi, struct stmmac_channel, rx_napi);
3886         struct stmmac_priv *priv = ch->priv_data;
3887         u32 chan = ch->index;
3888         int work_done;
3889
3890         priv->xstats.napi_poll++;
3891
3892         work_done = stmmac_rx(priv, budget, chan);
3893         if (work_done < budget && napi_complete_done(napi, work_done)) {
3894                 unsigned long flags;
3895
3896                 spin_lock_irqsave(&ch->lock, flags);
3897                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
3898                 spin_unlock_irqrestore(&ch->lock, flags);
3899         }
3900
3901         return work_done;
3902 }
3903
3904 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3905 {
3906         struct stmmac_channel *ch =
3907                 container_of(napi, struct stmmac_channel, tx_napi);
3908         struct stmmac_priv *priv = ch->priv_data;
3909         u32 chan = ch->index;
3910         int work_done;
3911
3912         priv->xstats.napi_poll++;
3913
3914         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3915         work_done = min(work_done, budget);
3916
3917         if (work_done < budget && napi_complete_done(napi, work_done)) {
3918                 unsigned long flags;
3919
3920                 spin_lock_irqsave(&ch->lock, flags);
3921                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
3922                 spin_unlock_irqrestore(&ch->lock, flags);
3923         }
3924
3925         return work_done;
3926 }
3927
3928 /**
3929  *  stmmac_tx_timeout
3930  *  @dev : Pointer to net device structure
3931  *  Description: this function is called when a packet transmission fails to
3932  *   complete within a reasonable time. The driver will mark the error in the
3933  *   netdev structure and arrange for the device to be reset to a sane state
3934  *   in order to transmit a new packet.
3935  */
3936 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
3937 {
3938         struct stmmac_priv *priv = netdev_priv(dev);
3939
3940         stmmac_global_err(priv);
3941 }
3942
3943 /**
3944  *  stmmac_set_rx_mode - entry point for multicast addressing
3945  *  @dev : pointer to the device structure
3946  *  Description:
3947  *  This function is a driver entry point which gets called by the kernel
3948  *  whenever multicast addresses must be enabled/disabled.
3949  *  Return value:
3950  *  void.
3951  */
3952 static void stmmac_set_rx_mode(struct net_device *dev)
3953 {
3954         struct stmmac_priv *priv = netdev_priv(dev);
3955
3956         stmmac_set_filter(priv, priv->hw, dev);
3957 }
3958
3959 /**
3960  *  stmmac_change_mtu - entry point to change MTU size for the device.
3961  *  @dev : device pointer.
3962  *  @new_mtu : the new MTU size for the device.
3963  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3964  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3965  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3966  *  Return value:
3967  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3968  *  file on failure.
3969  */
3970 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3971 {
3972         struct stmmac_priv *priv = netdev_priv(dev);
3973         int txfifosz = priv->plat->tx_fifo_size;
3974
3975         if (txfifosz == 0)
3976                 txfifosz = priv->dma_cap.tx_fifo_size;
3977
3978         txfifosz /= priv->plat->tx_queues_to_use;
3979
3980         if (netif_running(dev)) {
3981                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3982                 return -EBUSY;
3983         }
3984
3985         new_mtu = STMMAC_ALIGN(new_mtu);
3986
3987         /* If condition true, FIFO is too small or MTU too large */
3988         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
3989                 return -EINVAL;
3990
3991         dev->mtu = new_mtu;
3992
3993         netdev_update_features(dev);
3994
3995         return 0;
3996 }
3997
3998 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3999                                              netdev_features_t features)
4000 {
4001         struct stmmac_priv *priv = netdev_priv(dev);
4002
4003         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
4004                 features &= ~NETIF_F_RXCSUM;
4005
4006         if (!priv->plat->tx_coe)
4007                 features &= ~NETIF_F_CSUM_MASK;
4008
4009         /* Some GMAC devices have a bugged Jumbo frame support that
4010          * needs to have the Tx COE disabled for oversized frames
4011          * (due to limited buffer sizes). In this case we disable
4012          * the TX csum insertion in the TDES and not use SF.
4013          */
4014         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
4015                 features &= ~NETIF_F_CSUM_MASK;
4016
4017         /* Disable tso if asked by ethtool */
4018         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4019                 if (features & NETIF_F_TSO)
4020                         priv->tso = true;
4021                 else
4022                         priv->tso = false;
4023         }
4024
4025         return features;
4026 }
4027
4028 static int stmmac_set_features(struct net_device *netdev,
4029                                netdev_features_t features)
4030 {
4031         struct stmmac_priv *priv = netdev_priv(netdev);
4032         bool sph_en;
4033         u32 chan;
4034
4035         /* Keep the COE Type in case of csum is supporting */
4036         if (features & NETIF_F_RXCSUM)
4037                 priv->hw->rx_csum = priv->plat->rx_coe;
4038         else
4039                 priv->hw->rx_csum = 0;
4040         /* No check needed because rx_coe has been set before and it will be
4041          * fixed in case of issue.
4042          */
4043         stmmac_rx_ipc(priv, priv->hw);
4044
4045         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
4046         for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
4047                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
4048
4049         return 0;
4050 }
4051
4052 /**
4053  *  stmmac_interrupt - main ISR
4054  *  @irq: interrupt number.
4055  *  @dev_id: to pass the net device pointer (must be valid).
4056  *  Description: this is the main driver interrupt service routine.
4057  *  It can call:
4058  *  o DMA service routine (to manage incoming frame reception and transmission
4059  *    status)
4060  *  o Core interrupts to manage: remote wake-up, management counter, LPI
4061  *    interrupts.
4062  */
4063 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
4064 {
4065         struct net_device *dev = (struct net_device *)dev_id;
4066         struct stmmac_priv *priv = netdev_priv(dev);
4067         u32 rx_cnt = priv->plat->rx_queues_to_use;
4068         u32 tx_cnt = priv->plat->tx_queues_to_use;
4069         u32 queues_count;
4070         u32 queue;
4071         bool xmac;
4072
4073         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
4074         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
4075
4076         if (priv->irq_wake)
4077                 pm_wakeup_event(priv->device, 0);
4078
4079         /* Check if adapter is up */
4080         if (test_bit(STMMAC_DOWN, &priv->state))
4081                 return IRQ_HANDLED;
4082         /* Check if a fatal error happened */
4083         if (stmmac_safety_feat_interrupt(priv))
4084                 return IRQ_HANDLED;
4085
4086         /* To handle GMAC own interrupts */
4087         if ((priv->plat->has_gmac) || xmac) {
4088                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
4089                 int mtl_status;
4090
4091                 if (unlikely(status)) {
4092                         /* For LPI we need to save the tx status */
4093                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
4094                                 priv->tx_path_in_lpi_mode = true;
4095                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
4096                                 priv->tx_path_in_lpi_mode = false;
4097                 }
4098
4099                 for (queue = 0; queue < queues_count; queue++) {
4100                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4101
4102                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
4103                                                                 queue);
4104                         if (mtl_status != -EINVAL)
4105                                 status |= mtl_status;
4106
4107                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
4108                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
4109                                                        rx_q->rx_tail_addr,
4110                                                        queue);
4111                 }
4112
4113                 /* PCS link status */
4114                 if (priv->hw->pcs) {
4115                         if (priv->xstats.pcs_link)
4116                                 netif_carrier_on(dev);
4117                         else
4118                                 netif_carrier_off(dev);
4119                 }
4120         }
4121
4122         /* To handle DMA interrupts */
4123         stmmac_dma_interrupt(priv);
4124
4125         return IRQ_HANDLED;
4126 }
4127
4128 #ifdef CONFIG_NET_POLL_CONTROLLER
4129 /* Polling receive - used by NETCONSOLE and other diagnostic tools
4130  * to allow network I/O with interrupts disabled.
4131  */
4132 static void stmmac_poll_controller(struct net_device *dev)
4133 {
4134         disable_irq(dev->irq);
4135         stmmac_interrupt(dev->irq, dev);
4136         enable_irq(dev->irq);
4137 }
4138 #endif
4139
4140 /**
4141  *  stmmac_ioctl - Entry point for the Ioctl
4142  *  @dev: Device pointer.
4143  *  @rq: An IOCTL specefic structure, that can contain a pointer to
4144  *  a proprietary structure used to pass information to the driver.
4145  *  @cmd: IOCTL command
4146  *  Description:
4147  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
4148  */
4149 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4150 {
4151         struct stmmac_priv *priv = netdev_priv (dev);
4152         int ret = -EOPNOTSUPP;
4153
4154         if (!netif_running(dev))
4155                 return -EINVAL;
4156
4157         switch (cmd) {
4158         case SIOCGMIIPHY:
4159         case SIOCGMIIREG:
4160         case SIOCSMIIREG:
4161                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
4162                 break;
4163         case SIOCSHWTSTAMP:
4164                 ret = stmmac_hwtstamp_set(dev, rq);
4165                 break;
4166         case SIOCGHWTSTAMP:
4167                 ret = stmmac_hwtstamp_get(dev, rq);
4168                 break;
4169         default:
4170                 break;
4171         }
4172
4173         return ret;
4174 }
4175
4176 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4177                                     void *cb_priv)
4178 {
4179         struct stmmac_priv *priv = cb_priv;
4180         int ret = -EOPNOTSUPP;
4181
4182         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
4183                 return ret;
4184
4185         stmmac_disable_all_queues(priv);
4186
4187         switch (type) {
4188         case TC_SETUP_CLSU32:
4189                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
4190                 break;
4191         case TC_SETUP_CLSFLOWER:
4192                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
4193                 break;
4194         default:
4195                 break;
4196         }
4197
4198         stmmac_enable_all_queues(priv);
4199         return ret;
4200 }
4201
4202 static LIST_HEAD(stmmac_block_cb_list);
4203
4204 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
4205                            void *type_data)
4206 {
4207         struct stmmac_priv *priv = netdev_priv(ndev);
4208
4209         switch (type) {
4210         case TC_SETUP_BLOCK:
4211                 return flow_block_cb_setup_simple(type_data,
4212                                                   &stmmac_block_cb_list,
4213                                                   stmmac_setup_tc_block_cb,
4214                                                   priv, priv, true);
4215         case TC_SETUP_QDISC_CBS:
4216                 return stmmac_tc_setup_cbs(priv, priv, type_data);
4217         case TC_SETUP_QDISC_TAPRIO:
4218                 return stmmac_tc_setup_taprio(priv, priv, type_data);
4219         case TC_SETUP_QDISC_ETF:
4220                 return stmmac_tc_setup_etf(priv, priv, type_data);
4221         default:
4222                 return -EOPNOTSUPP;
4223         }
4224 }
4225
4226 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
4227                                struct net_device *sb_dev)
4228 {
4229         int gso = skb_shinfo(skb)->gso_type;
4230
4231         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
4232                 /*
4233                  * There is no way to determine the number of TSO/USO
4234                  * capable Queues. Let's use always the Queue 0
4235                  * because if TSO/USO is supported then at least this
4236                  * one will be capable.
4237                  */
4238                 return 0;
4239         }
4240
4241         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
4242 }
4243
4244 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
4245 {
4246         struct stmmac_priv *priv = netdev_priv(ndev);
4247         int ret = 0;
4248
4249         ret = eth_mac_addr(ndev, addr);
4250         if (ret)
4251                 return ret;
4252
4253         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
4254
4255         return ret;
4256 }
4257
4258 #ifdef CONFIG_DEBUG_FS
4259 static struct dentry *stmmac_fs_dir;
4260
4261 static void sysfs_display_ring(void *head, int size, int extend_desc,
4262                                struct seq_file *seq)
4263 {
4264         int i;
4265         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
4266         struct dma_desc *p = (struct dma_desc *)head;
4267
4268         for (i = 0; i < size; i++) {
4269                 if (extend_desc) {
4270                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4271                                    i, (unsigned int)virt_to_phys(ep),
4272                                    le32_to_cpu(ep->basic.des0),
4273                                    le32_to_cpu(ep->basic.des1),
4274                                    le32_to_cpu(ep->basic.des2),
4275                                    le32_to_cpu(ep->basic.des3));
4276                         ep++;
4277                 } else {
4278                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4279                                    i, (unsigned int)virt_to_phys(p),
4280                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
4281                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
4282                         p++;
4283                 }
4284                 seq_printf(seq, "\n");
4285         }
4286 }
4287
4288 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
4289 {
4290         struct net_device *dev = seq->private;
4291         struct stmmac_priv *priv = netdev_priv(dev);
4292         u32 rx_count = priv->plat->rx_queues_to_use;
4293         u32 tx_count = priv->plat->tx_queues_to_use;
4294         u32 queue;
4295
4296         if ((dev->flags & IFF_UP) == 0)
4297                 return 0;
4298
4299         for (queue = 0; queue < rx_count; queue++) {
4300                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4301
4302                 seq_printf(seq, "RX Queue %d:\n", queue);
4303
4304                 if (priv->extend_desc) {
4305                         seq_printf(seq, "Extended descriptor ring:\n");
4306                         sysfs_display_ring((void *)rx_q->dma_erx,
4307                                            DMA_RX_SIZE, 1, seq);
4308                 } else {
4309                         seq_printf(seq, "Descriptor ring:\n");
4310                         sysfs_display_ring((void *)rx_q->dma_rx,
4311                                            DMA_RX_SIZE, 0, seq);
4312                 }
4313         }
4314
4315         for (queue = 0; queue < tx_count; queue++) {
4316                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4317
4318                 seq_printf(seq, "TX Queue %d:\n", queue);
4319
4320                 if (priv->extend_desc) {
4321                         seq_printf(seq, "Extended descriptor ring:\n");
4322                         sysfs_display_ring((void *)tx_q->dma_etx,
4323                                            DMA_TX_SIZE, 1, seq);
4324                 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
4325                         seq_printf(seq, "Descriptor ring:\n");
4326                         sysfs_display_ring((void *)tx_q->dma_tx,
4327                                            DMA_TX_SIZE, 0, seq);
4328                 }
4329         }
4330
4331         return 0;
4332 }
4333 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
4334
4335 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
4336 {
4337         struct net_device *dev = seq->private;
4338         struct stmmac_priv *priv = netdev_priv(dev);
4339
4340         if (!priv->hw_cap_support) {
4341                 seq_printf(seq, "DMA HW features not supported\n");
4342                 return 0;
4343         }
4344
4345         seq_printf(seq, "==============================\n");
4346         seq_printf(seq, "\tDMA HW features\n");
4347         seq_printf(seq, "==============================\n");
4348
4349         seq_printf(seq, "\t10/100 Mbps: %s\n",
4350                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4351         seq_printf(seq, "\t1000 Mbps: %s\n",
4352                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
4353         seq_printf(seq, "\tHalf duplex: %s\n",
4354                    (priv->dma_cap.half_duplex) ? "Y" : "N");
4355         seq_printf(seq, "\tHash Filter: %s\n",
4356                    (priv->dma_cap.hash_filter) ? "Y" : "N");
4357         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4358                    (priv->dma_cap.multi_addr) ? "Y" : "N");
4359         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4360                    (priv->dma_cap.pcs) ? "Y" : "N");
4361         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4362                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
4363         seq_printf(seq, "\tPMT Remote wake up: %s\n",
4364                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4365         seq_printf(seq, "\tPMT Magic Frame: %s\n",
4366                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4367         seq_printf(seq, "\tRMON module: %s\n",
4368                    (priv->dma_cap.rmon) ? "Y" : "N");
4369         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4370                    (priv->dma_cap.time_stamp) ? "Y" : "N");
4371         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4372                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
4373         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4374                    (priv->dma_cap.eee) ? "Y" : "N");
4375         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4376         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4377                    (priv->dma_cap.tx_coe) ? "Y" : "N");
4378         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4379                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4380                            (priv->dma_cap.rx_coe) ? "Y" : "N");
4381         } else {
4382                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4383                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4384                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4385                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4386         }
4387         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4388                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4389         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4390                    priv->dma_cap.number_rx_channel);
4391         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4392                    priv->dma_cap.number_tx_channel);
4393         seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
4394                    priv->dma_cap.number_rx_queues);
4395         seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
4396                    priv->dma_cap.number_tx_queues);
4397         seq_printf(seq, "\tEnhanced descriptors: %s\n",
4398                    (priv->dma_cap.enh_desc) ? "Y" : "N");
4399         seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
4400         seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
4401         seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
4402         seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
4403         seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
4404                    priv->dma_cap.pps_out_num);
4405         seq_printf(seq, "\tSafety Features: %s\n",
4406                    priv->dma_cap.asp ? "Y" : "N");
4407         seq_printf(seq, "\tFlexible RX Parser: %s\n",
4408                    priv->dma_cap.frpsel ? "Y" : "N");
4409         seq_printf(seq, "\tEnhanced Addressing: %d\n",
4410                    priv->dma_cap.addr64);
4411         seq_printf(seq, "\tReceive Side Scaling: %s\n",
4412                    priv->dma_cap.rssen ? "Y" : "N");
4413         seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
4414                    priv->dma_cap.vlhash ? "Y" : "N");
4415         seq_printf(seq, "\tSplit Header: %s\n",
4416                    priv->dma_cap.sphen ? "Y" : "N");
4417         seq_printf(seq, "\tVLAN TX Insertion: %s\n",
4418                    priv->dma_cap.vlins ? "Y" : "N");
4419         seq_printf(seq, "\tDouble VLAN: %s\n",
4420                    priv->dma_cap.dvlan ? "Y" : "N");
4421         seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
4422                    priv->dma_cap.l3l4fnum);
4423         seq_printf(seq, "\tARP Offloading: %s\n",
4424                    priv->dma_cap.arpoffsel ? "Y" : "N");
4425         seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
4426                    priv->dma_cap.estsel ? "Y" : "N");
4427         seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
4428                    priv->dma_cap.fpesel ? "Y" : "N");
4429         seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
4430                    priv->dma_cap.tbssel ? "Y" : "N");
4431         return 0;
4432 }
4433 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4434
4435 /* Use network device events to rename debugfs file entries.
4436  */
4437 static int stmmac_device_event(struct notifier_block *unused,
4438                                unsigned long event, void *ptr)
4439 {
4440         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4441         struct stmmac_priv *priv = netdev_priv(dev);
4442
4443         if (dev->netdev_ops != &stmmac_netdev_ops)
4444                 goto done;
4445
4446         switch (event) {
4447         case NETDEV_CHANGENAME:
4448                 if (priv->dbgfs_dir)
4449                         priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
4450                                                          priv->dbgfs_dir,
4451                                                          stmmac_fs_dir,
4452                                                          dev->name);
4453                 break;
4454         }
4455 done:
4456         return NOTIFY_DONE;
4457 }
4458
4459 static struct notifier_block stmmac_notifier = {
4460         .notifier_call = stmmac_device_event,
4461 };
4462
4463 static void stmmac_init_fs(struct net_device *dev)
4464 {
4465         struct stmmac_priv *priv = netdev_priv(dev);
4466
4467         rtnl_lock();
4468
4469         /* Create per netdev entries */
4470         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4471
4472         /* Entry to report DMA RX/TX rings */
4473         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
4474                             &stmmac_rings_status_fops);
4475
4476         /* Entry to report the DMA HW features */
4477         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
4478                             &stmmac_dma_cap_fops);
4479
4480         rtnl_unlock();
4481 }
4482
4483 static void stmmac_exit_fs(struct net_device *dev)
4484 {
4485         struct stmmac_priv *priv = netdev_priv(dev);
4486
4487         debugfs_remove_recursive(priv->dbgfs_dir);
4488 }
4489 #endif /* CONFIG_DEBUG_FS */
4490
4491 static u32 stmmac_vid_crc32_le(__le16 vid_le)
4492 {
4493         unsigned char *data = (unsigned char *)&vid_le;
4494         unsigned char data_byte = 0;
4495         u32 crc = ~0x0;
4496         u32 temp = 0;
4497         int i, bits;
4498
4499         bits = get_bitmask_order(VLAN_VID_MASK);
4500         for (i = 0; i < bits; i++) {
4501                 if ((i % 8) == 0)
4502                         data_byte = data[i / 8];
4503
4504                 temp = ((crc & 1) ^ data_byte) & 1;
4505                 crc >>= 1;
4506                 data_byte >>= 1;
4507
4508                 if (temp)
4509                         crc ^= 0xedb88320;
4510         }
4511
4512         return crc;
4513 }
4514
4515 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
4516 {
4517         u32 crc, hash = 0;
4518         __le16 pmatch = 0;
4519         int count = 0;
4520         u16 vid = 0;
4521
4522         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
4523                 __le16 vid_le = cpu_to_le16(vid);
4524                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
4525                 hash |= (1 << crc);
4526                 count++;
4527         }
4528
4529         if (!priv->dma_cap.vlhash) {
4530                 if (count > 2) /* VID = 0 always passes filter */
4531                         return -EOPNOTSUPP;
4532
4533                 pmatch = cpu_to_le16(vid);
4534                 hash = 0;
4535         }
4536
4537         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
4538 }
4539
4540 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
4541 {
4542         struct stmmac_priv *priv = netdev_priv(ndev);
4543         bool is_double = false;
4544         int ret;
4545
4546         if (be16_to_cpu(proto) == ETH_P_8021AD)
4547                 is_double = true;
4548
4549         set_bit(vid, priv->active_vlans);
4550         ret = stmmac_vlan_update(priv, is_double);
4551         if (ret) {
4552                 clear_bit(vid, priv->active_vlans);
4553                 return ret;
4554         }
4555
4556         if (priv->hw->num_vlan) {
4557                 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
4558                 if (ret)
4559                         return ret;
4560         }
4561
4562         return 0;
4563 }
4564
4565 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
4566 {
4567         struct stmmac_priv *priv = netdev_priv(ndev);
4568         bool is_double = false;
4569         int ret;
4570
4571         if (be16_to_cpu(proto) == ETH_P_8021AD)
4572                 is_double = true;
4573
4574         clear_bit(vid, priv->active_vlans);
4575
4576         if (priv->hw->num_vlan) {
4577                 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
4578                 if (ret)
4579                         return ret;
4580         }
4581
4582         return stmmac_vlan_update(priv, is_double);
4583 }
4584
4585 static const struct net_device_ops stmmac_netdev_ops = {
4586         .ndo_open = stmmac_open,
4587         .ndo_start_xmit = stmmac_xmit,
4588         .ndo_stop = stmmac_release,
4589         .ndo_change_mtu = stmmac_change_mtu,
4590         .ndo_fix_features = stmmac_fix_features,
4591         .ndo_set_features = stmmac_set_features,
4592         .ndo_set_rx_mode = stmmac_set_rx_mode,
4593         .ndo_tx_timeout = stmmac_tx_timeout,
4594         .ndo_do_ioctl = stmmac_ioctl,
4595         .ndo_setup_tc = stmmac_setup_tc,
4596         .ndo_select_queue = stmmac_select_queue,
4597 #ifdef CONFIG_NET_POLL_CONTROLLER
4598         .ndo_poll_controller = stmmac_poll_controller,
4599 #endif
4600         .ndo_set_mac_address = stmmac_set_mac_address,
4601         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
4602         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
4603 };
4604
4605 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4606 {
4607         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4608                 return;
4609         if (test_bit(STMMAC_DOWN, &priv->state))
4610                 return;
4611
4612         netdev_err(priv->dev, "Reset adapter.\n");
4613
4614         rtnl_lock();
4615         netif_trans_update(priv->dev);
4616         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4617                 usleep_range(1000, 2000);
4618
4619         set_bit(STMMAC_DOWN, &priv->state);
4620         dev_close(priv->dev);
4621         dev_open(priv->dev, NULL);
4622         clear_bit(STMMAC_DOWN, &priv->state);
4623         clear_bit(STMMAC_RESETING, &priv->state);
4624         rtnl_unlock();
4625 }
4626
4627 static void stmmac_service_task(struct work_struct *work)
4628 {
4629         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4630                         service_task);
4631
4632         stmmac_reset_subtask(priv);
4633         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4634 }
4635
4636 /**
4637  *  stmmac_hw_init - Init the MAC device
4638  *  @priv: driver private structure
4639  *  Description: this function is to configure the MAC device according to
4640  *  some platform parameters or the HW capability register. It prepares the
4641  *  driver to use either ring or chain modes and to setup either enhanced or
4642  *  normal descriptors.
4643  */
4644 static int stmmac_hw_init(struct stmmac_priv *priv)
4645 {
4646         int ret;
4647
4648         /* dwmac-sun8i only work in chain mode */
4649         if (priv->plat->has_sun8i)
4650                 chain_mode = 1;
4651         priv->chain_mode = chain_mode;
4652
4653         /* Initialize HW Interface */
4654         ret = stmmac_hwif_init(priv);
4655         if (ret)
4656                 return ret;
4657
4658         /* Get the HW capability (new GMAC newer than 3.50a) */
4659         priv->hw_cap_support = stmmac_get_hw_features(priv);
4660         if (priv->hw_cap_support) {
4661                 dev_info(priv->device, "DMA HW capability register supported\n");
4662
4663                 /* We can override some gmac/dma configuration fields: e.g.
4664                  * enh_desc, tx_coe (e.g. that are passed through the
4665                  * platform) with the values from the HW capability
4666                  * register (if supported).
4667                  */
4668                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4669                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4670                 priv->hw->pmt = priv->plat->pmt;
4671                 if (priv->dma_cap.hash_tb_sz) {
4672                         priv->hw->multicast_filter_bins =
4673                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
4674                         priv->hw->mcast_bits_log2 =
4675                                         ilog2(priv->hw->multicast_filter_bins);
4676                 }
4677
4678                 /* TXCOE doesn't work in thresh DMA mode */
4679                 if (priv->plat->force_thresh_dma_mode)
4680                         priv->plat->tx_coe = 0;
4681                 else
4682                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4683
4684                 /* In case of GMAC4 rx_coe is from HW cap register. */
4685                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4686
4687                 if (priv->dma_cap.rx_coe_type2)
4688                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4689                 else if (priv->dma_cap.rx_coe_type1)
4690                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4691
4692         } else {
4693                 dev_info(priv->device, "No HW DMA feature register supported\n");
4694         }
4695
4696         if (priv->plat->rx_coe) {
4697                 priv->hw->rx_csum = priv->plat->rx_coe;
4698                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4699                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4700                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4701         }
4702         if (priv->plat->tx_coe)
4703                 dev_info(priv->device, "TX Checksum insertion supported\n");
4704
4705         if (priv->plat->pmt) {
4706                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4707                 device_set_wakeup_capable(priv->device, 1);
4708         }
4709
4710         if (priv->dma_cap.tsoen)
4711                 dev_info(priv->device, "TSO supported\n");
4712
4713         /* Run HW quirks, if any */
4714         if (priv->hwif_quirks) {
4715                 ret = priv->hwif_quirks(priv);
4716                 if (ret)
4717                         return ret;
4718         }
4719
4720         /* Rx Watchdog is available in the COREs newer than the 3.40.
4721          * In some case, for example on bugged HW this feature
4722          * has to be disable and this can be done by passing the
4723          * riwt_off field from the platform.
4724          */
4725         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4726             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4727                 priv->use_riwt = 1;
4728                 dev_info(priv->device,
4729                          "Enable RX Mitigation via HW Watchdog Timer\n");
4730         }
4731
4732         return 0;
4733 }
4734
4735 /**
4736  * stmmac_dvr_probe
4737  * @device: device pointer
4738  * @plat_dat: platform data pointer
4739  * @res: stmmac resource pointer
4740  * Description: this is the main probe function used to
4741  * call the alloc_etherdev, allocate the priv structure.
4742  * Return:
4743  * returns 0 on success, otherwise errno.
4744  */
4745 int stmmac_dvr_probe(struct device *device,
4746                      struct plat_stmmacenet_data *plat_dat,
4747                      struct stmmac_resources *res)
4748 {
4749         struct net_device *ndev = NULL;
4750         struct stmmac_priv *priv;
4751         u32 queue, rxq, maxq;
4752         int i, ret = 0;
4753
4754         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4755                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4756         if (!ndev)
4757                 return -ENOMEM;
4758
4759         SET_NETDEV_DEV(ndev, device);
4760
4761         priv = netdev_priv(ndev);
4762         priv->device = device;
4763         priv->dev = ndev;
4764
4765         stmmac_set_ethtool_ops(ndev);
4766         priv->pause = pause;
4767         priv->plat = plat_dat;
4768         priv->ioaddr = res->addr;
4769         priv->dev->base_addr = (unsigned long)res->addr;
4770
4771         priv->dev->irq = res->irq;
4772         priv->wol_irq = res->wol_irq;
4773         priv->lpi_irq = res->lpi_irq;
4774
4775         if (!IS_ERR_OR_NULL(res->mac))
4776                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4777
4778         dev_set_drvdata(device, priv->dev);
4779
4780         /* Verify driver arguments */
4781         stmmac_verify_args();
4782
4783         /* Allocate workqueue */
4784         priv->wq = create_singlethread_workqueue("stmmac_wq");
4785         if (!priv->wq) {
4786                 dev_err(priv->device, "failed to create workqueue\n");
4787                 return -ENOMEM;
4788         }
4789
4790         INIT_WORK(&priv->service_task, stmmac_service_task);
4791
4792         /* Override with kernel parameters if supplied XXX CRS XXX
4793          * this needs to have multiple instances
4794          */
4795         if ((phyaddr >= 0) && (phyaddr <= 31))
4796                 priv->plat->phy_addr = phyaddr;
4797
4798         if (priv->plat->stmmac_rst) {
4799                 ret = reset_control_assert(priv->plat->stmmac_rst);
4800                 reset_control_deassert(priv->plat->stmmac_rst);
4801                 /* Some reset controllers have only reset callback instead of
4802                  * assert + deassert callbacks pair.
4803                  */
4804                 if (ret == -ENOTSUPP)
4805                         reset_control_reset(priv->plat->stmmac_rst);
4806         }
4807
4808         /* Init MAC and get the capabilities */
4809         ret = stmmac_hw_init(priv);
4810         if (ret)
4811                 goto error_hw_init;
4812
4813         stmmac_check_ether_addr(priv);
4814
4815         /* Configure real RX and TX queues */
4816         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4817         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4818
4819         ndev->netdev_ops = &stmmac_netdev_ops;
4820
4821         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4822                             NETIF_F_RXCSUM;
4823
4824         ret = stmmac_tc_init(priv, priv);
4825         if (!ret) {
4826                 ndev->hw_features |= NETIF_F_HW_TC;
4827         }
4828
4829         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4830                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4831                 if (priv->plat->has_gmac4)
4832                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
4833                 priv->tso = true;
4834                 dev_info(priv->device, "TSO feature enabled\n");
4835         }
4836
4837         if (priv->dma_cap.sphen) {
4838                 ndev->hw_features |= NETIF_F_GRO;
4839                 priv->sph = true;
4840                 dev_info(priv->device, "SPH feature enabled\n");
4841         }
4842
4843         if (priv->dma_cap.addr64) {
4844                 ret = dma_set_mask_and_coherent(device,
4845                                 DMA_BIT_MASK(priv->dma_cap.addr64));
4846                 if (!ret) {
4847                         dev_info(priv->device, "Using %d bits DMA width\n",
4848                                  priv->dma_cap.addr64);
4849
4850                         /*
4851                          * If more than 32 bits can be addressed, make sure to
4852                          * enable enhanced addressing mode.
4853                          */
4854                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
4855                                 priv->plat->dma_cfg->eame = true;
4856                 } else {
4857                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4858                         if (ret) {
4859                                 dev_err(priv->device, "Failed to set DMA Mask\n");
4860                                 goto error_hw_init;
4861                         }
4862
4863                         priv->dma_cap.addr64 = 32;
4864                 }
4865         }
4866
4867         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4868         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4869 #ifdef STMMAC_VLAN_TAG_USED
4870         /* Both mac100 and gmac support receive VLAN tag detection */
4871         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4872         if (priv->dma_cap.vlhash) {
4873                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4874                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4875         }
4876         if (priv->dma_cap.vlins) {
4877                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4878                 if (priv->dma_cap.dvlan)
4879                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
4880         }
4881 #endif
4882         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4883
4884         /* Initialize RSS */
4885         rxq = priv->plat->rx_queues_to_use;
4886         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
4887         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
4888                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
4889
4890         if (priv->dma_cap.rssen && priv->plat->rss_en)
4891                 ndev->features |= NETIF_F_RXHASH;
4892
4893         /* MTU range: 46 - hw-specific max */
4894         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4895         if (priv->plat->has_xgmac)
4896                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4897         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4898                 ndev->max_mtu = JUMBO_LEN;
4899         else
4900                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4901         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4902          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4903          */
4904         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4905             (priv->plat->maxmtu >= ndev->min_mtu))
4906                 ndev->max_mtu = priv->plat->maxmtu;
4907         else if (priv->plat->maxmtu < ndev->min_mtu)
4908                 dev_warn(priv->device,
4909                          "%s: warning: maxmtu having invalid value (%d)\n",
4910                          __func__, priv->plat->maxmtu);
4911
4912         if (flow_ctrl)
4913                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4914
4915         /* Setup channels NAPI */
4916         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4917
4918         for (queue = 0; queue < maxq; queue++) {
4919                 struct stmmac_channel *ch = &priv->channel[queue];
4920
4921                 spin_lock_init(&ch->lock);
4922                 ch->priv_data = priv;
4923                 ch->index = queue;
4924
4925                 if (queue < priv->plat->rx_queues_to_use) {
4926                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4927                                        NAPI_POLL_WEIGHT);
4928                 }
4929                 if (queue < priv->plat->tx_queues_to_use) {
4930                         netif_tx_napi_add(ndev, &ch->tx_napi,
4931                                           stmmac_napi_poll_tx,
4932                                           NAPI_POLL_WEIGHT);
4933                 }
4934         }
4935
4936         mutex_init(&priv->lock);
4937
4938         /* If a specific clk_csr value is passed from the platform
4939          * this means that the CSR Clock Range selection cannot be
4940          * changed at run-time and it is fixed. Viceversa the driver'll try to
4941          * set the MDC clock dynamically according to the csr actual
4942          * clock input.
4943          */
4944         if (priv->plat->clk_csr >= 0)
4945                 priv->clk_csr = priv->plat->clk_csr;
4946         else
4947                 stmmac_clk_csr_set(priv);
4948
4949         stmmac_check_pcs_mode(priv);
4950
4951         if (priv->hw->pcs != STMMAC_PCS_TBI &&
4952             priv->hw->pcs != STMMAC_PCS_RTBI) {
4953                 /* MDIO bus Registration */
4954                 ret = stmmac_mdio_register(ndev);
4955                 if (ret < 0) {
4956                         dev_err(priv->device,
4957                                 "%s: MDIO bus (id: %d) registration failed",
4958                                 __func__, priv->plat->bus_id);
4959                         goto error_mdio_register;
4960                 }
4961         }
4962
4963         ret = stmmac_phy_setup(priv);
4964         if (ret) {
4965                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4966                 goto error_phy_setup;
4967         }
4968
4969         ret = register_netdev(ndev);
4970         if (ret) {
4971                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4972                         __func__, ret);
4973                 goto error_netdev_register;
4974         }
4975
4976         if (priv->plat->serdes_powerup) {
4977                 ret = priv->plat->serdes_powerup(ndev,
4978                                                  priv->plat->bsp_priv);
4979
4980                 if (ret < 0)
4981                         goto error_serdes_powerup;
4982         }
4983
4984 #ifdef CONFIG_DEBUG_FS
4985         stmmac_init_fs(ndev);
4986 #endif
4987
4988         return ret;
4989
4990 error_serdes_powerup:
4991         unregister_netdev(ndev);
4992 error_netdev_register:
4993         phylink_destroy(priv->phylink);
4994 error_phy_setup:
4995         if (priv->hw->pcs != STMMAC_PCS_TBI &&
4996             priv->hw->pcs != STMMAC_PCS_RTBI)
4997                 stmmac_mdio_unregister(ndev);
4998 error_mdio_register:
4999         for (queue = 0; queue < maxq; queue++) {
5000                 struct stmmac_channel *ch = &priv->channel[queue];
5001
5002                 if (queue < priv->plat->rx_queues_to_use)
5003                         netif_napi_del(&ch->rx_napi);
5004                 if (queue < priv->plat->tx_queues_to_use)
5005                         netif_napi_del(&ch->tx_napi);
5006         }
5007 error_hw_init:
5008         destroy_workqueue(priv->wq);
5009
5010         return ret;
5011 }
5012 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
5013
5014 /**
5015  * stmmac_dvr_remove
5016  * @dev: device pointer
5017  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
5018  * changes the link status, releases the DMA descriptor rings.
5019  */
5020 int stmmac_dvr_remove(struct device *dev)
5021 {
5022         struct net_device *ndev = dev_get_drvdata(dev);
5023         struct stmmac_priv *priv = netdev_priv(ndev);
5024
5025         netdev_info(priv->dev, "%s: removing driver", __func__);
5026
5027         stmmac_stop_all_dma(priv);
5028
5029         if (priv->plat->serdes_powerdown)
5030                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
5031
5032         stmmac_mac_set(priv, priv->ioaddr, false);
5033         netif_carrier_off(ndev);
5034         unregister_netdev(ndev);
5035 #ifdef CONFIG_DEBUG_FS
5036         stmmac_exit_fs(ndev);
5037 #endif
5038         phylink_destroy(priv->phylink);
5039         if (priv->plat->stmmac_rst)
5040                 reset_control_assert(priv->plat->stmmac_rst);
5041         clk_disable_unprepare(priv->plat->pclk);
5042         clk_disable_unprepare(priv->plat->stmmac_clk);
5043         if (priv->hw->pcs != STMMAC_PCS_TBI &&
5044             priv->hw->pcs != STMMAC_PCS_RTBI)
5045                 stmmac_mdio_unregister(ndev);
5046         destroy_workqueue(priv->wq);
5047         mutex_destroy(&priv->lock);
5048
5049         return 0;
5050 }
5051 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
5052
5053 /**
5054  * stmmac_suspend - suspend callback
5055  * @dev: device pointer
5056  * Description: this is the function to suspend the device and it is called
5057  * by the platform driver to stop the network queue, release the resources,
5058  * program the PMT register (for WoL), clean and release driver resources.
5059  */
5060 int stmmac_suspend(struct device *dev)
5061 {
5062         struct net_device *ndev = dev_get_drvdata(dev);
5063         struct stmmac_priv *priv = netdev_priv(ndev);
5064         u32 chan;
5065
5066         if (!ndev || !netif_running(ndev))
5067                 return 0;
5068
5069         phylink_mac_change(priv->phylink, false);
5070
5071         mutex_lock(&priv->lock);
5072
5073         netif_device_detach(ndev);
5074         stmmac_stop_all_queues(priv);
5075
5076         stmmac_disable_all_queues(priv);
5077
5078         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
5079                 del_timer_sync(&priv->tx_queue[chan].txtimer);
5080
5081         /* Stop TX/RX DMA */
5082         stmmac_stop_all_dma(priv);
5083
5084         if (priv->plat->serdes_powerdown)
5085                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
5086
5087         /* Enable Power down mode by programming the PMT regs */
5088         if (device_may_wakeup(priv->device)) {
5089                 stmmac_pmt(priv, priv->hw, priv->wolopts);
5090                 priv->irq_wake = 1;
5091         } else {
5092                 mutex_unlock(&priv->lock);
5093                 rtnl_lock();
5094                 phylink_stop(priv->phylink);
5095                 rtnl_unlock();
5096                 mutex_lock(&priv->lock);
5097
5098                 stmmac_mac_set(priv, priv->ioaddr, false);
5099                 pinctrl_pm_select_sleep_state(priv->device);
5100                 /* Disable clock in case of PWM is off */
5101                 if (priv->plat->clk_ptp_ref)
5102                         clk_disable_unprepare(priv->plat->clk_ptp_ref);
5103                 clk_disable_unprepare(priv->plat->pclk);
5104                 clk_disable_unprepare(priv->plat->stmmac_clk);
5105         }
5106         mutex_unlock(&priv->lock);
5107
5108         priv->speed = SPEED_UNKNOWN;
5109         return 0;
5110 }
5111 EXPORT_SYMBOL_GPL(stmmac_suspend);
5112
5113 /**
5114  * stmmac_reset_queues_param - reset queue parameters
5115  * @dev: device pointer
5116  */
5117 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
5118 {
5119         u32 rx_cnt = priv->plat->rx_queues_to_use;
5120         u32 tx_cnt = priv->plat->tx_queues_to_use;
5121         u32 queue;
5122
5123         for (queue = 0; queue < rx_cnt; queue++) {
5124                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5125
5126                 rx_q->cur_rx = 0;
5127                 rx_q->dirty_rx = 0;
5128         }
5129
5130         for (queue = 0; queue < tx_cnt; queue++) {
5131                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5132
5133                 tx_q->cur_tx = 0;
5134                 tx_q->dirty_tx = 0;
5135                 tx_q->mss = 0;
5136         }
5137 }
5138
5139 /**
5140  * stmmac_resume - resume callback
5141  * @dev: device pointer
5142  * Description: when resume this function is invoked to setup the DMA and CORE
5143  * in a usable state.
5144  */
5145 int stmmac_resume(struct device *dev)
5146 {
5147         struct net_device *ndev = dev_get_drvdata(dev);
5148         struct stmmac_priv *priv = netdev_priv(ndev);
5149         int ret;
5150
5151         if (!netif_running(ndev))
5152                 return 0;
5153
5154         /* Power Down bit, into the PM register, is cleared
5155          * automatically as soon as a magic packet or a Wake-up frame
5156          * is received. Anyway, it's better to manually clear
5157          * this bit because it can generate problems while resuming
5158          * from another devices (e.g. serial console).
5159          */
5160         if (device_may_wakeup(priv->device)) {
5161                 mutex_lock(&priv->lock);
5162                 stmmac_pmt(priv, priv->hw, 0);
5163                 mutex_unlock(&priv->lock);
5164                 priv->irq_wake = 0;
5165         } else {
5166                 pinctrl_pm_select_default_state(priv->device);
5167                 /* enable the clk previously disabled */
5168                 clk_prepare_enable(priv->plat->stmmac_clk);
5169                 clk_prepare_enable(priv->plat->pclk);
5170                 if (priv->plat->clk_ptp_ref)
5171                         clk_prepare_enable(priv->plat->clk_ptp_ref);
5172                 /* reset the phy so that it's ready */
5173                 if (priv->mii)
5174                         stmmac_mdio_reset(priv->mii);
5175         }
5176
5177         if (priv->plat->serdes_powerup) {
5178                 ret = priv->plat->serdes_powerup(ndev,
5179                                                  priv->plat->bsp_priv);
5180
5181                 if (ret < 0)
5182                         return ret;
5183         }
5184
5185         mutex_lock(&priv->lock);
5186
5187         stmmac_reset_queues_param(priv);
5188
5189         stmmac_clear_descriptors(priv);
5190
5191         stmmac_hw_setup(ndev, false);
5192         stmmac_init_coalesce(priv);
5193         stmmac_set_rx_mode(ndev);
5194
5195         stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
5196
5197         stmmac_enable_all_queues(priv);
5198
5199         stmmac_start_all_queues(priv);
5200
5201         mutex_unlock(&priv->lock);
5202
5203         if (!device_may_wakeup(priv->device)) {
5204                 rtnl_lock();
5205                 phylink_start(priv->phylink);
5206                 rtnl_unlock();
5207         }
5208
5209         phylink_mac_change(priv->phylink, true);
5210
5211         netif_device_attach(ndev);
5212
5213         return 0;
5214 }
5215 EXPORT_SYMBOL_GPL(stmmac_resume);
5216
5217 #ifndef MODULE
5218 static int __init stmmac_cmdline_opt(char *str)
5219 {
5220         char *opt;
5221
5222         if (!str || !*str)
5223                 return -EINVAL;
5224         while ((opt = strsep(&str, ",")) != NULL) {
5225                 if (!strncmp(opt, "debug:", 6)) {
5226                         if (kstrtoint(opt + 6, 0, &debug))
5227                                 goto err;
5228                 } else if (!strncmp(opt, "phyaddr:", 8)) {
5229                         if (kstrtoint(opt + 8, 0, &phyaddr))
5230                                 goto err;
5231                 } else if (!strncmp(opt, "buf_sz:", 7)) {
5232                         if (kstrtoint(opt + 7, 0, &buf_sz))
5233                                 goto err;
5234                 } else if (!strncmp(opt, "tc:", 3)) {
5235                         if (kstrtoint(opt + 3, 0, &tc))
5236                                 goto err;
5237                 } else if (!strncmp(opt, "watchdog:", 9)) {
5238                         if (kstrtoint(opt + 9, 0, &watchdog))
5239                                 goto err;
5240                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
5241                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
5242                                 goto err;
5243                 } else if (!strncmp(opt, "pause:", 6)) {
5244                         if (kstrtoint(opt + 6, 0, &pause))
5245                                 goto err;
5246                 } else if (!strncmp(opt, "eee_timer:", 10)) {
5247                         if (kstrtoint(opt + 10, 0, &eee_timer))
5248                                 goto err;
5249                 } else if (!strncmp(opt, "chain_mode:", 11)) {
5250                         if (kstrtoint(opt + 11, 0, &chain_mode))
5251                                 goto err;
5252                 }
5253         }
5254         return 0;
5255
5256 err:
5257         pr_err("%s: ERROR broken module parameter conversion", __func__);
5258         return -EINVAL;
5259 }
5260
5261 __setup("stmmaceth=", stmmac_cmdline_opt);
5262 #endif /* MODULE */
5263
5264 static int __init stmmac_init(void)
5265 {
5266 #ifdef CONFIG_DEBUG_FS
5267         /* Create debugfs main directory if it doesn't exist yet */
5268         if (!stmmac_fs_dir)
5269                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
5270         register_netdevice_notifier(&stmmac_notifier);
5271 #endif
5272
5273         return 0;
5274 }
5275
5276 static void __exit stmmac_exit(void)
5277 {
5278 #ifdef CONFIG_DEBUG_FS
5279         unregister_netdevice_notifier(&stmmac_notifier);
5280         debugfs_remove_recursive(stmmac_fs_dir);
5281 #endif
5282 }
5283
5284 module_init(stmmac_init)
5285 module_exit(stmmac_exit)
5286
5287 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
5288 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
5289 MODULE_LICENSE("GPL");