1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/mii.h>
15 #include <linux/phylink.h>
16 #include <linux/net_tstamp.h>
20 #include "dwmac_dma.h"
23 #define REG_SPACE_SIZE 0x1060
24 #define GMAC4_REG_SPACE_SIZE 0x116C
25 #define MAC100_ETHTOOL_NAME "st_mac100"
26 #define GMAC_ETHTOOL_NAME "st_gmac"
27 #define XGMAC_ETHTOOL_NAME "st_xgmac"
29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h
31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the
32 * same time due to the conflicting macro names.
34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100
36 #define ETHTOOL_DMA_OFFSET 55
39 char stat_string[ETH_GSTRING_LEN];
44 #define STMMAC_STAT(m) \
45 { #m, sizeof_field(struct stmmac_extra_stats, m), \
46 offsetof(struct stmmac_priv, xstats.m)}
48 static const struct stmmac_stats stmmac_gstrings_stats[] = {
50 STMMAC_STAT(tx_underflow),
51 STMMAC_STAT(tx_carrier),
52 STMMAC_STAT(tx_losscarrier),
53 STMMAC_STAT(vlan_tag),
54 STMMAC_STAT(tx_deferred),
56 STMMAC_STAT(tx_jabber),
57 STMMAC_STAT(tx_frame_flushed),
58 STMMAC_STAT(tx_payload_error),
59 STMMAC_STAT(tx_ip_header_error),
62 STMMAC_STAT(sa_filter_fail),
63 STMMAC_STAT(overflow_error),
64 STMMAC_STAT(ipc_csum_error),
65 STMMAC_STAT(rx_collision),
66 STMMAC_STAT(rx_crc_errors),
67 STMMAC_STAT(dribbling_bit),
68 STMMAC_STAT(rx_length),
70 STMMAC_STAT(rx_multicast),
71 STMMAC_STAT(rx_gmac_overflow),
72 STMMAC_STAT(rx_watchdog),
73 STMMAC_STAT(da_rx_filter_fail),
74 STMMAC_STAT(sa_rx_filter_fail),
75 STMMAC_STAT(rx_missed_cntr),
76 STMMAC_STAT(rx_overflow_cntr),
78 STMMAC_STAT(rx_split_hdr_pkt_n),
79 /* Tx/Rx IRQ error info */
80 STMMAC_STAT(tx_undeflow_irq),
81 STMMAC_STAT(tx_process_stopped_irq),
82 STMMAC_STAT(tx_jabber_irq),
83 STMMAC_STAT(rx_overflow_irq),
84 STMMAC_STAT(rx_buf_unav_irq),
85 STMMAC_STAT(rx_process_stopped_irq),
86 STMMAC_STAT(rx_watchdog_irq),
87 STMMAC_STAT(tx_early_irq),
88 STMMAC_STAT(fatal_bus_error_irq),
89 /* Tx/Rx IRQ Events */
90 STMMAC_STAT(rx_early_irq),
91 STMMAC_STAT(threshold),
92 STMMAC_STAT(irq_receive_pmt_irq_n),
94 STMMAC_STAT(mmc_tx_irq_n),
95 STMMAC_STAT(mmc_rx_irq_n),
96 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
102 STMMAC_STAT(phy_eee_wakeup_error_n),
103 /* Extended RDES status */
104 STMMAC_STAT(ip_hdr_err),
105 STMMAC_STAT(ip_payload_err),
106 STMMAC_STAT(ip_csum_bypassed),
107 STMMAC_STAT(ipv4_pkt_rcvd),
108 STMMAC_STAT(ipv6_pkt_rcvd),
109 STMMAC_STAT(no_ptp_rx_msg_type_ext),
110 STMMAC_STAT(ptp_rx_msg_type_sync),
111 STMMAC_STAT(ptp_rx_msg_type_follow_up),
112 STMMAC_STAT(ptp_rx_msg_type_delay_req),
113 STMMAC_STAT(ptp_rx_msg_type_delay_resp),
114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
117 STMMAC_STAT(ptp_rx_msg_type_announce),
118 STMMAC_STAT(ptp_rx_msg_type_management),
119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
120 STMMAC_STAT(ptp_frame_type),
121 STMMAC_STAT(ptp_ver),
122 STMMAC_STAT(timestamp_dropped),
123 STMMAC_STAT(av_pkt_rcvd),
124 STMMAC_STAT(av_tagged_pkt_rcvd),
125 STMMAC_STAT(vlan_tag_priority_val),
126 STMMAC_STAT(l3_filter_match),
127 STMMAC_STAT(l4_filter_match),
128 STMMAC_STAT(l3_l4_filter_no_match),
130 STMMAC_STAT(irq_pcs_ane_n),
131 STMMAC_STAT(irq_pcs_link_n),
132 STMMAC_STAT(irq_rgmii_n),
134 STMMAC_STAT(mtl_tx_status_fifo_full),
135 STMMAC_STAT(mtl_tx_fifo_not_empty),
136 STMMAC_STAT(mmtl_fifo_ctrl),
137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
141 STMMAC_STAT(mac_tx_in_pause),
142 STMMAC_STAT(mac_tx_frame_ctrl_xfer),
143 STMMAC_STAT(mac_tx_frame_ctrl_idle),
144 STMMAC_STAT(mac_tx_frame_ctrl_wait),
145 STMMAC_STAT(mac_tx_frame_ctrl_pause),
146 STMMAC_STAT(mac_gmii_tx_proto_engine),
147 STMMAC_STAT(mtl_rx_fifo_fill_level_full),
148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
155 STMMAC_STAT(mtl_rx_fifo_ctrl_active),
156 STMMAC_STAT(mac_rx_frame_ctrl_fifo),
157 STMMAC_STAT(mac_gmii_rx_proto_engine),
159 STMMAC_STAT(mtl_est_cgce),
160 STMMAC_STAT(mtl_est_hlbs),
161 STMMAC_STAT(mtl_est_hlbf),
162 STMMAC_STAT(mtl_est_btre),
163 STMMAC_STAT(mtl_est_btrlm),
165 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
167 /* statistics collected in queue which will be summed up for all TX or RX
168 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n).
170 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = {
182 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string)
184 /* HW MAC Management counters (if supported) */
185 #define STMMAC_MMC_STAT(m) \
186 { #m, sizeof_field(struct stmmac_counters, m), \
187 offsetof(struct stmmac_priv, mmc.m)}
189 static const struct stmmac_stats stmmac_mmc[] = {
190 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
191 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
192 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
193 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
194 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
195 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
196 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
197 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
198 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
199 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
200 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
201 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
202 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
203 STMMAC_MMC_STAT(mmc_tx_underflow_error),
204 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
205 STMMAC_MMC_STAT(mmc_tx_multicol_g),
206 STMMAC_MMC_STAT(mmc_tx_deferred),
207 STMMAC_MMC_STAT(mmc_tx_latecol),
208 STMMAC_MMC_STAT(mmc_tx_exesscol),
209 STMMAC_MMC_STAT(mmc_tx_carrier_error),
210 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
211 STMMAC_MMC_STAT(mmc_tx_framecount_g),
212 STMMAC_MMC_STAT(mmc_tx_excessdef),
213 STMMAC_MMC_STAT(mmc_tx_pause_frame),
214 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
215 STMMAC_MMC_STAT(mmc_tx_lpi_usec),
216 STMMAC_MMC_STAT(mmc_tx_lpi_tran),
217 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
218 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
219 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
220 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
221 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
222 STMMAC_MMC_STAT(mmc_rx_crc_error),
223 STMMAC_MMC_STAT(mmc_rx_align_error),
224 STMMAC_MMC_STAT(mmc_rx_run_error),
225 STMMAC_MMC_STAT(mmc_rx_jabber_error),
226 STMMAC_MMC_STAT(mmc_rx_undersize_g),
227 STMMAC_MMC_STAT(mmc_rx_oversize_g),
228 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
229 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
230 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
231 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
232 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
233 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
234 STMMAC_MMC_STAT(mmc_rx_unicast_g),
235 STMMAC_MMC_STAT(mmc_rx_length_error),
236 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
237 STMMAC_MMC_STAT(mmc_rx_pause_frames),
238 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
239 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
240 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
241 STMMAC_MMC_STAT(mmc_rx_lpi_usec),
242 STMMAC_MMC_STAT(mmc_rx_lpi_tran),
243 STMMAC_MMC_STAT(mmc_rx_discard_frames_gb),
244 STMMAC_MMC_STAT(mmc_rx_discard_octets_gb),
245 STMMAC_MMC_STAT(mmc_rx_align_err_frames),
246 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
247 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
248 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
249 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
250 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
251 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
252 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
253 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
254 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
255 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
256 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
257 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
258 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
259 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
260 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
261 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
262 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
263 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
264 STMMAC_MMC_STAT(mmc_rx_udp_gd),
265 STMMAC_MMC_STAT(mmc_rx_udp_err),
266 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
267 STMMAC_MMC_STAT(mmc_rx_tcp_err),
268 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
269 STMMAC_MMC_STAT(mmc_rx_icmp_err),
270 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
271 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
272 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
273 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
274 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
275 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
276 STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr),
277 STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr),
278 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
279 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
280 STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr),
281 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
282 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
283 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
284 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
286 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
288 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = {
291 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string)
294 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = {
297 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string)
300 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
301 struct ethtool_drvinfo *info)
303 struct stmmac_priv *priv = netdev_priv(dev);
305 if (priv->plat->has_gmac || priv->plat->has_gmac4)
306 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
307 else if (priv->plat->has_xgmac)
308 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver));
310 strscpy(info->driver, MAC100_ETHTOOL_NAME,
311 sizeof(info->driver));
313 if (priv->plat->pdev) {
314 strscpy(info->bus_info, pci_name(priv->plat->pdev),
315 sizeof(info->bus_info));
319 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
320 struct ethtool_link_ksettings *cmd)
322 struct stmmac_priv *priv = netdev_priv(dev);
324 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) &&
325 (priv->hw->pcs & STMMAC_PCS_RGMII ||
326 priv->hw->pcs & STMMAC_PCS_SGMII)) {
327 struct rgmii_adv adv;
328 u32 supported, advertising, lp_advertising;
330 if (!priv->xstats.pcs_link) {
331 cmd->base.speed = SPEED_UNKNOWN;
332 cmd->base.duplex = DUPLEX_UNKNOWN;
335 cmd->base.duplex = priv->xstats.pcs_duplex;
337 cmd->base.speed = priv->xstats.pcs_speed;
339 /* Get and convert ADV/LP_ADV from the HW AN registers */
340 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
341 return -EOPNOTSUPP; /* should never happen indeed */
343 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
345 ethtool_convert_link_mode_to_legacy_u32(
346 &supported, cmd->link_modes.supported);
347 ethtool_convert_link_mode_to_legacy_u32(
348 &advertising, cmd->link_modes.advertising);
349 ethtool_convert_link_mode_to_legacy_u32(
350 &lp_advertising, cmd->link_modes.lp_advertising);
352 if (adv.pause & STMMAC_PCS_PAUSE)
353 advertising |= ADVERTISED_Pause;
354 if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
355 advertising |= ADVERTISED_Asym_Pause;
356 if (adv.lp_pause & STMMAC_PCS_PAUSE)
357 lp_advertising |= ADVERTISED_Pause;
358 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
359 lp_advertising |= ADVERTISED_Asym_Pause;
361 /* Reg49[3] always set because ANE is always supported */
362 cmd->base.autoneg = ADVERTISED_Autoneg;
363 supported |= SUPPORTED_Autoneg;
364 advertising |= ADVERTISED_Autoneg;
365 lp_advertising |= ADVERTISED_Autoneg;
368 supported |= (SUPPORTED_1000baseT_Full |
369 SUPPORTED_100baseT_Full |
370 SUPPORTED_10baseT_Full);
371 advertising |= (ADVERTISED_1000baseT_Full |
372 ADVERTISED_100baseT_Full |
373 ADVERTISED_10baseT_Full);
375 supported |= (SUPPORTED_1000baseT_Half |
376 SUPPORTED_100baseT_Half |
377 SUPPORTED_10baseT_Half);
378 advertising |= (ADVERTISED_1000baseT_Half |
379 ADVERTISED_100baseT_Half |
380 ADVERTISED_10baseT_Half);
383 lp_advertising |= (ADVERTISED_1000baseT_Full |
384 ADVERTISED_100baseT_Full |
385 ADVERTISED_10baseT_Full);
387 lp_advertising |= (ADVERTISED_1000baseT_Half |
388 ADVERTISED_100baseT_Half |
389 ADVERTISED_10baseT_Half);
390 cmd->base.port = PORT_OTHER;
392 ethtool_convert_legacy_u32_to_link_mode(
393 cmd->link_modes.supported, supported);
394 ethtool_convert_legacy_u32_to_link_mode(
395 cmd->link_modes.advertising, advertising);
396 ethtool_convert_legacy_u32_to_link_mode(
397 cmd->link_modes.lp_advertising, lp_advertising);
402 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
406 stmmac_ethtool_set_link_ksettings(struct net_device *dev,
407 const struct ethtool_link_ksettings *cmd)
409 struct stmmac_priv *priv = netdev_priv(dev);
411 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) &&
412 (priv->hw->pcs & STMMAC_PCS_RGMII ||
413 priv->hw->pcs & STMMAC_PCS_SGMII)) {
414 /* Only support ANE */
415 if (cmd->base.autoneg != AUTONEG_ENABLE)
418 mutex_lock(&priv->lock);
419 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
420 mutex_unlock(&priv->lock);
425 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
428 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
430 struct stmmac_priv *priv = netdev_priv(dev);
431 return priv->msg_enable;
434 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
436 struct stmmac_priv *priv = netdev_priv(dev);
437 priv->msg_enable = level;
441 static int stmmac_check_if_running(struct net_device *dev)
443 if (!netif_running(dev))
448 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
450 struct stmmac_priv *priv = netdev_priv(dev);
452 if (priv->plat->has_xgmac)
453 return XGMAC_REGSIZE * 4;
454 else if (priv->plat->has_gmac4)
455 return GMAC4_REG_SPACE_SIZE;
456 return REG_SPACE_SIZE;
459 static void stmmac_ethtool_gregs(struct net_device *dev,
460 struct ethtool_regs *regs, void *space)
462 struct stmmac_priv *priv = netdev_priv(dev);
463 u32 *reg_space = (u32 *) space;
465 stmmac_dump_mac_regs(priv, priv->hw, reg_space);
466 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
468 /* Copy DMA registers to where ethtool expects them */
469 if (priv->plat->has_gmac4) {
470 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */
471 memcpy(®_space[ETHTOOL_DMA_OFFSET],
472 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4],
473 NUM_DWMAC4_DMA_REGS * 4);
474 } else if (!priv->plat->has_xgmac) {
475 memcpy(®_space[ETHTOOL_DMA_OFFSET],
476 ®_space[DMA_BUS_MODE / 4],
477 NUM_DWMAC1000_DMA_REGS * 4);
481 static int stmmac_nway_reset(struct net_device *dev)
483 struct stmmac_priv *priv = netdev_priv(dev);
485 return phylink_ethtool_nway_reset(priv->phylink);
488 static void stmmac_get_ringparam(struct net_device *netdev,
489 struct ethtool_ringparam *ring,
490 struct kernel_ethtool_ringparam *kernel_ring,
491 struct netlink_ext_ack *extack)
493 struct stmmac_priv *priv = netdev_priv(netdev);
495 ring->rx_max_pending = DMA_MAX_RX_SIZE;
496 ring->tx_max_pending = DMA_MAX_TX_SIZE;
497 ring->rx_pending = priv->dma_conf.dma_rx_size;
498 ring->tx_pending = priv->dma_conf.dma_tx_size;
501 static int stmmac_set_ringparam(struct net_device *netdev,
502 struct ethtool_ringparam *ring,
503 struct kernel_ethtool_ringparam *kernel_ring,
504 struct netlink_ext_ack *extack)
506 if (ring->rx_mini_pending || ring->rx_jumbo_pending ||
507 ring->rx_pending < DMA_MIN_RX_SIZE ||
508 ring->rx_pending > DMA_MAX_RX_SIZE ||
509 !is_power_of_2(ring->rx_pending) ||
510 ring->tx_pending < DMA_MIN_TX_SIZE ||
511 ring->tx_pending > DMA_MAX_TX_SIZE ||
512 !is_power_of_2(ring->tx_pending))
515 return stmmac_reinit_ringparam(netdev, ring->rx_pending,
520 stmmac_get_pauseparam(struct net_device *netdev,
521 struct ethtool_pauseparam *pause)
523 struct stmmac_priv *priv = netdev_priv(netdev);
524 struct rgmii_adv adv_lp;
526 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
531 phylink_ethtool_get_pauseparam(priv->phylink, pause);
536 stmmac_set_pauseparam(struct net_device *netdev,
537 struct ethtool_pauseparam *pause)
539 struct stmmac_priv *priv = netdev_priv(netdev);
540 struct rgmii_adv adv_lp;
542 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
548 return phylink_ethtool_set_pauseparam(priv->phylink, pause);
552 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)
554 u32 tx_cnt = priv->plat->tx_queues_to_use;
555 u32 rx_cnt = priv->plat->rx_queues_to_use;
560 for (q = 0; q < tx_cnt; q++) {
561 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q];
562 struct stmmac_txq_stats snapshot;
565 start = u64_stats_fetch_begin(&txq_stats->syncp);
566 snapshot = *txq_stats;
567 } while (u64_stats_fetch_retry(&txq_stats->syncp, start));
569 p = (char *)&snapshot + offsetof(struct stmmac_txq_stats, tx_pkt_n);
570 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
571 *data++ = (*(u64 *)p);
576 for (q = 0; q < rx_cnt; q++) {
577 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q];
578 struct stmmac_rxq_stats snapshot;
581 start = u64_stats_fetch_begin(&rxq_stats->syncp);
582 snapshot = *rxq_stats;
583 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start));
585 p = (char *)&snapshot + offsetof(struct stmmac_rxq_stats, rx_pkt_n);
586 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
587 *data++ = (*(u64 *)p);
593 static void stmmac_get_ethtool_stats(struct net_device *dev,
594 struct ethtool_stats *dummy, u64 *data)
596 struct stmmac_priv *priv = netdev_priv(dev);
597 u32 rx_queues_count = priv->plat->rx_queues_to_use;
598 u32 tx_queues_count = priv->plat->tx_queues_to_use;
599 u64 napi_poll = 0, normal_irq_n = 0;
600 int i, j = 0, pos, ret;
604 if (priv->dma_cap.asp) {
605 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
606 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
612 /* Update the DMA HW counters for dwmac10/100 */
613 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr);
615 /* If supported, for new GMAC chips expose the MMC counters */
616 if (priv->dma_cap.rmon) {
617 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
619 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
621 p = (char *)priv + stmmac_mmc[i].stat_offset;
623 data[j++] = (stmmac_mmc[i].sizeof_stat ==
624 sizeof(u64)) ? (*(u64 *)p) :
628 if (priv->eee_enabled) {
629 int val = phylink_get_eee_err(priv->phylink);
631 priv->xstats.phy_eee_wakeup_error_n = val;
634 if (priv->synopsys_id >= DWMAC_CORE_3_50)
635 stmmac_mac_debug(priv, priv->ioaddr,
636 (void *)&priv->xstats,
637 rx_queues_count, tx_queues_count);
639 for (i = 0; i < STMMAC_STATS_LEN; i++) {
640 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
641 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
642 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
646 for (i = 0; i < rx_queues_count; i++) {
647 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i];
648 struct stmmac_rxq_stats snapshot;
652 start = u64_stats_fetch_begin(&rxq_stats->syncp);
653 snapshot = *rxq_stats;
654 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start));
656 data[j++] += snapshot.rx_pkt_n;
657 data[j++] += snapshot.rx_normal_irq_n;
658 normal_irq_n += snapshot.rx_normal_irq_n;
659 napi_poll += snapshot.napi_poll;
663 for (i = 0; i < tx_queues_count; i++) {
664 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i];
665 struct stmmac_txq_stats snapshot;
669 start = u64_stats_fetch_begin(&txq_stats->syncp);
670 snapshot = *txq_stats;
671 } while (u64_stats_fetch_retry(&txq_stats->syncp, start));
673 data[j++] += snapshot.tx_pkt_n;
674 data[j++] += snapshot.tx_normal_irq_n;
675 normal_irq_n += snapshot.tx_normal_irq_n;
676 data[j++] += snapshot.tx_clean;
677 data[j++] += snapshot.tx_set_ic_bit;
678 data[j++] += snapshot.tx_tso_frames;
679 data[j++] += snapshot.tx_tso_nfrags;
680 napi_poll += snapshot.napi_poll;
682 normal_irq_n += priv->xstats.rx_early_irq;
683 data[j++] = normal_irq_n;
684 data[j++] = napi_poll;
686 stmmac_get_per_qstats(priv, &data[j]);
689 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
691 struct stmmac_priv *priv = netdev_priv(netdev);
692 u32 tx_cnt = priv->plat->tx_queues_to_use;
693 u32 rx_cnt = priv->plat->rx_queues_to_use;
694 int i, len, safety_len = 0;
698 len = STMMAC_STATS_LEN + STMMAC_QSTATS +
699 STMMAC_TXQ_STATS * tx_cnt +
700 STMMAC_RXQ_STATS * rx_cnt;
702 if (priv->dma_cap.rmon)
703 len += STMMAC_MMC_STATS_LEN;
704 if (priv->dma_cap.asp) {
705 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
706 if (!stmmac_safety_feat_dump(priv,
717 return stmmac_selftest_get_count(priv);
723 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data)
725 u32 tx_cnt = priv->plat->tx_queues_to_use;
726 u32 rx_cnt = priv->plat->rx_queues_to_use;
729 for (q = 0; q < tx_cnt; q++) {
730 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
731 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
732 stmmac_qstats_tx_string[stat]);
733 data += ETH_GSTRING_LEN;
736 for (q = 0; q < rx_cnt; q++) {
737 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
738 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
739 stmmac_qstats_rx_string[stat]);
740 data += ETH_GSTRING_LEN;
745 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
749 struct stmmac_priv *priv = netdev_priv(dev);
753 if (priv->dma_cap.asp) {
754 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
756 if (!stmmac_safety_feat_dump(priv,
759 memcpy(p, desc, ETH_GSTRING_LEN);
760 p += ETH_GSTRING_LEN;
764 if (priv->dma_cap.rmon)
765 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
766 memcpy(p, stmmac_mmc[i].stat_string,
768 p += ETH_GSTRING_LEN;
770 for (i = 0; i < STMMAC_STATS_LEN; i++) {
771 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN);
772 p += ETH_GSTRING_LEN;
774 for (i = 0; i < STMMAC_QSTATS; i++) {
775 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN);
776 p += ETH_GSTRING_LEN;
778 stmmac_get_qstats_string(priv, p);
781 stmmac_selftest_get_strings(priv, p);
789 /* Currently only support WOL through Magic packet. */
790 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
792 struct stmmac_priv *priv = netdev_priv(dev);
794 if (!priv->plat->pmt)
795 return phylink_ethtool_get_wol(priv->phylink, wol);
797 mutex_lock(&priv->lock);
798 if (device_can_wakeup(priv->device)) {
799 wol->supported = WAKE_MAGIC | WAKE_UCAST;
800 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame)
801 wol->supported &= ~WAKE_MAGIC;
802 wol->wolopts = priv->wolopts;
804 mutex_unlock(&priv->lock);
807 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
809 struct stmmac_priv *priv = netdev_priv(dev);
810 u32 support = WAKE_MAGIC | WAKE_UCAST;
812 if (!device_can_wakeup(priv->device))
815 if (!priv->plat->pmt) {
816 int ret = phylink_ethtool_set_wol(priv->phylink, wol);
819 device_set_wakeup_enable(priv->device, !!wol->wolopts);
823 /* By default almost all GMAC devices support the WoL via
824 * magic frame but we can disable it if the HW capability
825 * register shows no support for pmt_magic_frame. */
826 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
827 wol->wolopts &= ~WAKE_MAGIC;
829 if (wol->wolopts & ~support)
833 pr_info("stmmac: wakeup enable\n");
834 device_set_wakeup_enable(priv->device, 1);
835 /* Avoid unbalanced enable_irq_wake calls */
836 if (priv->wol_irq_disabled)
837 enable_irq_wake(priv->wol_irq);
838 priv->wol_irq_disabled = false;
840 device_set_wakeup_enable(priv->device, 0);
841 /* Avoid unbalanced disable_irq_wake calls */
842 if (!priv->wol_irq_disabled)
843 disable_irq_wake(priv->wol_irq);
844 priv->wol_irq_disabled = true;
847 mutex_lock(&priv->lock);
848 priv->wolopts = wol->wolopts;
849 mutex_unlock(&priv->lock);
854 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
855 struct ethtool_eee *edata)
857 struct stmmac_priv *priv = netdev_priv(dev);
859 if (!priv->dma_cap.eee)
862 edata->eee_enabled = priv->eee_enabled;
863 edata->eee_active = priv->eee_active;
864 edata->tx_lpi_timer = priv->tx_lpi_timer;
865 edata->tx_lpi_enabled = priv->tx_lpi_enabled;
867 return phylink_ethtool_get_eee(priv->phylink, edata);
870 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
871 struct ethtool_eee *edata)
873 struct stmmac_priv *priv = netdev_priv(dev);
876 if (!priv->dma_cap.eee)
879 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled)
880 netdev_warn(priv->dev,
881 "Setting EEE tx-lpi is not supported\n");
883 if (!edata->eee_enabled)
884 stmmac_disable_eee_mode(priv);
886 ret = phylink_ethtool_set_eee(priv->phylink, edata);
890 if (edata->eee_enabled &&
891 priv->tx_lpi_timer != edata->tx_lpi_timer) {
892 priv->tx_lpi_timer = edata->tx_lpi_timer;
893 stmmac_eee_init(priv);
899 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
901 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
904 clk = priv->plat->clk_ref_rate;
909 return (usec * (clk / 1000000)) / 256;
912 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
914 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
917 clk = priv->plat->clk_ref_rate;
922 return (riwt * 256) / (clk / 1000000);
925 static int __stmmac_get_coalesce(struct net_device *dev,
926 struct ethtool_coalesce *ec,
929 struct stmmac_priv *priv = netdev_priv(dev);
934 rx_cnt = priv->plat->rx_queues_to_use;
935 tx_cnt = priv->plat->tx_queues_to_use;
936 max_cnt = max(rx_cnt, tx_cnt);
940 else if (queue >= max_cnt)
943 if (queue < tx_cnt) {
944 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue];
945 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue];
947 ec->tx_coalesce_usecs = 0;
948 ec->tx_max_coalesced_frames = 0;
951 if (priv->use_riwt && queue < rx_cnt) {
952 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue];
953 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue],
956 ec->rx_max_coalesced_frames = 0;
957 ec->rx_coalesce_usecs = 0;
963 static int stmmac_get_coalesce(struct net_device *dev,
964 struct ethtool_coalesce *ec,
965 struct kernel_ethtool_coalesce *kernel_coal,
966 struct netlink_ext_ack *extack)
968 return __stmmac_get_coalesce(dev, ec, -1);
971 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue,
972 struct ethtool_coalesce *ec)
974 return __stmmac_get_coalesce(dev, ec, queue);
977 static int __stmmac_set_coalesce(struct net_device *dev,
978 struct ethtool_coalesce *ec,
981 struct stmmac_priv *priv = netdev_priv(dev);
982 bool all_queues = false;
983 unsigned int rx_riwt;
988 rx_cnt = priv->plat->rx_queues_to_use;
989 tx_cnt = priv->plat->tx_queues_to_use;
990 max_cnt = max(rx_cnt, tx_cnt);
994 else if (queue >= max_cnt)
997 if (priv->use_riwt) {
998 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
1000 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
1006 for (i = 0; i < rx_cnt; i++) {
1007 priv->rx_riwt[i] = rx_riwt;
1008 stmmac_rx_watchdog(priv, priv->ioaddr,
1010 priv->rx_coal_frames[i] =
1011 ec->rx_max_coalesced_frames;
1013 } else if (queue < rx_cnt) {
1014 priv->rx_riwt[queue] = rx_riwt;
1015 stmmac_rx_watchdog(priv, priv->ioaddr,
1017 priv->rx_coal_frames[queue] =
1018 ec->rx_max_coalesced_frames;
1022 if ((ec->tx_coalesce_usecs == 0) &&
1023 (ec->tx_max_coalesced_frames == 0))
1026 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
1027 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
1033 for (i = 0; i < tx_cnt; i++) {
1034 priv->tx_coal_frames[i] =
1035 ec->tx_max_coalesced_frames;
1036 priv->tx_coal_timer[i] =
1037 ec->tx_coalesce_usecs;
1039 } else if (queue < tx_cnt) {
1040 priv->tx_coal_frames[queue] =
1041 ec->tx_max_coalesced_frames;
1042 priv->tx_coal_timer[queue] =
1043 ec->tx_coalesce_usecs;
1049 static int stmmac_set_coalesce(struct net_device *dev,
1050 struct ethtool_coalesce *ec,
1051 struct kernel_ethtool_coalesce *kernel_coal,
1052 struct netlink_ext_ack *extack)
1054 return __stmmac_set_coalesce(dev, ec, -1);
1057 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue,
1058 struct ethtool_coalesce *ec)
1060 return __stmmac_set_coalesce(dev, ec, queue);
1063 static int stmmac_get_rxnfc(struct net_device *dev,
1064 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1066 struct stmmac_priv *priv = netdev_priv(dev);
1068 switch (rxnfc->cmd) {
1069 case ETHTOOL_GRXRINGS:
1070 rxnfc->data = priv->plat->rx_queues_to_use;
1079 static u32 stmmac_get_rxfh_key_size(struct net_device *dev)
1081 struct stmmac_priv *priv = netdev_priv(dev);
1083 return sizeof(priv->rss.key);
1086 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)
1088 struct stmmac_priv *priv = netdev_priv(dev);
1090 return ARRAY_SIZE(priv->rss.table);
1093 static int stmmac_get_rxfh(struct net_device *dev,
1094 struct ethtool_rxfh_param *rxfh)
1096 struct stmmac_priv *priv = netdev_priv(dev);
1100 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1101 rxfh->indir[i] = priv->rss.table[i];
1105 memcpy(rxfh->key, priv->rss.key, sizeof(priv->rss.key));
1106 rxfh->hfunc = ETH_RSS_HASH_TOP;
1111 static int stmmac_set_rxfh(struct net_device *dev,
1112 struct ethtool_rxfh_param *rxfh,
1113 struct netlink_ext_ack *extack)
1115 struct stmmac_priv *priv = netdev_priv(dev);
1118 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
1119 rxfh->hfunc != ETH_RSS_HASH_TOP)
1123 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1124 priv->rss.table[i] = rxfh->indir[i];
1128 memcpy(priv->rss.key, rxfh->key, sizeof(priv->rss.key));
1130 return stmmac_rss_configure(priv, priv->hw, &priv->rss,
1131 priv->plat->rx_queues_to_use);
1134 static void stmmac_get_channels(struct net_device *dev,
1135 struct ethtool_channels *chan)
1137 struct stmmac_priv *priv = netdev_priv(dev);
1139 chan->rx_count = priv->plat->rx_queues_to_use;
1140 chan->tx_count = priv->plat->tx_queues_to_use;
1141 chan->max_rx = priv->dma_cap.number_rx_queues;
1142 chan->max_tx = priv->dma_cap.number_tx_queues;
1145 static int stmmac_set_channels(struct net_device *dev,
1146 struct ethtool_channels *chan)
1148 struct stmmac_priv *priv = netdev_priv(dev);
1150 if (chan->rx_count > priv->dma_cap.number_rx_queues ||
1151 chan->tx_count > priv->dma_cap.number_tx_queues ||
1152 !chan->rx_count || !chan->tx_count)
1155 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count);
1158 static int stmmac_get_ts_info(struct net_device *dev,
1159 struct ethtool_ts_info *info)
1161 struct stmmac_priv *priv = netdev_priv(dev);
1163 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
1165 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1166 SOF_TIMESTAMPING_TX_HARDWARE |
1167 SOF_TIMESTAMPING_RX_SOFTWARE |
1168 SOF_TIMESTAMPING_RX_HARDWARE |
1169 SOF_TIMESTAMPING_SOFTWARE |
1170 SOF_TIMESTAMPING_RAW_HARDWARE;
1172 if (priv->ptp_clock)
1173 info->phc_index = ptp_clock_index(priv->ptp_clock);
1175 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1177 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
1178 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1179 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1180 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1181 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1182 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1183 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1184 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1185 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1186 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
1187 (1 << HWTSTAMP_FILTER_ALL));
1190 return ethtool_op_get_ts_info(dev, info);
1193 static int stmmac_get_tunable(struct net_device *dev,
1194 const struct ethtool_tunable *tuna, void *data)
1196 struct stmmac_priv *priv = netdev_priv(dev);
1200 case ETHTOOL_RX_COPYBREAK:
1201 *(u32 *)data = priv->rx_copybreak;
1211 static int stmmac_set_tunable(struct net_device *dev,
1212 const struct ethtool_tunable *tuna,
1215 struct stmmac_priv *priv = netdev_priv(dev);
1219 case ETHTOOL_RX_COPYBREAK:
1220 priv->rx_copybreak = *(u32 *)data;
1230 static const struct ethtool_ops stmmac_ethtool_ops = {
1231 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1232 ETHTOOL_COALESCE_MAX_FRAMES,
1233 .begin = stmmac_check_if_running,
1234 .get_drvinfo = stmmac_ethtool_getdrvinfo,
1235 .get_msglevel = stmmac_ethtool_getmsglevel,
1236 .set_msglevel = stmmac_ethtool_setmsglevel,
1237 .get_regs = stmmac_ethtool_gregs,
1238 .get_regs_len = stmmac_ethtool_get_regs_len,
1239 .get_link = ethtool_op_get_link,
1240 .nway_reset = stmmac_nway_reset,
1241 .get_ringparam = stmmac_get_ringparam,
1242 .set_ringparam = stmmac_set_ringparam,
1243 .get_pauseparam = stmmac_get_pauseparam,
1244 .set_pauseparam = stmmac_set_pauseparam,
1245 .self_test = stmmac_selftest_run,
1246 .get_ethtool_stats = stmmac_get_ethtool_stats,
1247 .get_strings = stmmac_get_strings,
1248 .get_wol = stmmac_get_wol,
1249 .set_wol = stmmac_set_wol,
1250 .get_eee = stmmac_ethtool_op_get_eee,
1251 .set_eee = stmmac_ethtool_op_set_eee,
1252 .get_sset_count = stmmac_get_sset_count,
1253 .get_rxnfc = stmmac_get_rxnfc,
1254 .get_rxfh_key_size = stmmac_get_rxfh_key_size,
1255 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size,
1256 .get_rxfh = stmmac_get_rxfh,
1257 .set_rxfh = stmmac_set_rxfh,
1258 .get_ts_info = stmmac_get_ts_info,
1259 .get_coalesce = stmmac_get_coalesce,
1260 .set_coalesce = stmmac_set_coalesce,
1261 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce,
1262 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce,
1263 .get_channels = stmmac_get_channels,
1264 .set_channels = stmmac_set_channels,
1265 .get_tunable = stmmac_get_tunable,
1266 .set_tunable = stmmac_set_tunable,
1267 .get_link_ksettings = stmmac_ethtool_get_link_ksettings,
1268 .set_link_ksettings = stmmac_ethtool_set_link_ksettings,
1271 void stmmac_set_ethtool_ops(struct net_device *netdev)
1273 netdev->ethtool_ops = &stmmac_ethtool_ops;