1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 DWMAC Management Counters
5 Copyright (C) 2011 STMicroelectronics Ltd
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
11 #include <linux/kernel.h>
16 /* MAC Management Counters register offset */
18 #define MMC_CNTRL 0x00 /* MMC Control */
19 #define MMC_RX_INTR 0x04 /* MMC RX Interrupt */
20 #define MMC_TX_INTR 0x08 /* MMC TX Interrupt */
21 #define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */
22 #define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */
23 #define MMC_DEFAULT_MASK 0xffffffff
25 /* MMC TX counter registers */
28 * _GB register stands for good and bad frames
29 * _G is for good only.
31 #define MMC_TX_OCTETCOUNT_GB 0x14
32 #define MMC_TX_FRAMECOUNT_GB 0x18
33 #define MMC_TX_BROADCASTFRAME_G 0x1c
34 #define MMC_TX_MULTICASTFRAME_G 0x20
35 #define MMC_TX_64_OCTETS_GB 0x24
36 #define MMC_TX_65_TO_127_OCTETS_GB 0x28
37 #define MMC_TX_128_TO_255_OCTETS_GB 0x2c
38 #define MMC_TX_256_TO_511_OCTETS_GB 0x30
39 #define MMC_TX_512_TO_1023_OCTETS_GB 0x34
40 #define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38
41 #define MMC_TX_UNICAST_GB 0x3c
42 #define MMC_TX_MULTICAST_GB 0x40
43 #define MMC_TX_BROADCAST_GB 0x44
44 #define MMC_TX_UNDERFLOW_ERROR 0x48
45 #define MMC_TX_SINGLECOL_G 0x4c
46 #define MMC_TX_MULTICOL_G 0x50
47 #define MMC_TX_DEFERRED 0x54
48 #define MMC_TX_LATECOL 0x58
49 #define MMC_TX_EXESSCOL 0x5c
50 #define MMC_TX_CARRIER_ERROR 0x60
51 #define MMC_TX_OCTETCOUNT_G 0x64
52 #define MMC_TX_FRAMECOUNT_G 0x68
53 #define MMC_TX_EXCESSDEF 0x6c
54 #define MMC_TX_PAUSE_FRAME 0x70
55 #define MMC_TX_VLAN_FRAME_G 0x74
57 /* MMC RX counter registers */
58 #define MMC_RX_FRAMECOUNT_GB 0x80
59 #define MMC_RX_OCTETCOUNT_GB 0x84
60 #define MMC_RX_OCTETCOUNT_G 0x88
61 #define MMC_RX_BROADCASTFRAME_G 0x8c
62 #define MMC_RX_MULTICASTFRAME_G 0x90
63 #define MMC_RX_CRC_ERROR 0x94
64 #define MMC_RX_ALIGN_ERROR 0x98
65 #define MMC_RX_RUN_ERROR 0x9C
66 #define MMC_RX_JABBER_ERROR 0xA0
67 #define MMC_RX_UNDERSIZE_G 0xA4
68 #define MMC_RX_OVERSIZE_G 0xA8
69 #define MMC_RX_64_OCTETS_GB 0xAC
70 #define MMC_RX_65_TO_127_OCTETS_GB 0xb0
71 #define MMC_RX_128_TO_255_OCTETS_GB 0xb4
72 #define MMC_RX_256_TO_511_OCTETS_GB 0xb8
73 #define MMC_RX_512_TO_1023_OCTETS_GB 0xbc
74 #define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0
75 #define MMC_RX_UNICAST_G 0xc4
76 #define MMC_RX_LENGTH_ERROR 0xc8
77 #define MMC_RX_AUTOFRANGETYPE 0xcc
78 #define MMC_RX_PAUSE_FRAMES 0xd0
79 #define MMC_RX_FIFO_OVERFLOW 0xd4
80 #define MMC_RX_VLAN_FRAMES_GB 0xd8
81 #define MMC_RX_WATCHDOG_ERROR 0xdc
83 #define MMC_TX_LPI_USEC 0xec
84 #define MMC_TX_LPI_TRAN 0xf0
85 #define MMC_RX_LPI_USEC 0xf4
86 #define MMC_RX_LPI_TRAN 0xf8
89 #define MMC_RX_IPC_INTR_MASK 0x100
90 #define MMC_RX_IPC_INTR 0x108
92 #define MMC_RX_IPV4_GD 0x110
93 #define MMC_RX_IPV4_HDERR 0x114
94 #define MMC_RX_IPV4_NOPAY 0x118
95 #define MMC_RX_IPV4_FRAG 0x11C
96 #define MMC_RX_IPV4_UDSBL 0x120
98 #define MMC_RX_IPV4_GD_OCTETS 0x150
99 #define MMC_RX_IPV4_HDERR_OCTETS 0x154
100 #define MMC_RX_IPV4_NOPAY_OCTETS 0x158
101 #define MMC_RX_IPV4_FRAG_OCTETS 0x15c
102 #define MMC_RX_IPV4_UDSBL_OCTETS 0x160
105 #define MMC_RX_IPV6_GD_OCTETS 0x164
106 #define MMC_RX_IPV6_HDERR_OCTETS 0x168
107 #define MMC_RX_IPV6_NOPAY_OCTETS 0x16c
109 #define MMC_RX_IPV6_GD 0x124
110 #define MMC_RX_IPV6_HDERR 0x128
111 #define MMC_RX_IPV6_NOPAY 0x12c
114 #define MMC_RX_UDP_GD 0x130
115 #define MMC_RX_UDP_ERR 0x134
116 #define MMC_RX_TCP_GD 0x138
117 #define MMC_RX_TCP_ERR 0x13c
118 #define MMC_RX_ICMP_GD 0x140
119 #define MMC_RX_ICMP_ERR 0x144
121 #define MMC_RX_UDP_GD_OCTETS 0x170
122 #define MMC_RX_UDP_ERR_OCTETS 0x174
123 #define MMC_RX_TCP_GD_OCTETS 0x178
124 #define MMC_RX_TCP_ERR_OCTETS 0x17c
125 #define MMC_RX_ICMP_GD_OCTETS 0x180
126 #define MMC_RX_ICMP_ERR_OCTETS 0x184
128 #define MMC_TX_FPE_FRAG 0x1a8
129 #define MMC_TX_HOLD_REQ 0x1ac
130 #define MMC_RX_PKT_ASSEMBLY_ERR 0x1c8
131 #define MMC_RX_PKT_SMD_ERR 0x1cc
132 #define MMC_RX_PKT_ASSEMBLY_OK 0x1d0
133 #define MMC_RX_FPE_FRAG 0x1d4
135 /* XGMAC MMC Registers */
136 #define MMC_XGMAC_TX_OCTET_GB 0x14
137 #define MMC_XGMAC_TX_PKT_GB 0x1c
138 #define MMC_XGMAC_TX_BROAD_PKT_G 0x24
139 #define MMC_XGMAC_TX_MULTI_PKT_G 0x2c
140 #define MMC_XGMAC_TX_64OCT_GB 0x34
141 #define MMC_XGMAC_TX_65OCT_GB 0x3c
142 #define MMC_XGMAC_TX_128OCT_GB 0x44
143 #define MMC_XGMAC_TX_256OCT_GB 0x4c
144 #define MMC_XGMAC_TX_512OCT_GB 0x54
145 #define MMC_XGMAC_TX_1024OCT_GB 0x5c
146 #define MMC_XGMAC_TX_UNI_PKT_GB 0x64
147 #define MMC_XGMAC_TX_MULTI_PKT_GB 0x6c
148 #define MMC_XGMAC_TX_BROAD_PKT_GB 0x74
149 #define MMC_XGMAC_TX_UNDER 0x7c
150 #define MMC_XGMAC_TX_OCTET_G 0x84
151 #define MMC_XGMAC_TX_PKT_G 0x8c
152 #define MMC_XGMAC_TX_PAUSE 0x94
153 #define MMC_XGMAC_TX_VLAN_PKT_G 0x9c
154 #define MMC_XGMAC_TX_LPI_USEC 0xa4
155 #define MMC_XGMAC_TX_LPI_TRAN 0xa8
157 #define MMC_XGMAC_RX_PKT_GB 0x100
158 #define MMC_XGMAC_RX_OCTET_GB 0x108
159 #define MMC_XGMAC_RX_OCTET_G 0x110
160 #define MMC_XGMAC_RX_BROAD_PKT_G 0x118
161 #define MMC_XGMAC_RX_MULTI_PKT_G 0x120
162 #define MMC_XGMAC_RX_CRC_ERR 0x128
163 #define MMC_XGMAC_RX_RUNT_ERR 0x130
164 #define MMC_XGMAC_RX_JABBER_ERR 0x134
165 #define MMC_XGMAC_RX_UNDER 0x138
166 #define MMC_XGMAC_RX_OVER 0x13c
167 #define MMC_XGMAC_RX_64OCT_GB 0x140
168 #define MMC_XGMAC_RX_65OCT_GB 0x148
169 #define MMC_XGMAC_RX_128OCT_GB 0x150
170 #define MMC_XGMAC_RX_256OCT_GB 0x158
171 #define MMC_XGMAC_RX_512OCT_GB 0x160
172 #define MMC_XGMAC_RX_1024OCT_GB 0x168
173 #define MMC_XGMAC_RX_UNI_PKT_G 0x170
174 #define MMC_XGMAC_RX_LENGTH_ERR 0x178
175 #define MMC_XGMAC_RX_RANGE 0x180
176 #define MMC_XGMAC_RX_PAUSE 0x188
177 #define MMC_XGMAC_RX_FIFOOVER_PKT 0x190
178 #define MMC_XGMAC_RX_VLAN_PKT_GB 0x198
179 #define MMC_XGMAC_RX_WATCHDOG_ERR 0x1a0
180 #define MMC_XGMAC_RX_LPI_USEC 0x1a4
181 #define MMC_XGMAC_RX_LPI_TRAN 0x1a8
182 #define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac
183 #define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4
184 #define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc
186 #define MMC_XGMAC_SGF_PASS_PKT 0x1f0
187 #define MMC_XGMAC_SGF_FAIL_PKT 0x1f4
188 #define MMC_XGMAC_TX_FPE_INTR_MASK 0x204
189 #define MMC_XGMAC_TX_FPE_FRAG 0x208
190 #define MMC_XGMAC_TX_HOLD_REQ 0x20c
191 #define MMC_XGMAC_TX_GATE_OVERRUN 0x210
192 #define MMC_XGMAC_RX_FPE_INTR_MASK 0x224
193 #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228
194 #define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c
195 #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230
196 #define MMC_XGMAC_RX_FPE_FRAG 0x234
197 #define MMC_XGMAC_RX_IPC_INTR_MASK 0x25c
199 #define MMC_XGMAC_RX_IPV4_GD 0x264
200 #define MMC_XGMAC_RX_IPV4_HDERR 0x26c
201 #define MMC_XGMAC_RX_IPV4_NOPAY 0x274
202 #define MMC_XGMAC_RX_IPV4_FRAG 0x27c
203 #define MMC_XGMAC_RX_IPV4_UDSBL 0x284
205 #define MMC_XGMAC_RX_IPV6_GD 0x28c
206 #define MMC_XGMAC_RX_IPV6_HDERR 0x294
207 #define MMC_XGMAC_RX_IPV6_NOPAY 0x29c
209 #define MMC_XGMAC_RX_UDP_GD 0x2a4
210 #define MMC_XGMAC_RX_UDP_ERR 0x2ac
211 #define MMC_XGMAC_RX_TCP_GD 0x2b4
212 #define MMC_XGMAC_RX_TCP_ERR 0x2bc
213 #define MMC_XGMAC_RX_ICMP_GD 0x2c4
214 #define MMC_XGMAC_RX_ICMP_ERR 0x2cc
216 #define MMC_XGMAC_RX_IPV4_GD_OCTETS 0x2d4
217 #define MMC_XGMAC_RX_IPV4_HDERR_OCTETS 0x2dc
218 #define MMC_XGMAC_RX_IPV4_NOPAY_OCTETS 0x2e4
219 #define MMC_XGMAC_RX_IPV4_FRAG_OCTETS 0x2ec
220 #define MMC_XGMAC_RX_IPV4_UDSBL_OCTETS 0x2f4
222 #define MMC_XGMAC_RX_IPV6_GD_OCTETS 0x2fc
223 #define MMC_XGMAC_RX_IPV6_HDERR_OCTETS 0x304
224 #define MMC_XGMAC_RX_IPV6_NOPAY_OCTETS 0x30c
226 #define MMC_XGMAC_RX_UDP_GD_OCTETS 0x314
227 #define MMC_XGMAC_RX_UDP_ERR_OCTETS 0x31c
228 #define MMC_XGMAC_RX_TCP_GD_OCTETS 0x324
229 #define MMC_XGMAC_RX_TCP_ERR_OCTETS 0x32c
230 #define MMC_XGMAC_RX_ICMP_GD_OCTETS 0x334
231 #define MMC_XGMAC_RX_ICMP_ERR_OCTETS 0x33c
233 static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
235 u32 value = readl(mmcaddr + MMC_CNTRL);
237 value |= (mode & 0x3F);
239 writel(value, mmcaddr + MMC_CNTRL);
241 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
245 /* To mask all interrupts.*/
246 static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
248 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
249 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
250 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
253 /* This reads the MAC core counters (if actaully supported).
254 * by default the MMC core is programmed to reset each
255 * counter after a read. So all the field of the mmc struct
256 * have to be incremented.
258 static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
260 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
261 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
262 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +
263 MMC_TX_BROADCASTFRAME_G);
264 mmc->mmc_tx_multicastframe_g += readl(mmcaddr +
265 MMC_TX_MULTICASTFRAME_G);
266 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);
267 mmc->mmc_tx_65_to_127_octets_gb +=
268 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);
269 mmc->mmc_tx_128_to_255_octets_gb +=
270 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);
271 mmc->mmc_tx_256_to_511_octets_gb +=
272 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);
273 mmc->mmc_tx_512_to_1023_octets_gb +=
274 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);
275 mmc->mmc_tx_1024_to_max_octets_gb +=
276 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
277 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);
278 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);
279 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);
280 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);
281 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);
282 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);
283 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);
284 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);
285 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);
286 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);
287 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);
288 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);
289 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
290 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
291 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
292 mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_TX_LPI_USEC);
293 mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_TX_LPI_TRAN);
295 /* MMC RX counter registers */
296 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
297 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);
298 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);
299 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +
300 MMC_RX_BROADCASTFRAME_G);
301 mmc->mmc_rx_multicastframe_g += readl(mmcaddr +
302 MMC_RX_MULTICASTFRAME_G);
303 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);
304 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);
305 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);
306 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);
307 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);
308 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);
309 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);
310 mmc->mmc_rx_65_to_127_octets_gb +=
311 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);
312 mmc->mmc_rx_128_to_255_octets_gb +=
313 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);
314 mmc->mmc_rx_256_to_511_octets_gb +=
315 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);
316 mmc->mmc_rx_512_to_1023_octets_gb +=
317 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);
318 mmc->mmc_rx_1024_to_max_octets_gb +=
319 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
320 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);
321 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);
322 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);
323 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);
324 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
325 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
326 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
327 mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_RX_LPI_USEC);
328 mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_RX_LPI_TRAN);
331 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
332 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
333 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);
334 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);
335 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);
337 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);
338 mmc->mmc_rx_ipv4_hderr_octets +=
339 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);
340 mmc->mmc_rx_ipv4_nopay_octets +=
341 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);
342 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +
343 MMC_RX_IPV4_FRAG_OCTETS);
344 mmc->mmc_rx_ipv4_udsbl_octets +=
345 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);
348 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);
349 mmc->mmc_rx_ipv6_hderr_octets +=
350 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);
351 mmc->mmc_rx_ipv6_nopay_octets +=
352 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);
354 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);
355 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);
356 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);
359 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);
360 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);
361 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);
362 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);
363 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);
364 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);
366 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);
367 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);
368 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);
369 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
370 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
371 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
373 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);
374 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);
375 mmc->mmc_rx_packet_assembly_err_cntr +=
376 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);
377 mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);
378 mmc->mmc_rx_packet_assembly_ok_cntr +=
379 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);
380 mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);
383 const struct stmmac_mmc_ops dwmac_mmc_ops = {
384 .ctrl = dwmac_mmc_ctrl,
385 .intr_all_mask = dwmac_mmc_intr_all_mask,
386 .read = dwmac_mmc_read,
389 static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
391 u32 value = readl(mmcaddr + MMC_CNTRL);
393 value |= (mode & 0x3F);
395 writel(value, mmcaddr + MMC_CNTRL);
398 static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
400 writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
401 writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
402 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK);
403 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK);
404 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
407 static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
411 tmp += readl(addr + reg);
412 tmp += ((u64 )readl(addr + reg + 0x4)) << 32;
413 if (tmp > GENMASK(31, 0))
419 /* This reads the MAC core counters (if actaully supported).
420 * by default the MMC core is programmed to reset each
421 * counter after a read. So all the field of the mmc struct
422 * have to be incremented.
424 static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
426 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,
427 &mmc->mmc_tx_octetcount_gb);
428 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,
429 &mmc->mmc_tx_framecount_gb);
430 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,
431 &mmc->mmc_tx_broadcastframe_g);
432 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,
433 &mmc->mmc_tx_multicastframe_g);
434 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,
435 &mmc->mmc_tx_64_octets_gb);
436 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,
437 &mmc->mmc_tx_65_to_127_octets_gb);
438 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,
439 &mmc->mmc_tx_128_to_255_octets_gb);
440 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,
441 &mmc->mmc_tx_256_to_511_octets_gb);
442 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,
443 &mmc->mmc_tx_512_to_1023_octets_gb);
444 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,
445 &mmc->mmc_tx_1024_to_max_octets_gb);
446 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,
447 &mmc->mmc_tx_unicast_gb);
448 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,
449 &mmc->mmc_tx_multicast_gb);
450 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,
451 &mmc->mmc_tx_broadcast_gb);
452 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,
453 &mmc->mmc_tx_underflow_error);
454 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,
455 &mmc->mmc_tx_octetcount_g);
456 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,
457 &mmc->mmc_tx_framecount_g);
458 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,
459 &mmc->mmc_tx_pause_frame);
460 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,
461 &mmc->mmc_tx_vlan_frame_g);
462 mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_XGMAC_TX_LPI_USEC);
463 mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_XGMAC_TX_LPI_TRAN);
465 /* MMC RX counter registers */
466 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,
467 &mmc->mmc_rx_framecount_gb);
468 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,
469 &mmc->mmc_rx_octetcount_gb);
470 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,
471 &mmc->mmc_rx_octetcount_g);
472 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,
473 &mmc->mmc_rx_broadcastframe_g);
474 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,
475 &mmc->mmc_rx_multicastframe_g);
476 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
477 &mmc->mmc_rx_crc_error);
478 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
479 &mmc->mmc_rx_crc_error);
480 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);
481 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);
482 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);
483 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);
484 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,
485 &mmc->mmc_rx_64_octets_gb);
486 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,
487 &mmc->mmc_rx_65_to_127_octets_gb);
488 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,
489 &mmc->mmc_rx_128_to_255_octets_gb);
490 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,
491 &mmc->mmc_rx_256_to_511_octets_gb);
492 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,
493 &mmc->mmc_rx_512_to_1023_octets_gb);
494 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,
495 &mmc->mmc_rx_1024_to_max_octets_gb);
496 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,
497 &mmc->mmc_rx_unicast_g);
498 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,
499 &mmc->mmc_rx_length_error);
500 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,
501 &mmc->mmc_rx_autofrangetype);
502 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,
503 &mmc->mmc_rx_pause_frames);
504 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,
505 &mmc->mmc_rx_fifo_overflow);
506 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,
507 &mmc->mmc_rx_vlan_frames_gb);
508 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);
509 mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_XGMAC_RX_LPI_USEC);
510 mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_XGMAC_RX_LPI_TRAN);
511 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_PKT_GB,
512 &mmc->mmc_rx_discard_frames_gb);
513 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_OCT_GB,
514 &mmc->mmc_rx_discard_octets_gb);
515 mmc->mmc_rx_align_err_frames +=
516 readl(mmcaddr + MMC_XGMAC_RX_ALIGN_ERR_PKT);
518 mmc->mmc_sgf_pass_fragment_cntr +=
519 readl(mmcaddr + MMC_XGMAC_SGF_PASS_PKT);
520 mmc->mmc_sgf_fail_fragment_cntr +=
521 readl(mmcaddr + MMC_XGMAC_SGF_FAIL_PKT);
522 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);
523 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);
524 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_GATE_OVERRUN,
525 &mmc->mmc_tx_gate_overrun_cntr);
526 mmc->mmc_rx_packet_assembly_err_cntr +=
527 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);
528 mmc->mmc_rx_packet_smd_err_cntr +=
529 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);
530 mmc->mmc_rx_packet_assembly_ok_cntr +=
531 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);
532 mmc->mmc_rx_fpe_fragment_cntr +=
533 readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);
535 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD,
536 &mmc->mmc_rx_ipv4_gd);
537 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR,
538 &mmc->mmc_rx_ipv4_hderr);
539 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY,
540 &mmc->mmc_rx_ipv4_nopay);
541 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG,
542 &mmc->mmc_rx_ipv4_frag);
543 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL,
544 &mmc->mmc_rx_ipv4_udsbl);
546 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD,
547 &mmc->mmc_rx_ipv6_gd);
548 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR,
549 &mmc->mmc_rx_ipv6_hderr);
550 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY,
551 &mmc->mmc_rx_ipv6_nopay);
553 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD,
554 &mmc->mmc_rx_udp_gd);
555 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR,
556 &mmc->mmc_rx_udp_err);
557 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD,
558 &mmc->mmc_rx_tcp_gd);
559 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR,
560 &mmc->mmc_rx_tcp_err);
561 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD,
562 &mmc->mmc_rx_icmp_gd);
563 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR,
564 &mmc->mmc_rx_icmp_err);
566 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD_OCTETS,
567 &mmc->mmc_rx_ipv4_gd_octets);
568 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR_OCTETS,
569 &mmc->mmc_rx_ipv4_hderr_octets);
570 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY_OCTETS,
571 &mmc->mmc_rx_ipv4_nopay_octets);
572 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG_OCTETS,
573 &mmc->mmc_rx_ipv4_frag_octets);
574 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL_OCTETS,
575 &mmc->mmc_rx_ipv4_udsbl_octets);
577 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD_OCTETS,
578 &mmc->mmc_rx_ipv6_gd_octets);
579 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR_OCTETS,
580 &mmc->mmc_rx_ipv6_hderr_octets);
581 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY_OCTETS,
582 &mmc->mmc_rx_ipv6_nopay_octets);
584 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD_OCTETS,
585 &mmc->mmc_rx_udp_gd_octets);
586 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR_OCTETS,
587 &mmc->mmc_rx_udp_err_octets);
588 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD_OCTETS,
589 &mmc->mmc_rx_tcp_gd_octets);
590 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR_OCTETS,
591 &mmc->mmc_rx_tcp_err_octets);
592 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD_OCTETS,
593 &mmc->mmc_rx_icmp_gd_octets);
594 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR_OCTETS,
595 &mmc->mmc_rx_icmp_err_octets);
598 const struct stmmac_mmc_ops dwxgmac_mmc_ops = {
599 .ctrl = dwxgmac_mmc_ctrl,
600 .intr_all_mask = dwxgmac_mmc_intr_all_mask,
601 .read = dwxgmac_mmc_read,