1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
11 #include "stmmac_ptp.h"
13 struct intel_priv_data {
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
15 unsigned long crossts_adj;
19 /* This struct is used to associate PCI Function of MAC controller on a board,
20 * discovered via DMI, with the address of PHY connected to the MAC. The
21 * negative value of the address means that MAC controller is not connected
24 struct stmmac_pci_func_data {
29 struct stmmac_pci_dmi_data {
30 const struct stmmac_pci_func_data *func;
34 struct stmmac_pci_info {
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 const struct dmi_system_id *dmi_list)
41 const struct stmmac_pci_func_data *func_data;
42 const struct stmmac_pci_dmi_data *dmi_data;
43 const struct dmi_system_id *dmi_id;
44 int func = PCI_FUNC(pdev->devfn);
47 dmi_id = dmi_first_match(dmi_list);
51 dmi_data = dmi_id->driver_data;
52 func_data = dmi_data->func;
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 if (func_data->func == func)
56 return func_data->phy_addr;
61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
62 int phyreg, u32 mask, u32 val)
64 unsigned int retries = 10;
68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
69 if ((val_rd & mask) == (val & mask))
71 udelay(POLL_DELAY_US);
77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
79 struct intel_priv_data *intel_priv = priv_data;
80 struct stmmac_priv *priv = netdev_priv(ndev);
81 int serdes_phy_addr = 0;
84 if (!intel_priv->mdio_adhoc_addr)
87 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
89 /* Set the serdes rate and the PCLK rate */
90 data = mdiobus_read(priv->mii, serdes_phy_addr,
93 data &= ~SERDES_RATE_MASK;
94 data &= ~SERDES_PCLK_MASK;
96 if (priv->plat->max_speed == 2500)
97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
107 data |= SERDES_PLL_CLK;
108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
110 /* check for clk_ack assertion */
111 data = serdes_status_poll(priv, serdes_phy_addr,
117 dev_err(priv->device, "Serdes PLL clk request timeout\n");
121 /* assert lane reset */
122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
126 /* check for assert lane reset reflection */
127 data = serdes_status_poll(priv, serdes_phy_addr,
133 dev_err(priv->device, "Serdes assert lane reset timeout\n");
137 /* move power state to P0 */
138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
140 data &= ~SERDES_PWR_ST_MASK;
141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
145 /* Check for P0 state */
146 data = serdes_status_poll(priv, serdes_phy_addr,
149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
152 dev_err(priv->device, "Serdes power state P0 timeout.\n");
156 /* PSE only - ungate SGMII PHY Rx Clock */
157 if (intel_priv->is_pse)
158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
159 0, SERDES_PHY_RX_CLK);
164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
166 struct intel_priv_data *intel_priv = intel_data;
167 struct stmmac_priv *priv = netdev_priv(ndev);
168 int serdes_phy_addr = 0;
171 if (!intel_priv->mdio_adhoc_addr)
174 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
176 /* PSE only - gate SGMII PHY Rx Clock */
177 if (intel_priv->is_pse)
178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
179 SERDES_PHY_RX_CLK, 0);
181 /* move power state to P3 */
182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
184 data &= ~SERDES_PWR_ST_MASK;
185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
189 /* Check for P3 state */
190 data = serdes_status_poll(priv, serdes_phy_addr,
193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
196 dev_err(priv->device, "Serdes power state P3 timeout\n");
200 /* de-assert clk_req */
201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
202 data &= ~SERDES_PLL_CLK;
203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
205 /* check for clk_ack de-assert */
206 data = serdes_status_poll(priv, serdes_phy_addr,
209 (u32)~SERDES_PLL_CLK);
212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
216 /* de-assert lane reset */
217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
221 /* check for de-assert lane reset reflection */
222 data = serdes_status_poll(priv, serdes_phy_addr,
228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
235 struct intel_priv_data *intel_priv = intel_data;
236 struct stmmac_priv *priv = netdev_priv(ndev);
237 int serdes_phy_addr = 0;
240 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
242 /* Determine the link speed mode: 2.5Gbps/1Gbps */
243 data = mdiobus_read(priv->mii, serdes_phy_addr,
246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
247 SERDES_LINK_MODE_2G5) {
248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
249 priv->plat->max_speed = 2500;
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 priv->plat->mdio_bus_data->xpcs_an_inband = false;
253 priv->plat->max_speed = 1000;
254 priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
255 priv->plat->mdio_bus_data->xpcs_an_inband = true;
259 /* Program PTP Clock Frequency for different variant of
260 * Intel mGBE that has slightly different GPO mapping
262 static void intel_mgbe_ptp_clk_freq_config(void *npriv)
264 struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
265 struct intel_priv_data *intel_priv;
268 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
270 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
272 if (intel_priv->is_pse) {
273 /* For PSE GbE, use 200MHz */
274 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
275 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
277 /* For PCH GbE, use 200MHz */
278 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
279 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
282 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
285 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
290 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
291 ns <<= GMAC4_ART_TIME_SHIFT;
292 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
293 ns <<= GMAC4_ART_TIME_SHIFT;
294 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
295 ns <<= GMAC4_ART_TIME_SHIFT;
296 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
301 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
303 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
306 static int intel_crosststamp(ktime_t *device,
307 struct system_counterval_t *system,
310 struct intel_priv_data *intel_priv;
312 struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
313 void __iomem *ptpaddr = priv->ptpaddr;
314 void __iomem *ioaddr = priv->hw->pcsr;
323 if (!boot_cpu_has(X86_FEATURE_ART))
326 intel_priv = priv->plat->bsp_priv;
328 /* Both internal crosstimestamping and external triggered event
329 * timestamping cannot be run concurrently.
331 if (priv->plat->ext_snapshot_en)
334 priv->plat->int_snapshot_en = 1;
336 mutex_lock(&priv->aux_ts_lock);
337 /* Enable Internal snapshot trigger */
338 acr_value = readl(ptpaddr + PTP_ACR);
339 acr_value &= ~PTP_ACR_MASK;
340 switch (priv->plat->int_snapshot_num) {
342 acr_value |= PTP_ACR_ATSEN0;
345 acr_value |= PTP_ACR_ATSEN1;
348 acr_value |= PTP_ACR_ATSEN2;
351 acr_value |= PTP_ACR_ATSEN3;
354 mutex_unlock(&priv->aux_ts_lock);
355 priv->plat->int_snapshot_en = 0;
358 writel(acr_value, ptpaddr + PTP_ACR);
361 acr_value = readl(ptpaddr + PTP_ACR);
362 acr_value |= PTP_ACR_ATSFC;
363 writel(acr_value, ptpaddr + PTP_ACR);
364 /* Release the mutex */
365 mutex_unlock(&priv->aux_ts_lock);
367 /* Trigger Internal snapshot signal
368 * Create a rising edge by just toggle the GPO1 to low
371 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
372 gpio_value &= ~GMAC_GPO1;
373 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
374 gpio_value |= GMAC_GPO1;
375 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
377 /* Time sync done Indication - Interrupt method */
378 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
379 stmmac_cross_ts_isr(priv),
381 priv->plat->int_snapshot_en = 0;
385 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
386 GMAC_TIMESTAMP_ATSNS_MASK) >>
387 GMAC_TIMESTAMP_ATSNS_SHIFT;
389 /* Repeat until the timestamps are from the FIFO last segment */
390 for (i = 0; i < num_snapshot; i++) {
391 read_lock_irqsave(&priv->ptp_lock, flags);
392 stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
393 *device = ns_to_ktime(ptp_time);
394 read_unlock_irqrestore(&priv->ptp_lock, flags);
395 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
396 *system = convert_art_to_tsc(art_time);
399 system->cycles *= intel_priv->crossts_adj;
400 priv->plat->int_snapshot_en = 0;
405 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
408 if (boot_cpu_has(X86_FEATURE_ART)) {
409 unsigned int art_freq;
411 /* On systems that support ART, ART frequency can be obtained
412 * from ECX register of CPUID leaf (0x15).
414 art_freq = cpuid_ecx(ART_CPUID_LEAF);
415 do_div(art_freq, base);
416 intel_priv->crossts_adj = art_freq;
420 static void common_default_data(struct plat_stmmacenet_data *plat)
422 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
424 plat->force_sf_dma_mode = 1;
426 plat->mdio_bus_data->needs_reset = true;
428 /* Set default value for multicast hash bins */
429 plat->multicast_filter_bins = HASH_TABLE_SIZE;
431 /* Set default value for unicast filter entries */
432 plat->unicast_filter_entries = 1;
434 /* Set the maxmtu to a default of JUMBO_LEN */
435 plat->maxmtu = JUMBO_LEN;
437 /* Set default number of RX and TX queues to use */
438 plat->tx_queues_to_use = 1;
439 plat->rx_queues_to_use = 1;
441 /* Disable Priority config by default */
442 plat->tx_queues_cfg[0].use_prio = false;
443 plat->rx_queues_cfg[0].use_prio = false;
445 /* Disable RX queues routing by default */
446 plat->rx_queues_cfg[0].pkt_route = 0x0;
449 static int intel_mgbe_common_data(struct pci_dev *pdev,
450 struct plat_stmmacenet_data *plat)
461 plat->force_sf_dma_mode = 0;
463 plat->sph_disable = 1;
465 /* Multiplying factor to the clk_eee_i clock time
466 * period to make it closer to 100 ns. This value
467 * should be programmed such that the clk_eee_time_period *
468 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
469 * clk_eee frequency is 19.2Mhz
470 * clk_eee_time_period is 52ns
471 * 52ns * (1 + 1) = 104ns
472 * MULT_FACT_100NS = 1
474 plat->mult_fact_100ns = 1;
476 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
478 for (i = 0; i < plat->rx_queues_to_use; i++) {
479 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
480 plat->rx_queues_cfg[i].chan = i;
482 /* Disable Priority config by default */
483 plat->rx_queues_cfg[i].use_prio = false;
485 /* Disable RX queues routing by default */
486 plat->rx_queues_cfg[i].pkt_route = 0x0;
489 for (i = 0; i < plat->tx_queues_to_use; i++) {
490 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
492 /* Disable Priority config by default */
493 plat->tx_queues_cfg[i].use_prio = false;
494 /* Default TX Q0 to use TSO and rest TXQ for TBS */
496 plat->tx_queues_cfg[i].tbs_en = 1;
499 /* FIFO size is 4096 bytes for 1 tx/rx queue */
500 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
501 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
503 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
504 plat->tx_queues_cfg[0].weight = 0x09;
505 plat->tx_queues_cfg[1].weight = 0x0A;
506 plat->tx_queues_cfg[2].weight = 0x0B;
507 plat->tx_queues_cfg[3].weight = 0x0C;
508 plat->tx_queues_cfg[4].weight = 0x0D;
509 plat->tx_queues_cfg[5].weight = 0x0E;
510 plat->tx_queues_cfg[6].weight = 0x0F;
511 plat->tx_queues_cfg[7].weight = 0x10;
513 plat->dma_cfg->pbl = 32;
514 plat->dma_cfg->pblx8 = true;
515 plat->dma_cfg->fixed_burst = 0;
516 plat->dma_cfg->mixed_burst = 0;
517 plat->dma_cfg->aal = 0;
518 plat->dma_cfg->dche = true;
520 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
525 plat->axi->axi_lpi_en = 0;
526 plat->axi->axi_xit_frm = 0;
527 plat->axi->axi_wr_osr_lmt = 1;
528 plat->axi->axi_rd_osr_lmt = 1;
529 plat->axi->axi_blen[0] = 4;
530 plat->axi->axi_blen[1] = 8;
531 plat->axi->axi_blen[2] = 16;
533 plat->ptp_max_adj = plat->clk_ptp_rate;
534 plat->eee_usecs_rate = plat->clk_ptp_rate;
536 /* Set system clock */
537 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
539 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
543 if (IS_ERR(plat->stmmac_clk)) {
544 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
545 plat->stmmac_clk = NULL;
548 ret = clk_prepare_enable(plat->stmmac_clk);
550 clk_unregister_fixed_rate(plat->stmmac_clk);
554 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
556 /* Set default value for multicast hash bins */
557 plat->multicast_filter_bins = HASH_TABLE_SIZE;
559 /* Set default value for unicast filter entries */
560 plat->unicast_filter_entries = 1;
562 /* Set the maxmtu to a default of JUMBO_LEN */
563 plat->maxmtu = JUMBO_LEN;
565 plat->vlan_fail_q_en = true;
567 /* Use the last Rx queue */
568 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
570 /* Intel mgbe SGMII interface uses pcs-xcps */
571 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII) {
572 plat->mdio_bus_data->has_xpcs = true;
573 plat->mdio_bus_data->xpcs_an_inband = true;
576 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
577 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
578 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
580 plat->int_snapshot_num = AUX_SNAPSHOT1;
581 plat->ext_snapshot_num = AUX_SNAPSHOT0;
583 plat->has_crossts = true;
584 plat->crosststamp = intel_crosststamp;
585 plat->int_snapshot_en = 0;
587 /* Setup MSI vector offset specific to Intel mGbE controller */
588 plat->msi_mac_vec = 29;
589 plat->msi_lpi_vec = 28;
590 plat->msi_sfty_ce_vec = 27;
591 plat->msi_sfty_ue_vec = 26;
592 plat->msi_rx_base_vec = 0;
593 plat->msi_tx_base_vec = 1;
598 static int ehl_common_data(struct pci_dev *pdev,
599 struct plat_stmmacenet_data *plat)
601 plat->rx_queues_to_use = 8;
602 plat->tx_queues_to_use = 8;
603 plat->clk_ptp_rate = 200000000;
604 plat->use_phy_wol = 1;
606 plat->safety_feat_cfg->tsoee = 1;
607 plat->safety_feat_cfg->mrxpee = 1;
608 plat->safety_feat_cfg->mestee = 1;
609 plat->safety_feat_cfg->mrxee = 1;
610 plat->safety_feat_cfg->mtxee = 1;
611 plat->safety_feat_cfg->epsi = 0;
612 plat->safety_feat_cfg->edpp = 0;
613 plat->safety_feat_cfg->prtyen = 0;
614 plat->safety_feat_cfg->tmouten = 0;
616 return intel_mgbe_common_data(pdev, plat);
619 static int ehl_sgmii_data(struct pci_dev *pdev,
620 struct plat_stmmacenet_data *plat)
623 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
624 plat->speed_mode_2500 = intel_speed_mode_2500;
625 plat->serdes_powerup = intel_serdes_powerup;
626 plat->serdes_powerdown = intel_serdes_powerdown;
628 return ehl_common_data(pdev, plat);
631 static struct stmmac_pci_info ehl_sgmii1g_info = {
632 .setup = ehl_sgmii_data,
635 static int ehl_rgmii_data(struct pci_dev *pdev,
636 struct plat_stmmacenet_data *plat)
639 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
641 return ehl_common_data(pdev, plat);
644 static struct stmmac_pci_info ehl_rgmii1g_info = {
645 .setup = ehl_rgmii_data,
648 static int ehl_pse0_common_data(struct pci_dev *pdev,
649 struct plat_stmmacenet_data *plat)
651 struct intel_priv_data *intel_priv = plat->bsp_priv;
653 intel_priv->is_pse = true;
657 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
659 return ehl_common_data(pdev, plat);
662 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
663 struct plat_stmmacenet_data *plat)
665 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
666 return ehl_pse0_common_data(pdev, plat);
669 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
670 .setup = ehl_pse0_rgmii1g_data,
673 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
674 struct plat_stmmacenet_data *plat)
676 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
677 plat->speed_mode_2500 = intel_speed_mode_2500;
678 plat->serdes_powerup = intel_serdes_powerup;
679 plat->serdes_powerdown = intel_serdes_powerdown;
680 return ehl_pse0_common_data(pdev, plat);
683 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
684 .setup = ehl_pse0_sgmii1g_data,
687 static int ehl_pse1_common_data(struct pci_dev *pdev,
688 struct plat_stmmacenet_data *plat)
690 struct intel_priv_data *intel_priv = plat->bsp_priv;
692 intel_priv->is_pse = true;
696 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
698 return ehl_common_data(pdev, plat);
701 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
702 struct plat_stmmacenet_data *plat)
704 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
705 return ehl_pse1_common_data(pdev, plat);
708 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
709 .setup = ehl_pse1_rgmii1g_data,
712 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
713 struct plat_stmmacenet_data *plat)
715 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
716 plat->speed_mode_2500 = intel_speed_mode_2500;
717 plat->serdes_powerup = intel_serdes_powerup;
718 plat->serdes_powerdown = intel_serdes_powerdown;
719 return ehl_pse1_common_data(pdev, plat);
722 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
723 .setup = ehl_pse1_sgmii1g_data,
726 static int tgl_common_data(struct pci_dev *pdev,
727 struct plat_stmmacenet_data *plat)
729 plat->rx_queues_to_use = 6;
730 plat->tx_queues_to_use = 4;
731 plat->clk_ptp_rate = 200000000;
732 plat->speed_mode_2500 = intel_speed_mode_2500;
734 plat->safety_feat_cfg->tsoee = 1;
735 plat->safety_feat_cfg->mrxpee = 0;
736 plat->safety_feat_cfg->mestee = 1;
737 plat->safety_feat_cfg->mrxee = 1;
738 plat->safety_feat_cfg->mtxee = 1;
739 plat->safety_feat_cfg->epsi = 0;
740 plat->safety_feat_cfg->edpp = 0;
741 plat->safety_feat_cfg->prtyen = 0;
742 plat->safety_feat_cfg->tmouten = 0;
744 return intel_mgbe_common_data(pdev, plat);
747 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
748 struct plat_stmmacenet_data *plat)
751 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
752 plat->serdes_powerup = intel_serdes_powerup;
753 plat->serdes_powerdown = intel_serdes_powerdown;
754 return tgl_common_data(pdev, plat);
757 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
758 .setup = tgl_sgmii_phy0_data,
761 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
762 struct plat_stmmacenet_data *plat)
765 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
766 plat->serdes_powerup = intel_serdes_powerup;
767 plat->serdes_powerdown = intel_serdes_powerdown;
768 return tgl_common_data(pdev, plat);
771 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
772 .setup = tgl_sgmii_phy1_data,
775 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
776 struct plat_stmmacenet_data *plat)
779 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
781 /* SerDes power up and power down are done in BIOS for ADL */
783 return tgl_common_data(pdev, plat);
786 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
787 .setup = adls_sgmii_phy0_data,
790 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
791 struct plat_stmmacenet_data *plat)
794 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
796 /* SerDes power up and power down are done in BIOS for ADL */
798 return tgl_common_data(pdev, plat);
801 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
802 .setup = adls_sgmii_phy1_data,
804 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
811 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
812 .func = galileo_stmmac_func_data,
813 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
816 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
827 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
828 .func = iot2040_stmmac_func_data,
829 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
832 static const struct dmi_system_id quark_pci_dmi[] = {
835 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
837 .driver_data = (void *)&galileo_stmmac_dmi_data,
841 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
843 .driver_data = (void *)&galileo_stmmac_dmi_data,
845 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
846 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
847 * has only one pci network device while other asset tags are
848 * for IOT2040 which has two.
852 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
853 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
854 "6ES7647-0AA00-0YA2"),
856 .driver_data = (void *)&galileo_stmmac_dmi_data,
860 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
862 .driver_data = (void *)&iot2040_stmmac_dmi_data,
867 static int quark_default_data(struct pci_dev *pdev,
868 struct plat_stmmacenet_data *plat)
872 /* Set common default data first */
873 common_default_data(plat);
875 /* Refuse to load the driver and register net device if MAC controller
876 * does not connect to any PHY interface.
878 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
880 /* Return error to the caller on DMI enabled boards. */
881 if (dmi_get_system_info(DMI_BOARD_NAME))
884 /* Galileo boards with old firmware don't support DMI. We always
885 * use 1 here as PHY address, so at least the first found MAC
886 * controller would be probed.
891 plat->bus_id = pci_dev_id(pdev);
892 plat->phy_addr = ret;
893 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
895 plat->dma_cfg->pbl = 16;
896 plat->dma_cfg->pblx8 = true;
897 plat->dma_cfg->fixed_burst = 1;
903 static const struct stmmac_pci_info quark_info = {
904 .setup = quark_default_data,
907 static int stmmac_config_single_msi(struct pci_dev *pdev,
908 struct plat_stmmacenet_data *plat,
909 struct stmmac_resources *res)
913 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
915 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
920 res->irq = pci_irq_vector(pdev, 0);
921 res->wol_irq = res->irq;
922 plat->multi_msi_en = 0;
923 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
929 static int stmmac_config_multi_msi(struct pci_dev *pdev,
930 struct plat_stmmacenet_data *plat,
931 struct stmmac_resources *res)
936 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
937 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
938 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
943 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
944 PCI_IRQ_MSI | PCI_IRQ_MSIX);
946 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
952 for (i = 0; i < plat->rx_queues_to_use; i++) {
953 res->rx_irq[i] = pci_irq_vector(pdev,
954 plat->msi_rx_base_vec + i * 2);
958 for (i = 0; i < plat->tx_queues_to_use; i++) {
959 res->tx_irq[i] = pci_irq_vector(pdev,
960 plat->msi_tx_base_vec + i * 2);
963 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
964 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
965 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
966 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
967 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
968 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
969 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
970 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
971 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
972 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
974 plat->multi_msi_en = 1;
975 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
981 * intel_eth_pci_probe
983 * @pdev: pci device pointer
984 * @id: pointer to table of device id/id's.
986 * Description: This probing function gets called for all PCI devices which
987 * match the ID table and are not "owned" by other driver yet. This function
988 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
989 * matches the device. The probe functions returns zero when the driver choose
990 * to take "ownership" of the device or an error code(-ve no) otherwise.
992 static int intel_eth_pci_probe(struct pci_dev *pdev,
993 const struct pci_device_id *id)
995 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
996 struct intel_priv_data *intel_priv;
997 struct plat_stmmacenet_data *plat;
998 struct stmmac_resources res;
1001 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1005 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1009 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1010 sizeof(*plat->mdio_bus_data),
1012 if (!plat->mdio_bus_data)
1015 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1020 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1021 sizeof(*plat->safety_feat_cfg),
1023 if (!plat->safety_feat_cfg)
1026 /* Enable pci device */
1027 ret = pcim_enable_device(pdev);
1029 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1034 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1038 pci_set_master(pdev);
1040 plat->bsp_priv = intel_priv;
1041 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1042 intel_priv->crossts_adj = 1;
1044 /* Initialize all MSI vectors to invalid so that it can be set
1045 * according to platform data settings below.
1046 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1048 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1049 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1050 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1051 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1052 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1053 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1054 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1056 ret = info->setup(pdev, plat);
1060 memset(&res, 0, sizeof(res));
1061 res.addr = pcim_iomap_table(pdev)[0];
1063 if (plat->eee_usecs_rate > 0) {
1066 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1067 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1070 ret = stmmac_config_multi_msi(pdev, plat, &res);
1072 ret = stmmac_config_single_msi(pdev, plat, &res);
1074 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1080 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1088 clk_disable_unprepare(plat->stmmac_clk);
1089 clk_unregister_fixed_rate(plat->stmmac_clk);
1094 * intel_eth_pci_remove
1096 * @pdev: pci device pointer
1097 * Description: this function calls the main to free the net resources
1098 * and releases the PCI resources.
1100 static void intel_eth_pci_remove(struct pci_dev *pdev)
1102 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1103 struct stmmac_priv *priv = netdev_priv(ndev);
1105 stmmac_dvr_remove(&pdev->dev);
1107 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1109 pcim_iounmap_regions(pdev, BIT(0));
1112 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1114 struct pci_dev *pdev = to_pci_dev(dev);
1117 ret = stmmac_suspend(dev);
1121 ret = pci_save_state(pdev);
1125 pci_wake_from_d3(pdev, true);
1126 pci_set_power_state(pdev, PCI_D3hot);
1130 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1132 struct pci_dev *pdev = to_pci_dev(dev);
1135 pci_restore_state(pdev);
1136 pci_set_power_state(pdev, PCI_D0);
1138 ret = pcim_enable_device(pdev);
1142 pci_set_master(pdev);
1144 return stmmac_resume(dev);
1147 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1148 intel_eth_pci_resume);
1150 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937
1151 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
1152 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31
1153 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
1154 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1155 * which are named PSE0 and PSE1
1157 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
1158 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
1159 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
1160 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
1161 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
1162 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
1163 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac
1164 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2
1165 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac
1166 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac
1167 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad
1168 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac
1169 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac
1171 static const struct pci_device_id intel_eth_pci_id_table[] = {
1172 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1173 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1174 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1175 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1176 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1177 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1178 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1179 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1180 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1181 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1182 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1183 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1184 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1185 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1186 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1187 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1188 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1191 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1193 static struct pci_driver intel_eth_pci_driver = {
1194 .name = "intel-eth-pci",
1195 .id_table = intel_eth_pci_id_table,
1196 .probe = intel_eth_pci_probe,
1197 .remove = intel_eth_pci_remove,
1199 .pm = &intel_eth_pm_ops,
1203 module_pci_driver(intel_eth_pci_driver);
1205 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1206 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1207 MODULE_LICENSE("GPL v2");