drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/delay.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/string.h>
  17 #include "qed.h"
  18 #include "qed_hsi.h"
  19 #include "qed_hw.h"
  20 #include "qed_mcp.h"
  21 #include "qed_reg_addr.h"
  22 #define CHIP_MCP_RESP_ITER_US 10
  23
  24 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  25 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  26
  27 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  28         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  29                _val)
  30
  31 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  32         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  33
  34 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  35         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  36                      offsetof(struct public_drv_mb, _field), _val)
  37
  38 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  39         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  40                      offsetof(struct public_drv_mb, _field))
  41
  42 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  43                   DRV_ID_PDA_COMP_VER_SHIFT)
  44
  45 #define MCP_BYTES_PER_MBIT_SHIFT 17
  46
  47 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  48 {
  49         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  50                 return false;
  51         return true;
  52 }
  53
  54 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn,
  55                            struct qed_ptt *p_ptt)
  56 {
  57         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  58                                         PUBLIC_PORT);
  59         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  60
  61         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  62                                                    MFW_PORT(p_hwfn));
  63         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  64                    "port_addr = 0x%x, port_id 0x%02x\n",
  65                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  66 }
  67
  68 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn,
  69                      struct qed_ptt *p_ptt)
  70 {
  71         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  72         u32 tmp, i;
  73
  74         if (!p_hwfn->mcp_info->public_base)
  75                 return;
  76
  77         for (i = 0; i < length; i++) {
  78                 tmp = qed_rd(p_hwfn, p_ptt,
  79                              p_hwfn->mcp_info->mfw_mb_addr +
  80                              (i << 2) + sizeof(u32));
  81
  82                 /* The MB data is actually BE; Need to force it to cpu */
  83                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  84                         be32_to_cpu((__force __be32)tmp);
  85         }
  86 }
  87
  88 int qed_mcp_free(struct qed_hwfn *p_hwfn)
  89 {
  90         if (p_hwfn->mcp_info) {
  91                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
  92                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
  93         }
  94         kfree(p_hwfn->mcp_info);
  95
  96         return 0;
  97 }
  98
  99 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn,
 100                                 struct qed_ptt *p_ptt)
 101 {
 102         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 103         u32 drv_mb_offsize, mfw_mb_offsize;
 104         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 105
 106         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 107         if (!p_info->public_base)
 108                 return 0;
 109
 110         p_info->public_base |= GRCBASE_MCP;
 111
 112         /* Calculate the driver and MFW mailbox address */
 113         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 114                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 115                                                      PUBLIC_DRV_MB));
 116         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 117         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 118                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 119                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 120
 121         /* Set the MFW MB address */
 122         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 123                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 124                                                      PUBLIC_MFW_MB));
 125         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 126         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
 127
 128         /* Get the current driver mailbox sequence before sending
 129          * the first command
 130          */
 131         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 132                              DRV_MSG_SEQ_NUMBER_MASK;
 133
 134         /* Get current FW pulse sequence */
 135         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 136                                 DRV_PULSE_SEQ_MASK;
 137
 138         p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 139
 140         return 0;
 141 }
 142
 143 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn,
 144                      struct qed_ptt *p_ptt)
 145 {
 146         struct qed_mcp_info *p_info;
 147         u32 size;
 148
 149         /* Allocate mcp_info structure */
 150         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 151         if (!p_hwfn->mcp_info)
 152                 goto err;
 153         p_info = p_hwfn->mcp_info;
 154
 155         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 156                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 157                 /* Do not free mcp_info here, since public_base indicate that
 158                  * the MCP is not initialized
 159                  */
 160                 return 0;
 161         }
 162
 163         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 164         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 165         p_info->mfw_mb_shadow =
 166                 kzalloc(sizeof(u32) * MFW_DRV_MSG_MAX_DWORDS(
 167                                 p_info->mfw_mb_length), GFP_KERNEL);
 168         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 169                 goto err;
 170
 171         /* Initialize the MFW spinlock */
 172         spin_lock_init(&p_info->lock);
 173
 174         return 0;
 175
 176 err:
 177         DP_NOTICE(p_hwfn, "Failed to allocate mcp memory\n");
 178         qed_mcp_free(p_hwfn);
 179         return -ENOMEM;
 180 }
 181
 182 /* Locks the MFW mailbox of a PF to ensure a single access.
 183  * The lock is achieved in most cases by holding a spinlock, causing other
 184  * threads to wait till a previous access is done.
 185  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 186  * access is achieved by setting a blocking flag, which will fail other
 187  * competing contexts to send their mailboxes.
 188  */
 189 static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn,
 190                            u32 cmd)
 191 {
 192         spin_lock_bh(&p_hwfn->mcp_info->lock);
 193
 194         /* The spinlock shouldn't be acquired when the mailbox command is
 195          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 196          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 197          * (i.e. interrupts are disabled) - can lead to a deadlock.
 198          * It is assumed that for a single PF, no other mailbox commands can be
 199          * sent from another context while sending LOAD_REQ, and that any
 200          * parallel commands to UNLOAD_REQ can be cancelled.
 201          */
 202         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 203                 p_hwfn->mcp_info->block_mb_sending = false;
 204
 205         if (p_hwfn->mcp_info->block_mb_sending) {
 206                 DP_NOTICE(p_hwfn,
 207                           "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
 208                           cmd);
 209                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 210                 return -EBUSY;
 211         }
 212
 213         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 214                 p_hwfn->mcp_info->block_mb_sending = true;
 215                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 216         }
 217
 218         return 0;
 219 }
 220
 221 static void qed_mcp_mb_unlock(struct qed_hwfn   *p_hwfn,
 222                               u32               cmd)
 223 {
 224         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 225                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 226 }
 227
 228 int qed_mcp_reset(struct qed_hwfn *p_hwfn,
 229                   struct qed_ptt *p_ptt)
 230 {
 231         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 232         u8 delay = CHIP_MCP_RESP_ITER_US;
 233         u32 org_mcp_reset_seq, cnt = 0;
 234         int rc = 0;
 235
 236         /* Ensure that only a single thread is accessing the mailbox at a
 237          * certain time.
 238          */
 239         rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 240         if (rc != 0)
 241                 return rc;
 242
 243         /* Set drv command along with the updated sequence */
 244         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 245         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header,
 246                   (DRV_MSG_CODE_MCP_RESET | seq));
 247
 248         do {
 249                 /* Wait for MFW response */
 250                 udelay(delay);
 251                 /* Give the FW up to 500 second (50*1000*10usec) */
 252         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 253                                               MISCS_REG_GENERIC_POR_0)) &&
 254                  (cnt++ < QED_MCP_RESET_RETRIES));
 255
 256         if (org_mcp_reset_seq !=
 257             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 258                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 259                            "MCP was reset after %d usec\n", cnt * delay);
 260         } else {
 261                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 262                 rc = -EAGAIN;
 263         }
 264
 265         qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 266
 267         return rc;
 268 }
 269
 270 static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn,
 271                           struct qed_ptt *p_ptt,
 272                           u32 cmd,
 273                           u32 param,
 274                           u32 *o_mcp_resp,
 275                           u32 *o_mcp_param)
 276 {
 277         u8 delay = CHIP_MCP_RESP_ITER_US;
 278         u32 seq, cnt = 1, actual_mb_seq;
 279         int rc = 0;
 280
 281         /* Get actual driver mailbox sequence */
 282         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 283                         DRV_MSG_SEQ_NUMBER_MASK;
 284
 285         /* Use MCP history register to check if MCP reset occurred between
 286          * init time and now.
 287          */
 288         if (p_hwfn->mcp_info->mcp_hist !=
 289             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 290                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n");
 291                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 292                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 293         }
 294         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 295
 296         /* Set drv param */
 297         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 298
 299         /* Set drv command along with the updated sequence */
 300         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 301
 302         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 303                    "wrote command (%x) to MFW MB param 0x%08x\n",
 304                    (cmd | seq), param);
 305
 306         do {
 307                 /* Wait for MFW response */
 308                 udelay(delay);
 309                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 310
 311                 /* Give the FW up to 5 second (500*10ms) */
 312         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 313                  (cnt++ < QED_DRV_MB_MAX_RETRIES));
 314
 315         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 316                    "[after %d ms] read (%x) seq is (%x) from FW MB\n",
 317                    cnt * delay, *o_mcp_resp, seq);
 318
 319         /* Is this a reply to our command? */
 320         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 321                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 322                 /* Get the MCP param */
 323                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 324         } else {
 325                 /* FW BUG! */
 326                 DP_ERR(p_hwfn, "MFW failed to respond!\n");
 327                 *o_mcp_resp = 0;
 328                 rc = -EAGAIN;
 329         }
 330         return rc;
 331 }
 332
 333 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 334                                  struct qed_ptt *p_ptt,
 335                                  struct qed_mcp_mb_params *p_mb_params)
 336 {
 337         u32 union_data_addr;
 338         int rc;
 339
 340         /* MCP not initialized */
 341         if (!qed_mcp_is_init(p_hwfn)) {
 342                 DP_NOTICE(p_hwfn, "MFW is not initialized !\n");
 343                 return -EBUSY;
 344         }
 345
 346         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 347                           offsetof(struct public_drv_mb, union_data);
 348
 349         /* Ensure that only a single thread is accessing the mailbox at a
 350          * certain time.
 351          */
 352         rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 353         if (rc)
 354                 return rc;
 355
 356         if (p_mb_params->p_data_src != NULL)
 357                 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 358                               p_mb_params->p_data_src,
 359                               sizeof(*p_mb_params->p_data_src));
 360
 361         rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 362                             p_mb_params->param, &p_mb_params->mcp_resp,
 363                             &p_mb_params->mcp_param);
 364
 365         if (p_mb_params->p_data_dst != NULL)
 366                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 367                                 union_data_addr,
 368                                 sizeof(*p_mb_params->p_data_dst));
 369
 370         qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 371
 372         return rc;
 373 }
 374
 375 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 376                 struct qed_ptt *p_ptt,
 377                 u32 cmd,
 378                 u32 param,
 379                 u32 *o_mcp_resp,
 380                 u32 *o_mcp_param)
 381 {
 382         struct qed_mcp_mb_params mb_params;
 383         int rc;
 384
 385         memset(&mb_params, 0, sizeof(mb_params));
 386         mb_params.cmd = cmd;
 387         mb_params.param = param;
 388         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 389         if (rc)
 390                 return rc;
 391
 392         *o_mcp_resp = mb_params.mcp_resp;
 393         *o_mcp_param = mb_params.mcp_param;
 394
 395         return 0;
 396 }
 397
 398 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 399                      struct qed_ptt *p_ptt,
 400                      u32 *p_load_code)
 401 {
 402         struct qed_dev *cdev = p_hwfn->cdev;
 403         struct qed_mcp_mb_params mb_params;
 404         union drv_union_data union_data;
 405         int rc;
 406
 407         memset(&mb_params, 0, sizeof(mb_params));
 408         /* Load Request */
 409         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 410         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 411                           cdev->drv_type;
 412         memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE);
 413         mb_params.p_data_src = &union_data;
 414         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 415
 416         /* if mcp fails to respond we must abort */
 417         if (rc) {
 418                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 419                 return rc;
 420         }
 421
 422         *p_load_code = mb_params.mcp_resp;
 423
 424         /* If MFW refused (e.g. other port is in diagnostic mode) we
 425          * must abort. This can happen in the following cases:
 426          * - Other port is in diagnostic mode
 427          * - Previously loaded function on the engine is not compliant with
 428          *   the requester.
 429          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 430          *      -
 431          */
 432         if (!(*p_load_code) ||
 433             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 434             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 435             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 436                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 437                 return -EBUSY;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
 444                                               struct qed_ptt *p_ptt)
 445 {
 446         u32 transceiver_state;
 447
 448         transceiver_state = qed_rd(p_hwfn, p_ptt,
 449                                    p_hwfn->mcp_info->port_addr +
 450                                    offsetof(struct public_port,
 451                                             transceiver_data));
 452
 453         DP_VERBOSE(p_hwfn,
 454                    (NETIF_MSG_HW | QED_MSG_SP),
 455                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
 456                    transceiver_state,
 457                    (u32)(p_hwfn->mcp_info->port_addr +
 458                          offsetof(struct public_port,
 459                                   transceiver_data)));
 460
 461         transceiver_state = GET_FIELD(transceiver_state,
 462                                       PMM_TRANSCEIVER_STATE);
 463
 464         if (transceiver_state == PMM_TRANSCEIVER_STATE_PRESENT)
 465                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
 466         else
 467                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
 468 }
 469
 470 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
 471                                        struct qed_ptt *p_ptt,
 472                                        bool b_reset)
 473 {
 474         struct qed_mcp_link_state *p_link;
 475         u8 max_bw, min_bw;
 476         u32 status = 0;
 477
 478         p_link = &p_hwfn->mcp_info->link_output;
 479         memset(p_link, 0, sizeof(*p_link));
 480         if (!b_reset) {
 481                 status = qed_rd(p_hwfn, p_ptt,
 482                                 p_hwfn->mcp_info->port_addr +
 483                                 offsetof(struct public_port, link_status));
 484                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
 485                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
 486                            status,
 487                            (u32)(p_hwfn->mcp_info->port_addr +
 488                                  offsetof(struct public_port,
 489                                           link_status)));
 490         } else {
 491                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 492                            "Resetting link indications\n");
 493                 return;
 494         }
 495
 496         if (p_hwfn->b_drv_link_init)
 497                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 498         else
 499                 p_link->link_up = false;
 500
 501         p_link->full_duplex = true;
 502         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 503         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 504                 p_link->speed = 100000;
 505                 break;
 506         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 507                 p_link->speed = 50000;
 508                 break;
 509         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 510                 p_link->speed = 40000;
 511                 break;
 512         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 513                 p_link->speed = 25000;
 514                 break;
 515         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 516                 p_link->speed = 20000;
 517                 break;
 518         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 519                 p_link->speed = 10000;
 520                 break;
 521         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 522                 p_link->full_duplex = false;
 523         /* Fall-through */
 524         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 525                 p_link->speed = 1000;
 526                 break;
 527         default:
 528                 p_link->speed = 0;
 529         }
 530
 531         if (p_link->link_up && p_link->speed)
 532                 p_link->line_speed = p_link->speed;
 533         else
 534                 p_link->line_speed = 0;
 535
 536         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 537         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 538
 539         /* Max bandwidth configuration */
 540         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
 541
 542         /* Min bandwidth configuration */
 543         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
 544         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate);
 545
 546         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 547         p_link->an_complete = !!(status &
 548                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 549         p_link->parallel_detection = !!(status &
 550                                         LINK_STATUS_PARALLEL_DETECTION_USED);
 551         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 552
 553         p_link->partner_adv_speed |=
 554                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 555                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
 556         p_link->partner_adv_speed |=
 557                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 558                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
 559         p_link->partner_adv_speed |=
 560                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 561                 QED_LINK_PARTNER_SPEED_10G : 0;
 562         p_link->partner_adv_speed |=
 563                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 564                 QED_LINK_PARTNER_SPEED_20G : 0;
 565         p_link->partner_adv_speed |=
 566                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 567                 QED_LINK_PARTNER_SPEED_40G : 0;
 568         p_link->partner_adv_speed |=
 569                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 570                 QED_LINK_PARTNER_SPEED_50G : 0;
 571         p_link->partner_adv_speed |=
 572                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 573                 QED_LINK_PARTNER_SPEED_100G : 0;
 574
 575         p_link->partner_tx_flow_ctrl_en =
 576                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 577         p_link->partner_rx_flow_ctrl_en =
 578                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 579
 580         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 581         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 582                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
 583                 break;
 584         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 585                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
 586                 break;
 587         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 588                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
 589                 break;
 590         default:
 591                 p_link->partner_adv_pause = 0;
 592         }
 593
 594         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 595
 596         qed_link_update(p_hwfn);
 597 }
 598
 599 int qed_mcp_set_link(struct qed_hwfn *p_hwfn,
 600                      struct qed_ptt *p_ptt,
 601                      bool b_up)
 602 {
 603         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 604         struct qed_mcp_mb_params mb_params;
 605         union drv_union_data union_data;
 606         struct pmm_phy_cfg *phy_cfg;
 607         int rc = 0;
 608         u32 cmd;
 609
 610         /* Set the shmem configuration according to params */
 611         phy_cfg = &union_data.drv_phy_cfg;
 612         memset(phy_cfg, 0, sizeof(*phy_cfg));
 613         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 614         if (!params->speed.autoneg)
 615                 phy_cfg->speed = params->speed.forced_speed;
 616         phy_cfg->pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0;
 617         phy_cfg->pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0;
 618         phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0;
 619         phy_cfg->adv_speed = params->speed.advertised_speeds;
 620         phy_cfg->loopback_mode = params->loopback_mode;
 621
 622         p_hwfn->b_drv_link_init = b_up;
 623
 624         if (b_up) {
 625                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 626                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
 627                            phy_cfg->speed,
 628                            phy_cfg->pause,
 629                            phy_cfg->adv_speed,
 630                            phy_cfg->loopback_mode,
 631                            phy_cfg->feature_config_flags);
 632         } else {
 633                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 634                            "Resetting link\n");
 635         }
 636
 637         memset(&mb_params, 0, sizeof(mb_params));
 638         mb_params.cmd = cmd;
 639         mb_params.p_data_src = &union_data;
 640         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 641
 642         /* if mcp fails to respond we must abort */
 643         if (rc) {
 644                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 645                 return rc;
 646         }
 647
 648         /* Reset the link status if needed */
 649         if (!b_up)
 650                 qed_mcp_handle_link_change(p_hwfn, p_ptt, true);
 651
 652         return 0;
 653 }
 654
 655 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
 656                                   struct public_func *p_shmem_info)
 657 {
 658         struct qed_mcp_function_info *p_info;
 659
 660         p_info = &p_hwfn->mcp_info->func_info;
 661
 662         p_info->bandwidth_min = (p_shmem_info->config &
 663                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 664                                         FUNC_MF_CFG_MIN_BW_SHIFT;
 665         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 666                 DP_INFO(p_hwfn,
 667                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 668                         p_info->bandwidth_min);
 669                 p_info->bandwidth_min = 1;
 670         }
 671
 672         p_info->bandwidth_max = (p_shmem_info->config &
 673                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 674                                         FUNC_MF_CFG_MAX_BW_SHIFT;
 675         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 676                 DP_INFO(p_hwfn,
 677                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 678                         p_info->bandwidth_max);
 679                 p_info->bandwidth_max = 100;
 680         }
 681 }
 682
 683 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
 684                                   struct qed_ptt *p_ptt,
 685                                   struct public_func *p_data,
 686                                   int pfid)
 687 {
 688         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 689                                         PUBLIC_FUNC);
 690         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
 691         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 692         u32 i, size;
 693
 694         memset(p_data, 0, sizeof(*p_data));
 695
 696         size = min_t(u32, sizeof(*p_data),
 697                      QED_SECTION_SIZE(mfw_path_offsize));
 698         for (i = 0; i < size / sizeof(u32); i++)
 699                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
 700                                             func_addr + (i << 2));
 701         return size;
 702 }
 703
 704 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn,
 705                               struct qed_ptt *p_ptt)
 706 {
 707         struct qed_mcp_function_info *p_info;
 708         struct public_func shmem_info;
 709         u32 resp = 0, param = 0;
 710
 711         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
 712                                MCP_PF_ID(p_hwfn));
 713
 714         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
 715
 716         p_info = &p_hwfn->mcp_info->func_info;
 717
 718         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
 719         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
 720
 721         /* Acknowledge the MFW */
 722         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
 723                     &param);
 724 }
 725
 726 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
 727                           struct qed_ptt *p_ptt)
 728 {
 729         struct qed_mcp_info *info = p_hwfn->mcp_info;
 730         int rc = 0;
 731         bool found = false;
 732         u16 i;
 733
 734         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
 735
 736         /* Read Messages from MFW */
 737         qed_mcp_read_mb(p_hwfn, p_ptt);
 738
 739         /* Compare current messages to old ones */
 740         for (i = 0; i < info->mfw_mb_length; i++) {
 741                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
 742                         continue;
 743
 744                 found = true;
 745
 746                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 747                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
 748                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
 749
 750                 switch (i) {
 751                 case MFW_DRV_MSG_LINK_CHANGE:
 752                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
 753                         break;
 754                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
 755                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
 756                         break;
 757                 case MFW_DRV_MSG_BW_UPDATE:
 758                         qed_mcp_update_bw(p_hwfn, p_ptt);
 759                         break;
 760                 default:
 761                         DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i);
 762                         rc = -EINVAL;
 763                 }
 764         }
 765
 766         /* ACK everything */
 767         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
 768                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
 769
 770                 /* MFW expect answer in BE, so we force write in that format */
 771                 qed_wr(p_hwfn, p_ptt,
 772                        info->mfw_mb_addr + sizeof(u32) +
 773                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
 774                        sizeof(u32) + i * sizeof(u32),
 775                        (__force u32)val);
 776         }
 777
 778         if (!found) {
 779                 DP_NOTICE(p_hwfn,
 780                           "Received an MFW message indication but no new message!\n");
 781                 rc = -EINVAL;
 782         }
 783
 784         /* Copy the new mfw messages into the shadow */
 785         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
 786
 787         return rc;
 788 }
 789
 790 int qed_mcp_get_mfw_ver(struct qed_dev *cdev,
 791                         u32 *p_mfw_ver)
 792 {
 793         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
 794         struct qed_ptt *p_ptt;
 795         u32 global_offsize;
 796
 797         p_ptt = qed_ptt_acquire(p_hwfn);
 798         if (!p_ptt)
 799                 return -EBUSY;
 800
 801         global_offsize = qed_rd(p_hwfn, p_ptt,
 802                                 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
 803                                                      public_base,
 804                                                      PUBLIC_GLOBAL));
 805         *p_mfw_ver = qed_rd(p_hwfn, p_ptt,
 806                             SECTION_ADDR(global_offsize, 0) +
 807                             offsetof(struct public_global, mfw_ver));
 808
 809         qed_ptt_release(p_hwfn, p_ptt);
 810
 811         return 0;
 812 }
 813
 814 int qed_mcp_get_media_type(struct qed_dev *cdev,
 815                            u32 *p_media_type)
 816 {
 817         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
 818         struct qed_ptt  *p_ptt;
 819
 820         if (!qed_mcp_is_init(p_hwfn)) {
 821                 DP_NOTICE(p_hwfn, "MFW is not initialized !\n");
 822                 return -EBUSY;
 823         }
 824
 825         *p_media_type = MEDIA_UNSPECIFIED;
 826
 827         p_ptt = qed_ptt_acquire(p_hwfn);
 828         if (!p_ptt)
 829                 return -EBUSY;
 830
 831         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
 832                                offsetof(struct public_port, media_type));
 833
 834         qed_ptt_release(p_hwfn, p_ptt);
 835
 836         return 0;
 837 }
 838
 839 static int
 840 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
 841                         struct public_func *p_info,
 842                         enum qed_pci_personality *p_proto)
 843 {
 844         int rc = 0;
 845
 846         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
 847         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
 848                 *p_proto = QED_PCI_ETH;
 849                 break;
 850         default:
 851                 rc = -EINVAL;
 852         }
 853
 854         return rc;
 855 }
 856
 857 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
 858                                  struct qed_ptt *p_ptt)
 859 {
 860         struct qed_mcp_function_info *info;
 861         struct public_func shmem_info;
 862
 863         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
 864                                MCP_PF_ID(p_hwfn));
 865         info = &p_hwfn->mcp_info->func_info;
 866
 867         info->pause_on_host = (shmem_info.config &
 868                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
 869
 870         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info,
 871                                     &info->protocol)) {
 872                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
 873                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
 874                 return -EINVAL;
 875         }
 876
 877         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
 878
 879         if (shmem_info.mac_upper || shmem_info.mac_lower) {
 880                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
 881                 info->mac[1] = (u8)(shmem_info.mac_upper);
 882                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
 883                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
 884                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
 885                 info->mac[5] = (u8)(shmem_info.mac_lower);
 886         } else {
 887                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
 888         }
 889
 890         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
 891                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
 892         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
 893                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
 894
 895         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
 896
 897         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
 898                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n",
 899                 info->pause_on_host, info->protocol,
 900                 info->bandwidth_min, info->bandwidth_max,
 901                 info->mac[0], info->mac[1], info->mac[2],
 902                 info->mac[3], info->mac[4], info->mac[5],
 903                 info->wwn_port, info->wwn_node, info->ovlan);
 904
 905         return 0;
 906 }
 907
 908 struct qed_mcp_link_params
 909 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
 910 {
 911         if (!p_hwfn || !p_hwfn->mcp_info)
 912                 return NULL;
 913         return &p_hwfn->mcp_info->link_input;
 914 }
 915
 916 struct qed_mcp_link_state
 917 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
 918 {
 919         if (!p_hwfn || !p_hwfn->mcp_info)
 920                 return NULL;
 921         return &p_hwfn->mcp_info->link_output;
 922 }
 923
 924 struct qed_mcp_link_capabilities
 925 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
 926 {
 927         if (!p_hwfn || !p_hwfn->mcp_info)
 928                 return NULL;
 929         return &p_hwfn->mcp_info->link_capabilities;
 930 }
 931
 932 int qed_mcp_drain(struct qed_hwfn *p_hwfn,
 933                   struct qed_ptt *p_ptt)
 934 {
 935         u32 resp = 0, param = 0;
 936         int rc;
 937
 938         rc = qed_mcp_cmd(p_hwfn, p_ptt,
 939                          DRV_MSG_CODE_NIG_DRAIN, 1000,
 940                          &resp, &param);
 941
 942         /* Wait for the drain to complete before returning */
 943         msleep(1020);
 944
 945         return rc;
 946 }
 947
 948 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
 949                            struct qed_ptt *p_ptt,
 950                            u32 *p_flash_size)
 951 {
 952         u32 flash_size;
 953
 954         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
 955         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
 956                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
 957         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
 958
 959         *p_flash_size = flash_size;
 960
 961         return 0;
 962 }
 963
 964 int
 965 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
 966                          struct qed_ptt *p_ptt,
 967                          struct qed_mcp_drv_version *p_ver)
 968 {
 969         struct drv_version_stc *p_drv_version;
 970         struct qed_mcp_mb_params mb_params;
 971         union drv_union_data union_data;
 972         __be32 val;
 973         u32 i;
 974         int rc;
 975
 976         p_drv_version = &union_data.drv_version;
 977         p_drv_version->version = p_ver->version;
 978
 979         for (i = 0; i < MCP_DRV_VER_STR_SIZE - 1; i += 4) {
 980                 val = cpu_to_be32(p_ver->name[i]);
 981                 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val;
 982         }
 983
 984         memset(&mb_params, 0, sizeof(mb_params));
 985         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
 986         mb_params.p_data_src = &union_data;
 987         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 988         if (rc)
 989                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 990
 991         return rc;
 992 }
 993
 994 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 995                     enum qed_led_mode mode)
 996 {
 997         u32 resp = 0, param = 0, drv_mb_param;
 998         int rc;
 999
1000         switch (mode) {
1001         case QED_LED_MODE_ON:
1002                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1003                 break;
1004         case QED_LED_MODE_OFF:
1005                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1006                 break;
1007         case QED_LED_MODE_RESTORE:
1008                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1009                 break;
1010         default:
1011                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
1012                 return -EINVAL;
1013         }
1014
1015         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1016                          drv_mb_param, &resp, &param);
1017
1018         return rc;
1019 }
1020
1021 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1022 {
1023         u32 drv_mb_param = 0, rsp, param;
1024         int rc = 0;
1025
1026         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
1027                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1028
1029         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1030                          drv_mb_param, &rsp, &param);
1031
1032         if (rc)
1033                 return rc;
1034
1035         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1036             (param != DRV_MB_PARAM_BIST_RC_PASSED))
1037                 rc = -EAGAIN;
1038
1039         return rc;
1040 }
1041
1042 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1043 {
1044         u32 drv_mb_param, rsp, param;
1045         int rc = 0;
1046
1047         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
1048                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1049
1050         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1051                          drv_mb_param, &rsp, &param);
1052
1053         if (rc)
1054                 return rc;
1055
1056         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1057             (param != DRV_MB_PARAM_BIST_RC_PASSED))
1058                 rc = -EAGAIN;
1059
1060         return rc;
1061 }